LTC1416
Low Power 14-Bit, 400ksps
Sampling ADC
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FEATURES
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DESCRIPTIO
The LTC ®1416 is a 2.2µs, 400ksps, 14-bit sampling A/D
converter that draws only 70mW from ±5V supplies. This
easy-to-use device includes a high dynamic range sampleand-hold and a precision reference. Two digitally selectable power shutdown modes provide flexibility for low
power systems.
Sample Rate: 400ksps
Power Dissipation: 70mW
Guaranteed ± 1.5LSB DNL, ± 2LSB INL (Max)
80.5dB S/(N + D) and 93dB THD at 100kHz
80dB S/(N + D) and 90dB THD at Nyquist
Nap and Sleep Shutdown Modes
Operates with Internal or External Reference
True Differential Inputs Reject Common Mode Noise
15MHz Full Power Bandwidth Sampling
±2.5V Bipolar Input Range
28-Pin SSOP Package
The LTC1416’s full-scale input range is ±2.5V. Maximum
DC specifications include ±2LSB INL, ±1.5LSB DNL over
temperature. Outstanding AC performance includes 80.5dB
S/(N + D) and 93dB THD with a 100kHz input, and 80dB
S/(N + D) and 90dB THD at the Nyquist input frequency of
200kHz.
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APPLICATIO S
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The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its
15MHz bandwidth. The 60dB common mode rejection
allows users to eliminate ground loops and common
mode noise by measuring signals differentially from the
source.
Telecommunications
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
Imaging Systems
The ADC has a µP compatible, 14-bit parallel output
port. There is no pipeline delay in the conversion
results. A separate convert start input and a data ready
signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
Effective Bits and
Signal-to-(Noise + Distortion)
vs Input Frequency
Complete, 70mW, 14-Bit ADC with 80.5dB S/(N + D)
10µF
DVDD
AVDD
REFCOMP
22µF
BUFFER
4k
TIMING
AND
LOGIC
2.5V
REFERENCE
VREF
1µF
VSS
10µF –5V
AGND
DGND
•
•
•
D13 (MSB)
D0 (LSB)
BUSY
CS
CONVST
RD
SHDN
1416 TA01
EFFECTIVE BITS
OUTPUT
BUFFERS
14-BIT ADC
S/H
AIN–
86
80
74
68
62
NYQUIST
FREQUENCY
SIGNAL/(NOISE + DISTORTION) (dB)
LTC1416
14
AIN+
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
fSAMPLE = 400kHz
1k
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
1416 TA02
1
LTC1416
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ABSOLUTE
PACKAGE/ORDER I FOR ATIO
RATI GS
AVDD = DVDD = VDD (Notes 1, 2)
ORDER
PART NUMBER
TOP VIEW
Supply Voltage (VDD) ................................................ 6V
Negative Supply Voltage (VSS) ............................... – 6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V)
Digital Input Voltage (Note 4) ..........(VSS – 0.3V) to 10V
Digital Output Voltage ....... (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation ............................................. 500mW
Operating Temperature Range
Commercial ............................................ 0°C to 70°C
Industrial ........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
AIN+ 1
28 AVDD
AIN– 2
27 DVDD
VREF 3
26 VSS
REFCOMP 4
LTC1416CG
LTC1416IG
25 BUSY
AGND 5
24 CS
D13(MSB) 6
23 CONVST
D12 7
22 RD
D11 8
21 SHDN
D10 9
20 D0
D9 10
19 D1
D8 11
18 D2
D7 12
17 D3
D6 13
16 D4
DGND 14
15 D5
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 95°C/W
Consult factory for Military grade parts and for A grade parts.
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CO VERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6)
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
Integral Linearity Error
(Note 7)
MAX
13
●
Differential Linearity Error
TYP
UNITS
Bits
●
±0.8
±2
LSB
●
±0.7
±1.5
LSB
●
±5
±20
LSB
±60
±40
LSB
LSB
Offset Error
(Note 8)
Full-Scale Error
Internal Reference
External Reference = 2.5V
±20
±10
Full-Scale Tempco
IOUT(REF) = 0
±15
ppm/°C
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A ALOG I PUT
The ● denotes specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 9)
4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.75V
●
IIN
Analog Input Leakage Current
CS = High
●
CIN
Analog Input Capacitance
Between Conversions
During Conversions
t ACQ
Sample-and-Hold Acquisition Time
(Note 9)
t AP
Sample-and-Hold Aperture Delay Time
tjitter
Sample-and-Hold Aperture Delay Time Jitter
CMRR
2
Analog Input Common Mode Rejection Ratio
MIN
TYP
15
5
●
100
= AIN
+ ) < 2.5V
UNITS
V
±1
–1.5
– 2.5V < (AIN–
MAX
±2.5
µA
pF
pF
400
ns
ns
2
psRMS
60
dB
LTC1416
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DY A IC ACCURACY
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
S/(N + D)
Signal-to-(Noise + Distortion) Ratio
100kHz Input Signal
200kHz Input Signal
●
MIN
TYP
77
80.5
80
THD
Total Harmonic Distortion
100kHz Input Signal, First 5 Harmonics
200kHz Input Signal, First 5 Harmonics
●
– 93
– 90
– 86
dB
dB
SFDR
Spurious-Free Dynamic Range
100kHz Input Signal
●
– 95
– 86
dB
IMD
Intermodulation Distortion
fIN1 = 87.01172kHz, fIN2 = 113.18359kHz
UNITS
dB
dB
– 90
Full Power Bandwidth
S/(N + D) ≥ 77dB
Full Linear Bandwidth
MAX
dB
15
MHz
0.8
MHz
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I TER AL REFERE CE CHARACTERISTICS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VREF Output Voltage
IOUT = 0
2.480
2.500
2.520
V
VREF Output Tempco
IOUT = 0
±15
ppm/°C
VREF Line Regulation
4.75V ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ – 4.75V
0.05
0.05
LSB/V
LSB/V
VREF Output Resistance
– 0.1mA ≤ IOUT ≤ 0.1mA
COMP Output Voltage
IOUT = 0
4
kΩ
4.06
V
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
●
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
MIN
VDD = 4.75V
IOUT = – 10µA
IOUT = – 200µA
●
VDD = 4.75V
IOUT = 160µA
IOUT = 1.6mA
●
TYP
MAX
UNITS
2.4
V
5
pF
4.5
V
V
4.0
0.05
0.10
0.4
V
V
IOZ
Hi-Z Output Leakage D13 to D0
VOUT = 0V to VDD, CS High
●
±10
µA
COZ
Hi-Z Output Capacitance D13 to D0
CS High (Note 9 )
●
15
pF
ISOURCE
Output Source Current
VOUT = 0V
– 10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
VDD
Positive Supply Voltage
(Note 10)
VSS
Negative Supply Voltage
(Note 10)
IDD
Positive Supply Current
Nap Mode
Sleep Mode
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
MIN
●
TYP
MAX
UNITS
4.75
5.25
V
– 4.75
– 5.25
V
7
1
1
10
1.6
mA
mA
µA
3
LTC1416
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
ISS
Negative Supply Current
Nap Mode
Sleep Mode
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
Power Dissipation
Power Dissipation, Nap Mode
Power Dissipation, Sleep Mode
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
PDISS
CONDITIONS
TYP
MAX
●
MIN
7
20
15
10
UNITS
mA
µA
µA
●
70
4
0.1
100
6
mW
mW
mW
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5, see Figures 15 to 21)
SYMBOL
PARAMETER
CONDITIONS
fSAMPLE(MAX)
Maximum Sampling Frequency
●
400
tCONV
Conversion Time
●
1.5
tACQ
Acquisition Time
tACQ+CONV
Acquisition + Conversion Time
t1
CS to RD Setup Time
t2
t3
t4
SHDN↑ to CONVST↓ Wake-Up Time
CS = 0V (Note 10)
t5
CONVST Low Time
(Notes 10, 11)
t6
CONVST to BUSY Delay
CL = 25pF
(Note 9)
MIN
TYP
MAX
1.9
2.2
µs
●
100
400
ns
●
2
2.5
µs
kHz
(Notes 9, 10)
●
0
ns
CS↓ to CONVST↓ Setup Time
(Notes 9, 10)
●
10
ns
CS↓ to SHDN↓ Setup Time
(Notes 9, 10)
●
10
ns
●
40
400
Data Ready Before BUSY↑
25
(Note 9)
●
t8
Delay Between Conversions
t9
Wait Time RD↓ After BUSY↑
t10
Data Access Time After RD↓
(Note 10)
50
75
50
100
40
ns
–5
ns
CL = 25pF
15
25
35
ns
ns
20
35
50
ns
ns
8
20
25
30
ns
ns
ns
●
0°C ≤ TA ≤ 70°C
– 40°C ≤ TA ≤ 85°C
ns
ns
●
CL = 100pF
Bus Relinquish Time
ns
ns
●
●
t11
ns
ns
●
t7
UNITS
●
●
t12
RD Low Time
●
t 10
ns
t13
CONVST High Time
●
40
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.
Note 4: When these pin voltages are taken below VSS, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, t r = t f = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN– grounded.
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Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 900ns after the
start of the conversion or after BUSY rises.
LTC1416
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TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
VIN = 0dB
80
80
70
VIN = –20dB
60
50
40
30
VIN = –60dB
20
70
60
50
40
30
20
10
10
0
0
1k
10k
100k
INPUT FREQUENCY (Hz)
1k
1M 2M
10k
100k
INPUT FREQUENCY (Hz)
Spurious-Free Dynamic Range
vs Input Frequency
–20
–30
–40
–50
–60
–70
–80
–90
1M 2M
1k
–50
–60
–70
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
1416 G03
Differential Nonlinearity
vs Output Code
1.0
VOUT = ±2.5V
VREF = 2.5V
0.5
–40
DNL ERROR (LSB)
–20
–40
2ND
–110
fSAMPLE = 400kHz
fa=87.01171876kHz
fb=113.1835938kHz
–20
–30
3RD
THD
–100
0
–10
AMPLITUDE (dB)
SPURIOUS-FREE DYNAMIC RANGE (dB)
–10
Intermodulation Distortion Plot
0
–60
–80
–100
0
–0.5
–80
–120
–90
–100
1k
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
–140
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (Hz)
1416 G04
–1.0
0
–0.5
–20
–30
–40
–50
–60
–70
–80
4096
8192
12288
16384
OUTPUT CODE
1416 G07
16384
80
–10
DGND (VIN = 100mV)
VSS (VIN = 10mV)
–90
–100
0
12288
Input Common Mode Rejection
vs Input Frequency
COMMON MODE REJECTION (dB)
AMPLITUDE OF
POWER SUPPLY FEEDTHROUGH (dB)
0.5
8192
1416 G06
Power Supply Feedthrough
vs Ripple Frequency
VOUT = ±2.5V
VREF = 2.5V
4096
OUTPUT CODE
0
1.0
0
1416 G05
Integral Nonlinearity
vs Output Code
–1.0
0
1416 G02
1416 G01
INL ERROR (LSB)
Distortion vs Input Frequency
90
SIGNAL-TO-NOISE RATIO (dB)
SIGNAL/(NOISE + DISTORTION) (dB)
90
Signal-to-Noise Ratio
vs Input Frequency
VDD (VIN = 10mV)
70
60
50
40
30
20
10
0
1k
10k
100k
RIPPLE FREQUENCY (Hz)
1M 2M
1416 G08
1k
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
1416 G09
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LTC1416
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PI FU CTIO S
AIN+ (Pin 1): ±2.5V Positive Analog Input.
AIN– (Pin 2): ±2.5V Negative Analog Input.
VREF (Pin 3): 2.5V Reference Output. Bypass to AGND
with 1µF.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND with 22µF tantalum in parallel with 0.1µF
ceramic, or 22µF ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 to D0 (Pins 15 to 20): Three-State Data Outputs.
SHDN (Pin 21): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): The Chip Select input must be low for the
ADC to recognize CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
is valid on the rising edge of BUSY.
VSS (Pin 26): – 5V Negative Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic, or
10µF ceramic.
DVDD (Pin 27): 5V Positive Supply. Tie to Pin 28.
AVDD (Pin 28): 5V Positive Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic, or
10µF ceramic.
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FU CTIO AL BLOCK DIAGRA
CSAMPLE
AIN+
AVDD
DVDD
CSAMPLE
AIN–
VSS
4k
VREF
ZEROING SWITCHES
2.5V REF
+
REF AMP
COMP
14-BIT CAPACITIVE DAC
–
REFCOMP
(4.06V)
SUCCESSIVE APPROXIMATION
REGISTER
AGND
DGND
INTERNAL
CLOCK
OUTPUT LATCHES
•
•
•
D13
D0
CONTROL LOGIC
SHDN CONVST
6
14
RD
CS
BUSY
1416 BD
LTC1416
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
1k
DBN
DBN
DBN
1k
CL
1k
CL
(A) Hi-Z TO VOH AND VOL TO VOH
DBN
(B) Hi-Z TO VOL AND VOH TO VOL
1416 TC01
(A) VOH TO Hi-Z
100pF
100pF
(B) VOL TO Hi-Z
1416 TC02
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APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1416 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)
AIN+
CSAMPLE+
SAMPLE
HOLD
AIN–
CSAMPLE–
SAMPLE
HOLD
HOLD
ZEROING SWITCHES
CDAC+
HOLD
+
VDAC+
CDAC–
COMP
–
VDAC–
14
SAR
OUTPUT
LATCH
•
•
•
D13
D0
1416 F01
Figure 1. Simplified Block Diagram
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun, it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are
connected to the sample-and-hold capacitors (CSAMPLE)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 400ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively compared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 14-bit data word) which
represents the difference of AIN+ and AIN– are loaded into
the 14-bit output latches.
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LTC1416
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APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
The LTC1416 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1416 FFT plot.
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2a shows a typical spectral content with
a 400kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 200kHz, Figure 2b.
0
fSAMPLE = 400kHz
fIN = 101.5625kHz
SFDR = 95.2dB
SINAD = 80.5dB
AMPLITUDE (dB)
–20
–40
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
–60
–80
ENOB = [S/(N + D) – 1.76]/6.02
–100
–120
–140
0
25
50
75
100 125 150 175 200
FREQUENCY (kHz)
1416 F02a
where ENOB is the Effective Number of Bits of resolution
and S/(N + D) is expressed in dB. At the maximum
sampling rate of 400kHz, the LTC1416 maintains near
ideal ENOBs up to the Nyquist input frequency of 200kHz
(refer to Figure 3).
Figure 2a. LTC1416 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
AMPLITUDE (dB)
–40
EFFECTIVE BITS
fSAMPLE = 400kHz
fIN = 189.9414kHz
SFDR = 94.8dB
SINAD = 80.2dB
–20
–60
–80
–100
–120
NYQUIST
FREQUENCY
fSAMPLE = 400kHz
1k
–140
0
25
50
75
100 125 150 175 200
86
80
74
68
62
SIGNAL/(NOISE + DISTORTION) (dB)
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
1416 TA02
FREQUENCY (kHz)
1416 F02b
Figure 2b. LTC1416 Nonaveraged, 4096 Point FFT,
Input Frequency = 190kHz
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Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
LTC1416
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APPLICATIONS INFORMATION
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD = 20 log
V22 + V32 + V42 + ...Vn2
V1
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through Nth harmonics. THD versus input frequency is shown in Figure 4. The LTC1416 has good
distortion performance up to the Nyquist frequency and
beyond.
difference frequencies of mfa ± nfb, where m and n = 0, 1,
2, 3, etc. For example, the 2nd order IMD terms include (fa
+ fb). If the two input sine waves are equal in magnitude,
the value (in decibels) of the 2nd order IMD products can
be expressed by the following formula:
(
)
IMD fa + fb = 20 log
(
)
Amplitude at fa + fb
Amplitude at fa
0
–20
AMPLITUDE (dB)
Total Harmonic Distortion
fSAMPLE = 400kHz
fa=87.01171876kHz
fb=113.1835938kHz
–40
–60
–80
–100
0
–10
–120
–20
–140
–30
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (Hz)
–40
–50
1416 G05
–60
Figure 5. Intermodulation Distortion Plot
–70
–80
–90
3RD
THD
Peak Harmonic or Spurious Noise
2ND
–100
–110
1k
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
1416 G03
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal. The full-linear
bandwidth is the input frequency at which the S/(N + D)
has dropped to 77dB (12.5 effective bits). The LTC1416
has been designed to optimize input bandwidth, allowing
the ADC to undersample input signals with frequencies
above the converter’s Nyquist frequency. The noise floor
stays very low at high frequencies; S/(N + D) becomes
dominated by distortion at frequencies far beyond Nyquist.
9
LTC1416
U
W
U
U
APPLICATIONS INFORMATION
Driving the Analog Input
The differential analog inputs of the LTC1416 are easy to
drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The AIN+ and
AIN– inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be
reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1416
inputs can be driven directly. As source impedance
increases so will acquisition time (see Figure 6). For
minimum acquisition time, with high source impedance, a
buffer amplifier should be used. The only requirement
is that the amplifier driving the analog input(s) must
settle after the small current spike before the next
conversion starts (settling time must be 400ns for full
throughput rate).
ACQUISITION TIME (µs)
The best choice for an op amp to drive LTC1416 will
depend on the application. Generally, applications fall into
two categories: AC applications where dynamic specifications are most critical and time domain applications where
DC accuracy and settling time are most critical. The
following list is a summary of the op amps that are suitable
for driving the LTC1416. More detailed information is
available in the Linear Technology Databooks and the
LinearViewTM CD-ROM.
LT ®1220: 30MHz unity-gain bandwidth voltage feedback
amplifier. ±5V to ±15V supplies, excellent DC specifications.
LT1223: 100MHz video current feedback amplifier. 6mA
supply current, ±5V to ±15V supplies, low distortion at
frequencies above 400kHz, low noise, good for AC applications.
10
1
LT1227: 140MHz video current feedback amplifier. 10mA
supply current, ±5V to ±15V supplies, lowest distortion at
frequencies above 400kHz, low noise, best for AC applications.
0.1
0.01
10
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz should be less than 100Ω.
The second requirement is that the closed-loop bandwidth
must be greater than 10MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions.
100
1k
10k
SOURCE RESISTANCE (Ω)
100k
LT1229/LT1230: Dual and quad 100MHz current feedback
amplifiers. ±2V to ±15V supplies, low noise, good AC
specs, 6mA supply current each amplifier.
1416 F06
Figure 6. Acquisition Time vs Source Resistance
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging the
sampling capacitor, choose an amplifier that has a low
output impedance (
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