LTC1426CS8#PBF

LTC1426 Micropower Dual 6-Bit PWM DAC FEATURES DESCRIPTION Wide Supply Range: 2.7V ≤ VCC ≤ 5.5V nn Wide Reference Voltage Range: 0V to 5.5V nn Two Interface Modes: Pulse Mode (Increment Only) Pushbutton Mode (Increment/Decrement) nn Low Supply Current: 50µA nn 0.2µA Supply Current in Shutdown nn Available in 8-Pin MSOP and SO Packages nn DAC Contents Are Retained in Shutdown nn DACs Power-Up at Midrange nn Low Output Impedance: < 100Ω nn Output Frequency: 5kHz Typ The LTC®1426 is a dual micropower 6-bit PWM DAC featuring versatile PWM outputs and a flexible pushbutton compatible digital interface. The DAC outputs provide a PWM signal that swings from 0V to VREF, allowing the full-scale output to be varied by adjusting the voltage at VREF. The PWM output frequency is typically 5kHz, easing output filtering requirements. VCC supply current is typically 50µA and drops to 0.2µA in shutdown. nn The LTC1426 can be controlled using one of two interface modes: pushbutton and pulse. The LTC1426 automatically configures itself into the appropriate mode at start-up by monitoring the state of the CLK pins. In pushbutton mode, the CLK pins can be directly connected to external pushbuttons to control the DAC output. In pulse mode, the CLK pins can be connected to CMOS compatible logic. The DAC outputs initially power up at half scale and the contents of the internal DAC registers are retained in shutdown. APPLICATIONS LCD Contrast and Backlight Brightness Control Power Supply Voltage Adjustment nn Battery Charger Voltage and Current Adjustment nn GaAs FET Bias Adjustment nn Trimmer Pot Elimination nn nn The LTC1426 is available in 8-pin MSOP and SO packages. All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION Pushbutton Adjustable CCFL/LCD Contrast Generator R1 44.2k 1% 5V RP1 47k UP RP2 47k SHDN UP CONTRAST UP/DOWN 1 CCFL UP/DOWN 2 DOWN DOWN 3 4 SHDN CLK2 VCC GND VREF PWM1 PWM2 R3 5.1k 1% R4 4.99k 1% 1 2 3 4 C7 1µF LTC1426 CLK1 ICCFL = 0µA TO 50µA R2 44.2k 1% C2 1µF C1 0.1µF RSHDN 1M 5 8 6 7 7 CCFL PGND CCFL VSW BULB ICCFL DIO LT1182 CCFL VC 5 BAT ROYER AGND VIN SHDN FBP LCD VC R7 8 C8 10k LCD PGND 0.68µF 6 UP TO 6mA LAMP FBN LCD VSW R5 20k 1% HIGH VOLTAGE ROYER 16 15 14 13 12 11 10 9 + 5V C9 2.2µF + 8V TO 28V C10 2.2µF 35V C11 2.2µF 35V LCD CONTRAST CONVERTER 1426 TA01 C3 10µF Document Feedback C4 0.1µF R6 40k 1% CONSULT THE LT1182 DATA SHEET FOR DETAILS ON THE HIGH VOLTAGE ROYER AND LCD CONTRAST CONVERTER SECTIONS For more information www.analog.com VOUT NEGATIVE LCD CONTRAST VOUT = –10V TO –30V Rev A 1 LTC1426 ABSOLUTE MAXIMUM RATINGS (Note 1) Total Supply Voltage (VCC) .........................................7V Reference Voltage (VREF)................................ – 0.3 to 7V Input Voltage (All Inputs) ............... – 0.3 to (VCC + 0.3V) DAC Output Short-Circuit Duration .................. Indefinite IPWM(MAX) ........................................................... 100mA Operating Temperature Range LTC1426C................................................. 0°C to 70°C LTC1426I............................................. – 40°C to 85°C Storage Temperature Range.................... –65°C to 150°C Lead Temperature (Soldering, 10 sec)................... 300°C PIN CONFIGURATION TOP VIEW TOP VIEW CLK1 CLK2 GND PWM1 1 2 3 4 8 7 6 5 SHDN VCC VREF PWM2 MS8 PACKAGE 8-LEAD PLASTIC MSOP SHDN CLK1 1 8 CLK2 2 7 VCC GND 3 6 VREF PWM1 4 5 PWM2 S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 100°C, θJA = 200°C/W TJMAX = 100°C, θJA = 130°C/W OBSOLETE PACKAGE ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1426CMS8#PBF LTC1426CMS8#TRPBF LTBQ 8-Lead Plastic MSOP 0°C to 70°C LTC1426CS8#PBF LTC1426CS8#TRPBF 1426 8-Lead Plastic SO 0°C to 70°C LTC1426IS8#PBF LTC1426IS8#TRPBF 1426I 8-Lead Plastic SO –40°C to 85°C Consult ADI Marketing for parts specified with wider operating temperature ranges. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER VCC Supply Voltage VREF Reference Voltage ICC Supply Current IREF Reference Current CONDITIONS MIN TYP MAX UNITS l 2.7 5.5 V l 0 5.5 V Pulse Mode: VSHDN = VCC, VCLK1 = VCLK2 = 0V, PWM1 = PWM2 = NC Pushbutton Mode: VSHDN = VCC, VCLK1 = VCLK2 = PWM1 = PWM2 = NC SHDN = 0 (Note 3) l l l 40 50 0.2 100 100 ±10 µA µA µA Pulse Mode: VSHDN = VCC, VCLK1 = VCLK2 = 0V, PWM1 = PWM2 = NC Pushbutton Mode: VSHDN = VCC, VCLK1 = VCLK2 = PWM1 = PWM2 = NC SHDN = 0 (Note 3) l l l 75 75 0.2 150 150 ±10 µA µA µA DAC Resolution 6 bits Rev A 2 For more information www.analog.com LTC1426 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS DAC Frequency 0°C ≤ TA ≤ 70°C – 40°C ≤ TA ≤ 85°C l l DAC Output Impedance VCC = 2.7V, VREF = 0.5V l MIN TYP MAX 3 2 5 5 6 6 20 100 UNITS kHz kHz Ω DAC Full-Scale Duty Cycle 98.44 % DAC Zero-Scale Duty Cycle 0 % DNL DAC Differential Nonlinearity Monotonicity Guaranteed (Note 4) l ±0.05 LSB INL DAC Integral Nonlinearity l ±0.05 LSB FS Error DAC Full-Scale Error l ±0.50 LSB IIN Logic Input Current Pulse Mode: 0V ≤ VIN ≤ VCC SHDN CLK1, CLK2 l l ±5 ±5 µA µA SHDN Pushbutton Mode: 0V ≤ VIN ≤ VCC CLK1, CLK2 l l ±5 ±10 µA µA VCC = 5.5V SHDN CLK1, CLK2 l l 2.0 4.4 V V SHDN VCC = 3.6V CLK1, CLK2 l l 1.9 2.9 V V VCC = 4.5V SHDN CLK1, CLK2 l l 0.8 0.8 V V SHDN VCC = 2.7V CLK1, CLK2 l l 0.45 0.45 V V l VIH VIL CLK High Level Input Voltage (Note 5) CLK Low Level Input Voltage (Note 5) (Note 4) IOZ Three-State Output Leakage SHDN = 0 ZIN CLK Input Resistance Pushbutton Mode, CLK1/CLK2 fCLK Clock Frequency Pulse Mode, VCC = 3.3V Pulse Mode, VCC = 2.7V l l tCKHI Clock High Time Pulse Mode, VCC = 3.3V Pulse Mode, VCC = 2.7V l l 450 600 ns ns tCKLO Clock Low Time Pulse Mode, VCC = 3.3V Pulse Mode, VCC = 2.7V l l 450 600 ns ns tPW Pulse Width Pushbutton Mode l 670 µs tDEB Debounce Time Pushbutton Mode l 10.7 tDELAY Repeat Rate Delay Pushbutton Mode l 340 fREPEAT Repeat Frequency Pushbutton Mode l 11.7 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground, unless otherwise specified. All typicals are given for VCC = VREF = 5V, TA = 25°C and PWM1/ PWM2 output to GND, CPWM = 10pF. ±5 2.5 1 750 12.8 µA MΩ MHz kHz 21.3 ms 410 680 ms 19.5 23.4 Hz Note 3: Shutdown current can be negative due to leakage currents if VCC > VREF or VREF > VCC. Note 4: Guaranteed by Design. Decouple the VCC and VREF pins to GND using high quality, low ESR, low ESL 0.1µF capacitors to eliminate PWM switching noise that may otherwise get coupled into the CLK1/CLK2 high impedance input buffers. The decoupling capacitors should be located in close proximity to these pins and the ground line to have maximum effect. Note 5: Input thresholds apply for both pushbutton and pulse modes. Rev A For more information www.analog.com 3 LTC1426 TYPICAL PERFORMANCE CHARACTERISTICS 0.05 0.05 0.03 0.03 0.02 0.02 1000 0.01 0 – 0.01 OUTPUT PULL-DOWN VOLTAGE (mV) VCC = VREF = 5V 0.04 TA = 25°C ERROR (LSB) 0.01 0 – 0.01 – 0.02 – 0.02 – 0.03 – 0.03 – 0.04 – 0.04 0 8 16 24 32 40 CODE 48 56 64 – 0.05 0 8 16 24 32 40 CODE 48 1426 G01 SUPPLY CURRENT (µA) CLOCK HIGH TIME (ns) VCC = 5V 100 0 – 40 10 35 TEMPERATURE (°C) 60 1 85 1 10 100 OUTPUT CURRENT SINK CAPABILITY (mA) 1426 G03 Supply Current vs Temperature PUSHBUTTON MODE 32.5 PULSE MODE 30.5 28.5 26.5 22.5 TA = 25°C CLK1 AND CLK2 TIED TOGETHER 0 1 3 4 2 LOGIC INPUT VOLTAGE (V) 1426 G04 VCC = 5V 50 34.5 24.5 – 15 – 40°C 10 60 36.5 500 200 25°C 0.1 0.1 64 38.5 600 300 85°C 100 Supply Current vs Logic Input Voltage VCC = 3V VCC = 5V 1426 G02 Minimum Clock High Time vs Temperature 400 56 SUPPLY CURRENT (µA) DNL ERROR (LSB) VCC = VREF = 5V 0.04 TA = 25°C – 0.05 Output Pull-Down Voltage vs Output Current Sink Capability Integral Nonlinearity (INL) Differential Nonlinearity (DNL) PUSHBUTTON MODE 40 30 PULSE MODE 20 10 5 1426 F05 0 – 40 – 15 10 35 TEMPERATURE (°C) 60 85 1426 G06 PIN FUNCTIONS CLK1 (Pin 1): Channel 1 Clock/Pushbutton Input. CLK2 (Pin 2): Channel 2 Clock/Pushbutton Input. GND (Pin 3): Ground. It is recommended that GND be tied to a ground plane. PWM1 (Pin 4): Channel 1 PWM Output. PWM2 (Pin 5): Channel 2 PWM Output. VREF (Pin 6): Voltage Reference Input. VREF powers the DAC output buffers and can be used to control the output span. Bypass VREF to GND with an external capacitor to minimize output errors. VREF can be tied to VCC if desired. VCC (Pin 7): Voltage Supply. This supply must be kept free from noise and ripple by bypassing directly to the ground plane. SHDN (Pin 8): Shutdown. A logic low puts the chip into shutdown mode with the PWM outputs in high impedance. The digital settings for the DACs are retained in shutdown. Rev A 4 For more information www.analog.com LTC1426 TIMING DIAGRAMS Pulse Mode Timing tCKL0 Pushbutton Mode Timing tPW tCKHI CLK1 CLK2 CLK1 CLK2 1426 TC02 1426 TC01 BLOCK DIAGRAM LATCH AND LOGIC CLK1 CLK2 INPUT CONDITIONING MODE SELECT 0 = PUSHBUTTON MODE 1 = PULSE MODE CONTROL LOGIC DEBOUNCE CIRCUIT SHDN POWER-ON RESET VREF 6-BIT UP/DOWN COUNTER 6 6-BIT UP/DOWN COUNTER 6 6-BIT UP COUNTER 6 COMPARATOR DRIVER PWM1 DRIVER PWM2 COMPARATOR OSCILLATOR 1426 F01 Figure 1. LTC1426 Block Diagram DEFINITIONS LSB: The least significant bit or the ideal duty cycle difference between two successive codes. LSB = DCMAX/64 DCMAX = The DAC output maximum duty cycle Resolution: The resolution is the number of DAC output states (64) that divide the full-scale output duty cycle range. The resolution does not necessarily imply linearity. INL: End point integral nonlinearity is the maximum deviation from a straight line passing through the end points of the DAC transfer curve. The INL error at a given code is calculated as follows: INL = (DCOUT – DCIDEAL)/LSB DCIDEAL = (Code)(LSB) DCOUT = the DAC output duty cycle measured at the given number of clocked in pulses. DNL: Differential nonlinearity is the difference between the measured duty cycle change and the ideal 1LSB duty cycle change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (∆DCOUT – LSB)/LSB ∆DCOUT = The measured duty cycle difference between two adjacent codes. Full-Scale Error: Full-scale error is the difference between the ideal and measured DAC output duty cycles with all bits set to one (Code = 63). The full-scale error is calculated as follows: FSE = (DCOUT – DCIDEAL)/LSB DCIDEAL = DCMAX For more information www.analog.com Rev A 5 LTC1426 APPLICATIONS INFORMATION Dual 6-Bit PWM DAC Digital Interface Figure 1 shows a block diagram of the LTC1426. Each 6-bit PWM DAC is guaranteed monotonic and is digitally adjustable in 64 equal steps, which corresponds from 0% to 98.5% duty cycle full scale. At power-up, the counters reset to 100000B and both DAC outputs assume midscale duty cycle. The PWM outputs have an output impedance of less than 100Ω. The DAC outputs swing from 0V to the reference voltage, VREF, which can be biased from 0V to 5.5V. The frequency of the DAC outputs is above 3kHz, easing output filtering. The LTC1426 can be controlled by using one of two interface modes: pulse mode and pushbutton mode. The operating interface mode is determined during powerup. If both CLK1 and CLK2 inputs are floating on powerup, then an interface mode detect circuit configures the chip in pushbutton mode until the next VCC reset (Figure 3). However, if either of CLK1 or CLK2 is at logic 0 or 1 at power-up, then the chip configures in pulse mode until the next VCC reset. In the case of a pure resistive load, the voltage measured across load RL is given by: V = (VPWM)RL/(RL + ROUT) where VPWM is the no load DAC output voltage, RL is the resistive load and ROUT is the DAC output impedance. Therefore, the resistive load RL should be sufficiently large to ignore the effect of output impedance on the load voltage. Figure 2 shows a typical lowpass filter recommended to filter the PWM outputs. Without filtering, results obtained from unfiltered outputs can be erroneous when taking measurements from a voltmeter. The ratio of the filter time constant, t, to the PWM frequency determines the amount of output ripple frequency that feeds into the system. In addition, the loading of the output also determines an additional error voltage drop across R1. INPUT R1 10k C1 0.1µF Figure 3 shows the simplified logic for determining the interface mode at power-up. A set of pull-up/pull-down resistors allow the LTC1426 to sense the state of the CLK pins at power-up. If both CLK1 and CLK2 pins are floating on power-up then the control signal from the LTC1426 leaves these resistors in place, allowing the LTC1426 to detect three operating states at each CLK pin: high, low and “middle” (floating). If the CLK pins are tied to either logic 0 or 1 at power-up, then the control signal will disconnect these resistors, making CLK1 and CLK2 CMOS compatible input pins. Note that both CLK pins will always be in the same mode. If one pin is floating and the other is at logic high/low on power-up, the LTC1426 will assume pulse mode. VCC INTERNAL LOGIC CLK1 INPUT CLK2 INPUT CONTROL CLK1 CLK2 OUTPUT 1426 F02 LTC1426 Figure 2. Lowpass Filter for PWM Averaging 1426 F03 Figure 3. Interface Mode Detect Circuit Rev A 6 For more information www.analog.com LTC1426 TYPICAL APPLICATIONS Typical applications for this part include digital calibration, industrial process control, automatic test equipment, cellular telephones and portable battery-powered applications. Figures 4 and 5 show how easy this part is to use. In all applications, the PWM full-scale output voltage is set by VREF. This makes interfacing convenient when a variety of reference spans are needed. Pulse Mode Figure 4 shows the LTC1426 in a pulse mode, standalone application. The LTC1426 can interface directly with minimum external components to most popular microprocessors (MPUs). The Intel 8051 was chosen to demonstrate direct interface for the LTC1426, as this microprocessor has “quasi-bidirectional” ports that eliminate additional pull-up resistors to VCC. However, external pull-up resistors should be used if the microprocessor doesn’t pull the port pins high during reset. In pulse mode, each clock pulse applied to the CLK1 or CLK2 input increments the respective counter by one count. When the counter increases beyond full scale (111111B), the counter rolls over and becomes zero scale (000000B). In this way, a single pulse applied to the CLK1 or CLK2 input increases the respective counter by one count, and 63 pulses decrease that counter by one count. Pushbutton Mode Figure 5 shows how to use the LTC1426 in a typical pushbutton application. In pushbutton mode, a logic 1 pulse applied to the CLK1 or CLK2 input increments the respective counter by one count, and stops incrementing when the counter reaches full scale (111111B). A logic 0 pulse applied to the CLK1 or CLK2 input decrements the respective counter by one count, and stops decrementing when the counter reaches zero scale (000000B). An onchip debouncing circuit has a debounce time of 12.8ms to prevent unintended counts with bouncing pushbuttons. After a time delay of 410ms, the counter will begin to increment/decrement at a repeat rate of 19.5Hz if the pushbutton remains pressed. Care should be taken to avoid running the CLK and PWM traces close to one another. Since the CLK pins are high impedance input nodes in pushbutton mode, current spikes caused by the switching of the PWM outputs feedthrough via any stray capacitance between PWM and CLK lines if not properly routed. Use of proper grounding techniques and spacing of these lines are highly recommended for optimal performance. VCC 2.7V TO 5.5V R VCC 2.7V TO 5.5V MPU (e.g. 8051) 1 2 P1.1 3 PWM1 4 CLK1 SHDN CLK2 VCC GND VREF PWM1 PWM2 R UP LTC1426 1 UP 2 3 0.1µF LTC1426 P1.0 VCC 2.7V TO 5.5V 8 7 DOWN SHDN 6 VREF 0V TO 5.5V 5 PWM2 PWM1/PWM2: 0V TO 0.985(VREF) 1426 F04 DOWN PWM1 4 CLK1 SHDN CLK2 VCC GND VREF PWM1 PWM2 0.1µF 8 7 SHDN 6 VREF 0V TO 5.5V 5 PWM2 PWM1/PWM2: 0V TO 0.985(VREF) 1426 F05 LIMITING RESISTOR R PREVENTS SHORTING OF VCC AND GND WHEN BOTH BUTTONS ARE SIMULTANEOUSLY PUSHED. THIS RESISTOR CAN BE PLACED EITHER IN THE VCC OR GND LEG AND THIS DETERMINES THE FUNCTION WHEN BOTH BUTTONS ARE PUSHED. VALUE OF R < 50k Figure 4. Stand-Alone Pulse Mode Interface Figure 5. Pushbutton Mode Interface Rev A For more information www.analog.com 7 LTC1426 TYPICAL APPLICATIONS Shutdown Mode Figure 6 shows a dual digitally programmable current source using the LT ®1013 dual precision op amp and two NPN transistors (2N3904). After the lowpass filter combination of R1, C1 (R2, C2), its output swings from 0V to 4.93V. In the configuration shown, this voltage will be forced across the resistor RA1 (RA2). If RA1 (RA2) is chosen to be 493Ω, the output current will range from 0mA at zero scale to 10mA at full scale. The minimum voltage for VS is determined by the load resistor RL1 (RL2) and Q1(Q2)’s VCESAT voltage. With a load resistor of 50Ω, the voltage source can be as low as 5V. SHDN MPU (e.g. 8051) P1.0 P1.1 5V Upon the application of a logic low shutdown signal, the entire IC converts to micropower shutdown mode where VCC supply current reduces to less than 0.3µA typical. The shutdown function features the data retention of the current PWM1 and PWM2 codes so that upon release from a shutdown condition, these states are reinstated. This is a functional difference in comparison to the half-scale preset for both PWM1 and PWM2 outputs upon power-up. VS RL1 0.1µF LTC1426 1 2 3 4 CLK1 SHDN CLK2 VCC GND VREF PWM1 PWM2 0.1µF 2N3904 8 7 6 5 1 2 3 C1 0.1µF R2 10k 4 OUT A V+ –IN A OUT B +IN A – IN B V– + IN B C2 0.1µF RL2 2N3904 LT1013 RA1 493Ω R1 10k VS 10V 8 7 RA2 493Ω 6 5 1426 F06 IOUT1/IOUT2: 0mA TO 10mA RL1/RL2: < 50Ω VS: 5V TO 30V Figure 6. Dual Digitally Programmable Current Source Rev A 8 For more information www.analog.com LTC1426 PACKAGE DESCRIPTION MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev G) 0.889 ±0.127 (.035 ±.005) 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 3.00 ±0.102 (.118 ±.004) (NOTE 3) 0.65 (.0256) BSC 0.42 ± 0.038 (.0165 ±.0015) TYP 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) DETAIL “A” 0° – 6° TYP GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 1 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.1016 ±0.0508 (.004 ±.002) MSOP (MS8) 0213 REV G NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX OBSOLETE PACKAGE Rev A For more information www.analog.com 9 LTC1426 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610 Rev G) .050 BSC .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 8 .245 MIN .160 ±.005 .010 – .020 × 45° (0.254 – 0.508) NOTE: 1. DIMENSIONS IN 5 .150 – .157 (3.810 – 3.988) NOTE 3 1 RECOMMENDED SOLDER PAD LAYOUT .053 – .069 (1.346 – 1.752) 0°– 8° TYP .016 – .050 (0.406 – 1.270) 6 .228 – .244 (5.791 – 6.197) .030 ±.005 TYP .008 – .010 (0.203 – 0.254) 7 .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE 2 3 4 .004 – .010 (0.101 – 0.254) .050 (1.270) BSC SO8 REV G 0212 Rev A 10 For more information www.analog.com LTC1426 REVISION HISTORY REV DATE DESCRIPTION A 06/18 Obsoleted MS8 package option PAGE NUMBER 2, 9 Rev A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 11 LTC1426 RELATED PARTS PART NUMBER DESCRIPTION LT1182/LT1183 CCFL/LCD Contrast Switching Regulators 3V to 30V Single Supply in 16-Pin SO LTC1257 Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V. Reference Can Be Overdriven Up to 12V, i.e., FS Max = 12V 5V to 15V Single Supply, Complete VOUT DAC in SO-8 LTC1329/ LTC1329-10/ LTC1329-50 Micropower IOUT 8-Bit Current DAC 2.7V to 6.5V Single Supply in SO-8 LTC1446/ LTC1446L Dual, Serial I/O VOUT 12-Bit DAC in SO-8 Rail-to-Rail VOUT, 5V/3V Single Supply LTC1451/LTC1452/ Complete Serial I/O VOUT 12-Bit DACs LTC1453 COMMENTS Rail-to-Rail VOUT, 3V/5V Single Supply in S0-8 LTC1590 Dual, Serial I/O Multiplying IOUT 12-Bit DAC 5V Single Supply in 16-Pin SO Package LTC8043 Serial I/O Mulitplying IOUT 12-Bit DAC 5V Single Supply in SO-8 Rev A 12 D16986-0-6/18(A) www.analog.com  ANALOG DEVICES, INC. 1997-2018