LTC1596-1CISW#TRPBF

LTC1595/LTC1596/LTC1596-1 Serial 16-Bit Multiplying DACs FEATURES DESCRIPTION SO-8 Package (LTC1595) nn DNL and INL: 1LSB Max nn Low Glitch Impulse: 1nV-s Typ nn Fast Settling to 1LSB: 2µs (with LT1468) nn Pin Compatible with Industry Standard 12-Bit DACs: DAC8043 and DAC8143/AD7543 nn 4-Quadrant Multiplication nn Low Supply Current: 10µA Max nn Power-On Reset nn LTC1595/LTC1596: Resets to Zero-Scale nn LTC1596-1: Resets to Mid-Scale nn 3-Wire SPI and MICROWIRE Compatible Serial Interface nn Daisy-Chain Serial Output (LTC1596) nn Asynchronous Clear Input nn LTC1596: Clears to Zero-Scale nn LTC1596-1: Clears to Mid-Scale The LTC®1595/LTC1596/LTC1596-1 are serial input, 16‑bit multiplying current output DACs. The LTC1595 is pin and hardware compatible with the 12-bit DAC8043 and comes in 8-pin PDIP and SO packages. The LTC1596 is pin and hardware compatible with the 12-bit DAC8143/AD7543 and comes in the 16-pin SO wide package. nn Both are specified over the industrial temperature range. Sensitivity of INL to op amp VOS is reduced by five times compared to the industry standard 12-bit DACs, so most systems can be easily upgraded to true 16-bit resolution and linearity without requiring more precise op amps. These DACs include an internal deglitching circuit that reduces the glitch impulse by more than ten times to less than 1nV-s typ. The DACs have a clear input and a power-on reset. The LTC1595 and LTC1596 reset to zero-scale. The LTC1596‑1 is a version of the LTC1596 that resets to mid-scale. APPLICATIONS L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Process Control and Industrial Automation Software Controlled Gain Adjustment nn Digitally Controlled Filter and Power Supplies nn Automatic Test Equipment nn nn TYPICAL APPLICATION SO-8 Multiplying 16-Bit DAC Has Easy 3-Wire Serial Interface VIN DATA LOAD 0.8 5V 7 6 5 8 1 VDD VREF CLK SRI 2 RFB LTC1595 LD 33pF OUT1 3 – LT ®1468 GND 4 + VOUT 1595/96 TA01 INTEGRAL NONLINEARITY (LSB) CLOCK Integral Nonlinearity 1.0 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 – 0.8 –1.0 0 49152 16384 32768 DIGITAL INPUT CODE 65535 1595/96 TA02 159561fc For more information www.linear.com/LTC1595 1 LTC1595/LTC1596/LTC1596-1 ABSOLUTE MAXIMUM RATINGS (Note 1) VDD to AGND................................................ –0.5V to 7V VDD to DGND............................................... –0.5V to 7V AGND to DGND ............................................ VDD + 0.5V DGND to AGND .............................................VDD + 0.5V VREF to AGND, DGND...............................................±25V RFB to AGND, DGND.................................................±25V Digital Inputs to DGND ................ –0.5V to (VDD + 0.5V) VOUT1, VOUT2 to AGND.................. –0.5V to (VDD + 0.5V) Maximum Junction Temperature........................... 150°C Operating Temperature Range LTC1595C/LTC1596C/LTC1596-1C........... 0°C to 70°C LTC1595I/LTC1596I/LTC1596-1I.......... –40°C to 85°C Storage Temperature Range.................. –65°C to 150°C Lead Temperature (Soldering, 10 sec)................... 300°C PIN CONFIGURATION TOP VIEW TOP VIEW 1 16 RFB OUT2 2 15 VREF VREF 1 8 VDD AGND 3 14 VDD RFB 2 7 CLK STB1 4 13 CLR OUT1 3 6 SRI LD1 5 12 DGND GND 4 5 LD SRO 6 11 STB4 SRI 7 10 STB3 STB2 8 9 N8 PACKAGE S8 PACKAGE 8-LEAD PDIP 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 130°C/W (N) TJMAX = 150°C, θJA = 190°C/W (S) 2 OUT1 LD2 SW PACKAGE 16-LEAD PLASTIC SO WIDE TJMAX = 150°C, θJA = 100°C/W (N) TJMAX = 150°C, θJA = 130°C/W (SW) 159561fc For more information www.linear.com/LTC1595 LTC1595/LTC1596/LTC1596-1 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1595ACN8#PBF LTC1595ACN8#TRPBF LTC1595ACN8 8-Lead PDIP 0°C to 70°C LTC1595ACS8#PBF LTC1595ACS8#TRPBF 1595A 8-Lead Plastic SO 0°C to 70°C LTC1595BCN8#PBF LTC1595BCN8#TRPBF LTC1595BCN8 8-Lead PDIP 0°C to 70°C LTC1595BCS8#PBF LTC1595BCS8#TRPBF 1595B 8-Lead Plastic SO 0°C to 70°C LTC1595CCN8#PBF LTC1595CCN8#TRPBF LTC1595CCN8 8-Lead PDIP 0°C to 70°C LTC1595CCS8#PBF LTC1595CCS8#TRPBF 1595C 8-Lead Plastic SO 0°C to 70°C LTC1595AIN8#PBF LTC1595AIN8#TRPBF LTC1595AIN8 8-Lead PDIP –40°C to 85°C LTC1595AIS8#PBF LTC1595AIS8#TRPBF 1595AI 8-Lead Plastic SO –40°C to 85°C LTC1595BIN8#PBF LTC1595BIN8#TRPBF LTC1595BIN8 8-Lead PDIP –40°C to 85°C LTC1595BIS8#PBF LTC1595BIS8#TRPBF 1595BI 8-Lead Plastic SO –40°C to 85°C LTC1595CIN8#PBF LTC1595CIN8#TRPBF LTC1595CIN8 8-Lead PDIP –40°C to 85°C LTC1595CIS8#PBF LTC1595CIS8#TRPBF 1595CI 8-Lead Plastic SO –40°C to 85°C LTC1596ACSW#PBF LTC1596ACSW#TRPBF LTC1596ACSW 16-Lead Plastic SO Wide 0°C to 70°C LTC1596BCSW#PBF LTC1596BCSW#TRPBF LTC1596BCSW 16-Lead Plastic SO Wide 0°C to 70°C LTC1596CCSW#PBF LTC1596CCSW#TRPBF LTC1596CCSW 16-Lead Plastic SO Wide 0°C to 70°C LTC1596AISW#PBF LTC1596AISW#TRPBF LTC1596AISW 16-Lead Plastic SO Wide –40°C to 85°C LTC1596BISW#PBF LTC1596BISW#TRPBF LTC1596BISW 16-Lead Plastic SO Wide –40°C to 85°C LTC1596CISW#PBF LTC1596CISW#TRPBF LTC1596CISW 16-Lead Plastic SO Wide –40°C to 85°C LTC1596-1ACSW#PBF LTC1596-1ACSW#TRPBF LTC1596-1ACSW 16-Lead Plastic SO Wide 0°C to 70°C LTC1596-1BCSW#PBF LTC1596-1BCSW#TRPBF LTC1596-1BCSW 16-Lead Plastic SO Wide 0°C to 70°C LTC1596-1CCSW#PBF LTC1596-1CCSW#TRPBF LTC1596-1CCSW 16-Lead Plastic SO Wide 0°C to 70°C LTC1596-1AISW#PBF LTC1596-1AISW#TRPBF LTC1596-1AISW 16-Lead Plastic SO Wide –40°C to 85°C LTC1596-1BISW#PBF LTC1596-1BISW#TRPBF LTC1596-1BISW 16-Lead Plastic SO Wide –40°C to 85°C LTC1596-1CISW#PBF LTC1596-1CISW#TRPBF LTC1596-1CISW 16-Lead Plastic SO Wide –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 159561fc For more information www.linear.com/LTC1595 3 LTC1595/LTC1596/LTC1596-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS LTC1595A/96A/96-1A LTC1595B/96B/96-1B LTC1595C/96C/96-1C MIN MIN MIN TYP MAX TYP MAX TYP MAX UNITS Accuracy Resolution Monotonicity INL Integral Nonlinearity (Note 2) TA = 25°C TMIN to TMAX DNL Differential Nonlinearity TA = 25°C TMIN to TMAX Gain Error (Note 3) TA = 25°C TMIN to TMAX GE l 16 l 16 16 16 16 Bits 15 Bits l ±0.25 ±0.35 ±1 ±1 ±2 ±2 ±4 ±4 LSB LSB l ±0.2 ±0.2 ±1 ±1 ±1 ±1 ±2 ±2 LSB LSB l 2 3 ±16 ±16 ±16 ±32 ±32 ±32 LSB LSB MAX UNITS 2 ppm/°C VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted. SYMBOL ILEAKAGE PARAMETER CONDITIONS Gain Temperature Coefficient (Note 4) ∆Gain/∆Temperature OUT1 Leakage Current (Note 5) TA = 25°C TMIN to TMAX Zero-Scale Error PSRR Power Supply Rejection TA = 25°C TMIN to TMAX MIN TYP 1 l l ±3 ±15 nA nA l ±0.2 ±1 LSB LSB VDD = 5V ±10% l (Note 6) l ±1 ±2 LSB/V 7 10 kΩ Reference Input RREF VREF Input Resistance 5 AC Performance THD Output Current Settling Time (Notes 7, 8) 1 µs Mid-Scale Glitch Impulse Using LT1122 Op Amp, CFEEDBACK = 33pF 1 nV-s Digital-to-Analog Glitch Impulse Full-Scale Transition, VREF = 0V, Using LT1122 Op Amp, CFEEDBACK = 33pF 2 nV-s Multiplying Feedthrough Error VREF = ±10V, 10kHz Sine Wave 1 mVP-P Total Harmonic Distortion (Note 9) 108 dB Equivalent DAC Thermal Noise Voltage Density (Note 10) f = 1kHz 11 nV/√Hz Analog Outputs (Note 4) COUT Output Capacitance (Note 4) DAC Register Loaded to All 1s, COUT1 l 115 130 pF DAC Register Loaded to All 0s, COUT1 l 70 80 pF Digital Inputs VIH Digital Input High Voltage l VIL Digital Input Low Voltage l IIN Digital Input Current l CIN Digital Input Capacitance (Note 4) VIN = 0V l 2.4 V 0.001 0.8 V ±1 µA 8 pF Digital Outputs: SRO (LTC1596/LTC1596-1) VOH Digital Output High Voltage IOH = 200µA l VOL Digital Output Low Voltage IOL = 1.6mA l 4 4 V 0.4 V 159561fc For more information www.linear.com/LTC1595 LTC1595/LTC1596/LTC1596-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V ±10%, VREF = 10V, VOUT1 = GND = 0V, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Timing Characteristics (LTC1595) tDS Serial Input to CLK Setup Time l 30 5 ns tDH Serial Input to CLK Hold Time l 30 5 ns tSRI Serial Input Data Pulse Width l 60 ns tCH Clock Pulse Width High l 60 ns tCL Clock Pulse Width Low l 60 ns tLD Load Pulse Width l 60 ns tASB LSB Clocked into Input Register to DAC Register Load Time l 0 ns VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Timing Characteristics (LTC1596/LTC1596-1) STB1 Used as the Strobe l 30 5 ns tDS2 STB2 Used as the Strobe l 20 –5 ns tDS3 STB3 Used as the Strobe l 25 0 ns tDS4 STB4 Used as the Strobe l 20 –5 ns STB1 Used as the Strobe l 30 5 ns tDH2 STB2 Used as the Strobe l 40 15 ns tDH3 STB3 Used as the Strobe l 35 10 ns tDH4 STB4 Used as the Strobe l 40 15 ns tDS1 tDH1 Serial Input to Strobe Setup Time Serial Input to Strobe Hold Time tSRI Serial Input Data Pulse Width l 60 ns tSTB1 to tSTB4 Strobe Pulse Width (Note 11) l 60 ns tSTB1 to tSTB4 Strobe Pulse Width (Note 12) l 60 ns tLD1, tLD2 LD Pulse Width l 60 ns tASB LSB Strobed Into Input Register to Load DAC Register Time l 0 ns tCLR Clear Pulse Width l 100 ns tPD1 STB1 to SRO Propagation Delay CL = 50pF l 30 150 ns tPD STB2, STB3, STB4 to SRO Propagation Delay CL = 50pF l 30 200 ns l 4.5 Power Supply VDD Supply Voltage IDD Supply Current Digital Inputs = 0V or VDD Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: ±1LSB = ±0.0015% of full-scale = ±15.3ppm of full-scale. Note 3: Using internal feedback resistor. Note 4: Guaranteed by design, not subject to test. Note 5: IOUT1 with DAC register loaded with all 0s. Note 6: Typical temperature coefficient is 100ppm/°C. Note 7: OUT1 load = 100Ω in parallel with 13pF. l 5 5.5 V 1.5 10 µA Note 8: To 0.0015% for a full-scale change, measured from the falling edge of LD1, LD2 or LD. Note 9: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s; op amp = LT1007. Note 10: Calculation from en = √4kTRB where: k = Boltzmann constant (J/°K); R = resistance (Ω); T = temperature (°K); B = bandwidth (Hz). Note 11: Minimum high time for STB1, STB2, STB4. Minimum low time for STB3. Note 12: Minimum low time for STB1, STB2, STB4. Minimum high time for STB3. 159561fc For more information www.linear.com/LTC1595 5 LTC1595/LTC1596/LTC1596-1 TYPICAL PERFORMANCE CHARACTERISTICS Mid-Scale Glitch Impulse 0 LD FALLING EDGE –10 Differential Nonlinearity (INL) 1.0 0.8 0.8 DIFFERENTIAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY (LSB) 1nV-s TYP USING LT1122 OP AMP CFEEDBACK = 33pF VREF = 10V +10 OUTPUT VOLTAGE (mV) Integral Nonlinearity (INL) 1.0 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 0 1 2 TIME (s) 3 –1.0 4 16384 49152 32768 DIGITAL INPUT CODE 0 1595/96 G01 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 65535 1.0 DIFFERENTIAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY (LSB) 1595/96 G04 0.5 0 –10 – 8 – 6 – 4 – 2 0 2 4 6 REFERENCE VOLTAGE (V) 8 0.5 0 –10 – 8 – 6 – 4 – 2 0 2 4 6 REFERENCE VOLTAGE (V) 10 – 40 – 60 – 80 –100 –120 100 ALL BITS ON ALL BITS OFF 1k USING LT1122 OP AMP CFEEDBACK = 33pF 100k 10k FREQUENCY (Hz) 1M 10M 1595/96 G07 6 2 1.0 VREF = 10V 1 VREF = 2.5V 0 10 Differential Nonlinearity vs Supply Voltage DIFFERENTIAL NONLINEARITY (LSB) ATTENUATION (dB) –20 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Integral Nonlinearity vs Supply Voltage INTEGRAL NONLINEARITY (LSB) 0 8 1595/96 G06 1595/96 G05 Multiplying Mode Frequency Response vs Digital Code 65535 Differential Nonlinearity vs Reference Voltage 1.0 GATED SETTLING WAVEFORM 500µV/DIV 49152 32768 16384 DIGITAL INPUT CODE 1595/96 G03 Integral Nonlinearity vs Reference Voltage DAC OUTPUT 5V/DIV 0 1595/96 G02 Full-Scale Settling Waveform 1µs/DIV USING LT1122 OP AMP CFEEDBACK = 33pF 0.6 0.4 2 3 4 8 6 5 7 SUPPLY VOLTAGE (V) 9 10 1595/96 G08 0.5 0 2 3 4 8 6 5 7 SUPPLY VOLTAGE (V) 9 10 1595/96 G09 159561fc For more information www.linear.com/LTC1595 LTC1595/LTC1596/LTC1596-1 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Logic Input Voltage 1.0 Logic Threshold vs Supply Voltage 3.0 VDD = 5V 0.9 2.5 LOGIC THRESHOLD (V) SUPPLY CURRENT (mA) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 2.0 1.5 1.0 0.5 0.1 0 0 1 3 2 INPUT VOLTAGE (V) 4 5 0 0 1 2 3 4 5 6 7 8 SUPPLY VOLTAGE (V) 9 10 1595/96 G11 1595/96 G10 PIN FUNCTIONS LTC1595 VREF (Pin 1): Reference Input. RFB (Pin 2): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp. OUT1 (Pin 3): Current Output Pin. Tie to inverting input of current to voltage converter op amp. GND (Pin 4): Ground Pin. LD (Pin 5): The Serial Interface Load Control Input. When LD is pulled low, data is loaded from the shift register into the DAC register, updating the DAC output. SRI (Pin 6): The Serial Data Input. Data on the SRI pin is latched into the shift register on the rising edge of the serial clock. Data is loaded MSB first. CLK (Pin 7): The Serial Interface Clock Input. VDD (Pin 8): The Positive Supply Input. 4.5V ≤ VDD ≤ 5.5V. Requires a bypass capacitor to ground. LTC1596/LTC1596-1 OUT1 (Pin 1): True Current Output Pin. Tie to inverting input of current to voltage converter op amp. OUT2 (Pin 2): Complement Current Output Pin. Tie to analog ground. AGND (Pin 3): Analog Ground Pin. STB1, STB2, STB3, STB4 (Pins 4, 8, 10, 11): Serial Interface Clock Inputs. STB1, STB2 and STB4 are rising edge triggered inputs. STB3 is a falling edge triggered input (see Truth Tables). LD1, LD2 (Pins 5, 9): Serial Interface Load Control Inputs. When LD1 and LD2 are pulled low, data is loaded from the shift register into the DAC register, updating the DAC output (see Truth Tables). SRO (Pin 6): The Output of the Shift Register. Becomes valid on the active edge of the serial clock. SRI (Pin 7): The Serial Data Input. Data on the SRI pin is latched into the shift register on the active edge of the serial clock. Data is loaded MSB first. DGND (Pin 12): Digital Ground Pin. CLR (Pin 13): The Clear Pin for the DAC. Clears DAC to zero-scale when pulled low on LTC1596. Clears DAC to mid-scale when pulled low on LTC1596-1. This pin should be tied to VDD for normal operation. VDD (Pin 14): The Positive Supply Input. 4.5V ≤ VDD ≤ 5.5V. Requires a bypass capacitor to ground. VREF (Pin 15): Reference Input. RFB (Pin 16): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp. 159561fc For more information www.linear.com/LTC1595 7 LTC1595/LTC1596/LTC1596-1 TRUTH TABLES Table 2. LTC1596/LTC1596-1 DAC Register Table 1. LTC1596/LTC1596-1 Input Register CONTROL INPUTS CONTROL INPUTS STB1 STB2 STB3 STB4 INPUT REGISTER AND SRO OPERATION 0 0 0 0 0 1 X X X 0 X 1 X X 1 0 1 0 0 1 X X 0 X X X X 1 Serial Data Bit on SRI Loaded Into Input Register, MSB First Data Bit or SRI Appears on SRO Pin After 16 Clocked Bits No Input Register Operation No SRO Operation BLOCK DIAGRAM VREF CLR LD1 LD2 DAC Register Operation 0 X X Reset DAC Register and Input Register to All 0s (LTC1596) or to Mid-Scale (LTC1596-1) (Asynchronous Operation) 1 1 X No DAC Register Operation 1 X 1 1 0 0 Load DAC Register with the Contents of Input Register (LTC1595) 56k 1 56k 56k 56k 56k 56k 56k 56k 56k 112k 112k 2 RFB 112k 112k 7k 3 OUT1 4 GND VDD 8 DECODER LOAD LD 5 D15 (MSB) CLK 7 D14 D13 D12 D11 • • • DAC REGISTER INPUT 16-BIT SHIFT REGISTER CLK D0 (LSB) IN 6 SRI 1595 BD TIMING DIAGRAM (LTC1595) tDH tDS tCL tCH CLK INPUT tSRI SRI PREVIOUS WORD D15 MSB D14 D1 D0 LSB tASB LD tLD 1595 TD 8 159561fc For more information www.linear.com/LTC1595 LTC1595/LTC1596/LTC1596-1 BLOCK DIAGRAM (LTC1596/LTC1596-1) 56k VREF 15 56k 56k 56k 56k 56k 56k 56k 56k 112k 16 RFB 112k 112k 112k 7k 1 OUT1 2 OUT2 VDD 14 3 AGND DECODER CLR 13 CLR LD1 5 LOAD LD2 9 D14 D15 (MSB) D12 D13 D11 • • • DAC REGISTER D0 (LSB) CLR STB1 4 IN INPUT 16-BIT SHIFT REGISTER CLK STB2 8 7 SRI OUT STB3 10 1596 BD STB4 11 6 SRO DGND 12 TIMING DIAGRAM (LTC1596/LTC1596-1) t DS1 t DS2 t DS3 t DS4 t DH1 t DH2 t DH3 t DH4 STROBE INPUT STB1, STB2, STB4 (INVERT FOR STB3) D15 MSB SRI D14 t STB1 t STB2 t STB3 t STB4 t STB1 t STB2 t STB3 t STB4 D13 D0 LSB D1 t SRI t ASB t LD1 t LD2 LD1, LD2 t PD t PD1 SRO D15 (MSB) PREVIOUS WORD D14 PREVIOUS WORD D13 PREVIOUS WORD D0 (LSB) PREVIOUS WORD D15 (MSB) CURRENT WORD 1596 TD 159561fc For more information www.linear.com/LTC1595 9 LTC1595/LTC1596/LTC1596-1 APPLICATIONS INFORMATION Description The 16-pin LTC1596 can operate in identical fashion to the LTC1595 but offers additional pins for flexibility. Four clock pins are available STB1, STB2, STB3 and STB4. STB1, STB2 and STB4 operate like the CLK pin of the LTC1595, capturing data on their rising edges. STB3 captures data on its falling edge (see Truth Table 1). The LTC1595/LTC1596 are 16-bit multiplying DACs which have serial inputs and current outputs. They use precision R/2R technology to provide exceptional linearity and stability. The devices operate from a single 5V supply and provide ±10V reference input and voltage output ranges when used with an external op amp. These devices have a proprietary deglitcher that reduces glitch impulse to 1nV-s over a 0V to 10V output range. The LTC1596 has two load pins, LD1 and LD2. To load data, both pins must be taken low. If one of the pins is grounded, the other pin will operate identically to LTC1595’s LD pin. An asynchronous clear input (CLR) resets the LTC1596 to zero-scale (and the LTC1596-1 to mid-scale) when pulled low (see Truth Table 2). Serial I/O The LTC1595/LTC1596 have SPI/MICROWIRE compatible serial ports that accept 16-bit serial words. Data is accepted MSB first and loaded with a load pin. The LTC1596 also has a data output pin SRO that can be connected to the SRI input of another DAC to daisy chain multiple DACs on one 3-wire interface (see LTC1596 Timing Diagram). The 8-pin LTC1595 has a 3-wire interface. Data is shifted into the SRI data input on the rising edge of the CLK pin. At the end of the data transfer, data is loaded into the DAC register by pulling the LD pin low (see LTC1595 Timing Diagram). VREF –10V TO 10V Unipolar (2-Quadrant Multiplying) Mode (VOUT = 0V to –VREF) The LTC1595/LTC1596 can be used with a single op amp to provide 2-quadrant multiplying operation as shown in Figure 1. With a fixed –10V reference, the circuits shown give a precision unipolar 0V to 10V output swing. 5V 0.1µF 10 4 7 5 6 9 8 11 µP 13 14 15 16 STB3 CLR VDD VREF RFB STB1 SRI LD1 LTC1596 SRO LD2 STB2 STB4 DGND AGND 12 33pF OUT1 OUT2 1 – + LT1001 VOUT 0V TO –VREF 2 3 TO NEXT DAC FOR DAISY-CHAINING 1595/96 F01a (a) VREF –10V TO 10V 5V 0.1µF 7 P 6 5 8 1 2 VDD VREF CLK RFB SRI LTC1595 33pF OUT1 3 LD – + GND 4 LT1001 1595/96 F01b (b) 10 Table 1. Unipolar Binary Code Table VOUT 0V TO –VREF DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB LSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 ANALOG OUTPUT VOUT –VREF (65,535/65,536) –VREF (32,768/65,536) = –VREF /2 –VREF (1/65,536) 0V Figure 1. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to – VREF For more information www.linear.com/LTC1595 159561fc LTC1595/LTC1596/LTC1596-1 APPLICATIONS INFORMATION Bipolar (4-Quadrant Multiplying) Mode (VOUT = – VREF to VREF) The LTC1595/LTC1596 can be used with a dual op amp and three external resistors to provide 4-quadrant multiplying operation as shown in Figure 2 (last page). With a fixed 10V reference, the circuits shown give a precision bipolar –10V to 10V output swing. Using the LTC1596-1 will cause the power-on reset and clear pin to reset the DAC to mid-scale (bipolar zero). Op Amp Selection Because of the extremely high accuracy of the 16-bit LTC1595/LTC1596, thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Op amp offset will contribute mostly to output offset and gain and will have minimal effect on INL and DNL. For example, a 500µV op amp offset will cause about 0.55LSB INL degradation and 0.15LSB DNL degradation with a 10V full-scale range. The main effects of op amp offset will be a degradation of zero-scale error equal to the op amp offset, and a degradation of full-scale error equal to twice the op amp offset. For example, the same 500µV op amp offset will cause a 3.3LSB zero-scale error and a 6.5LSB full-scale error with a 10V full-scale range. Op amp input bias current (IBIAS) contributes only a zeroscale error equal to IBIAS(RFB) = IBIAS(RREF) = IBIAS(7k). Table 2 shows a selection of LTC op amps which are suitable for use with the LTC1595/LTC1596. For a thorough discussion of 16-bit DAC settling time and op amp selection, refer to Application Note 74, “Component and Measurement Advances Ensure 16-Bit DAC Settling Time. ” Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding should be used. IOUT2 (LTC1596) and GND (LTC1595) must be tied to the star ground with as low a resistance as possible. Table 2. 16-Bit Settling Time for Various Amplifiers Driven by the LT1595 DAC. LT1468 (Shaded) Offers Fastest Settling Time While Maintaining Accuracy Over Temperature AMPLIFIER CONSERVATIVE SETTLING TIME AND COMPENSATION VALUE COMMENTS LT1001 120µs 100pF Good Low Speed Choice LT1007 19µs 100pF IB Gives ≈1LSB Error at 25°C LT1013 75µs 150pF ≈1LSB Error Due to VOS Over Temperature LT1077 200µs 100pF LT1097 120µs 75pF Good Low Speed Choice LT1112 120µs 100pF Good Low Speed Choice Dual LT1178 450µs 100pF Low Power Dual LT1468 2.5µs 30pF Fastest Settling with 16-Bit Performance 159561fc For more information www.linear.com/LTC1595 11 LTC1595/LTC1596/LTC1596-1 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. N8 Package N Package 8-Lead PDIP (Narrow .300 Inch) 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510 Rev I) (Reference LTC DWG # 05-08-1510 Rev I) .400* (10.160) MAX 8 7 6 5 1 2 3 4 .255 ± .015* (6.477 ± 0.381) .300 – .325 (7.620 – 8.255) .008 – .015 (0.203 – 0.381) ( +.035 .325 –.015 8.255 +0.889 –0.381 ) .045 – .065 (1.143 – 1.651) .065 (1.651) TYP .100 (2.54) BSC .130 ± .005 (3.302 ± 0.127) .120 (3.048) .020 MIN (0.508) MIN .018 ± .003 N8 REV I 0711 (0.457 ± 0.076) NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) 12 159561fc For more information www.linear.com/LTC1595 LTC1595/LTC1596/LTC1596-1 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610 Rev G) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 .245 MIN .160 ±.005 .010 – .020 × 45° (0.254 – 0.508) 2 .053 – .069 (1.346 – 1.752) 0°– 8° TYP .016 – .050 (0.406 – 1.270) 5 .150 – .157 (3.810 – 3.988) NOTE 3 1 RECOMMENDED SOLDER PAD LAYOUT .008 – .010 (0.203 – 0.254) 6 .228 – .244 (5.791 – 6.197) .030 ±.005 TYP NOTE: 1. DIMENSIONS IN 7 .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE 3 4 .004 – .010 (0.101 – 0.254) .050 (1.270) BSC SO8 REV G 0212 159561fc For more information www.linear.com/LTC1595 13 LTC1595/LTC1596/LTC1596-1 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. SW Package 16-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) .050 BSC .045 .005 .030 .005 TYP .398 – .413 (10.109 – 10.490) NOTE 4 16 N 15 14 13 12 11 10 9 N .325 .005 .420 MIN .394 – .419 (10.007 – 10.643) NOTE 3 1 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT 1 .005 (0.127) RAD MIN .009 – .013 (0.229 – 0.330) NOTE: 1. DIMENSIONS IN .291 – .299 (7.391 – 7.595) NOTE 4 .010 – .029 ¥ 45∞ (0.254 – 0.737) 2 3 4 5 6 .093 – .104 (2.362 – 2.642) 8 .037 – .045 (0.940 – 1.143) 0 – 8 TYP NOTE 3 .016 – .050 (0.406 – 1.270) .050 (1.270) BSC .014 – .019 (0.356 – 0.482) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 14 7 .004 – .012 (0.102 – 0.305) S16 (WIDE) 0502 159561fc For more information www.linear.com/LTC1595 LTC1595/LTC1596/LTC1596-1 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION B 02/12 Removed 16-Lead PDIP PAGE NUMBER 1, 2 C 8/15 Fixed errors in Table 3 16 159561fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC1595 15 LTC1595/LTC1596/LTC1596-1 TYPICAL APPLICATION R2 20k VREF –10V TO 10V R3 20k 5V 0.1µF 10 4 7 5 6 9 8 11 µP 13 14 15 16 33pF STB3 CLR VDD VREF RFB STB1 SRI LD1 LTC1596-1 SRO LD2 STB2 STB4 DGND AGND OUT1 – 1 R1 10k 1/2 LT1112 OUT2 + (20k 2) 1/2 LT1112 + 2 3 12 – TO NEXT DAC FOR DAISY-CHAINING 1595/96 F02a VOUT –VREF TO VREF RESISTORS: CADDOCK T914-20K-010-02 (OR EQUIVALENT) 20k, 0.01%, TC TRACK = 2ppm/°C (a) VREF –10V TO 10V 5V 0.1F 7 µP 6 5 8 1 2 VDD VREF RFB LTC1595 Table 3. Bipolar Offset Binary Code Table 33pF CLK SRI R3 20k R2 20k OUT1 – 3 LD 1/2 LT1112 + GND 4 R1 10k (20k 2) – 1/2 LT1112 + VOUT –VREF TO VREF DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB LSB 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 1595/96 F02b ANALOG OUTPUT VOUT VREF (32,767/32,768) VREF (1/32,768) 0V –VREF (1/32,768) –VREF (b) Figure 2. Bipolar Operation (4-Quadrant Multiplication) VOUT = – VREF to VREF RELATED PARTS PART NUMBER DACs LTC1590 LTC1597 LTC1650 LTC1658 LTC7543/LTC8143/LTC8043 ADCs LTC1418 LTC1604 LTC1605 LTC2400 Op Amps LT1001 LT1112 LT1468 References LT1236 LT1634 DESCRIPTION COMMENTS Dual Serial I/O Multiplying IOUT 12-Bit DAC Parallel 16-Bit Current Output DAC Serial 16-Bit Voltage Output DAC Serial 14-Bit Voltage Output DAC Serial I/O Multiplying IOUT 12-Bit DACs 16-Pin SO and PDIP, SPI Interface Low Glitch, ±1LSB Maximum INL, DNL Low Noise and Glitch Rail-to-Rail VOUT Low Power, 8-Lead MSOP Rail-to-Rail VOUT Clear Pin and Serial Data Output (LTC8143) 14-Bit, 200ksps 5V Sampling ADC 16-Bit, 333ksps Sampling ADC Single 5V, 16-Bit 100ksps ADC 24-Bit, ∆∑ ADC in SO-8 16mW Dissipation, Serial and Parallel Outputs ±2.5V Input, SINAD = 90dB, THD = 100dB Low Power, ±10V Inputs 1ppm (4ppm) Offset (Full-Scale), Internal 50Hz/60Hz Notches Precision Operational Amplifier Dual Low Power, Precision Picoamp Input Op Amp 90MHz, 22V/µs, 16-Bit Accurate Op Amp Low Offset, Low Drift Low Offset, Low Drift Precise, 1µs Settling to 0.0015% Precision Reference Micropower Reference Ultralow Drift, 5ppm/°C, High Accuracy 0.05% Ultralow Drift, 10ppm/°C, High Accuracy 0.05% 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC1595 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC1595 159561fc LT 0815 REV C • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 1997