LTC1605ACN

LTC1605 16-Bit, 100ksps, Sampling ADC FEATURES DESCRIPTION Single 5V Supply nn Bipolar Input Range: ±10V nn Power Dissipation: 55mW Typ nn Guaranteed No Missing Codes nn Sample Rate: 100ksps nn Integral Nonlinearity: ±2.0LSB Max nn Signal-to-Noise Ratio: 86dB Typ nn Operates with Internal or External Reference nn Internal Synchronized Clock nn Improved 2nd Source to ADS7805 and AD976 nn 28-Lead SSOP and SW Packages The LTC®1605 is a 100ksps, sampling 16-bit A/D converter that draws only 55mW (typical) from a single 5V supply. This easy-to-use device includes sample-and-hold, precision reference, switched capacitor successive approximation A/D and trimmed internal clock. nn The LTC1605’s input range is an industry standard ±10V. Maximum DC specs include ±2.0LSB INL and 16-bits no missing codes over temperature. An external reference can be used if greater accuracy over temperature is needed. The ADC has a microprocessor compatible, 16-bit or twobyte parallel output port. A convert start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. APPLICATIONS Industrial Process Control Multiplexed Data Acquisition Systems nn High Speed Data Acquisition for PCs nn Digital Signal Processing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. nn nn TYPICAL APPLICATION Typical INL Curve Low Power, 100kHz, 16-Bit Sampling ADC on 5V Supply 5V 2.0 10μF 28 0.1μF 1.5 27 1.0 10V 200Ω INPUT 1 VIN 20k 16-BIT SAMPLING ADC 33.2k 4k CONTROL LOGIC AND TIMING REFERENCE 2 AGND2 5 CS 25 R/C 24 DIGITAL CONTROL SIGNALS BYTE 23 2.2μF AGND1 0 –0.5 –1.5 BUSY 26 4k 0.5 –1.0 BUFFER 3 REF D15 TO D0 16-BIT OR 2 BYTE PARALLEL BUS 10k 4 CAP 2.2μF 6 TO 13 15 TO 22 INL (LSBs) VDIG VANA –2.0 0 16384 32768 49152 65535 CODE 1605 • TA02 DGND 14 1605 • TA01 1605fd For more information www.linear.com/LTC1605 1 LTC1605 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) VANA ...........................................................................7V VDIG to VANA .............................................................0.3V VDIG ............................................................................7V Ground Voltage Difference DGND, AGND1 and AGND2.................................±0.3V Analog Inputs (Note 3) VIN ......................................................................±25V CAP.............................. VANA + 0.3V to AGND2 – 0.3V REF.....................................Indefinite Short to AGND2 ........................................... Momentary Short to VANA Digital Input Voltage (Note 4)...........DGND – 0.3V to 10V Digital Output Voltage......... VDGND – 0.3V to VDIG + 0.3V Power Dissipation............................................... 500mW Operating Ambient Temperature Range LTC1605C................................................. 0°C to 70°C LTC1605I..............................................–40°C to 85°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec).................... 300°C TOP VIEW VIN 1 28 VDIG AGND1 2 27 VANA REF 3 26 BUSY CAP 4 25 CS AGND2 5 D15 (MSB) 6 24 R/C 23 BYTE D14 7 22 D0 D13 8 21 D1 D12 9 20 D2 D11 10 19 D3 D10 11 18 D4 D9 12 17 D5 D8 13 16 D6 DGND 14 15 D7 OBSOLETE PACKAGE G PACKAGE N PACKAGE 28-LEAD PLASTIC SSOP 28-LEAD PDIP SW PACKAGE 28-LEAD PLASTIC SO WIDE TJMAX = 125°C, θJA = 95°C/W (G) TJMAX = 125°C, θJA = 130°C/W (N) TJMAX = 125°C, θJA = 130°C/W (SW) EXPOSED PAD (PIN #) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1605ACG#PBF LTC1605ACG#TRPBF 1605ACG 28-Lead Plastic SSOP 0°C to 70°C LTC1605AIG#PBF LTC1605AIG#TRPBF 1605AIG 28-Lead Plastic SSOP –40°C to 85°C LTC1605CG#PBF LTC1605CG#TRPBF 1605CG 28-Lead Plastic SSOP 0°C to 70°C LTC1605IG#PBF LTC1605IG#TRPBF 1605IG 28-Lead Plastic SSOP –40°C to 85°C LTC1605ACSW#PBF LTC1605ACSW#TRPBF 1605ACSW 28-Lead Plastic SO Wide 0°C to 70°C LTC1605AISW#PBF LTC1605AISW#TRPBF 1605AISW 28-Lead Plastic SO Wide –40°C to 85°C LTC1605CSW#PBF LTC1605CSW#TRPBF 1605CSW 28-Lead Plastic SO Wide 0°C to 70°C LTC1605ISW#PBF LTC1605ISW#TRPBF 1605ISW 28-Lead Plastic SO Wide –40°C to 85°C OBSOLETE PACKAGE LTC1605CN#PBF LTC1605CN#TRPBF 1605CN 28-Lead PDIP 0°C to 70°C LTC1605IN#PBF LTC1605IN#TRPBF 1605IN 28-Lead PDIP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2 1605fd For more information www.linear.com/LTC1605 LTC1605 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 6) LTC1605 PARAMETER CONDITIONS MIN Resolution l 16 No Missing Codes l 15 TYP Transition Noise LTC1605A MAX MIN TYP MAX UNITS 16 Bits 16 Bits 1.0 1.0 LSB Integral Linearity Error (Note 7) l ±3 ±2 LSB Bipolar Zero Error Ext. Reference = 2.5V (Note 8) l ±10 ±10 mV Bipolar Zero Error Drift ±2 ±2 ppm/°C Full-Scale Error Drift ±7 ±5 ppm/°C Full-Scale Error Ext. Reference = 2.5V (Notes 12, 13) Full-Scale Error Drift Ext. Reference = 2.5V Power Supply Sensitivity VANA = VDIG = VDD VDD = 5V ±5% (Note 9) ±0.50 l ±0.25 ±2 ±2 % ppm/°C ±8 ±8 LSB ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS LTC1605/LTC1605A SYMBOL PARAMETER MIN VIN Analog Input Range (Note 9) ±10 V CIN Analog Input Capacitance 10 pF RIN Analog Input Impedance 20 kΩ 4.75V ≤ VANA ≤ 5.25V, 4.75V ≤ VDIG ≤ 5.25V l TYP MAX UNITS DYNAMIC ACCURACY (Notes 5, 14) LTC1605/LTC1605A SYMBOL PARAMETER CONDITIONS S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal (Note 14) THD Total Harmonic Distortion Peak Harmonic or Spurious Noise Full-Power Bandwidth MIN TYP MAX UNITS 87.5 dB 10kHz Input Signal 87 dB 20kHz, –60dB Input Signal 30 dB 1kHz Input Signal, First 5 Harmonics –102 dB 10kHz Input Signal, First 5 Harmonics –94 dB 1kHz Input Signal –102 dB 10kHz Input Signal –94 dB (Note 15) 275 kHz 40 ns Aperture Delay Aperture Jitter Sufficient to Meet AC Specs Transient Response Full-Scale Step (Note 9) Overvoltage Recovery (Note 16) 2 150 µs ns 1605fd For more information www.linear.com/LTC1605 3 LTC1605 INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC1605/LTC1605A PARAMETER CONDITIONS VREF Output Voltage IOUT = 0 VREF Output Tempco IOUT = 0 l MIN TYP MAX 2.470 2.500 2.520 ±5 Internal Reference Source Current UNITS V ppm/°C 1 External Reference Voltage for Specified Linearity (Notes 9, 10) 2.30 External Reference Current Drain Ext. Reference = 2.5V (Note 9) CAP Output Voltage IOUT = 0 2.50 l µA 2.70 V 100 µA 2.50 V DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC1605/LTC1605A SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VDD = 5.25V l VIL Low Level Input Voltage VDD = 4.75V l IIN Digital Input Current VIN = 0V to VDD l CIN Digital Input Capacitance VOH High Level Output Voltage VDD = 4.75V MIN IO = –10µA IO = –200µA l IO = 160µA TYP MAX 2.4 UNITS V 0.8 V ±10 µA 5 pF 4.5 V 4.0 V VOL Low Level Output Voltage VDD = 4.75V 0.4 V IOZ Hi-Z Output Leakage D15 to D0 VOUT = 0V to VDD, CS High l ±10 µA COZ Hi-Z Output Capacitance D15 to D0 CS High (Note 9) l 15 pF ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VDD 10 mA IO = 1.6mA 4 0.05 l 0.10 V 1605fd For more information www.linear.com/LTC1605 LTC1605 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC1605/LTC1605A SYMBOL PARAMETER fSAMPLE(MAX) Maximum Sampling Frequency l tCONV Conversion Time l 8 µs tACQ Acquisition Time l 2 µs t1 Convert Pulse Width (Note 11) l t2 Data Valid Delay After R/C↓ (Note 9) l 8 µs t3 BUSY Delay from R/C↓ CL = 50pF l 65 ns t4 BUSY Low t5 BUSY Delay After End of Conversion 220 ns t6 Aperture Delay 40 ns t7 Bus Relinquish Time l 10 35 t8 BUSY Delay After Data Valid l 50 200 ns 7.4 µs t9 Previous Data Valid After R/C↓ t10 R/C to CS Setup Time t11 Time Between Conversions t12 Bus Access and Byte Delay CONDITIONS MIN TYP MAX UNITS 100 kHz 40 ns 8 (Notes 9, 10) (Notes 9, 10) µs 83 ns 10 ns 10 µs 10 83 ns POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC1605/LTC1605A SYMBOL PARAMETER CONDITIONS MIN VDD Positive Supply Voltage (Notes 9, 10) 4.75 IDD Positive Supply Current PDIS Power Dissipation l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with DGND, AGND1 and AGND2 wired together (unless otherwise noted). Note 3: When these pin voltages are taken below ground or above VANA = VDIG = VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below ground or above VDD without latch-up. Note 4: When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents of 90mA below ground without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a VIN input with respect to ground. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. TYP MAX UNITS 5.25 V 11 16 mA 55 80 mW Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: With CS low the falling R/C edge starts a conversion. If R/C returns high at a critical point during the conversion it can create small errors. For best results ensure that R/C returns high within 3µs after the start of the conversion. Note 12: As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer. Note 13: Full-scale error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. Note 14: All specifications in dB are referred to a full-scale ±10V input. Note 15: Full-power bandwidth is defined as full-scale input frequency at which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of accuracy. Note 16: Recovers to specified performance after (2 • FS) input overvoltage. 1605fd For more information www.linear.com/LTC1605 5 LTC1605 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Supply Voltage 12.5 12.0 fSAMPLE = 100kHz POSITIVE SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 11.5 11.0 10.5 10.0 4.75 5.00 5.25 CHANGE IN CAP VOLTAGE (V) fSAMPLE = 100kHz 12.0 9.5 4.50 11.5 11.0 10.5 10.0 –50 5.50 –25 SUPPLY VOLTAGE (V) 0 25 50 TEMPERATURE (°C) 75 1605 • TPC01 1.5 1.0 1.0 0.5 0.5 0 –0.5 –0.5 –1.0 –1.5 –1.5 16384 32768 –2.0 65535 49152 –20 0 –1.0 10 Power Supply Feedthrough vs Ripple Frequency POWER SUPPLY FEEDTHROUGH (dB) 1.5 DNL (LSBs) INL (LSBs) 2.0 0 1605 • TPC03 Typical DNL Curve 2.0 0 100 0.05 0.04 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 –0.05 –0.06 –0.07 –0.08 –0.09 –0.10 –80 –70 –60 –50 –40 –30 –20 –10 LOAD CURRENT (mA) 1605 • TPC02 Typical INL Curve –2.0 Change in CAP Voltage vs Load Current Supply Current vs Temperature 0 16384 CODE 32768 49152 –30 –40 –50 –60 –70 65535 1 CODE 10 100 1k 10k 100k RIPPLE FREQUENCY (Hz) 1605 • TPC05 1605 • TPC04 1M 1605 • TPC06 LTC1605 Nonaveraged 4096 Point FFT Plot fSAMPLE = 100kHz fIN = 1kHz SINAD = 87.5dB THD = –101.7dB MAGNITUDE (dB) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 6 0 5 10 15 20 25 30 FREQUENCY (kHz) 35 40 45 50 1605 • TPC07 1605fd For more information www.linear.com/LTC1605 LTC1605 TYPICAL PERFORMANCE CHARACTERISTICS Total Harmonic Distortion vs Input Frequency SINAD vs Input Frequency 90 –70 TOTAL HARMONIC DISTORTION (dB) 89 88 SINAD (dB) 87 86 85 84 83 82 81 1 10 INPUT FREQUENCY (kHz) 100 –80 –90 –100 –110 1 1605 • TPC08 10 INPUT FREQUENCY (kHz) 100 1605 • TPC09 PIN FUNCTIONS VIN (Pin 1): Analog Input. Connect through a 200Ω resistor to the analog input. Full-scale input range is ±10V. AGND1 (Pin 2): Analog Ground. Tie to analog ground plane. REF (Pin 3): 2.5V Reference Output. Bypass with 2.2µF tantalum capacitor. Can be driven with an external reference. CAP (Pin 4): Reference Buffer Output. Bypass with 2.2µF tantalum capacitor. AGND2 (Pin 5): Analog Ground. Tie to analog ground plane. D15 to D8 (Pins 6 to 13): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. DGND (Pin 14): Digital Ground. D7 to D0 (Pins 15 to 22): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. BYTE (Pin 23): Byte Select. With BYTE low, data will be output with Pin 6 (D15) being the MSB and Pin 22 (D0) being the LSB. With BYTE high the upper eight bits and the lower eight bits will be switched. The MSB is output on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on Pin 6 and the LSB is output on Pin 13. R/C (Pin 24): Read/Convert Input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold state and starts a conversion. With CS low, a rising edge on R/C enables the output data bits. CS (Pin 25): ChipSelect. Internally OR’d with R/C. With R/C low, a falling edge on CS will initiate a conversion. With R/C high, a falling edge on CS will enable the output data. BUSY (Pin 26): Output Shows Converter Status. It is low when a conversion is in progress. Data valid on the rising edge of BUSY. CS or R/C must be high when BUSY rises or another conversion will start without time for signal acquisition. VANA (Pin 27): 5V Analog Supply. Bypass to ground with a 0.1µF ceramic and a 10µF tantalum capacitor. VDIG (Pin 28): 5V Digital Supply. Connect directly to Pin 27. 1605fd For more information www.linear.com/LTC1605 7 LTC1605 TEST CIRCUIT Load Circuit for Access Timing Load Circuit for Output Float Delay 5V 5V 1k 1k DBN 1k CL DBN DBN DBN 1k CL 50pF 50pF LTC1605 • TC02 LTC1605 • TC01 A. HI-Z TO VOH AND VOL TO VOH A. VOH TO HI-Z B. HI-Z TO VOL AND VOH TO VOL B. VOL TO HI-Z FUNCTIONAL BLOCK DIAGRAM VIN CSAMPLE 20k 10k REF 4k 4k VANA CSAMPLE VDIG ZEROING SWITCHES 2.5V REF + REF BUF COMP 16-BIT CAPACITIVE DAC – CAP (2.5V) AGND1 AGND2 DGND INTERNAL CLOCK • • • OUTPUT LATCHES D15 D0 CONTROL LOGIC CS 8 16 SUCCESSIVE APPROXIMATION REGISTER R/C BYTE BUSY LTC1605 • BD 1605fd For more information www.linear.com/LTC1605 LTC1605 APPLICATIONS INFORMATION Conversion Details The LTC1605 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 16-bit or two byte parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and R/C inputs. At the start of conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, VIN is connected through the resistor divider to the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the autozero switches. In this acquire phase, a minimum delay of 2µs will provide enough time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the autozero switches open, putting the comparator into the compare mode. The input switch switches CSAMPLE to ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At RIN1 RIN2 SAMPLE SI CSAMPLE – + DAC COMPARATOR VDAC S A R 16-BIT LATCH 1605 • F01 Figure 1. LTC1605 Simplified Equivalent Circuit The nominal input range for the LTC1605 is ±10V or (±4 • VREF) and the input is overvoltage protected to ±25V. The input impedance is typically 20kΩ, therefore, it should be driven with a low impedance source. Wideband noise coupling into the input can be minimized by placing a 1000pF capacitor at the input as shown in Figure 2. An NPO-type capacitor gives the lowest distortion. Place the capacitor as close to the device input pin as possible. If an amplifier is to be used to drive the input, care should be taken to select an amplifier with adequate accuracy, linearity and noise for the application. The following list is a summary of the op amps that are suitable for driving the LTC1605. More detailed information is available at www.linear.com. AIN 200Ω VIN 1000pF 33.2k CAP 1605 • F02 Figure 2. Analog Input Filtering LT®1007: Low noise precision amplifier. 2.7mA supply current ±5V to ±15V supplies. Gain bandwidth product 8MHz. DC applications. LT1227: 140MHz video current feedback amplifier. 10mA supply current. ±5V to ±15V supplies. Low noise and low distortion. HOLD CDAC Driving the Analog Inputs LT1097: Low cost, low power precision amplifier. 300µA supply current. ±5V to ±15V supplies. Gain bandwidth product 0.7MHz. DC applications. SAMPLE VIN the end of a conversion, the DAC output balances the VIN input charge. The SAR contents (a 16-bit data word) that represents the VIN are loaded into the 16-bit output latches. LT1360: 37MHz voltage feedback amplifier. 3.8mA supply current. ±5V to ±15V supplies. Good AC/DC specs. LT1363: 50MHz voltage feedback amplifier. 6.3mA supply current. Good AC/DC specs. LT1364/LT1365: Dual and quad 50MHz voltage feedback amplifiers. 6.3mA supply current per amplifier. Good AC/ DC specs. 1605fd For more information www.linear.com/LTC1605 9 LTC1605 APPLICATIONS INFORMATION The LTC1605 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.50V. The full-scale range of the ADC is equal to (±4 • VREF) or nominally ±10V. The output of the reference is connected to the input of a unity-gain buffer through a 4k resistor (see Figure 3). The input to the buffer or the output of the reference is available at REF (Pin 3). The internal reference can be overdriven with an external reference if more accuracy is needed. The buffer output drives the internal DAC and is available at CAP (Pin 4). The CAP pin can be used to drive a steady DC load of less than 2mA. Driving an AC load is not recommended because it can cause the performance of the converter to degrade. REF (2.5V) 4k 3 2.2μF + is adjusted until the output code is changing between 0111 1111 1111 1110 and 0111 1111 1111 1111. Figure 6 shows the bipolar transfer characteristic of the LTC1605. 10V INPUT 1 33.2k 1% + 10V INPUT BANDGAP REFERENCE AGND2 VIN AGND1 2.2μF + 3 5V REF LTC1605 576k + 4 2.2μF 5 CAP AGND2 1605 • F05 INTERNAL CAPACITOR DAC Figure 5. ±10V Input with Offset and Gain Trim 011...111 BIPOLAR ZERO 011...110 OUTPUT CODE Figure 3. Internal or External Reference Source 000...001 000...000 111...111 111...110 100...001 FS = 20V 1LSB = FS/65536 100...000 The LTC1605 offset and full-scale errors have been trimmed at the factory with the external resistors shown in Figure 4. This allows for external adjustment of offset and full scale in applications where absolute accuracy is important. See Figure 5 for the offset and gain trim circuit. First adjust the offset to zero by adjusting resistor R3. Apply an input voltage of –152.6mV (–0.5LSB) and adjust R3 so the code is changing between 1111 1111 1111 1111 and 0000 0000 0000 0000. The gain error is trimmed by adjusting resistor R4. An input voltage of 9.999542V (+FS – 1.5LSB) is applied to VIN and R4 CAP 2 R3 50k Offset and Gain Adjustments 5 LTC1605 REF 1 R4 50k 1605 • F03 10 2.2μF 200Ω 1% 33.2k 1% VANA For minimum code transition noise the REF pin and the CAP pin should each be decoupled with a capacitor to filter wideband noise from the reference and the buffer (2.2µF tantalum). 4 AGND1 Figure 4. ±10V Input Without Trim 4 2.2μF 2.2μF 3 VIN 1605 • F04 – CAP (2.5V) 2 200Ω 1% + Internal Voltage Reference –FS/2 –1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 – 1LSB 1605 • F06 Figure 6. LTC1605 Bipolar Transfer Characteristics DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the ADC and the resulting output codes are collected over a large number of conversions. For example in Figure 7 the distribution of 1605fd For more information www.linear.com/LTC1605 LTC1605 TYPICAL APPLICATIONS output code is shown for a DC input that has been digitized 10000 times. The distribution is Gaussian and the RMS code transition is about 1LSB. 4500 4000 3500 COUNT 3000 2500 2000 1500 1000 500 0 –5 –4 –3 –2 –1 0 1 CODE 2 3 4 5 1605 • F07 Figure 7. Histogram for 10000 Conversions DIGITAL INTERFACE Internal Clock The ADC has an internal clock that is trimmed to achieve a typical conversion time of 7µs. No external adjustments are required and, with the typical acquisition time of 1µs, throughput performance of 100ksps is assured. Timing and Control Conversion start and data read are controlled by two digital inputs: CS and R/C. To start a conversion and put the sample-and-hold into the hold mode bring CS and R/C low for no less than 40ns. Once initiated it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output and this is low while the conversion is in progress. There are two modes of operation. The first mode is shown in Figure 8. The digital input R/C is used to control the start of conversion. CS is tied low. When R/C goes low the sample-and-hold goes into the hold mode and a conversion is started. BUSY goes low and stays low during the conversion and will go back high after the conversion has been completed and the internal output shift registers have been updated. R/C should remain low for no less than 40ns. During the time R/C is low the digital outputs are in a Hi-Z state. R/C should be brought back high within 3µs after the start of the conversion to ensure that no errors occur in the digitized result. The second mode, shown in Figure 9, uses the CS signal to control the start of a conversion and the reading of the digital output. In this mode the R/C input signal should be brought low no less than 10ns before the falling edge of CS. The minimum pulse width for CS is 40ns. When CS falls, BUSY goes low and will stay low until the end of the conversion. BUSY will go high after the conversion has been completed. The new data is valid when CS is brought back low again to initiate t1 R/C t 11 t2 t4 t3 BUSY t6 MODE t5 ACQUIRE t9 DATA MODE PREVIOUS DATA VALID HI-Z t7 CONVERT ACQUIRE t CONV t ACQ PREVIOUS DATA VALID CONVERT DATA VALID NOT VALID t8 HI-Z DATA VALID 1605 • F08 Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low) 1605fd For more information www.linear.com/LTC1605 11 LTC1605 APPLICATIONS INFORMATION t 10 t 10 t 10 t 10 R/C t1 t1 CS t3 t4 BUSY t6 ACQUIRE MODE CONVERT ACQUIRE t CONV HI-Z DATA BUS HI-Z DATA VALID t 12 t7 1605 • F09 Figure 9. Using CS to Control Conversion and Read Timing t 10 t 10 R/C CS BYTE HI-Z PINS 6 TO 13 HIGH BYTE t 12 t 12 HI-Z PINS 15 TO 22 HI-Z LOW BYTE LOW BYTE t7 HI-Z HIGH BYTE 1605 • F10 MAGNITUDE (dB) Figure 10. Using CS and BYTE to Control Data Bus Read Timing 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 fSAMPLE = 100kHz fIN = 1kHz SINAD = 87.5dB THD = –101.7dB 0 5 10 15 20 25 30 FREQUENCY (kHz) 35 40 45 50 1605 • F11 Figure 11. LTC1605 Nonaveraged 4096 Point FFT Plot 12 1605fd For more information www.linear.com/LTC1605 LTC1605 APPLICATIONS INFORMATION a read. Again it is recommended that both R/C and CS return high within 3µs after the start of the conversion. band between DC and half the sampling frequency. THD is expressed as: Output Data V22 + V32 + V42 +...VN 2 THD = 20Log V1 The output data can be read as a 16-bit word or it can be read as two 8-bit bytes. The format of the output data is two’s complement. The digital input pin BYTE is used to control the two byte read. With the BYTE pin low the first eight MSBs are output on the D15 to D8 pins and the eight LSBs are output on the D7 to D0 pins. When the BYTE pin is taken high the eight LSBs replace the eight MSBs (Figure 10). Dynamic Performance FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 11 shows a typical LTC1605 FFT plot which yields a SINAD of 87.5dB and THD of –102dB. Signal-to-Noise Ratio The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 11 shows a typical SINAD of 87.5dB with a 100kHz sampling rate and a 1kHz input. Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. Board Layout, Power Supplies and Decoupling Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1605, a printed circuit board is required. Layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. Figures 12 through 15 show a layout for a suggested evaluation circuit which will help obtain the best performance from the 16-bit ADC. Pay particular attention to the design of the analog and digital ground planes. The DGND pin of the LTC1605 can be tied to the analog ground plane. Placing the bypass capacitor as close as possible to the power supply, the reference and reference buffer output is very important. Low impedance common returns for these bypass capacitors are essential to low noise operation of the ADC, and the foil width for these tracks should be as wide as possible. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. The digital output latches and the onboard sampling clock have been placed on the digital ground plane. The two ground planes are tied together at the power supply ground connection. 1605fd For more information www.linear.com/LTC1605 13 LTC1605 TYPICAL APPLICATIONS Figure 12. Component Side Silkscreen for the Suggested LTC1605 Evaluation Circuit ANALOG GROUND PLANE DIGITAL GROUND PLANE Figure 13. Bottom Side Showing Analog Ground Plane 14 ANALOG GROUND PLANE Figure 14. Component Side Showing Separate Analog and Digital Ground Plane 1605fd For more information www.linear.com/LTC1605 2 1 For more information www.linear.com/LTC1605 2 1 2 R17 51 GND NA OUT U8 1MHz, OSC EXT_CLK 1 J1 J2 AIN GND E2 3 3 4 3 2 1 2 3 4 5 6 7 10 9 1 NC2 + 8 TRIM GND QD QC QB QA D B A RCO C ENP ENT CLK LOAD CLR 14 13 12 11 15 5 6 JP1 R18 200 1% VCC R21, 2k 3 15 2 1 JP4 2 CLK 13 CS VCC 3 VCC Q Q JP5 2 C3 0.1μF C4 2.2μF C16 1000pF C9 0.1μF C8 0.1μF C7 10μF VKK C5 0.1μF R19 33.2k 1% C10 0.1μF 28 27 26 25 24 23 14 5 4 3 2 1 VDIG VANA BUSY CS R/C BYTE DGND AGND2 CAP REF AGND1 VIN D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 U1 LTC1605 C11 0.1μF VCC D9 D8 D7 D6 12 13 15 16 D0 D1 D2 D3 D4 U4B 74HC04 3 4 22 21 20 19 18 D5 D10 11 17 D11 D12 D13 D14 D15 10 9 8 7 6 C12 0.1μF R20 1K C13 0.1μF 6 D11 1 5 D12 1 C1 15pF 11 9 8 D6 D7 7 D5 6 5 D3 D4 4 3 2 11 9 8 D2 D1 D0 D8 D9 7 4 D13 D10 3 2 D14 D15 C14 0.1μF Q0 CLK OC D7 Q7 Q6 D6 Q4 D4 Q5 Q3 D3 D5 Q2 Q1 D1 D2 Q0 D0 U3 74HC574 CLK OC Q7 Q6 D6 D7 Q5 Q4 Q3 Q2 Q1 D5 D4 D3 D2 D1 D0 U2 74HC574 C15 10μF U4C 74HC04 5 6 Figure 15. LTC1605 Suggested Evaluation Circuit Schematic GND 1 RCEXT CEXT B A 4 C2 2.2μF U6A 74HC221 NORNAL 1 BYTE REVERSE 3 C17 10μF EXT VREF INT VCC VDD JP3 2 C6 22μF 10V R16 20 INT 1 VCC CLK EXT 3 U4E 74HC04 11 10 U9 LT1019-2.5 OUT TEMP 7 8 VKK INPUT HEATER NC1 D16 MBR0520 U7 74HC160 U4D 74HC04 VCC 9 VKK VIN U5 LT1121 GND 2 VIN 7V TO 15V 1 E1 VIN DIGITAL I.C. BYPASSING 19 12 13 14 15 16 17 18 19 1 U4A 74HC04 12 13 14 15 16 17 18 2 R0, 1.2k R1, 1.2k R2, 1.2k R3, 1.2k R4, 1.2k R5, 1.2k R6, 1.2k R7, 1.2k R8, 1.2k R9, 1.2k R10, 1.2k R11, 1.2k R12, 1.2k R13, 1.2k R14, 1.2k R15, 1.2k 20 19 18 17 16 15 14 D7 D0 D1 D2 D3 D4 D5 D6 GND GND CLK D15 D0 D1 D2 D3 D4 12 13 D5 D6 11 D7 10 D8 D9 D10 D11 D12 D13 D14 D15 9 8 7 6 5 4 3 2 1 D8 D9 D10 D11 D12 D13 D14 D15 1605_07d.eps JP2 LED ENABLE LTC1605 1605fd 15 LTC1605 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. G Package 28-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 9.90 – 10.50* (.390 – .413) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1.25 ±0.12 7.8 – 8.2 5.3 – 5.7 0.42 ±0.03 7.40 – 8.20 (.291 – .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RECOMMENDED SOLDER PAD LAYOUT 2.0 (.079) MAX 5.00 – 5.60** (.197 – .221) 0° – 8° 0.09 – 0.25 (.0035 – .010) 0.65 (.0256) BSC 0.55 – 0.95 (.022 – .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.05 (.002) MIN 0.22 – 0.38 (.009 – .015) TYP G28 SSOP 0204 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE N Package 28-Lead Plastic PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510 Rev I) 1.400* (35.560) MAX 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 .240 – .295* (6.096 – 7.493) .045 – .065 (1.143 – 1.651) .130 ±.005 (3.302 ±0.127) .020 (0.508) MIN .065 (1.651) TYP .120 (3.048) MIN N28 REV I 0711 .005 (0.127) MIN .100 (2.54) BSC .018 ±.003 (0.457 ±0.076) NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) OBSOLETE PACKAGE 16 1605fd For more information www.linear.com/LTC1605 LTC1605 REVISION HISTORY (Revision history begins at Rev D) REV DATE DESCRIPTION D 07/15 Obsoleted 28-Lead PDIP Package PAGE NUMBER 2, 16 1605fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC1605 17 LTC1605 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. SW Package 28-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) .050 BSC .045 ±.005 .030 ±.005 TYP .697 – .712 (17.70 – 18.08) NOTE 4 N 28 26 25 24 23 22 21 20 19 18 17 16 15 N .325 ±.005 .420 MIN 27 .394 – .419 (10.007 – 10.643) NOTE 3 1 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT .291 – .299 (7.391 – 7.595) NOTE 4 .010 – .029 × 45° (0.254 – 0.737) .005 (0.127) RAD MIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 .037 – .045 (0.940 – 1.143) .093 – .104 (2.362 – 2.642) 0° – 8° TYP .009 – .013 (0.229 – 0.330) .050 (1.270) BSC NOTE 3 .004 – .012 (0.102 – 0.305) .014 – .019 (0.356 – 0.482) TYP .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) S28 (WIDE) 0502 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1019-2.5 Precision Bandgap Reference 0.05% Max, 5ppm/°C Max LTC1274/LTC1277 Low Power 12-Bit, 100ksps ADCs 10mW Power Dissipation, Parallel/Byte Interface LTC1415 Single 5V, 12-Bit, 1.25Msps ADC 55mW Power Dissipation, 72dB SINAD LTC1419 Low Power 14-Bit, 800ksps ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation LT1460-2.5 Micropower Precision Series Reference 0.075% Max, 10ppm/°C Max, Only 130µA Supply Current LTC1594/LTC1598 Micropower 4-/8-Channel 12-Bit ADCs Serial I/O, 3V and 5V Versions 18 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC1605 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC1605 1605fd LT 0715 REV D • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 2005