LTC1606CG#TRPBF

LTC1606 16-Bit, 250ksps, Single Supply ADC U FEATURES DESCRIPTIO ■ Sample Rate: 250ksps Single 5V Supply Bipolar Input Range: ±10V Signal-to-Noise Ratio: 90dB Typ Power Dissipation: 75mW Typ Guaranteed No Missing Codes Integral Nonlinearity: ±2.0LSB Max Operates with Internal or External Reference Internal Synchronized Clock 28-Pin SSOP and SO Packages 100ksps Version (LTC1605) Improved 2nd Source to AD976A and ADS7805 Available in 28-Lead Plastic SSOP and SO Packages The LTC ®1606 is a 250ksps, sampling 16-bit A/D converter that draws only 75mW (typical) from a single 5V supply. This easy-to-use device includes sample-andhold, precision reference, switched capacitor successive approximation A/D and trimmed internal clock. Industrial Process Control Multiplexed Data Acquisition Systems High Speed Data Acquisition for PCs Digital Signal Processing The ADC has a microprocessor compatible, 16-bit or two byte parallel output port. A convert start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC1606’s input range is an industry standard ±10V. Maximum DC specs include ±2.0LSB INL and 16 bits no missing codes over temperature. An external reference can be used if greater accuracy over temperature is needed. The 90dB signal-to-noise ratio offers an improvement of 3dB over competing devices, and the RMS transition noise is reduced (0.65LSB vs 1LSB) relative to competitive parts. U APPLICATIO S ■ ■ ■ ■ , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U U BASIC CO FIGURATIO Low Power, 250kHz, 16-Bit Sampling ADC on 5V Supply 5V 10µF 28 ±10V 200Ω INPUT 1 VIN 33.2k 4.096V 2.5V 2.0 VDIG VANA 6 TO 13 15 TO 22 7.35k 16-BIT SAMPLING ADC 2.5k D15 TO D0 1.5 16-BIT OR 2 BYTE PARALLEL BUS 9k 4 CAP 1.64x BUFFER 3 REF CONTROL LOGIC AND TIMING 4k REFERENCE CS 25 R/C 24 BYTE 23 2.2µF AGND1 2 AGND2 5 DGND 14 1.0 0.5 0 –0.5 BUSY 26 10µF Typical INL Curve INL (LSB) LTC1606 0.1µF 27 DIGITAL CONTROL SIGNALS –1.0 –1.5 –2.0 0 16384 32768 49152 65535 CODE 1606 TA01 1606 G04 1606fa 1 LTC1606 W W W AXI U U U W PACKAGE/ORDER I FOR ATIO U ABSOLUTE RATI GS (Notes 1, 2) VANA .......................................................................... 7V VDIG to VANA ........................................................... 0.3V VDIG ........................................................................... 7V Ground Voltage Difference DGND, AGND1 and AGND2 .............................. ±0.3V Analog Inputs (Note 3) VIN ..................................................................... ±25V CAP ............................ VANA + 0.3V to AGND2 – 0.3V REF .................................... Indefinite Short to AGND2 Momentary Short to VANA Digital Input Voltage (Note 4) ........ VDGND – 0.3V to 10V Digital Output Voltage ........ VDGND – 0.3V to VDIG + 0.3V Power Dissipation .............................................. 500mW Operating Ambient Temperature Range LTC1606AC/LTC1606C ............................ 0°C to 70°C LTC1606AI/LTC1606I ......................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW VIN 1 28 VDIG AGND1 2 27 VANA REF 3 26 BUSY CAP 4 25 CS AGND2 5 24 R/C D15 (MSB) 6 23 BYTE D14 7 22 D0 D13 8 21 D1 D12 9 20 D2 D11 10 19 D3 D10 11 18 D4 D9 12 17 D5 D8 13 16 D6 DGND 14 15 D7 G PACKAGE 28-LEAD PLASTIC SSOP LTC1606ACG LTC1606AIG LTC1606CG LTC1606IG LTC1606ACSW LTC1606AISW LTC1606CSW LTC1606ISW SW PACKAGE 28-LEAD PLASTIC SO TJMAX = 125°C, θJA = 95°C/W (G) TJMAX = 125°C, θJA = 130°C/W (SW) Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. U CO VERTER CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 6) PARAMETER CONDITIONS MIN LTC1606 TYP MAX MIN LTC1606A TYP MAX UNITS Resolution ● 16 16 Bits No Missing Codes ● 15 16 Bits Transition Noise 0.65 0.65 LSBRMS Integral Linearity Error (Note 7) ● ±3 ±2 LSB Bipolar Zero Error Ext. Reference = 2.5V (Note 8) ● ±10 ±10 mV ±2 Bipolar Zero Error Drift ±2 ±7 Full-Scale Error Drift Full-Scale Error Ext. Reference = 2.5V (Notes 12, 13) Full-Scale Error Drift Ext. Reference = 2.5V Power Supply Sensitivity VANA = VDIG = VDD VDD = 5V ±5% (Note 9) ±5 ±0.50 ● ppm/°C ±2 ppm/°C ±0.25 ±2 ±8 % ppm/°C ±8 LSB 1606fa 2 LTC1606 U U A ALOG I PUT The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS VIN Analog Input Range (Note 9) 4.75V ≤ VANA ≤ 5.25V, 4.75V ≤ VDIG ≤ 5.25V CIN Analog Input Capacitance 10 pF RIN Analog Input Impedance 10 kΩ W U DY A IC ACCURACY UNITS ±10 ● V (Notes 5, 14) SYMBOL PARAMETER S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal (Note 14) 10kHz Input Signal 20kHz, – 60dB Input Signal THD MIN LTC1606/LTC1606A TYP MAX SYMBOL Total Harmonic Distortion CONDITIONS 1kHz Input Signal, First 5 Harmonics 10kHz Input Signal, First 5 Harmonics MIN 83 – 87 LTC1606 TYP MAX MIN 90 90 30 LTC1606A TYP MAX dB dB dB – 102 – 94 dB dB 87 – 102 – 94 – 89 UNITS 90 90 30 Peak Harmonic or Spurious Noise 1kHz Input Signal 10kHz Input Signal – 102 – 94 – 102 – 94 dB dB Full-Power Bandwidth (Note 15) 275 275 kHz 40 40 ns Aperture Delay Aperture Jitter Sufficient to Meet AC Specs Sufficient to Meet AC Specs Transient Response Full-Scale Step (Note 9) Overvoltage Recovery (Note 16) 1 1 150 150 µs ns U U U I TER AL REFERE CE CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS VREF Output Voltage IOUT = 0 VREF Output Tempco IOUT = 0 MIN ● 2.470 Internal Reference Source Current External Reference Voltage for Specified Linearity (Notes 9, 10) External Reference Current Drain Ext. Reference = 2.5V (Note 9) CAP Output Voltage IOUT = 0 LTC1606/LTC1606A TYP MAX 2.30 2.500 2.520 UNITS V ±5 ppm/°C 1 µA 2.50 ● 4.096 2.70 V 100 µA V 1606fa 3 LTC1606 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS VIH High Level Input Voltage VDD = 5.25V ● VIL Low Level Input Voltage VDD = 4.75V ● 0.8 V IIN Digital Input Current VIN = 0V to VDD ● ±10 µA CIN Digital Input Capacitance VOH High Level Output Voltage VDD = 4.75V MIN LTC1606/LTC1606A TYP MAX SYMBOL VOL Low Level Output Voltage VDD = 4.75V 2.4 IO = –10µA IO = – 200µA ● V 5 pF 4.5 V 4.0 IO = 160µA IO = 1.6mA UNITS V 0.05 ● 0.10 V 0.4 V ±10 µA IOZ Hi-Z Output Leakage D15 to D0 VOUT = 0V to VDD, CS High ● COZ Hi-Z Output Capacitance D15 to D0 CS High (Note 9) ● ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VDD 10 mA 15 pF UW TIMING CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS MIN LTC1606/LTC1606A TYP MAX SYMBOL PARAMETER fSAMPLE(MAX) Maximum Sampling Frequency ● tCONV Conversion Time ● 2.5 µs tACQ Acquisition Time ● 1.5 µs t1 Convert Pulse Width t2 t3 t4 BUSY Low t5 BUSY Delay After End of Conversion 100 ns t6 Aperture Delay 40 ns t7 Bus Relinquish Time ● t8 BUSY Delay After Data Valid ● t9 Previous Data Valid After R/C↓ t10 R/C to CS Setup Time t11 Time Between Conversions t12 Bus Access CL = 30pF ● 15 60 ns Byte Delay CL = 30pF (Notes 9, 10) ● 15 60 ns 250 UNITS kHz (Note 11) ● Data Valid Delay After R/C↓ (Note 9) ● 2.5 µs BUSY Delay from R/C↓ CL = 30pF ● 65 ns ● 2.5 µs (Notes 9, 10) 40 ns 15 20 50 ns 90 ns 2 µs ● 5 ns ● 4 µs 1606fa 4 LTC1606 U W POWER REQUIREMENTS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS VDD Positive Supply Voltage (Notes 9, 10) IDD Positive Supply Current ● 15 20 mA PDIS Power Dissipation ● 75 100 mW Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND1 and AGND2 wired together (unless otherwise noted). Note 3: When these pin voltages are taken below ground or above VANA = VDIG = VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below ground or above VDD without latch-up. Note 4: When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents of 90mA below ground without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 250kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a VIN input with respect to ground. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5 LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. MIN LTC1606/LTC1606A TYP MAX SYMBOL 4.75 5.25 UNITS V Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: With CS low the falling R/C edge starts a conversion. If R/C returns high at a critical point during the conversion, it can create errors. For best results, ensure that R/C returns high within 1µs after the start of the conversion. Note 12: As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer. Note 13: Full-scale error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. Note 14: All specifications in dB are referred to a full-scale ±10V input. Note 15: Full-power bandwidth is defined as full-scale input frequency at which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of accuracy. Note 16: Recovers to specified performance after (2 • FS) input overvoltage. 1606fa 5 LTC1606 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 16.5 Change in CAP Voltage vs Load Current Supply Current vs Temperature 16.0 fSAMPLE = 250kHz 0.10 fSAMPLE = 250kHz 0.08 15.5 15.0 14.5 CHANGE IN CAP VOLTAGE (V) SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 16.0 15.5 15.0 14.5 14.0 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 14.0 –50 13.5 4.5 4.75 5.0 5.25 SUPPLY VOLTAGE (V) 5.5 –25 0 25 50 TEMPERATURE (°C) 75 1606 G01 0 1.5 1.5 –10 1.0 1.0 0.5 0.5 0 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 0 16384 32768 49152 65535 POWER SUPPLY REJECTION (dB) 2.0 –0.5 –2.0 16384 32768 49152 –20 –30 –40 –50 –60 1 65535 CODE 1606 G04 10 100 1k 10k 100k RIPPLE FREQUENCY (Hz) Total Harmonic Distortion (THD) vs Input Frequency SINAD vs Input Frequency 90 fSAMPLE = 250kHz fIN = 1.04kHz SINAD = 90dB THD = –100dB 1M LT1606 G06 1606 G04 –60 fSAMPLE = 250kHz 85 fSAMPLE = 250kHz –70 THD (dB) 80 SINAD (dB) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 fSAMPLE = 250kHz –70 0 CODE Nonaveraged 4096 Point FFT Plot 5 Power Supply Rejection vs Ripple Frequency 2.0 0 3 1606 G03 Typical DNL Curve DNL (LSB) INL (LSB) –0.10 –15 –13 –11 –9 –7 –5 –3 –1 1 LOAD CURRENT (mA) 1606 G02 Typical INL Curve MAGNITUDE (dB) 100 75 –80 –90 70 –100 65 –110 60 0 25 75 50 FREQUENCY (kHz) 100 125 1606 G07 1 10 100 FREQUENCY (kHz) 1000 1 10 100 1000 FREQUENCY (kHz) 1606 G08 1606 G09 1606fa 6 LTC1606 U U U PI FU CTIO S VIN (Pin 1): Analog Input. Connect through a 200Ω resistor to the analog input. Full-scale input range is ±10V. being the LSB. With BYTE high, the upper eight bits and the lower eight bits will be switched. The MSB is output on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on Pin 6 and the LSB is output on Pin 13. AGND1 (Pin 2): Analog Ground. Tie to analog ground plane. R/C (Pin 24): Read/Convert Input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold state and starts a conversion. With CS low, a rising edge on R/C enables the output data bits. REF (Pin 3): 2.5V Reference Output. Bypass with 2.2µF tantalum capacitor. Can be driven with an external reference. CS (Pin 25): Chip Select. Internally OR’d with R/C. With R/C low, a falling edge on CS will initiate a conversion. With R/C high, a falling edge on CS will enable the output data. CAP (Pin 4): Reference Buffer Output. Bypass with 10µF tantalum capacitor. The capacitor output voltage is 4.096V when REF = 2.5V. AGND2 (Pin 5): Analog Ground. Tie to analog ground plane. DGND (Pin 14): Digital Ground. BUSY (Pin 26): Output Shows Converter Status. It is low when a conversion is in progress. Data valid on the rising edge of BUSY. CS or R/C must be high when BUSY rises or another conversion will start without time for signal acquisition. D7 to D0 (Pins 15 to 22): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. VANA (Pin 27): 5V Analog Supply. Bypass to ground with a 0.1µF ceramic and a 10µF tantalum capacitor. BYTE (Pin 23): Byte Select. With BYTE low, data will be output with Pin 6 (D15) being the MSB and Pin 22 (D0) VDIG (Pin 28): 5V Digital Supply. Connect directly to Pin 27. D15 to D8 (Pins 6 to 13): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. W FU CTIO AL BLOCK DIAGRA U CSAMPLE 7.35k VIN 9k 2.5k VANA CSAMPLE REF VDIG ZEROING SWITCHES 4k 2.5V REF + REF BUF 1.64x COMP 16-BIT CAPACITIVE DAC – CAP (4.096V) 16 SUCCESSIVE APPROXIMATION REGISTER AGND1 • • • OUTPUT LATCHES D15 D0 AGND2 DGND INTERNAL CLOCK CONTROL LOGIC 1606 BD CS R/C BYTE BUSY 1606fa 7 U LTC1606 TEST CIRCUITS Load Circuit for Output Float Delay Load Circuit for Access Timing 5V 5V 1k DBN 1k DBN 1k DBN 30pF DBN 30pF 1k 30pF 30pF 1606 TC02 1606 TC01 B. Hi-Z TO VOL AND VOH TO VOL A. VOH TO Hi-Z B. VOL TO Hi-Z U A. Hi-Z TO VOH AND VOL TO VOH W U U APPLICATIO S I FOR ATIO Conversion Details The LTC1606 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 16-bit or two byte parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and R/C inputs. At the start of conversion, the successive approximation register (SAR) is reset. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, VIN is connected through the resistor divider to SAMPLE RIN1 SAMPLE SI CSAMPLE – VIN RIN2 HOLD + CDAC COMPARATOR the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the autozero switches. In this acquire phase, a minimum delay of 1.5µs will provide enough time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the autozero switches open, putting the comparator into the compare mode. The input switch switches CSAMPLE to ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the VIN input charge. The SAR contents (a 16-bit data word) that represents the VIN are loaded into the 16-bit output latches. Driving the Analog Inputs The nominal input range for the LTC1606 is ±10V or (±4 • VREF) and the input is overvoltage protected to ±25V. The input impedance is typically 10kΩ, therefore, it should be driven with a low impedance source. Wideband noise coupling into the input can be minimized by placing a 1000pF capacitor at the input as shown in Figure 2. An NPO-type capacitor gives the lowest distortion. Place the DAC VDAC S A R AIN 200Ω VIN 1000pF 16-BIT LATCH 33.2k LTC1606 CAP 1606 • F02 1606 • F01 Figure 1. LTC1606 Simplified Equivalent Circuit Figure 2. Analog Input Filtering 1606fa 8 LTC1606 U W U U APPLICATIO S I FOR ATIO LT1007: Low noise precision amplifier. 2.7mA supply current ±5V to ±15V supplies. Gain bandwidth product 8MHz. DC applications. LT1097: Low cost, low power precision amplifier. 300µA supply current. ±5V to ±15V supplies. Gain bandwidth product 0.7MHz. DC applications. LT1227: 140MHz video current feedback amplifier. 10mA supply current. ±5V to ±15V supplies. Low noise and low distortion. LT1360: 37MHz voltage feedback amplifier. 3.8mA supply current. ±5V to ±15V supplies. Good AC/DC specs. LT1363: 50MHz voltage feedback amplifier. 6.3mA supply current. Good AC/DC specs. LT1364/LT1365: Dual and quad 50MHz voltage feedback amplifiers. 6.3mA supply current per amplifier. Good AC/ DC specs. LT1468: 90MHz 22V/µs 16-bit accurate amplifier. LT1469: Dual LT1468 Internal Voltage Reference The LTC1606 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.50V. The full-scale range of the ADC is equal to (±4 • VREF) or nominally ±10V. The output of the reference is connected to the input of a buffer (1.64x) through a 4k resistor (see Figure 3). The input to the buffer or the output of the reference is available at REF (Pin 3). The internal reference can be overdriven with an external reference if more accuracy is needed. The buffer output drives the internal DAC and is available at CAP (Pin 4). The CAP pin can be used to drive a steady DC load of less than 2mA. Driving an AC load is not recommended because it can cause the performance of the converter to degrade. 4k 3 REF (2.5V) 2.2µF + BANDGAP REFERENCE – R 0.64R 4 CAP (4.096V) INTERNAL CAPACITOR DAC 10µF 1606 • F03 Figure 3. Internal or External Reference Source For minimum code transition noise, the REF pin and the CAP pin should each be decoupled with a capacitor to filter wideband noise from the reference and the buffer (2.2µF tantalum for the REF pin and 10µF tantalum for the CAP pin). To prevent the 10µF bypass capacitor from discharging through the CAP pin if the positive supply (VDIG and VANA) were to drop, a diode (1N4148 or equivalent) can be placed between the CAP pin and the positive supply. Offset and Gain Adjustments The LTC1606 offset and full-scale errors have been trimmed at the factory with the external resistors shown in Figure 4. This allows for external adjustment of offset and full scale in applications where absolute accuracy is important. See Figure 5 for the offset and gain trim circuit. The 100k resistor in parallel with the 33.2k is only needed for externally trimming the offset. First, adjust the offset to zero by adjusting resistor R3. Apply an input voltage of –152.6µV (– 0.5LSB) and adjust R3 so the code is ±10V INPUT 1 2 200Ω 1% 33.2k 1% 4.096V + capacitor as close to the device input pin as possible. If an amplifier is to be used to drive the input, care should be taken to select an amplifier with adequate accuracy, linearity and noise for the application. The following list is a summary of the op amps that are suitable for driving the LTC1606. More detailed information is available in the Linear Technology data books and LinearViewTM CD-ROM. 2.2µF 3 4 + 10µF 5 VIN AGND1 LTC1606 REF CAP AGND2 1606 • F04 Figure 4. ±10V Input Without Trim LinearView is a trademark of Linear Technology Corporation 1606fa 9 LTC1606 U W U U APPLICATIO S I FOR ATIO changing between 1111 1111 1111 1111 and 0000 0000 0000 0000. The gain error is trimmed by adjusting resistor R4. An input voltage of 9.999542V (+FS – 1.5LSB) is applied to VIN and R4 is adjusted until the output code is changing between 0111 1111 1111 1110 and 0111 1111 1111 1111. Figure 6 shows the bipolar transfer characteristic of the LTC1606. 1 ±10V INPUT 2 200Ω 1% + 33.2k 1% VIN AGND1 2.2µF 3 5V REF R4 50k R3 50k 4 + DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the ADC and the resulting output codes are collected over a large number of conversions. For example in Figure 7, the distribution of output code is shown for a DC input that has been digitized 4096 times. The distribution is Gaussian and the RMS code transition is about 0.65LSB. LTC1606 392k 100k If the external resistors are not used, the resulting offset and gain error ranges are shown in Table 1. DIGITAL INTERFACE CAP 10µF 5 Internal Clock AGND2 1606 • F05 Figure 5. ±10V Input with Offset and Gain Trim The ADC has an internal clock that is trimmed to achieve a typical conversion time of 2.3µs. No external adjustments are required and, with the typical acquisition time of 1µs, throughput performance of 250ksps is assured. 2500 011...111 BIPOLAR ZERO 2000 000...001 COUNTS OUTPUT CODE 011...110 000...000 111...111 111...110 1500 1000 500 100...001 FS = 20V 1LSB = FS/65536 100...000 0 –FS/2 –1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 – 1LSB –3 –2 –1 0 CODE 1 2 3 4 1606 • F07 1606 • F06 Figure 6. LTC1606 Bipolar Transfer Characteristics Figure 7. Histogram for 4096 Conversions Table 1 ERROR TERM WITH BOTH EXTERNAL RESISTORS INCLUDED WITHOUT THE EXTERNAL 33.2k RESISTOR WITHOUT EITHER EXTERNAL RESISTOR INCLUDED Offset Error – 10mV < Error < 10mV 10mV < Error< 55mV 54mV < Error < 155mV + Full-Scale Error – 0.25% < Error < 0.25% – 0.50% < Error < 0.50% – 1.3% < Error < –0.10% – 3.40% < Error < –0.85% – Full-Scale Error – 0.25% < Error < 0.25% – 0.50% < Error < 0.50% 0.25% < Error < 1.40% 2.10% < Error < 6.15% 1606fa 10 LTC1606 U W U U APPLICATIO S I FOR ATIO Timing and Control Conversion start and data read are controlled by two digital inputs: CS and R/C. To start a conversion and put the sample-and-hold into the hold mode, bring CS and R/C low for no less than 40ns. Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output and this is low while the conversion is in progress. There are two modes of operation. The first mode is shown in Figure 8. The digital input R/C is used to control the start of conversion. CS is tied low. When R/C goes low, the sample-and-hold goes into the hold mode and a conversion is started. BUSY goes low and stays low during the conversion and will go back high after the conversion has been completed and the internal output shift registers have been updated. R/C should remain low for no less than 40ns. During the time R/C is low, the digital outputs are in a Hi-Z state. R/C should be brought back high within 1µs after the start of the conversion to ensure that no errors occur in the digitized result. The second mode, shown in Figure 9, uses the CS signal to control the start of a conversion and the reading of the digital output. In this mode the R/C input signal should be brought low no less than 10ns before the falling edge of CS. The minimum pulse width for CS is 40ns. When CS falls, BUSY goes low and will stay low until the end of the conversion. BUSY will go high after the conversion has been completed. The new data is valid when CS is brought back low again to initiate a read. Again, it is recommended that both R/C and CS return high within 1µs after the start of the conversion. Output Data The output data can be read as a 16-bit word or it can be read as two 8-bit bytes. The format of the output data is two’s complement. The digital input pin BYTE is used to control the two byte read. With the BYTE pin low, the first eight MSBs are output on the D15 to D8 pins and the eight LSBs are output on the D7 to D0 pins. When the BYTE pin is taken high, the eight LSBs replace the eight MSBs (Figure 10). t1 R/C t 11 t2 t4 t3 BUSY t6 MODE t5 ACQUIRE CONVERT ACQUIRE t CONV t ACQ CONVERT t9 DATA MODE PREVIOUS DATA VALID Hi-Z t7 PREVIOUS DATA VALID DATA VALID NOT VALID t8 Hi-Z DATA VALID 1606 • F08 Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low) 1606fa 11 LTC1606 t 10 t 10 t 10 t 10 R/C t1 t1 CS t3 t4 BUSY t6 MODE ACQUIRE CONVERT ACQUIRE t CONV HI-Z DATA BUS DATA VALID t 12 t7 Hi-Z 1606 • F09 Figure 9. Using CS to Control Conversion and Read Timing t 10 t 10 R/C CS BYTE PINS 6 TO 13 Hi-Z HIGH BYTE t 12 PINS 15 TO 22 Hi-Z t 12 LOW BYTE Hi-Z LOW BYTE t7 HIGH BYTE Hi-Z 1606 • F10 Figure 10. Using CS and BYTE to Control Data Bus Read Timing 1606fa 12 LTC1606 U W U U APPLICATIO S I FOR ATIO Dynamic Performance FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Signal-to-Noise Ratio The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. A typical LTC1606 has a SINAD of 90dB and THD of –100dB with a 250kHz sampling rate and a 1kHz input. Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: 2 2 2 2 V + V3 + V4 ... + VN THD = 20 log 2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. Board Layout, Power Supplies and Decoupling Wire wrap boards and molded sockets are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1606, a printed circuit board is required. Layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. Pay particular attention to the design of the analog and digital ground planes. The DGND pin of the LTC1606 should be tied to the analog ground plane. Placing the bypass capacitor as close as possible to the power supply, the reference and reference buffer output is very important. Low impedance common returns for these bypass capacitors are essential to low noise operation of the ADC, and the foil width for these tracks should be as wide as possible. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. 1606fa 13 LTC1606 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 10.07 – 10.33* (0.397 – 0.407) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 7.65 – 7.90 (0.301 – 0.311) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 5.20 – 5.38** (0.205 – 0.212) 1.73 – 1.99 (0.068 – 0.078) 0° – 8° 0.13 – 0.22 (0.005 – 0.009) 0.55 – 0.95 (0.022 – 0.037) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE 0.65 (0.0256) BSC 0.25 – 0.38 (0.010 – 0.015) 0.05 – 0.21 (0.002 – 0.008) G28 SSOP 1098 1606fa 14 LTC1606 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. SW Package 28-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.697 – 0.712* (17.70 – 18.08) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.291 – 0.299** (7.391 – 7.595) 1 2 3 4 5 6 7 8 9 10 0.093 – 0.104 (2.362 – 2.642) 0.010 – 0.029 × 45° (0.254 – 0.737) 11 12 13 14 0.037 – 0.045 (0.940 – 1.143) 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) 0.050 (1.270) BSC NOTE 1 0.016 – 0.050 (0.406 – 1.270) 0.014 – 0.019 (0.356 – 0.482) TYP 0.004 – 0.012 (0.102 – 0.305) S28 (WIDE) 1098 NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 1606fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1606 U TYPICAL APPLICATIO High Impedance Buffered Input Exhibits 100dB SFDR and 98dB THD Performance 5V + 10µF 15V 0.1µF 28 VDIG LTC1606 VIN ±10V RS ≤ 20k 3 7 + LT1468 2 – 4 R2 200Ω 6 ±10V 0.1µF 1 VIN C1 1000pF R3 33.2k 7.35k 6 TO 13 15 TO 22 16-BIT SAMPLING ADC 2.5k 10µF –15V VANA D15 TO D0 9k 16-BIT OR 2 BYTE PARALLEL BUS 4 CAP 4.096V R1 50Ω 0.1µF 27 2.5V 3 REF 1.65x BUFFER 4k REFERENCE BUSY 26 CS 25 R/C 24 BYTE 23 CONTROL LOGIC AND TIMING 2.2µF AGND1 AGND2 2 5 DIGITAL CONTROL SIGNALS DGND 14 1606 TA02 SINGLE POINT GROUND RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1274/LTC1277 Low Power 12-Bit, 100ksps ADCs 10mW Power Dissipation, Parallel/Byte Interface LTC1415 Single 5V, 12-Bit, 1.25Msps ADC 55mW Power Dissipation, 72dB SINAD LTC1418 14-Bit, 200ksps ADC 15mW, Serial or Parallel Interface LTC1419 Low Power 14-Bit, 800ksps ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation LT1460-2.5 Micropower Precision Series Reference 0.075% Max, 10ppm/°C Max, Only 130µA Supply Current LT1461 Precision Bandgap Reference 0.04% Max, 3ppm/°C Max LTC1594/LTC1598 Micropower 4-/8-Channel 12-Bit ADCs Serial I/O, 3V and 5V Versions LTC1604 16-Bit, 333ksps ADC ±2.5V Input, 90dB SINAD, 100dB THD, No Missing Codes LTC1605 16-Bit, 100kHz ADC Pin Compatible with LTC1606 LTC1605-1/LTC1605-2 16-Bit, 100kHz ADC 0V to 4V/±4V Input Range, Pin Compatible with LTC1606 LTC1608 16-Bit, 500ksps ADC ±2.5V Input, No Missing Codes, Pin Compatible with LTC1604 1606fa 16 Linear Technology Corporation LT/LT 0605 REV A • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com © LINEAR TECHNOLOGY CORPORATION 2000