LTC1608ACG#TRPBF

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 ADC324x Dual-Channel, 14-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters 1 Features 3 Description • • • • • • The ADC324x are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS, analogto-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. 1 • • • • • • Dual Channel 14-Bit Resolution Single Supply: 1.8 V Serial LVDS Interface (SLVDS) Flexible Input Clock Buffer with Divide-by-1, -2, -4 SNR = 72.4 dBFS, SFDR = 87 dBc at fIN = 70 MHz Ultra-Low Power Consumption: – 116 mW/Ch at 125 MSPS Channel Isolation: 105 dB Internal Dither and Chopper Support for Multi-Chip Synchronization Pin-to-Pin Compatible with 12-Bit Version Package: VQFN-48 (7 mm × 7 mm) 2 Applications • • • • • • • • • • • Multi-Carrier, Multi-Mode Cellular Base Stations Radar and Smart Antenna Arrays Munitions Guidance Motor Control Feedback Network and Vector Analyzers Communications Test Equipment Nondestructive Testing Microwave Receivers Software-Defined Radios (SDRs) Quadrature and Diversity Radio Receivers Handheld Radio and Instrumentation Device Information(1) PART NUMBER ADC324x PACKAGE VQFN (48) BODY SIZE (NOM) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. space space space space space space Performance at fS = 125 MSPS, fIN = 10 MHz 0 -10 -20 Amplitude (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D101 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 1 1 1 2 4 4 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 7 Electrical Characteristics: ADC3241, ADC3242 ....... 7 Electrical Characteristics: ADC3243, ADC3244 ....... 7 Electrical Characteristics: General ............................ 8 AC Performance: ADC3241...................................... 9 AC Performance: ADC3242.................................... 11 AC Performance: ADC3243.................................. 13 AC Performance: ADC3244.................................. 15 Digital Characteristics ........................................... 17 Timing Requirements: General ............................. 17 Timing Requirements: LVDS Output..................... 18 Typical Characteristics: ADC3241 ........................ 19 Typical Characteristics: ADC3242 ........................ 25 Typical Characteristics: ADC3243 ........................ 31 Typical Characteristics: ADC3244 ........................ 37 7.19 Typical Characteristics: Common ......................... 43 7.20 Typical Characteristics: Contour ........................... 44 8 Parameter Measurement Information ................ 45 9 Detailed Description ............................................ 47 8.1 Timing Diagrams ..................................................... 45 9.1 9.2 9.3 9.4 9.5 9.6 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 47 47 48 52 53 57 10 Applications and Implementation...................... 69 10.1 Application Information.......................................... 69 10.2 Typical Applications .............................................. 70 11 Power-Supply Recommendations ..................... 72 12 Layout................................................................... 73 12.1 Layout Guidelines ................................................. 73 12.2 Layout Example .................................................... 73 13 Device and Documentation Support ................. 74 13.1 13.2 13.3 13.4 13.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 74 74 74 74 74 14 Mechanical, Packaging, and Orderable Information ........................................................... 74 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2015) to Revision C Page • Added Digital Inputs section to Digital Characteristics table ................................................................................................ 17 • Changed Wake-up time parameter maximum specifications in Timing Requirements: General table ................................ 17 • Updated Figure 19, Figure 20, Figure 23, Figure 24 , Figure 25, and Figure 26 ................................................................. 22 • Updated Figure 50 , Figure 51, Figure 54, Figure 55, Figure 56, and Figure 57. ................................................................ 28 • Updated Figure 81, Figure 82, Figure 85, Figure 86, Figure 87, and Figure 88 . ............................................................... 34 • Updated Figure 112, Figure 113, Figure 116, Figure 117, Figure 118, and Figure 119. ..................................................... 40 • Changed Figure 133. ........................................................................................................................................................... 45 • Changed SNR and Clock Jitter section: changed typical thermal noise value and changed Figure 141 to reflect updated thermal noise value ................................................................................................................................................ 49 • Changed Table 3 .................................................................................................................................................................. 50 • Changed Changed Figure 142 ............................................................................................................................................. 51 • Added Improving Wake-Up Time From Global Power-Down section .................................................................................. 53 • Changed Table 8: changed FLIP BITS to FLIP WIRE in register 4h, changed bit D7 in row 70A, and added register 13 row ................................................................................................................................................................................... 57 • Changed Summary of Special Mode Registers section: changed title, moved section to correct location ......................... 58 • Changed register 04h description......................................................................................................................................... 59 • Changed register 0Ah and 0Bh descriptions........................................................................................................................ 61 • Added register 13h ............................................................................................................................................................... 63 • Changed register 70Ah to include DIS CLK FILT bit ........................................................................................................... 68 2 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Revision History (continued) Changes from Revision A (December 2014) to Revision B • Page Changed document status from Mixed Status to Production Data: releasing ADC3241 and ADC3242 to Production; changes made to product preview devices ........................................................................................................................... 1 Changes from Original (July 2014) to Revision A Page • Changed document status to Mixed Status ........................................................................................................................... 1 • Made changes to product preview data sheet ...................................................................................................................... 1 Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 3 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 5 Device Comparison Table INTERFACE Serial LVDS JESD204B RESOLUTION (Bits) 25 MSPS 50 MSPS 80 MSPS 125 MSPS 160 MSPS 12 ADC3221 ADC3222 ADC3223 ADC3224 — 14 ADC3241 ADC3242 ADC3243 ADC3244 — 12 — ADC32J22 ADC32J23 ADC32J24 ADC32J25 14 — ADC32J42 ADC32J43 ADC32J44 ADC32J45 6 Pin Configuration and Functions 4 DA0M DA0P DA1M DA1P DCLKM DCLKP FCLKM FCLKP DB0M DB0P DB1M DB1P RGZ Package 48-Pin VQFN Top View 48 47 46 45 44 43 42 41 40 39 38 37 DVDD 4 33 DVDD GND 5 32 GND AVDD 6 GND Pad 31 PDN AVDD 7 (Back Side) 30 AVDD AVDD 8 29 AVDD AVDD 9 28 AVDD INAP 10 27 INBP INAM 11 26 INBM AVDD 12 25 AVDD 13 14 15 16 17 18 19 20 21 22 Submit Documentation Feedback 23 24 VCM GND SYSREFM 34 SYSREFP 3 RESET GND AVDD DVDD CLKP 35 CLKM 2 AVDD DVDD SDOUT GND SEN 36 SDATA 1 SCLK GND Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Pin Functions PIN I/O DESCRIPTION NAME NO. AVDD 6-9, 12, 17, 20, 25, 28-30 I Analog 1.8-V power supply CLKM 18 I Negative differential clock input for the ADC CLKP 19 I Positive differential clock input for the ADC DA0M 48 O Negative serial LVDS output for channel A0 DA0P 47 O Positive serial LVDS output for channel A0 DA1M 46 O Negative serial LVDS output for channel A1 DA1P 45 O Positive serial LVDS output for channel A1 DB0M 40 O Negative serial LVDS output for channel B0 DB0P 39 O Positive serial LVDS output for channel B0 DB1M 38 O Negative serial LVDS output for channel B1 DB1P 37 O Positive serial LVDS output for channel B1 DCLKM 44 O Negative bit clock output DCLKP 43 O Positive bit clock output DVDD 2, 4, 33, 35 I Digital 1.8-V power supply FCLKM 42 O Negative frame clock output FCLKP 41 O Positive frame clock output GND 1, 3, 5, 32, 34, 36, PowerPAD™ I Ground, 0 V INAM 11 I Negative differential analog input for channel A INAP 10 I Positive differential analog input for channel A INBM 26 I Negative differential analog input for channel B INBP 27 I Positive differential analog input for channel B PDN 31 I Power-down control. This pin can be configured via the SPI. This pin has an internal 150-kΩ pull-down resistor. RESET 21 I Hardware reset; active high. This pin has an internal 150-kΩ pull-down resistor. SCLK 13 I Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor. SDATA 14 I Serial interface data input. This pin has an internal 150-kΩ pull-down resistor. SDOUT 16 O Serial interface data output SEN 15 I Serial interface enable; active low. This pin has an internal 150-kΩ pull-up resistor to AVDD. SYSREFM 23 I Negative external SYSREF input SYSREFP 22 I Positive external SYSREF input VCM 24 O Common-mode voltage for analog inputs Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 5 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Analog supply voltage range, AVDD Digital supply voltage range, DVDD Voltage applied to input pins Temperature MAX UNIT 2.1 V V –0.3 2.1 INAP, INBP, INAM, INBM –0.3 min (1.9, AVDD + 0.3) CLKP, CLKM –0.3 AVDD + 0.3 SYSREFP, SYSREFM –0.3 AVDD + 0.3 SCLK, SEN, SDATA, RESET, PDN –0.3 3.9 Operating free-air, TA –40 85 Operating junction, TJ Storage, Tstg (1) MIN –0.3 V 125 –65 ºC 150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions (1) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage range 1.7 1.8 1.9 V DVDD Digital supply voltage range 1.7 1.8 1.9 V ANALOG INPUT VID Differential input voltage VIC Input common-mode voltage For input frequencies < 450 MHz 2 For input frequencies < 600 MHz 1 VPP VCM ± 0.025 V CLOCK INPUT Input clock frequency Input clock amplitude (differential) Input clock duty cycle Sampling clock frequency 10 Sine wave, ac-coupled 0.2 125 (2) 1.5 LVPECL, ac-coupled 1.6 LVDS, ac-coupled 0.7 35% Input clock common-mode voltage MSPS 50% VPP 65% 0.95 V DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF RLOAD Differential load resistance placed externally 100 Ω (1) (2) 6 After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section. With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 7.4 Thermal Information ADC324x THERMAL METRIC (1) RGZ (VQFN) UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 25.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 18.9 °C/W RθJB Junction-to-board thermal resistance 3.0 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics: ADC3241, ADC3242 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3241 PARAMETER MIN TYP ADC clock frequency ADC3242 MAX MIN TYP 125 MAX UNIT 125 MSPS 1.8-V analog supply current 31 71 39 81 mA 1.8-V digital supply current 35 65 43 75 mA 118 205 147 245 mW 5 17 5 17 mW 78 103 78 103 mW Total power dissipation Global power-down dissipation Standby power-down dissipation 7.6 Electrical Characteristics: ADC3243, ADC3244 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3243 PARAMETER MIN TYP ADC clock frequency ADC3244 MAX MIN TYP 80 1.8-V analog supply current 1.8-V digital supply current Total power dissipation Global power-down dissipation Standby power-down dissipation Copyright © 2014–2016, Texas Instruments Incorporated 50 91 65 MAX UNIT 125 MSPS 106 mA 52 85 64 95 mA 183 285 233 325 mW 5 17 5 17 mW 72 103 78 103 mW Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 7 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 7.7 Electrical Characteristics: General Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 14 Bits ANALOG INPUT Differential input full-scale RIN Input resistance Differential at dc CIN Input capacitance Differential at dc VOC(VCM) VCM common-mode voltage output 2.0 VPP 6.6 kΩ 3.7 pF 0.95 VCM output current capability V 10 mA Input common-mode current Per analog input pin 1.5 µA/MSPS Analog input bandwidth (3 dB) 50-Ω differential source driving 50-Ω termination across INP and INM 540 MHz DC ACCURACY EO Offset error αEO Temperature coefficient of offset error –25 EG(REF) Gain error as a result of internal reference inaccuracy alone EG(CHAN) Gain error of channel alone α(EGCHAN) Temperature coefficient of EG(CHAN) 25 ±0.024 –2 °C 2 –2 ±0.008 mV %FS %FS Δ%FS/°C CHANNEL-TO-CHANNEL ISOLATION Crosstalk (1) (1) 8 fIN = 10 MHz 105 fIN = 100 MHz 105 fIN = 200 MHz 105 fIN = 230 MHz 105 fIN = 300 MHz 105 dB Crosstalk is measured with a –1-dBFS input signal on one channel and no input on the other channel. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 7.8 AC Performance: ADC3241 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3241 (fS = 25 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN TYP DITHER OFF MAX MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz 73.3 73.7 73.4 73.7 fIN = 70 MHz 72.8 73.2 fIN = 100 MHz 72.4 72.8 fIN = 170 MHz 71.3 71.6 fIN = 230 MHz 70.1 70.4 fIN = 10 MHz 72.2 72.6 fIN = 20 MHz 72.3 72.6 fIN = 70 MHz 71.8 72.2 fIN = 100 MHz 71.5 71.9 fIN = 170 MHz 70.5 70.8 fIN = 230 MHz 69.3 69.6 fIN = 10 MHz –143.9 –144.3 fIN = 20 MHz –144.0 –140.7 –144.3 fIN = 70 MHz –143.4 –143.8 fIN = 100 MHz –143.0 –143.4 fIN = 170 MHz –141.9 –142.2 fIN = 230 MHz –140.7 –141.0 73.3 73.5 fIN = 20 MHz Signal-to-noise ratio (from 1-MHz offset) SNR Signal-to-noise ratio (full Nyquist band) NSD (1) Noise spectral density (averaged across Nyquist zone) 69.7 fIN = 10 MHz fIN = 20 MHz SINAD (1) Signal-to-noise and distortion ratio 73.1 73.5 fIN = 70 MHz 72.8 72.9 fIN = 100 MHz 72.2 72.4 fIN = 170 MHz 71.2 71.2 fIN = 230 MHz 69.7 69.7 fIN = 10 MHz 11.9 11.9 11.8 11.9 fIN = 70 MHz 11.8 11.8 fIN = 100 MHz 11.7 11.7 fIN = 170 MHz 11.5 11.5 fIN = 230 MHz 11.3 11.3 95 87 94 89 fIN = 70 MHz 92 86 fIN = 100 MHz 85 81 fIN = 170 MHz 86 83 fIN = 230 MHz 81 79 fIN = 20 MHz ENOB (1) Effective number of bits 69.1 11.2 fIN = 10 MHz fIN = 20 MHz SFDR (1) Spurious-free dynamic range 84 dBFS dBFS dBFS/Hz dBFS Bits dBc Reported from a 1-MHz offset. Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 9 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com AC Performance: ADC3241 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3241 (fS = 25 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz Second-order harmonic distortion 95 fIN = 70 MHz 100 95 fIN = 100 MHz 95 93 fIN = 170 MHz 87 87 fIN = 230 MHz 81 81 95 88 94 92 fIN = 70 MHz 92 86 fIN = 100 MHz 85 82 fIN = 170 MHz 87 83 fIN = 230 MHz 82 80 fIN = 10 MHz 100 92 fIN = 20 MHz Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) IMD3 10 Total harmonic distortion Two-tone, third-order intermodulation distortion Submit Documentation Feedback 84 101 92 fIN = 70 MHz 100 92 fIN = 100 MHz 98 92 fIN = 170 MHz 100 92 fIN = 230 MHz 96 92 fIN = 10 MHz 94 85 92 85 fIN = 70 MHz 91 84 fIN = 100 MHz 86 82 fIN = 170 MHz 84 81 fIN = 230 MHz 78 76 fIN1 = 45 MHz, fIN2 = 50 MHz –94 –93 fIN1 = 185 MHz, fIN2 = 190 MHz –92 –90 fIN = 20 MHz THD TYP 96 fIN = 20 MHz Third-order harmonic distortion MIN 100 84 fIN = 10 MHz HD3 DITHER OFF MAX 104 fIN = 20 MHz HD2 TYP 87 80.5 MAX UNIT dBc dBc dBc dBc dBFS Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 7.9 AC Performance: ADC3242 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3242 (fS = 50 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN TYP DITHER OFF MAX MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz fIN = 20 MHz fIN = 70 MHz Signal-to-noise ratio (from 1-MHz offset) SNR Signal-to-noise ratio (full Nyquist band) NSD (1) 70.5 Noise spectral density (averaged across Nyquist zone) 73 73.3 73.1 fIN = 170 MHz 71.7 72.1 fIN = 230 MHz 70.9 71.2 fIN = 10 MHz 72.5 72.9 fIN = 20 MHz 72.6 73.1 fIN = 70 MHz 72.3 72.6 fIN = 100 MHz 71.9 72.4 fIN = 170 MHz 71.1 71.5 fIN = 230 MHz 70.3 70.6 fIN = 10 MHz –147.1 –147.5 fIN = 20 MHz –147.1 –144.5 –147.6 fIN = 70 MHz –146.8 –147.1 fIN = 100 MHz –146.4 –146.9 fIN = 170 MHz –145.5 –145.9 fIN = 230 MHz –144.7 –145 73.2 73.6 73.4 73.6 fIN = 70 MHz 72.9 73.2 fIN = 100 MHz 72.5 72.9 fIN = 170 MHz 71.5 71.7 fIN = 230 MHz 70.5 70.6 fIN = 10 MHz 11.9 11.9 11.9 11.9 fIN = 70 MHz 11.8 11.9 fIN = 100 MHz 11.7 11.8 fIN = 170 MHz 11.6 11.6 fIN = 230 MHz 11.4 11.4 89 95 93 91 fIN = 70 MHz 94 93 fIN = 100 MHz 88 86 fIN = 170 MHz 85 82 fIN = 230 MHz 82 80 fIN = 20 MHz ENOB (1) Effective number of bits 69.6 11.3 fIN = 10 MHz fIN = 20 MHz SFDR (1) Spurious-free dynamic range 73.8 72.6 fIN = 20 MHz SINAD (1) 73.7 73.3 fIN = 100 MHz fIN = 10 MHz Signal-to-noise and distortion ratio 73.3 83 dBFS dBFS/Hz dBFS Bits dBc Reported from a 1-MHz offset. Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 11 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com AC Performance: ADC3242 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3242 (fS = 50 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz Second-order harmonic distortion 95 fIN = 70 MHz 96 94 fIN = 100 MHz 94 92 fIN = 170 MHz 88 89 fIN = 230 MHz 82 83 89 97 93 95 fIN = 70 MHz 94 93 fIN = 100 MHz 88 86 fIN = 170 MHz 85 82 fIN = 230 MHz 82 80 fIN = 10 MHz 99 96 fIN = 20 MHz Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) IMD3 12 Total harmonic distortion Two-tone, third-order intermodulation distortion Submit Documentation Feedback 83 101 93 fIN = 70 MHz 100 94 fIN = 100 MHz 99 94 fIN = 170 MHz 99 93 fIN = 230 MHz 97 93 fIN = 10 MHz 88 90 92 87 fIN = 70 MHz 92 88 fIN = 100 MHz 89 86 fIN = 170 MHz 83 81 fIN = 230 MHz 79 78 fIN1 = 45 MHz, fIN2 = 50 MHz –95 –95 fIN1 = 185 MHz, fIN2 = 190 MHz –92 –89 fIN = 20 MHz THD TYP 97 fIN = 20 MHz Third-order harmonic distortion MIN 99 83 fIN = 10 MHz HD3 DITHER OFF MAX 103 fIN = 20 MHz HD2 TYP 87 79 MAX UNIT dBc dBc dBc dBc dBFS Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 7.10 AC Performance: ADC3243 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3243 (fS = 80 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN TYP DITHER OFF MAX MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz fIN = 70 MHz Signal-to-noise ratio (from 1-MHz offset) SNR Signal-to-noise ratio (full Nyquist band) 70.7 NSD Noise spectral density (averaged across Nyquist zone) 72.7 73 72 72.4 fIN = 230 MHz 71.4 71.7 fIN = 10 MHz 72.4 72.8 fIN = 70 MHz 72.3 72.6 fIN = 100 MHz 72.1 72.3 fIN = 170 MHz 71.4 71.7 70.9 71.2 fIN = 10 MHz –149.0 –149.4 fIN = 70 MHz –148.8 –146.7 –149.2 fIN = 100 MHz –148.6 –148.9 fIN = 170 MHz –147.9 –148.3 fIN = 230 MHz –147.3 –147.6 73.1 73.4 fIN = 70 MHz Signal-to-noise and distortion ratio 72.9 73.2 fIN = 100 MHz 72.7 72.9 fIN = 170 MHz 71.9 72.2 fIN = 230 MHz 71.2 71.3 fIN = 10 MHz 11.8 11.9 11.8 11.9 fIN = 100 MHz 11.8 11.8 fIN = 170 MHz 11.6 11.7 fIN = 230 MHz 11.5 11.6 89 94 fIN = 70 MHz ENOB (1) Effective number of bits 69.6 11.3 fIN = 10 MHz fIN = 70 MHz SFDR (1) Spurious-free dynamic range 73.3 fIN = 170 MHz fIN = 10 MHz SINAD (1) 73.5 72.9 fIN = 100 MHz fIN = 230 MHz (1) 73.1 93 93 fIN = 100 MHz 82 93 91 fIN = 170 MHz 87 87 fIN = 230 MHz 85 83 dBFS dBFS/Hz dBFS Bits dBc Reported from a 1-MHz offset. Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 13 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com AC Performance: ADC3243 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3243 (fS = 80 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz Second-order harmonic distortion Third-order harmonic distortion 93 fIN = 100 MHz 95 93 fIN = 170 MHz 87 87 fIN = 230 MHz 85 85 fIN = 10 MHz 89 95 94 94 fIN = 100 MHz 95 96 fIN = 170 MHz 92 90 fIN = 230 MHz 89 84 83 93 95 100 95 fIN = 100 MHz 100 95 fIN = 170 MHz 99 95 fIN = 230 MHz 98 94 fIN = 10 MHz 88 91 fIN = 70 MHz Spurious-free dynamic range (excluding HD2, HD3) fIN = 70 MHz THD IMD3 14 Total harmonic distortion Two-tone, third-order intermodulation distortion Submit Documentation Feedback TYP 98 82 fIN = 10 MHz Non HD2, HD3 MIN 95 fIN = 70 MHz HD3 DITHER OFF MAX 102 fIN = 70 MHz HD2 TYP 86 91 89 fIN = 100 MHz 76 91 88 fIN = 170 MHz 85 84 fIN = 230 MHz 83 81 fIN1 = 45 MHz, fIN2 = 50 MHz –93 –92 fIN1 = 185 MHz, fIN2 = 190 MHz –91 –89 MAX UNIT dBc dBc dBc dBc dBFS Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 7.11 AC Performance: ADC3244 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3244 (fS = 125 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN TYP DITHER OFF MAX MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS fIN = 10 MHz 72.9 73.3 72.6 73 fIN = 100 MHz 72.4 72.8 fIN = 170 MHz 71.7 72.2 fIN = 230 MHz 71 71.6 fIN = 10 MHz 72.5 72.9 fIN = 70 MHz 72.2 72.6 fIN = 100 MHz 72.1 72.5 fIN = 170 MHz 71.4 71.9 fIN = 70 MHz Signal-to-noise ratio (from 1-MHz offset) SNR Signal-to-noise ratio (full Nyquist band) 71 fIN = 230 MHz NSD (1) Noise spectral density (averaged across Nyquist zone) 70.7 71.3 fIN = 10 MHz –150.8 –151.1 fIN = 70 MHz –150.5 –148.9 –150.9 fIN = 100 MHz –150.3 –150.7 fIN = 170 MHz –149.6 –150.1 fIN = 230 MHz –148.9 –149.5 72.8 73 fIN = 10 MHz fIN = 70 MHz SINAD (1) Signal-to-noise and distortion ratio 72.6 72.9 fIN = 100 MHz 72.3 72.5 fIN = 170 MHz 71.5 71.9 fIN = 230 MHz 70.7 71.1 fIN = 10 MHz 11.8 11.8 11.8 11.8 fIN = 100 MHz 11.7 11.8 fIN = 170 MHz 11.6 11.6 fIN = 230 MHz 11.5 11.5 93 86 fIN = 70 MHz ENOB (1) Effective number of bits 69.6 11.3 fIN = 10 MHz fIN = 70 MHz SFDR (1) Spurious-free dynamic range 94 89 fIN = 100 MHz 82 89 85 fIN = 170 MHz 85 85 fIN = 230 MHz 83 82 dBFS dBFS/Hz dBFS Bits dBc Reported from a 1-MHz offset. Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 15 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com AC Performance: ADC3244 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3244 (fS = 125 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz Second-order harmonic distortion Third-order harmonic distortion 95 fIN = 100 MHz 91 90 fIN = 170 MHz 85 85 fIN = 230 MHz 83 83 fIN = 10 MHz 94 86 94 89 fIN = 100 MHz 91 85 fIN = 170 MHz 97 89 fIN = 230 MHz 87 85 100 95 99 95 fIN = 100 MHz 99 95 fIN = 170 MHz 100 91 fIN = 230 MHz 96 92 fIN = 10 MHz 91 85 fIN = 70 MHz Spurious-free dynamic range (excluding HD2, HD3) fIN = 70 MHz THD IMD3 16 Total harmonic distortion Two-tone, third-order intermodulation distortion Submit Documentation Feedback TYP 96 82 83 fIN = 10 MHz Non HD2, HD3 MIN 96 fIN = 70 MHz HD3 DITHER OFF MAX 95 fIN = 70 MHz HD2 TYP 86 91 86 fIN = 100 MHz 76 87 83 fIN = 170 MHz 84 82 fIN = 230 MHz 81 80 fIN1 = 45 MHz, fIN2 = 50 MHz –97 –95 fIN1 = 185 MHz, fIN2 = 190 MHz –91 –90 MAX UNIT dBc dBc dBc dBc dBFS Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 7.12 Digital Characteristics The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN) VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels IIH High-level input current Low-level input current IIL RESET, SDATA, SCLK, PDN 1.3 V 0.4 VHIGH = 1.8 V 10 VHIGH = 1.8 V 0 RESET, SDATA, SCLK, PDN VLOW = 0 V 0 SEN VLOW = 0 V 10 SEN (1) V µA µA DIGITAL INPUTS (SYSREFP, SYSREFM) VIH High-level input voltage 1.3 V VIL Low-level input voltage 0.5 V Common-mode voltage for SYSREF 0.9 V DIGITAL OUTPUTS, CMOS INTERFACE (SDOUT) VOH High-level output voltage VOL Low-level output voltage DVDD – 0.1 DVDD 0 V 0.1 V DIGITAL OUTPUTS, LVDS INTERFACE VODH High-level output differential voltage With an external 100-Ω termination 280 410 460 mV VODL Low-level output differential voltage With an external 100-Ω termination –460 –410 –280 mV VOCM Output common-mode voltage (1) 1.05 V SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up resistor is weak, SEN can also be driven by 1.8-V or 3.3-V CMOS buffers. 7.13 Timing Requirements: General Typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C. tA Aperture delay MIN TYP MAX UNIT 1.24 1.44 1.64 ns Aperture delay matching between two channels of the same device ±70 Variation of aperture delay between two devices at the same temperature and supply voltage tJ Aperture jitter Wake-up time ADC latency (1) tSU_SYSREF tH_SYSREF (1) SYSREF reference time ps ±150 ps 130 fS rms Time to valid data after exiting standby power-down mode 35 65 Time to valid data after exiting global power-down mode (in this mode, both channels power down) 85 140 2-wire mode (default) 9 1-wire mode 8 Setup time for SYSREF referenced to input clock rising edge 1000 Hold time for SYSREF referenced to input clock rising edge 100 µs Clock cycles ps Overall latency = ADC latency + tPDI. Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 17 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 7.14 Timing Requirements: LVDS Output Typical values are at 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, 7x serialization, CLOAD = 3.3 pF (1), and RLOAD = 100 Ω (2), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C. (3) (4) MIN TYP tSU Data setup time: data valid to zero-crossing of differential output clock (CLKOUTP – CLKOUTM) (5) 0.36 0.42 ns tHO Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid (5) 0.36 0.47 ns LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM) MAX UNIT 49% tPDI Clock propagation delay: input clock falling edge cross-over to frame clock rising edge cross-over 10 MSPS < sampling frequency < 125 MSPS tDELAY Delay time tFALL, tRISE Data fall time, data rise time: rise time measured from –100 mV to 100 mV, 10 MSPS ≤ Sampling frequency ≤ 125 MSPS 0.11 ns tCLKRISE, tCLKFALL Output clock rise time, output clock fall time: rise time measured from –100 mV to 100 mV, 10 MSPS ≤ Sampling frequency ≤ 125 MSPS 0.11 ns (1) (2) (3) (4) (5) 1-wire mode 2.7 2-wire mode 0.44 × tS + tDELAY 3 4.5 4.5 6.5 ns 5.9 ns CLOAD is the effective external single-ended load capacitance between each output pin and ground RLOAD is the differential load resistance between the LVDS output pair. Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Timing parameters are ensured by design and characterization and are not tested in production. Data valid refers to a logic high of +100 mV and a logic low of –100 mV. Table 1. LVDS Timings at Lower Sampling Frequencies: 7x Serialization (2-Wire Mode) SETUP TIME (tSU, ns) HOLD TIME (tHO, ns) SAMPLING FREQUENCY (MSPS) MIN TYP MIN TYP 25 2.27 2.6 2.41 2.6 40 1.44 1.6 1.51 1.7 50 1.2 1.32 1.24 1.4 60 0.95 1.04 0.97 1.09 80 0.68 0.75 0.72 0.81 100 0.5 0.57 0.53 0.62 MAX MAX Table 2. LVDS Timings at Lower Sampling Frequencies: 14x Serialization (1-Wire Mode) SETUP TIME (tSU, ns) SAMPLING FREQUENCY (MSPS) 18 MIN TYP 25 1.1 40 0.66 50 HOLD TIME (tHO, ns) MIN TYP 1.24 1.19 1.34 0.72 0.74 0.82 0.48 0.55 0.54 0.64 60 0.35 0.41 0.42 0.51 80 0.17 0.24 0.3 0.38 Submit Documentation Feedback MAX MAX Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 7.15 Typical Characteristics: ADC3241 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -60 -70 -80 -90 -100 -100 -110 -110 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 0 2.5 D701 SFDR = 97.9 dBc, SNR = 73.8 dBFS, SINAD = 73.8 dBFS, THD = 96.8 dBc, HD2 = –110.0 dBc, HD3 = –97.9 dBc 5 7.5 Frequency (MHz) 10 12.5 D702 SFDR = 89.8 dBc, SNR = 74.5 dBFS, SINAD = 74.3 dBFS, THD = 88.3 dBc, HD2 = –89.8 dBc, HD3 = –100.3 dBc Figure 1. FFT for 10-MHz Input Signal (Dither On) Figure 2. FFT for 10-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) -50 -90 -120 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 0 2.5 D703 SFDR = 91.8 dBc, SNR = 73.4 dBFS, SINAD = 73.4 dBFS, THD = 91.4 dBc, HD2 = –108.2 dBc, HD3 = –91.8 dBc 5 7.5 Frequency (MHz) 10 12.5 D704 SFDR = 90.2 dBc, SNR = 74.1 dBFS, SINAD = 73.9 dBFS, THD = 88.7 dBc, HD2 = –90.2 dBc, HD3 = –100.5 dBc Figure 3. FFT for 70-MHz Input Signal (Dither On) Figure 4. FFT for 70-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) -40 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 D705 0 2.5 5 7.5 Frequency (MHz) 10 12.5 D706 SFDR = 86.6 dBc, SNR = 72.1 dBFS, SINAD = 71.9 dBFS, THD = 84.7 dBc, HD2 = –89.8 dBc, HD3 = –86.6 dBc SFDR = 87.7 dBc, SNR = 72.5 dBFS, SINAD = 72.3 dBFS, THD = 85 dBc, HD2 = –87.7 dBc, HD3 = –91.2 dBc Figure 5. FFT for 170-MHz Input Signal (Dither On) Figure 6. FFT for 170-MHz Input Signal (Dither Off) Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 19 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3241 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 0 2.5 D707 5 7.5 Frequency (MHz) 10 12.5 D708 SFDR = 75.3 dBc, SNR = 70.0 dBFS, SINAD = 68.8 dBFS, THD = 73.8 dBc, HD2 = –75.3 dBc, HD3 = –79.6 dBc Figure 7. FFT for 270-MHz Input Signal (Dither On) Figure 8. FFT for 270-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) SFDR = 75.6 dBc, SNR = 69.8 dBFS, SINAD = 68.8 dBFS, THD = 74.8 dBc, HD2 = –75.6 dBc, HD3 = –82.5 dBc -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 0 2.5 D709 5 7.5 Frequency (MHz) 10 12.5 D710 SFDR = 67.9 dBc, SNR = 67.2 dBFS, SINAD = 67.2 dBFS, THD = 87.6 dBc, HD2 = –67.9 dBc, HD3 = –96.9 dBc Figure 9. FFT for 450-MHz Input Signal (Dither On) Figure 10. FFT for 450-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) SFDR = 68.4 dBc, SNR = 67.2 dBFS, SINAD = 67.2 dBFS, THD = 92.6 dBc, HD2 = –68.4 dBc, HD3 = –89.5 dBc -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 82.4 dBFS, each tone at –7 dBFS Figure 11. FFT for Two-Tone Input Signal (–7 dBFS at 46 MHz and 50 MHz) 20 -40 Submit Documentation Feedback D711 0 2.5 5 7.5 Frequency (MHz) 10 12.5 D712 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 90 dBFS, each tone at –36 dBFS Figure 12. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Typical Characteristics: ADC3241 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 0 2.5 5 7.5 Frequency (MHz) D713 10 12.5 D714 fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 78 dBFS, each tone at –7 dBFS fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 89 dBFS, each tone at –36 dBFS Figure 13. FFT for Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) Figure 14. FFT for Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) -80 -90 -85 Two-Tone IMD (dBFS) -95 Two-Tone IMD (dBFS) -40 -100 -105 -110 -115 -35 -90 -95 -100 -105 -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -110 -35 -7 -31 D715 Figure 15. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -7 D716 Figure 16. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 104 75 Dither_EN Dither_DIS 74 Dither_EN Dither_DIS 96 72 SFDR (dBc) SNR (dBFS) 73 71 70 88 80 72 69 64 68 56 67 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D717 Figure 17. Signal-to-Noise Ratio vs Input Frequency Copyright © 2014–2016, Texas Instruments Incorporated 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D718 Figure 18. Spurious-Free Dynamic Range vs Input Frequency Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 21 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3241 (continued) Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 120 73 100 SNR (dBFS) 280 SNR (dBFS) SFDR (dBc) 240 SFDR (dBFS) 74.5 73.5 200 72.5 160 71.5 120 70.5 80 40 72.5 80 72 60 71.5 40 69.5 20 68.5 -70 71 -70 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 0 SFDR (dBc,dBFS) 73.5 74.5 75.5 SNR (dBFS) 74 180 SNR (dBFS) SFDR (dBc) 160 SFDR (dBFS) 140 SFDR (dBc,dBFS) 75 0 -60 -50 D719 -40 -30 Amplitude (dBFS) -20 -10 0 D720 . Figure 19. Performance vs Input Amplitude (30 MHz) Figure 20. Performance vs Input Amplitude (170 MHz) 97.5 78 87.5 78 95 76 92.5 74 90 72 87.5 70 0.85 0.9 85 1.1 0.95 1 1.05 Input Common-Mode Voltage (V) SNR (dBFS) SNR SFDR SFDR (dBc) SNR (dBFS) SNR SFDR 76 85 74 82.5 72 80 70 77.5 68 0.85 D721 Figure 21. Performance vs Input Common-Mode Voltage (30 MHz) 75 1.1 0.95 1 1.05 Input Common-Mode Voltage (V) D722 Figure 22. Performance vs Input Common-Mode Voltage (170 MHz) 106 74 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 104 AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 73.7 102 100 SNR (dBc) SFDR (dBc) 0.9 SFDR (dBc) 80 98 96 AVDD = 1.85 V AVDD = 1.9 V 73.4 73.1 94 72.8 92 90 -40 -15 10 35 Temperature (°C) 60 85 D723 Figure 23. Spurious-Free Dynamic Range vs AVDD Supply and Temperature (30 MHz) 22 Submit Documentation Feedback 72.5 -40 -15 10 35 Temperature (°C) 60 85 D724 Figure 24. Signal-to-Noise Ratio vs AVDD Supply and Temperature (30 MHz) Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Typical Characteristics: ADC3241 (continued) Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 74.5 98 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 74.1 SFDR (dBc) 96 95 73.7 73.3 72.9 94 -15 10 35 Temperature (°C) 60 72.5 -40 85 Figure 25. Spurious-Free Dynamic Range vs DVDD Supply and Temperature (30 MHz) 73.8 96 73 88 72.2 80 71.4 72 70.6 64 69.8 56 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 2 SNR (dBFS) SNR (dBFS) 78 112 SNR SFDR 104 74.6 73.2 93 73 91.5 45 50 55 60 Input Clock Duty Cycle (%) 65 90 70 D729 Figure 29. Performance vs Clock Duty Cycle (30 MHz) Copyright © 2014–2016, Texas Instruments Incorporated SNR (dBFS) 94.5 40 72 85 70 82.5 68 80 66 77.5 64 75 72.5 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 70 2.2 2 D728 90 SNR SFDR SFDR (dBc) SNR (dBFS) 73.4 35 87.5 74 97.5 96 72.8 30 74 Figure 28. Performance vs Clock Amplitude (150 MHz) 99 73.6 D726 62 Figure 27. Performance vs Clock Amplitude (40 MHz) 73.8 85 76 D727 SNR SFDR 60 92.5 SNR SFDR 90 60 0.2 48 2.2 74 10 35 Temperature (°C) Figure 26. Signal-to-Noise Ratio vs DVDD Supply and Temperature (30 MHz) SFDR (dBc) 75.4 -15 D725 SFDR (dBc) 93 -40 69 0.2 DVDD = 1.85 V DVDD = 1.9 V 73.2 88 72.4 86 71.6 84 70.8 82 70 30 35 40 45 50 55 60 Input Clock Duty Cycle (%) 65 SFDR (dBc) SFDR (dBc) 97 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V DVDD = 1.9 V 80 70 D730 Figure 30. Performance vs Clock Duty Cycle (150 MHz) Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 23 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3241 (continued) Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 15 Code Occurrence (%) 12.5 10 7.5 5 2.5 8193 8194 8195 8196 8197 8198 8199 8200 8201 8202 8203 8204 8205 8206 8207 8208 8209 8210 8211 8212 0 D731 Output Code (LSB) RMS Noise = 1.33 LSBs Figure 31. Idle Channel Histogram 24 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 7.16 Typical Characteristics: ADC3242 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -60 -70 -80 -90 -100 -100 -110 -110 -120 0 5 10 15 Frequency (MHz) 20 25 0 5 D501 SFDR = 88.9 dBc, SFDR = 99.8 dBc (non 23), SNR = 73.6 dBFS, SINAD = 73.5 dBFS, THD = 88.8 dBc, HD2 = –111.4 dBc, HD3 = –88.9 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 20 25 D502 Figure 33. FFT for 10-MHz Input Signal (Dither Off) 0 -40 10 15 Frequency (MHz) SFDR = 84.7 dBc, SFDR = 96.1 dBc (non 23), SNR = 74.1 dBFS, SINAD = 73.8 dBFS, THD = 83.5 dBc, HD2 = –92.2 dBc, HD3 = –84.7 dBc Figure 32. FFT for 10-MHz Input Signal (Dither On) Amplitude (dBFS) -50 -90 -120 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 5 10 15 Frequency (MHz) 20 25 0 5 D503 SFDR = 85.8 dBc, SFDR = 100.3 dBc (non 23), SNR = 72.4 dBFS, SINAD = 72.2 dBFS, THD = 84.8 dBc, HD2 = –92.3 dBc, HD3 = –85.8 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 25 D504 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 20 Figure 35. FFT for 70-MHz Input Signal (Dither Off) 0 -40 10 15 Frequency (MHz) SFDR = 90.4 dBc, SFDR = 94.7 dBc (non 23), SNR = 73.9 dBFS, SINAD = 73.7 dBFS, THD = 87.5 dBc, HD2 = –91.9 dBc, HD3 = –90.4 dBc Figure 34. FFT for 70-MHz Input Signal (Dither On) Amplitude (dBFS) -40 -120 0 5 10 15 Frequency (MHz) 20 25 D505 SFDR = 85.8 dBc, SFDR = 99.1 dBc (non 23), SNR = 72.4 dBFS, SINAD = 72.2 dBFS, THD = 84.8 dBc, HD2 = –92.3 dBc, HD3 = –85.8 dBc Figure 36. FFT for 170-MHz Input Signal (Dither On) Copyright © 2014–2016, Texas Instruments Incorporated 0 5 10 15 Frequency (MHz) 20 25 D506 SFDR = 89.7 dBc, SFDR = 93 dBc (non 23), SNR = 72.9 dBFS, SINAD = 72.8 dBFS, THD = 86.6 dBc, HD2 = –89.7 dBc, HD3 = –107.7 dBc Figure 37. FFT for 170-MHz Input Signal (Dither Off) Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 25 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3242 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -60 -70 -80 -90 -100 -100 -110 -110 -120 0 5 10 15 Frequency (MHz) 20 25 0 5 D507 SFDR = 74.7 dBc, SFDR = 95.2 dBc (non 23), SNR = 70.7 dBFS, SINAD = 69.3 dBFS, THD = 73.8 dBc, HD2 = –74.7 dBc, HD3 = –81.1 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 20 25 D508 Figure 39. FFT for 270-MHz Input Signal (Dither Off) 0 -40 10 15 Frequency (MHz) SFDR = 74.6 dBc, SFDR = 91.1 dBc (non 23), SNR = 70.9 dBFS, SINAD = 69.2 dBFS, THD = 72.9 dBc, HD2 = –74.6 dBc, HD3 = –78.0 dBc Figure 38. FFT for 270-MHz Input Signal (Dither On) Amplitude (dBFS) -50 -90 -120 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 5 10 15 Frequency (MHz) 20 25 0 5 D509 10 15 Frequency (MHz) 20 25 D510 SFDR = 68.2 dBc, SNR = 69.2 dBFS, SINAD = 69.2 dBFS, THD = –86.4 dBc, HD2 = 68.2 dBc, HD3 = –90.3 dBc Figure 40. FFT for 450-MHz Input Signal (Dither On) Figure 41. FFT for 450-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) SFDR = 68.2 dBc, SNR = 69.0 dBFS, SINAD = 69.0 dBFS, THD = –85.7 dBc, HD2 = –68.2 dBc, HD3 = –86.5 dBc -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 5 10 15 Frequency (MHz) 20 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 87 dBFS, each tone at –7 dBFS Figure 42. FFT for Two-Tone Input Signal (–7 dBFS at 46 MHz and 50 MHz) 26 -40 Submit Documentation Feedback 25 D511 0 5 10 15 Frequency (MHz) 20 25 D512 D511 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 88 dBFS, each tone at –36 dBFS Figure 43. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Typical Characteristics: ADC3242 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -60 -70 -80 -90 -100 -100 -110 -110 -120 0 5 10 15 Frequency (MHz) 20 25 0 5 10 15 Frequency (MHz) D513 20 25 D514 fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 83 dBFS, each tone at –7 dBFS fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 85 dBFS, each tone at –36 dBFS Figure 44. FFT for Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) Figure 45. FFT for Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) -80 -85 -85 Two-Tone IMD (dBFS) -90 Two-Tone IMD (dBFS) -50 -90 -120 -95 -100 -105 -90 -95 -100 -105 -110 -35 -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -110 -35 -7 -31 D515 Figure 46. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -7 D516 Figure 47. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 74.5 104 Dither_EN Dither_DIS 73.5 Dither_EN Dither_DIS 96 72.5 SFDR (dBc) SNR (dBFS) -40 71.5 88 80 70.5 72 69.5 64 68.5 56 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D517 Figure 48. Signal-to-Noise Ratio vs Input Frequency Copyright © 2014–2016, Texas Instruments Incorporated 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D518 Figure 49. Spurious-Free Dynamic Range vs Input Frequency Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 27 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3242 (continued) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 120 72.5 100 74.5 73.5 200 72.5 160 71.5 120 70.5 80 40 72 80 71.5 60 71 40 69.5 20 68.5 -70 70.5 -70 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 0 0 -60 -50 D519 Figure 50. Performance vs Input Amplitude (30 MHz) 80 -40 -30 Amplitude (dBFS) -20 -10 D520 Figure 51. Performance vs Input Amplitude (170 MHz) 95 78 90 78 92.5 76 90 74 87.5 72 85 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) 82.5 1.1 SNR (dBFS) SNR SFDR SFDR (dBc) SNR (dBFS) SNR SFDR 70 0.85 0 76 87.5 74 85 72 82.5 70 80 68 0.85 D521 Figure 52. Performance vs Input Common-Mode Voltage (30 MHz) 0.9 SFDR (dBc) SNR (dBFS) 280 SNR (dBFS) SFDR (dBc) 240 SFDR (dBFS) SFDR (dBc,dBFS) 73 74 75.5 SNR (dBFS) 73.5 180 SNR (dBFS) SFDR (dBc) 160 SFDR (dBFS) 140 SFDR (dBc,dBFS) 74.5 77.5 1.1 0.95 1 1.05 Input Common-Mode Voltage (V) D522 Figure 53. Performance vs Input Common-Mode Voltage (170 MHz) 74 96 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 94 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V 73.7 AVDD = 1.85 V AVDD = 1.9 V 90 SNR (dBc) SFDR (dBc) 92 88 86 73.4 73.1 84 72.8 82 80 -40 -15 10 35 Temperature (°C) 60 85 D523 Figure 54. Spurious-Free Dynamic Range vs AVDD Supply and Temperature (30 MHz) 28 Submit Documentation Feedback 72.5 -40 -15 10 35 Temperature (°C) 60 85 D524 Figure 55. Signal-to-Noise Ratio vs AVDD Supply and Temperature (30 MHz) Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Typical Characteristics: ADC3242 (continued) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 74.5 92 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 91 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V DVDD = 1.9 V 74.1 DVDD = 1.85 V DVDD = 1.9 V SNR (dBc) SFDR (dBc) 90 89 88 73.7 73.3 87 72.9 86 10 35 Temperature (°C) 60 72.5 -40 85 Figure 56. Spurious-Free Dynamic Range vs DVDD Supply and Temperature (30 MHz) 74 92 73 90 72 88 71 86 70 84 69 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 2 90 84 69 81 66 78 63 75 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 91.5 90 88.5 45 50 55 60 Input Clock Duty Cycle (%) 65 87 70 D529 Figure 60. Performance vs Clock Duty Cycle (30 MHz) Copyright © 2014–2016, Texas Instruments Incorporated SNR (dBFS) 73.4 SFDR (dBc) SNR (dBFS) 93 40 72 2.2 D528 90 SNR SFDR 73.8 35 2 72.4 SNR SFDR 72.2 30 87 Figure 59. Performance vs Clock Amplitude (150 MHz) 94.5 72.6 D526 72 60 0.2 Figure 58. Performance vs Clock Amplitude (40 MHz) 73 85 SNR SFDR 75 82 2.2 74.2 60 78 SNR (dBFS) 75 96 SNR SFDR 94 10 35 Temperature (°C) Figure 57. Signal-to-Noise Ratio vs DVDD Supply and Temperature (30 MHz) SFDR (dBc) SNR (dBFS) 76 -15 D525 SFDR (dBc) -15 72.2 88 72 86 71.8 84 71.6 82 71.4 30 35 40 45 50 55 60 Input Clock Duty Cycle (%) 65 SFDR (dBc) 85 -40 80 70 D530 Figure 61. Performance vs Clock Duty Cycle (150 MHz) Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 29 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3242 (continued) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 20 Code Occurrence (%) 16 12 8 4 8211 8210 8209 8208 8207 8206 8205 8204 8203 8202 8201 8200 8199 8198 8197 8196 8195 0 D531 Output Code (LSB) RMS Noise = 1.3 LSBs Figure 62. Idle Channel Histogram 30 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 7.17 Typical Characteristics: ADC3243 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 8 16 24 Frequency (MHz) 32 40 0 8 D301 16 24 Frequency (MHz) 32 40 D302 SFDR = 84.2 dBc, SNR = 73.8 dBFS, SINAD = 73.4 dBFS, THD = 83.2 dBc, HD2 = –93.6 dBc, HD3 = –84.2 dBc Figure 63. FFT for 10-MHz Input Signal (Dither On) Figure 64. FFT for 10-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) SFDR = 88.9 dBc, SNR = 73.4 dBFS, SINAD = 73.3 dBFS, THD = 88.8 dBc, HD2 = –109.9 dBc, HD3 = –88.9 dBc -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 8 16 24 Frequency (MHz) 32 40 0 8 D303 16 24 Frequency (MHz) 32 40 D304 SFDR = 85.4 dBc, SNR = 73.6 dBFS, SINAD = 73.3 dBFS, THD = 83.7 dBc, HD2 = –91.2 dBc, HD3 = –85.4 dBc Figure 65. FFT for 70-MHz Input Signal (Dither On) Figure 66. FFT for 70-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) SFDR = 91.3 dBc, SNR = 73.2 dBFS, SINAD = 73.1 dBFS, THD = 91 dBc, HD2 = –109.5 dBc, HD3 = –91.3 dBc -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 8 16 24 Frequency (MHz) 32 40 D305 0 8 16 24 Frequency (MHz) 32 40 D306 SFDR = 94.9 dBc, SNR = 72.4 dBFS, SINAD = 72.4 dBFS, THD = 93.2 dBc, HD2 = –106.1 dBc, HD3 = –94.9 dBc SFDR = 92.3 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS, THD = 88 dBc, HD2 = –92.3 dBc, HD3 = –95.4 dBc Figure 67. FFT for 170-MHz Input Signal (Dither On) Figure 68. FFT for 170-MHz Input Signal (Dither Off) Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 31 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3243 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 8 16 24 Frequency (MHz) 32 40 0 8 D307 16 24 Frequency (MHz) 32 40 D308 SFDR = 75.4 dBc, SNR = 71.2 dBFS, SINAD = 69.8 dBFS, THD = 74.2 dBc, HD2 =–75.4 dBc, HD3 = –81.2 dBc Figure 69. FFT for 270-MHz Input Signal (Dither On) Figure 70. FFT for 270-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) SFDR = 75.4 dBc, SNR = 70.9 dBFS, SINAD = 69.6 dBFS, THD = 74.3 dBc, HD2 = –75.4 dBc, HD3 = –81.0 dBc -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 8 16 24 Frequency (MHz) 32 40 0 8 D309 16 24 Frequency (MHz) 32 40 D310 SFDR = 77.8 dBc, SNR = 68.8 dBFS, SINAD = 68.3 dBFS, THD = 77.5 dBc, HD2 = –77.8 dBc, HD3 = –91.8 dBc Figure 71. FFT for 450-MHz Input Signal (Dither On) Figure 72. FFT for 450-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) SFDR = 77.8 dBc, SNR = 68.8 dBFS, SINAD = 68.3 dBFS, THD = 77.5 dBc, HD2 = –77.8 dBc, HD3 = –91.8 dBc -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 8 16 24 Frequency (MHz) 32 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 87 dBFS, each tone at –7 dBFS Figure 73. FFT for Two-Tone Input Signal (–7 dBFS at 46 MHz and 50 MHz) 32 -40 Submit Documentation Feedback 40 D311 0 8 16 24 Frequency (MHz) 32 40 D312 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 92.8 dBFS, each tone at –36 dBFS Figure 74. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Typical Characteristics: ADC3243 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -60 -70 -80 -90 -100 -100 -110 -110 -120 0 8 16 24 Frequency (MHz) 32 40 0 8 16 24 Frequency (MHz) D313 32 40 D314 fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 78.8 dBFS, each tone at –7 dBFS fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 91 dBFS, each tone at –36 dBFS Figure 75. FFT FOR Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) Figure 76. FFT FOR Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) -80 -85 -85 Two-Tone IMD (dBFS) -90 Two-Tone IMD (dBFS) -50 -90 -120 -95 -100 -105 -90 -95 -100 -105 -110 -35 -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -110 -35 -7 -31 D315 Figure 77. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -7 D316 Figure 78. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 74.5 100 Dither_EN Dither_DIS 73.5 Dither_EN Dither_DIS 95 72.5 SFDR (dBc) SNR (dBFS) -40 71.5 90 85 70.5 80 69.5 75 68.5 70 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D317 Figure 79. Signal-to-Noise Ratio vs Input Frequency Copyright © 2014–2016, Texas Instruments Incorporated 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D318 Figure 80. Spurious-Free Dynamic Range vs Input Frequency Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 33 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3243 (continued) 73 120 72.5 80 71.5 71 70.5 -70 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 73 120 74 100 72 73.5 180 SNR (dBFS) SFDR (dBc) 160 SFDR (dBFS) 140 72.5 100 72 80 60 71.5 60 40 71 40 20 70.5 -70 0 20 -60 -50 D319 Figure 81. Performance vs Input Amplitude (30 MHz) 78 -40 -30 Amplitude (dBFS) -20 -10 D320 Figure 82. Performance vs Input Amplitude (170 MHz) 92 78 92 76 90 74 88 72 86 70 84 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) SNR (dBFS) SNR SFDR SFDR (dBc) SNR (dBFS) SNR SFDR 68 0.85 82 1.1 76 90 74 88 72 86 70 84 68 0.85 D321 Figure 83. Performance vs Input Common-Mode Voltage (30 MHz) 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) 82 1.1 D322 Figure 84. Performance vs Input Common-Mode Voltage (170 MHz) 74 95 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 73.5 SNR (dBFS) 93 SFDR (dBc) 0 SFDR (dBc) SNR (dBFS) 74 74.5 SNR (dBFS) 73.5 180 SNR (dBFS) SFDR (dBc) 160 SFDR (dBFS) 140 SFDR (dBc,dBFS) 74.5 SFDR (dBc,dBFS) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 91 89 AVDD = 1.85 V AVDD = 1.9 V 73 72.5 72 87 85 -40 71.5 -15 10 35 Temperature (°C) 60 85 D323 Figure 85. Spurious-Free Dynamic Range vs AVDD Supply and Temperature (170 MHz) 34 Submit Documentation Feedback 71 -40 -15 10 35 Temperature (°C) 60 85 D324 Figure 86. Signal-to-Noise Ratio vs AVDD Supply and Temperature (170 MHz) Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Typical Characteristics: ADC3243 (continued) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 74 95 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 73.5 SNR (dBFS) SFDR (dBc) 93 DVDD = 1.85 V DVDD = 1.9 V 91 89 DVDD = 1.85 V DVDD = 1.9 V 73 72.5 72 87 71.5 10 35 Temperature (°C) 60 71 -40 85 Figure 87. Spurious-Free Dynamic Range vs DVDD Supply and Temperature (170 MHz) 74.5 72.5 96 72 SNR (dBFS) 98 SFDR (dBc) SNR (dBFS) 100 73 71.5 0.2 80 102 73.5 94 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 2 92 2.2 76 90 74 88 72 86 70 84 68 82 66 80 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 88 73 87 72.6 86 85 70 D329 Figure 91. Performance vs Clock Duty cycle (30 MHz) Copyright © 2014–2016, Texas Instruments Incorporated SNR (dBFS) 73.4 SFDR (dBc) SNR (dBFS) 89 65 78 2.2 D328 92 SNR SFDR 73.8 45 50 55 60 Input Clock Duty Cycle (%) 2 72.8 SNR SFDR 40 D326 Figure 90. Performance vs Clock Amplitude (150 MHz) 90 35 85 78 64 0.2 Figure 89. Performance vs Clock Amplitude (40 MHz) 72.2 30 60 94 SNR SFDR 92 D327 74.2 10 35 Temperature (°C) Figure 88. Signal-to-Noise Ratio vs DVDD Supply and Temperature (170 MHz) 104 SNR SFDR 74 -15 D325 SFDR (dBc) -15 72.6 90 72.4 88 72.2 86 72 84 71.8 30 35 40 45 50 55 60 Input Clock Duty Cycle (%) 65 SFDR (dBc) 85 -40 82 70 D330 Figure 92. Performance vs Clock Duty Cycle (150 MHz) Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 35 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3243 (continued) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 24 22 Code Occurrence(%) 20 18 16 14 12 10 8 6 4 2 8211 8210 8209 8208 8207 8206 8205 8204 8203 8202 8201 8200 8199 8198 8197 0 D331 Output Code (LSB) RMS Noise = 1.28 LSBs Figure 93. Idle Channel Histogram 36 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 7.18 Typical Characteristics: ADC3244 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 0 SFDR = 102.6 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS, THD = 99.8 dBc, HD2 = –108.6 dBc, HD3 = –104.0 dBc 25 37.5 Frequency (MHz) 50 62.5 D102 SFDR = 91.8 dBc, SNR = 73.5 dBFS, SINAD = 73.4 dBFS, THD = 87.3 dBc, HD2 = –93.8 dBc, HD3 = –91.8 dBc Figure 94. FFT for 10-MHz Input Signal (Chopper On, Dither On) Figure 95. FFT for 10-MHz Input Signal (Chopper On, Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) 12.5 D101 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 0 12.5 D103 25 37.5 Frequency (MHz) 50 62.5 D104 SFDR = 90.9 dBc, SNR = 73.3 dBFS, SINAD = 73.1 dBFS, THD = 87 dBc, HD2 = –90.9 dBc, HD3 = –94.9 dBc Figure 96. FFT for 70-MHz Input Signal (Dither On) Figure 97. FFT for 70-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) SFDR = 95.9 dBc, SNR = 72.7 dBFS, SINAD = 72.7 dBFS, THD = 93.6 dBc, HD2 = –100.6 dBc, HD3 = –95.9 dBc -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D105 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D106 SFDR = 96.4 dBc, SNR = 72.1 dBFS, SINAD = 72.0 dBFS, THD = 92.6 dBc, HD2 = –96.4 dBc, HD3 = –98.8 dBc SFDR = 89.9 dBc, SNR = 72.8 dBFS, SINAD = 72.6 dBFS, THD = 87.1 dBc, HD2 = –97.2 dBc, HD3 = –89.9 dBc Figure 98. FFT for 170-MHz Input Signal (Dither On) Figure 99. FFT for 170-MHz Input Signal (Dither Off) Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 37 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3244 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -70 -80 -90 -100 -110 -110 -120 12.5 25 37.5 Frequency (MHz) 50 62.5 0 12.5 D107 SFDR = 76.1 dBc, SNR = 70.8 dBFS, SINAD = 69.8 dBFS, THD = 74.8 dBc, HD2 = –76.1 dBc, HD3 = –80.9 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 50 62.5 D108 Figure 101. FFT for 270-MHz Input Signal (Dither Off) 0 -40 25 37.5 Frequency (MHz) SFDR = 76.1 dBc, SNR = 71.2 dBFS, SINAD = 70.2 dBFS, THD = 74.9 dBc, HD2 = –76.1 dBc, HD3 = –81.6 dBc Figure 100. FFT for 270-MHz Input Signal (Dither On) Amplitude (dBFS) -60 -100 0 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 0 12.5 D109 SFDR = 76.2 dBc, SNR = 68.3 dBFS, SINAD = 67.5 dBFS, THD = 74.3 dBc, HD2 = –76.2 dBc, HD3 = –79.2 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 50 62.5 D110 Figure 103. FFT for 450-MHz Input Signal (Dither Off) 0 -40 25 37.5 Frequency (MHz) SFDR = 75.3 dBc, SNR = 69.1 dBFS, SINAD = 67.8 dBFS, THD = 72.7 dBc, HD2 = –76.7 dBc, HD3 = –75.3 dBc Figure 102. FFT for 450-MHz Input Signal (Dither On) Amplitude (dBFS) -50 -90 -120 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 38 -40 12.5 25 37.5 Frequency (MHz) 50 62.5 D111 0 12.5 25 37.5 Frequency (MHz) 50 62.5 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 88.3 dBFS, each tone at –7 dBFS fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 90.8 dBFS, each tone at –36 dBFS Figure 104. FFT for Two-Tone Input Signal (–7 dBFS at 46 MHz and 50 MHz) Figure 105. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Submit Documentation Feedback D112 Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Typical Characteristics: ADC3244 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 0 fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 86.4 dBFS, each tone at –7 dBFS 62.5 D114 -80 -85 Two-Tone IMD (dBFS) -90 Two-Tone IMD (dBFS) 50 Figure 107. FFT for Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) -85 -95 -100 -105 -90 -95 -100 -105 -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -110 -35 -7 -31 D115 Figure 108. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -7 D116 Figure 109. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 100 74 Dither_EN Dither_DIS 73 Dither_EN Dither_DIS 95 72 SFDR (dBc) SNR (dBFS) 25 37.5 Frequency (MHz) fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 87.28 dBFS, each tone at –36 dBFS Figure 106. FFT for Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) -110 -35 12.5 D113 71 90 85 70 80 69 75 70 68 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D117 Figure 110. Signal-to-Noise Ratio vs Input Frequency Copyright © 2014–2016, Texas Instruments Incorporated 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D118 Figure 111. Spurious-Free Dynamic Range vs Input Frequency Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 39 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3244 (continued) 73 120 72.5 80 71.5 71 70.5 -70 72.5 120 72 100 73.5 100 72 73 180 SNR (dBFS) SFDR (dBc) 160 SFDR (dBFS) 140 71.5 80 60 71 60 40 70.5 40 20 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 70 -70 0 20 -60 -50 D119 Figure 112. Performance vs Input Amplitude (30 MHz) 78 -40 -30 Amplitude (dBFS) -20 -10 D120 Figure 113. Performance vs Input Amplitude (170 MHz) 96 78 92 76 94 74 92 72 90 70 88 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) SNR (dBFS) SNR SFDR SFDR (dBc) SNR (dBFS) SNR SFDR 68 0.85 76 90 74 88 72 86 70 84 68 0.85 86 1.1 D121 Figure 114. Performance vs Input Common-Mode Voltage (30 MHz) 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) 82 1.1 Figure 115. Performance vs Input Common-Mode Voltage (170 MHz) 92 73 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 72.5 SNR (dBFS) 90 SFDR (dBc) 0 SFDR (dBc) SNR (dBFS) 74 74 SNR (dBFS) 73.5 180 SNR (dBFS) SFDR (dBc) 160 SFDR (dBFS) 140 SFDR (dBc,dBFS) 74.5 SFDR (dBc,dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 88 86 AVDD = 1.85 V AVDD = 1.9 V 72 71.5 71 84 70.5 82 -40 -15 10 35 Temperature (°C) 60 85 D123 Figure 116. Spurious-Free Dynamic Range vs AVDD Supply and Temperature (170 MHz) 40 Submit Documentation Feedback 70 -40 -15 10 35 Temperature (°C) 60 85 D124 Figure 117. Signal-to-Noise Ratio vs AVDD Supply and Temperature (170 MHz) Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Typical Characteristics: ADC3244 (continued) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 73 92 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 72.6 SNR (dBFS) 88 86 72.2 71.8 71.4 84 -15 10 35 Temperature (°C) 60 71 -40 85 Figure 118. Spurious-Free Dynamic Range vs DVDD Supply and Temperature (170 MHz) 74.5 60 85 D126 77 95 SNR SFDR 75 73.5 92 73 85 73 91 71 80 72.5 90 69 75 72 89 67 70 71.5 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 2 SNR (dBFS) 93 SFDR (dBc) SNR (dBFS) 10 35 Temperature (°C) Figure 119. Signal-to-Noise Ratio vs DVDD Supply and Temperature (170 MHz) 94 SNR SFDR 74 -15 D125 65 0.2 88 2.2 0.4 D127 Figure 120. Performance vs Clock Amplitude (40 MHz) 74.2 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) Figure 121. Performance vs Clock Amplitude (150 MHz) 90 93 73 92 72.6 91 45 50 55 60 Input Clock Duty Cycle (%) 65 90 70 D129 Figure 122. Performance vs Clock Duty Cycle (30 MHz) Copyright © 2014–2016, Texas Instruments Incorporated SNR (dBFS) 73.4 72.2 SFDR (dBc) 94 40 D128 SNR SFDR 73.8 35 65 2.2 72.4 95 SNR SFDR 72.2 30 2 90 SFDR (dBc) 82 -40 SNR (dBFS) DVDD = 1.85 V DVDD = 1.9 V 87.5 72 85 71.8 82.5 71.6 80 71.4 30 35 40 45 50 55 60 Input Clock Duty Cycle (%) 65 SFDR (dBc) SFDR (dBc) 90 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V DVDD = 1.9 V 77.5 70 D130 Figure 123. Performance vs Clock Duty Cycle (150 MHz) Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 41 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Characteristics: ADC3244 (continued) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 20 Code Occurrence (%) 16 12 8 4 8211 8210 8209 8208 8207 8206 8205 8204 8203 8202 8201 8200 8199 8198 8197 8196 8195 0 D131 Output Code (LSB) RMS Noise = 1.4 LSBs Figure 124. Idle Channel Histogram 42 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 7.19 Typical Characteristics: Common Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 0 -5 Amplitude (dBFS) -10 PSRR (dB) -15 -20 -25 -30 -35 -40 -45 -50 0 50 100 150 200 250 Frequency of Signal on Supply (MHz) 0 300 25 37.5 Frequency (MHz) 50 62.5 D002 D001 fIN = 30.1 MHz, fPSRR = 3 MHz, APSRR = 50 mVPP, SNR = 58.51 dBFS, SINAD = 58.51 dBFS, SFDR = 60.53 dBc, THD = –90.71 dBc, SFDR = 60.53 dBc (non 23) Figure 126. Power-Supply Rejection Ratio Spectrum Figure 125. Power-Supply Rejection Ratio vs Test Signal Frequency 0 -5 -10 Amplitude (dBFS) -15 -20 CMRR (dB) 12.5 D001 fIN = 30 MHz, AIN = –1 dBFS, test signal amplitude = 50 mVPP -25 -30 -35 -40 -45 -50 -55 -60 0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 50 100 150 200 250 Frequency of Input Common-Mode Signal (MHz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 300 12.5 D003 fIN = 30 MHz, AIN = –1 dBFS, test signal amplitude = 50 mVPP 25 37.5 Frequency (MHz) 50 62.5 D004 fIN = 170.1 MHz, fCMRR = 5 MHz, ACMRR = 50 mVPP, SNR = 69.72 dBFS, SINAD = 69.66 dBFS, SFDR = 75.66 dBc, THD = –86.98 dBc, SFDR = 75.66 dBc (non 23) Figure 128. Common-Mode Rejection Ratio Spectrum Figure 127. Common-Mode Rejection Ratio vs Test Signal Frequency Power Consumption (mW) 240 Analog Power Digital Power Total Power 200 160 120 80 40 5 15 25 35 45 55 65 75 85 95 105 115 125 Sampling Speed (MSPS) Figure 129. Power vs Sampling Frequency (One-Wire Mode) Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 43 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 7.20 Typical Characteristics: Contour Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when is chopper enabled, unless otherwise noted. 90 110 Sampling Frequency, MSPS 80 85 120 80 90 100 75 90 90 85 80 75 80 70 70 60 90 50 85 40 30 90 80 50 100 150 70 75 70 200 250 300 Input Frequency, MHz 75 350 80 400 450 85 90 Figure 130. Spurious-Free Dynamic Range (SFDR) 120 Sampling Frequency, MSPS 72.5 73 110 72 71.5 71 70.5 69.5 70 100 69 90 80 72.5 73 70 72 71.5 71 70.5 69.5 70 60 69 50 40 30 72.5 73 50 67 100 68 71.5 71 72 150 69 70.5 70 68.5 69.5 69 200 250 300 Input Frequency, MHz 70 68 350 71 400 72 67.5 450 73 Figure 131. Signal-to-Noise Ratio (SNR) 44 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 8 Parameter Measurement Information 8.1 Timing Diagrams DAn_P DBn_P Logic 0 Logic 1 VODL = -410 mV (1) VODH = +410 mV (1) DAn_M DBn_M VOCM GND (1) With an external 100-Ω termination. Figure 132. Serial LVDS Output Voltage Levels CLKIN FCLK DCLK Dx0P Dx0M 1-Wire (14x Serialization) D 13 D 1 D 0 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 1 D 0 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 0 CLKIN FCLK DCLK Dx0P Dx0M Dx1P Dx1M SAMPLE N-1 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 7 SAMPLE N 2-Wire (7x Serialization) SAMPLE N+1 Figure 133. Output Timing Diagram Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 45 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Timing Diagrams (continued) DCLK t HO Dx0P Dx0M t SU Figure 134. Setup and Hold Time N+10 N+1 N+9 Sample N TA Input Signal on INxP, INxM pins Data Latency(1) = 9 Input Clock Cycles Sample N CLKINP, CLKINM tPDI FCLKP, FCLKM DCLK edges are centered within the data valid window. DCLKP, DCLKM DA0P, DA0M, DB0P, DB0M DA1P, DA1M, DB1P, DB1M (1) 5 6 0 1 2 0 1 2 12 13 7 8 9 10 11 12 13 7 8 9 tsu th 3 4 5 Sample N 6 3 4 10 11 Sample N+1 Overall latency = data latency + tPDI. Figure 135. Latency Diagram 46 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 9 Detailed Description 9.1 Overview The ADC324x are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-todigital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC324x family supports serial LVDS interface in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. 9.2 Functional Block Diagram INAP INAM CLKP CLKM DA0P DA0M Digital Encoder and Serializer 14-Bit ADC Divide by 1,2,4 DA1P DA1M Bit Clock DCLKP DCLKM PLL Frame Clock SYSREFP SYSREFM Copyright © 2014–2016, Texas Instruments Incorporated DB1P DB1M SDOUT SDATA SCLK Configuration Registers RESET Common Mode DB0P DB0M Digital Encoder and Serializer PDN VCM 14-Bit ADC SEN INBP INBM FCLKP FCLKM Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 47 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 9.3 Feature Description 9.3.1 Analog Inputs The ADC324x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω termination between INP and INM). 9.3.2 Clock Input The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC324x can be driven by the transformercoupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 136, Figure 137, and Figure 138. See Figure 139 for details regarding the internal clock buffer. 0.1 mF 0.1 mF Zo CLKP Differential Sine-Wave Clock Input CLKP RT Typical LVDS Clock Input 0.1 mF 100 W CLKM Device 0.1 mF Zo NOTE: RT = termination resistor, if necessary. CLKM Figure 136. Differential Sine-Wave Clock Driving Circuit Zo Device Figure 137. LVDS Clock Driving Circuit 0.1 mF CLKP 150 W Typical LVPECL Clock Input 100 W Zo 0.1 mF CLKM Device 150 W Figure 138. LVPECL Clock Driving Circuit 48 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Clock Buffer LPKG 2 nH 20 W CLKP CBOND 1 pF CEQ CEQ 5 kW RESR 100 W 1.4 V LPKG 2 nH 20 W 5 kW CLKM CBOND 1 pF RESR 100 W NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer. Figure 139. Internal Clock Buffer A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 140. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. 0.1 mF CMOS Clock Input CLKP 0.1 mF CLKM Device Figure 140. Single-Ended Clock Driving Circuit 9.3.2.1 SNR and Clock Jitter The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization noise (typically 86 dB for a 14-bit ADC) and thermal noise limit SNR at low input frequencies while the clock jitter sets SNR for higher input frequencies. SNRADC[dBc] § 20 ˜ log ¨10 ¨ © SNR Quantizatoin Noise 20 · ¸ ¸ ¹ 2 § ¨10 ¨ © SNR Thermal Noise 20 · ¸ ¸ ¹ 2 § ¨10 ¨ © SNR Jitter 20 · ¸ ¸ ¹ 2 (1) The SNR limitation resulting from sample clock jitter can be calculated with Equation 2. SNRJitter [dBc] 20 ˜ log( 2S ˜ f in ˜ TJitter ) (2) The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fs for the device) which is set by the noise of the clock input buffer and the external clock. TJitter can be calculated with Equation 3. TJitter (TJitter , Ext .Clock _ Input ) 2 (TAperture _ ADC ) 2 Copyright © 2014–2016, Texas Instruments Incorporated (3) Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 49 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band pass filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The ADC324x has a typical thermal noise of 73.5 dBFS and internal aperture jitter of 130 fs. Figure 141 shows SNR (from 1 MHz offset leaving the 1/f flicker noise) for different jitter of clock driver. 73.0 Ext Clock Jitter 35 fs 50 fs 100 fs 150 fs 200 fs 72.5 72.0 SNR (dBFS) 71.5 71.0 70.5 70.0 69.5 69.0 68.5 68.0 67.5 67.0 10 100 Input Frequency (MHz) 1000 D001 D036 Figure 141. SNR vs Frequency for Different Clock Jitter 9.3.3 Digital Output Interface The devices offer two different output format options, thus making interfacing to a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using the serial interface, as shown in Table 3. The output interface options are: • One-wire, 1x frame clock, 14x serialization with the DDR bit clock and • Two-wire, 0.5x frame clock, 7x serialization with the DDR bit clock. Table 3. Interface Rates INTERFACE OPTIONS 1-wire 2-wire (default after reset) (1) SERIALIZATION 14x 7x RECOMMENDED SAMPLING FREQUENCY (MSPS) MINIMUM MAXIMUM BIT CLOCK FREQUENCY (MHz) FRAME CLOCK FREQUENCY (MHz) SERIAL DATA RATE (Mbps) 15 (1) — 105 15 210 — 80 560 80 1120 20 (1) — 70 10 140 — 125 437.5 62.5 875 Use the LOW SPEED ENABLE register bits for low speed operation; see Table 22. 9.3.3.1 One-Wire Interface: 14x Serialization In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every frame clock, starting with the MSB. The data rate is 14x sample frequency (14x serialization). 50 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 9.3.3.2 Two-Wire Interface: 7x Serialization The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is 7x sample frequency because seven data bits are output every clock cycle on each differential pair. Each ADC sample is sent over the two wires with the seven MSBs on Dx1P, Dx1M and the seven LSBs on Dx0P, Dx0M, as shown in Figure 142. Note that in two-wire mode, the frame clock (FCLK) frequency is half of sampling clock (CLKIN) frequency. CLKIN FCLK DCLK Dx0P Dx0M 1-Wire (14x Serialization) D 13 D 1 D 0 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 1 D 0 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 0 CLKIN FCLK DCLK Dx0P Dx0M Dx1P Dx1M SAMPLE N-1 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 7 SAMPLE N 2-Wire (7x Serialization) SAMPLE N+1 Figure 142. Output Timing Diagram Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 51 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 9.4 Device Functional Modes 9.4.1 Input Clock Divider The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed for operation with a 125-MHz clock while the divide-by-2 option supports a maximum input clock of 250 MHz and the divide-by-4 option provides a maximum input clock frequency of 500 MHz. 9.4.2 Chopper Functionality 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC noise spectrum by shifting the 1/f noise from dc to fS / 2. Figure 143 shows the noise spectrum with the chopper off and Figure 144 shows the noise spectrum with the chopper on. This function is especially useful in applications requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper can be enabled via SPI register writes and is recommended for input frequencies below 30 MHz. The chopper function creates a spur at fS / 2 that must be filtered out digitally. -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 0 D052 fIN = 10 MHz, fS = 125 MHz 12.5 25 37.5 Frequency (MHz) 50 62.5 D051 fIN = 10 MHz, fS = 125 MHz Figure 143. Chopper Off Figure 144. Chopper On 9.4.3 Power-Down Control The power-down functions of the ADC324x can be controlled either through the parallel control pin (PDN) or through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global powerdown or standby functionality, as shown in Table 4. Table 4. Power-Down Modes 52 FUNCTION POWER CONSUMPTION (mW) WAKE-UP TIME (µs) Global power-down 5 85 Standby 81 35 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 9.4.3.1 Improving Wake-Up Time From Global Power-Down The device has an internal low-pass filter in the sampling clock path. This low-pass filter helps improve the aperture jitter of the device. However, in applications where input frequencies are < 200 MHz, noise from the aperture jitter does not dominate the overall SNR of the device. In such applications, the wake-up time from a global power-down can be reduced by bypassing the low-pass filter using the DIS CLK FILT register bit (write 80h to register address 70Ah). As shown in Table 5, setting the DIS CLK FILT bit improves the wake-up time from a global power-down from 85 µs to 55 µs. Table 5. Wake-Up Time From Global Power-Down WAKE-UP TIME DIS CLK FILT REGISTER BIT GLOBAL PDN REGISTER BIT TYP MAX UNIT 0 0→1→0 85 140 µs 1 0→1→0 55 81 µs 9.4.4 Internal Dither Algorithm 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) The ADC324x use an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm can be turned off by using the DIS DITH CHx registers bits. Figure 145 and Figure 146 show the effect of using dither algorithms. -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D103 SFDR = 95.9 dBc, SNR = 72.7 dBFS, SINAD = 72.7 dBFS, THD = 93.6 dBc, HD2 = –100.6 dBc, HD3 = –95.9 dBc Figure 145. FFT with Dither On 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D104 SFDR = 90.9 dBc, SNR = 73.3 dBFS, SINAD = 73.1 dBFS, THD = 87 dBc, HD2 = –90.9 dBc, HD3 = –94.9 dBc Figure 146. FFT with Dither Off 9.5 Programming The ADC324x can be configured using a serial programming interface, as described in this section. 9.5.1 Serial Interface The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle. Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 53 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Programming (continued) 9.5.1.1 Register Initialization After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 147. If required, the serial interface registers can be cleared during operation either: 1. Through a hardware reset, or 2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low. 9.5.1.1.1 Serial Register Write The device internal register can be programmed with these steps: 1. Drive the SEN pin low, 2. Set the R/W bit to 0 (bit A15 of the 16-bit address), 3. Set bit A14 in the address field to 1, 4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be written, and 5. Write the 8-bit data that are latched in on the SCLK rising edge. Figure 147 and Table 6 show the timing requirements for the serial register write operation. Register Address [13:0] SDATA R/W 1 A13 A12 A11 A1 Register Data [7:0] A0 D7 D6 D5 D4 =0 D3 D2 D1 D0 tDH tSCLK tDSU SCLK tSLOADS tSLOADH SEN RESET Figure 147. Serial Register Write Timing Diagram Table 6. Serial Interface Timing (1) MIN TYP UNIT 20 MHz fSCLK SCLK frequency (equal to 1 / tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDIO setup time 25 ns tDH SDIO hold time 25 ns (1) 54 > dc MAX Typical values are at 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, and AVDD = DVDD = 1.8 V, unless otherwise noted. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 9.5.1.1.2 Serial Register Readout The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin. This readback mode can be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. Given below is the procedure to read contents of serial registers: 1. Drive the SEN pin low. 2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers. 3. Set bit A14 in the address field to 1. 4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read. 5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin. 6. The external controller can latch the contents at the SCLK rising edge. 7. To enable register writes, reset the R/W register bit to 0. When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 148 shows a timing diagram of the serial register read operation. Data appear on the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 149. Register Data: 'RQ¶W &DUH Register Address [13:0] SDATA R/W 1 A13 A12 A11 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 =1 Register Read Data [7:0] SDOUT D7 D6 D5 D4 D3 D2 SCLK SEN Figure 148. Serial Register Read Timing Diagram SCLK tSD_DELAY SDOUT Figure 149. SDOUT Timing Diagram Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 55 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 9.5.2 Register Initialization After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 150 and Table 7. Power Supplies t1 RESET t2 t3 SEN Figure 150. Initialization of Serial Registers after Power-Up Table 7. Power-Up Timing MIN t1 Power-on delay: delay from power up to active high RESET pulse t2 Reset pulse duration: active high RESET pulse duration t3 Register write delay: delay from RESET disable to SEN active TYP MAX 1 10 100 UNIT ms 1000 ns ns If required, the serial interface registers can be cleared during operation either: 1. Through hardware reset, or 2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low. 56 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 9.6 Register Maps Table 8. Register Map Summary REGISTER ADDRESS REGISTER DATA A[13:0] (Hex) D7 D6 01 0 0 D5 D4 D3 03 0 0 0 0 0 04 0 0 0 0 0 05 0 0 0 0 0 DIS DITH CHA D2 D1 D0 0 0 0 0 ODD EVEN 0 0 FLIP WIRE 0 0 1W-2W TEST PATTERN EN RESET DIS DITH CHB 06 0 0 0 0 0 0 07 0 0 0 0 0 0 0 OVR ON LSB 0 0 ALIGN TEST PATTERN DATA FORMAT 0 0 0 0 0 0 LOW SPEED ENABLE 09 0 0A 0 0B 0 0 0 0 0 0 CHB TEST PATTERN CHA TEST PATTERN 0 0E CUSTOM PATTERN[13:6] 0F CUSTOM PATTERN[5:0] 13 0 0 0 0 0 0 15 0 CHA PDN CHB PDN 0 STANDBY GLOBAL PDN 0 0 0 0 0 0 25 0 CONFIG PDN PIN 0 0 0 0 HIGH IF MODE0 0 LVDS SWING 27 CLK DIV 41D 0 0 422 0 0 0 0 0 0 DIS CHOP CHA 0 434 0 0 DIS DITH CHA 0 DIS DITH CHA 0 0 0 439 0 0 0 0 SP1 CHA 0 0 0 51D 0 0 0 0 0 0 HIGH IF MODE1 0 522 0 0 0 0 0 0 DIS CHOP CHB 0 534 0 0 DIS DITH CHB 0 DIS DITH CHB 0 0 0 539 0 0 0 0 SP1 CHB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDN SYSREF 608 70A HIGH IF MODE[3:2] DIS CLK FILT 0 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 57 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 9.6.1 Summary of Special Mode Registers Table 9 lists the location, value, and functions of special mode registers in the device. Table 9. Special Modes Summary MODE REGISTER SETTINGS DESCRIPTION Special modes Registers 439h (bit 3) and 539h (bit 3) Always set these bits high for best performance Disable dither Registers 1h (bits 5-2), 434h (bits 5 and 3), and 534h (bits 5 and 3) Disable dither to improve SNR Disable chopper Registers 422h (bit 1) and 522h (bit 1) Disable chopper to shift 1/f noise floor at dc High IF modes Registers 41Dh (bit 1), 51Dh (bit 1), and 608h (bits 7-6) Improves HD3 for IF > 100 MHz 9.6.2 Serial Register Description 9.6.2.1 Register 01h Figure 151. Register 01h 7 0 W-0h 6 0 W-0h 5 4 3 DIS DITH CHA R/W-0h 2 DIS DITH CHB R/W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 10. Register 01h Description Bit Field Type Reset Description 7-6 0 W 0h Must write 0 0h These bits enable or disable the on-chip dither. Control this bit with bits 5 and 3 of register 434h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. 5-4 DIS DITH CHA R/W 3-2 DIS DITH CHB R/W 0h These bits enable or disable the on-chip dither. Control this bit with bits 5 and 3 of register 434h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. 1-0 0 W 0h Must write 0 9.6.2.2 Register 03h Figure 152. Register 03h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 ODD EVEN R/W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 11. Register 03h Description Bit Field Type Reset Description 7-1 0 W 0h Must write 0 ODD EVEN R/W 0h This bit selects the bit sequence on the output lanes (in 2-wire mode only). 0 = Bits 0, 1, and 2 appear on lane 0; bits 7, 8, and 9 appear on lane 1 1 = Bits 0, 2, and 4 appear on lane 0; bits 1, 3, and 5 appear on lane 1 0 58 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 9.6.2.3 Register 04h Figure 153. Register 04h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 FLIP WIRE R/W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 12. Register 04h Description Bit Field Type Reset Description 7-1 0 W 0h Must write 0 0h This bit flips the data on the output wires. Valid only in two wire configuration. 0 = Default 1 = Data on output wires is flipped. Pin D0x becomes D1x, and vice versa. 0 FLIP WIRE R/W 9.6.2.4 Register 05h Figure 154. Register 05h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 1W-2W R/W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 13. Register 05h Description Bit Field Type Reset Description 7-1 0 W 0h Must write 0 0h This bit transmits output data on either one or two wires. 0 = Output data are transmitted on two wires (Dx0P, Dx0M and Dx1P, Dx1M) 1 = Output data are transmitted on one wire (Dx0P, Dx0M). In this mode, the recommended fS is less than 62.5 MSPS. 0 1W-2W R/W 9.6.2.5 Register 06h Figure 155. Register 06h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 TEST PATTERN EN R/W-0h 0 RESET W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 14. Register 06h Description Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1 TEST PATTERN EN R/W 0h This bit enables test pattern selection for the digital outputs. 0 = Normal output 1 = Test pattern output enabled 0 RESET W 0h This bit applies a software reset. This bit resets all internal registers to the default values and selfclears to 0. Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 59 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 9.6.2.6 Register 07h Figure 156. Register 07h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 OVR ON LSB R/W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 15. Register 07h Description Bit Field Type Reset Description 7-1 0 W 0h Must write 0 OVR ON LSB R/W 0h This bit provides the overrange (OVR) information on the LSB bits. 0 = Output data bit 0 functions as the LSB of the 14-bit data 1 = Output data bit 0 carries the OVR information. 0 9.6.2.7 Register 09h Figure 157. Register 09h 7 6 5 4 3 2 0 0 0 0 0 0 W-0h W-0h W-0h W-0h W-0h W-0h 1 ALIGN TEST PATTERN R/W-0h 0 DATA FORMAT R/W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 16. Register 09h Description 60 Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1 ALIGN TEST PATTERN R/W 0h This bit aligns the test patterns across the outputs of both channels. 0 = Test patterns of both channels are free running 1 = Test patterns of both channels are aligned 0 DATA FORMAT R/W 0h This bit programs the digital output data format. 0 = Twos complement 1 = Offset binary Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 9.6.2.8 Register 0Ah Figure 158. Register 0Ah 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 2 1 CHA TEST PATTERN R/W-0h 0 LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 17. Register 0Ah Description Bit Field Type Reset Description 7-4 0 W 0h Must write 0 0h These bits control the test pattern for channel A after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits 0110 = Deskew pattern: data are 2AAAh 1000 = PRBS pattern: data are a sequence of pseudo random numbers 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399. Others = Do not use 3-0 CHA TEST PATTERN R/W 9.6.2.9 Register 0Bh Figure 159. Register 0Bh 7 6 5 CHB TEST PATTERN R/W-0h 4 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 18. Register 0Bh Description Bit Field Type Reset Description 7-4 CHB TEST PATTERN R/W 0h These bits control the test pattern for channel B after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits 0110 = Deskew pattern: data are 2AAAh 1000 = PRBS pattern: data are a sequence of pseudo random numbers 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399. Others = Do not use 3-0 0 W 0h Must write 0 Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 61 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 9.6.2.10 Register 0Eh Figure 160. Register 0Eh 7 6 5 4 3 CUSTOM PATTERN[13:6] R/W-0h 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 19. Register 0Eh Description Bit Field Type Reset Description 7-0 CUSTOM PATTERN[13:6] R/W 0h These bits set the 14-bit custom pattern (bits 13-6) for all channels. 9.6.2.11 Register 0Fh Figure 161. Register 0Fh 7 6 5 4 CUSTOM PATTERN[5:0] R/W-0h 3 2 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 20. Register 0Fh Description 62 Bit Field Type Reset Description 7-2 CUSTOM PATTERN[5:0] R/W 0h These bits set the 14-bit custom pattern (bits 5-0) for all channels. 1-0 0 W 0h Must write 0 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 9.6.2.12 Register 13h (address = 13h) Figure 162. Register 13h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 LOW SPEED ENABLE R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 21. Register 13h Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1-0 LOW SPEED ENABLE R/W 0h Enables low speed operation in 1-wire and 2-wire mode. Depending upon sampling frequency, write this bit as per Table 22. Table 22. LOW SPEED ENABLE Register Bit Settings Across fS fS (MSPS) REGISTER BIT LOW SPEED ENABLE MIN MAX 1-WIRE MODE 2-WIRE MODE 25 125 00 00 20 25 00 10 15 20 10 Not supported 9.6.2.13 Register 15h Figure 163. Register 15h 7 0 W-0h 6 CHA PDN R/W-0h 5 CHB PDN R/W-0h 4 0 W-0h 3 STANDBY R/W-0h 2 GLOBAL PDN R/W-0h 1 0 W-0h 0 CONFIG PDN PIN R/W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 23. Register 15h Description Bit Field Type Reset Description 7 0 W 0h Must write 0 6 CHA PDN R/W 0h 0 = Normal operation 1 = Power-down channel A 5 CHB PDN R/W 0h 0 = Normal operation 1 = Power-down channel B 4 0 W 0h Must write 0 3 STANDBY R/W 0h The ADCs of both channels enter standby. 0 = Normal operation 1 = Standby 2 GLOBAL PDN R/W 0h 0 = Normal operation 1 = Global power-down 1 0 W 0h Must write 0 0h This bit configures the PDN pin as either a global power-down or standby pin. 0 = Logic high voltage on the PDN pin sends the device into global power-down 1 = Logic high voltage on the PDN pin sends the device into standby 0 CONFIG PDN PIN R/W Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 63 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 9.6.2.14 Register 25h Figure 164. Register 25h 7 6 5 4 3 2 1 0 LVDS SWING R/W-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 24. Register 25h Description Bit Field Type Reset Description 7-0 LVDS SWING R/W 0h These bits control the swing of the LVDS outputs (including the data output, bit clock, and frame clock). For details see Table 25. Table 25. LVDS Output Swing BITS 7-4 BITS 3-0 LVDS OUTPUT SWING 0h 0h Default (±425 mV) Dh 9h Swing reduces by 50 mV Eh Ah Swing reduces by 100 mV Fh Dh Swing reduces by 300 mV Ch Eh Swing increases by 100 mV Others Others Do not use 9.6.2.15 Register 27h Figure 165. Register 27h 7 6 CLK DIV R/W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 26. Register 27h Description Bit 64 Field Type Reset Description 7-6 CLK DIV R/W 0h These bits set the internal clock divider for the input sampling clock. 00 = Divide-by-1 01 = Divide-by-1 10 = Divide-by-2 11 = Divide-by-4 5-0 0 W 0h Must write 0 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 9.6.2.16 Register 41Dh Figure 166. Register 41Dh 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 HIGH IF MODE0 R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 27. Register 41Dh Description Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1 HIGH IF MODE0 R/W 0h This bit improves HD3 for IF > 100 MHz. 0 = Normal operation For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111. 0 0 W 0h Must write 0 9.6.2.17 Register 422h Figure 167. Register 422h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 DIS CHOP CHA R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 28. Register 422h Description Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1 DIS CHOP CHA R/W 0h Disable chopper. Set this bit to shift a 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc 0 0 W 0h Must write 0 9.6.2.18 Register 434h Figure 168. Register 434h 7 0 W-0h 6 0 W-0h 5 DIS DITH CHA R/W-0h 4 0 W-0h 3 DIS DITH CHA R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 29. Register 434h Description Bit Field Type Reset Description 7-6 0 W 0h Must write 0 5 DIS DITH CHA R/W 0h Set this bit with bits 5 and 4 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. 4 0 W 0h Must write 0 3 2-0 DIS DITH CHA R/W 0h Set this bit with bits 5 and 4 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. 0 W 0h Must write 0 Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 65 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 9.6.2.19 Register 439h Figure 169. Register 439h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 SP1 CHA R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 30. Register 439h Description Bit Field Type Reset Description 7-4 0 W 0h Must write 0 SP1 CHA R/W 0h Special mode for best performance on channel A. Always write 1 after reset. 0 W 0h Must write 0 3 2-0 9.6.2.20 Register 51Dh Figure 170. Register 51Dh 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 HIGH IF MODE1 R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 31. Register 51Dh Description Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1 HIGH IF MODE1 R/W 0h This bit improves HD3 for IF > 100 MHz. 0 = Normal operation For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111. 0 0 W 0h Must write 0 9.6.2.21 Register 522h Figure 171. Register 522h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 DIS CHOP CHB R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 32. Register 522h Description 66 Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1 DIS CHOP CHB R/W 0h Disable chopper. Set this bit to shift a 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc 0 0 W 0h Must write 0 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 9.6.2.22 Register 534h Figure 172. Register 534h 7 0 W-0h 6 0 W-0h 5 DIS DITH CHA R/W-0h 4 0 W-0h 3 DIS DITH CHA R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 33. Register 534h Description Bit Field Type Reset Description 7-6 0 W 0h Must write 0 5 DIS DITH CHA R/W 0h Set this bit with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. 4 0 W 0h Must write 0 3 DIS DITH CHA R/W 0h Set this bit with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. 0 W 0h Must write 0 2-0 9.6.2.23 Register 539h Figure 173. Register 539h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 SP1 CHB R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 34. Register 539h Description Bit Field Type Reset Description 7-4 0 W 0h Must write 0 3 SP1 CHB R/W 0h Special mode for best performance on channel B. Always write 1 after reset. 0 0 W 0h Must write 0 9.6.2.24 Register 608h Figure 174. Register 608h 7 6 HIGH IF MODE[3:2] R/W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 35. Register 608h Description Bit Field Type Reset Description 7-6 HIGH IF MODE[3:2] R/W 0h This bit improves HD3 for IF > 100 MHz. 0 = Normal operation For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111. 5-0 0 W 0h Must write 0 Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 67 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 9.6.2.25 Register 70Ah Figure 175. Register 70Ah 7 DIS CLK FILT R/W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 PDN SYSREF R/W-0h LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset Table 36. Register 70Ah Description Bit 7 6-1 0 68 Field Type Reset Description DIS CLK FILT R/W 0h Set this bit to improve wake-up time from global power-down mode; see the Improving Wake-Up Time From Global PowerDown section for details. 0 W 0h Must write 0 0h If the SYSREF pins are not used in the system, the SYSREF buffer must be powered down by setting this bit. 0 = Normal operation 1 = Powers down the SYSREF buffer PDN SYSREF R/W Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 10 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information Typical applications involving transformer coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. While designing the dc driving circuits, the ADC input impedance must be considered. Figure 176 and Figure 177 show the impedance (Zin = Rin || Cin) across the ADC input pins. 6 Differential Capacitance, Cin (pF) Differential Resistance, Rin (kOhm) 10 1 0.1 5 4 3 2 1 0.01 0 100 200 300 400 500 600 700 Frequency (MHz) 800 900 1000 Figure 176. Differential Input Resistance (RIN) Copyright © 2014–2016, Texas Instruments Incorporated D024 0 100 200 300 400 500 600 700 Frequency (MHz) 800 900 1000 D025 D001 Figure 177. Differential Input Capacitance (CIN) Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 69 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 10.2 Typical Applications 10.2.1 Driving Circuit Design: Low Input Frequencies 39 nH 0.1 PF INP 0.1 PF 50 Ÿ 0.1 PF 50 Ÿ 25 Ÿ 22 pF 25 Ÿ 50 Ÿ 50 Ÿ INM 1:1 1:1 0.1 PF 39 nH VCM Device Figure 178. Driving Circuit for Low Input Frequencies 10.2.1.1 Design Requirements For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source. 10.2.1.2 Detailed Design Procedure A typical application involving using two back-to-back coupled transformers is shown in Figure 178. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used with the series inductor (39 nH), this combination helps absorb the sampling glitches. 10.2.1.3 Application Curve Figure 179 shows the performance obtained by using circuit shown in Figure 178. 0 -10 -20 Amplitude (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D101 SFDR = 102.6 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS, THD = 99.8 dBc, HD2 = –108.6 dBc, HD3 = –104.0 dBc Figure 179. Performance FFT at 10 MHz (Low Input Frequency) 70 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 Typical Applications (continued) 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz 0.1 PF 10 Ÿ INP 0.1 PF 0.1 PF 15 Ÿ 25 Ÿ 56 nH 10 pF 25 Ÿ 15 Ÿ INM 1:1 1:1 10 Ÿ 0.1 PF VCM Device Figure 180. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz) 10.2.2.1 Design Requirements See the Design Requirements section for further details. 10.2.2.2 Detailed Design Procedure When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize performance, as shown in Figure 180. 10.2.2.3 Application Curve Figure 181 shows the performance obtained by using circuit shown in Figure 180. 0 -10 -20 Amplitude (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D105 SFDR = 96.4 dBc, SNR = 72.1 dBFS, SINAD = 72.0 dBFS, THD = 92.6 dBc, HD2 = –96.4 dBc, HD3 = –98.8 dBc Figure 181. Performance FFT at 170 MHz (Mid Input Frequency) Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 71 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com Typical Applications (continued) 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz 0.1 PF 0.1 PF 10 Ÿ INP 0.1 PF 25 Ÿ 25 Ÿ INM 1:1 1:1 10 Ÿ 0.1 PF VCM Device Figure 182. Driving Circuit for High input Frequencies ( fIN > 230 MHz) 10.2.3.1 Design Requirements See the Design Requirements section for further details. 10.2.3.2 Detailed Design Procedure For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 182. 10.2.3.3 Application Curve Figure 183 shows the performance obtained by using circuit shown in Figure 182. 0 -10 -20 Amplitude (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D109 SFDR = 76.2 dBc, SNR = 68.3 dBFS, SINAD = 67.5 dBFS, THD = 74.3 dBc, HD2 = –76.2 dBc, HD3 = –79.2 dBc Figure 183. Performance FFT at 450 MHz (High Input Frequency) 11 Power-Supply Recommendations The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply requirements during device power-up. AVDD and DVDD can power up in any order. 72 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 ADC3241, ADC3242, ADC3243, ADC3244 www.ti.com SBAS671C – JULY 2014 – REVISED MARCH 2016 12 Layout 12.1 Layout Guidelines The ADC324x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in Figure 184. Some important points to remember during laying out the board are: 1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the package level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions, as shown in the reference layout of Figure 184 as much as possible. 2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling between them. This configuration is also maintained on the reference layout of Figure 184 as much as possible. 3. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, do not keep the digital output traces parallel to the analog input traces because this configuration can result in coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be matched in length to avoid skew among outputs. 4. At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF capacitors can be kept close to the supply source. 12.2 Layout Example Analog Input Routing Sampling Clock Routing ADC32xx Digital Output Routing Figure 184. Typical Layout of the ADC324x Board Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 73 ADC3241, ADC3242, ADC3243, ADC3244 SBAS671C – JULY 2014 – REVISED MARCH 2016 www.ti.com 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 37. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADC3241 Click here Click here Click here Click here Click here ADC3242 Click here Click here Click here Click here Click here ADC3243 Click here Click here Click here Click here Click here ADC3244 Click here Click here Click here Click here Click here 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks E2E is a trademark of Texas Instruments. PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 74 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ADC3241 ADC3242 ADC3243 ADC3244 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADC3241IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ3241 ADC3241IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ3241 ADC3242IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ3242 ADC3242IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ3242 ADC3243IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ3243 ADC3243IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ3243 ADC3244IRGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ3244 ADC3244IRGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ3244 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of