LTC1629IG#PBF

LTC1629/LTC1629-PG PolyPhase, High Efficiency, Synchronous Step-Down Switching Regulators U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Dual Controller Operates from One to Twelve Phases Reduces Required Input Capacitance and Power Supply Induced Noise Current Mode Control Ensures Current Sharing Phase-Lockable Fixed Frequency: 150kHz to 300kHz 1.8MHz Effective Switching Frequency True Remote Sensing Differential Amplifier OPTI-LOOPTM Compensation Reduces COUT ±1% Output Voltage Accuracy Power Good Output Voltage Monitor (LTC1629-PG) Wide VIN Range: 4V to 36V Operation Very Low Dropout Operation: 99% Duty Cycle Adjustable Soft-Start Current Ramping Internal Current Foldback Plus Shutdown Timer Overvoltage Soft-Latch Eliminates Nuisance Trips Micropower Shutdown Available in 28-Lead SSOP Package U APPLICATIO S ■ ■ ■ ■ The LTC®1629/LTC1629-PG are multiple phase, dual, synchronous step-down current mode switching regulator controllers that drive N-channel external power MOSFET stages in a phase-lockable fixed frequency architecture. The PolyPhaseTM controller drives its two output stages out of phase at frequencies up to 300kHz to minimize the RMS ripple currents in both input and output capacitors. The output clock signal allows expansion for up to 12 evenly phased controllers for systems requiring 15A to 200A of output current. The multiple phase technique effectively multiplies the fundamental frequency by the number of channels used, improving transient response while operating each channel at an optimum frequency for efficiency. Thermal design is also simplified. An internal differential amplifier provides true remote sensing of the regulated supply’s positive and negative output terminals as required for high current applications. A RUN/SS pin provides both soft-start and optional timed, short-circuit shutdown. Current foldback limits MOSFET dissipation during short-circuit conditions when the overcurrent latchoff is disabled. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The LTC1629-PG includes a power good output pin that replaces the AMPMD control pin of the LTC1629. Desktop Computers Internet Servers Large Memory Arrays DC Power Distribution Systems , LTC and LT are registered trademarks of Linear Technology Corporation. OPTI-LOOP and PolyPhase are trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO 10Ω 10µF ×4 35V CERAMIC 0.1µF S LTC1629-PG TG1 VIN 0.1µF 1000pF M1 S BOOST1 0.47µF SW1 BG1 PGOOD PGND ITH M3 TG2 S BOOST2 SW2 16k S BG2 INTVCC – SENSE2 + VOS + SENSE2 – VOS COUT: T510E108K004AS D1, D2: UP5840 S + EAIN 0.003Ω 0.47µF S VDIFFOUT 16k D1 SENSE1 – SGND S 0.003Ω L1 1µH SENSE1 + 3.3k S M2 ×2 S RUN/SS VIN 5V TO 28V M4 ×2 D2 10µF L1, L2: CEPH149-IROMC VOUT 1.6V/40A L2 1µH + M1, M3: IRF7811 M2, M4: IRF7809 COUT 1000µF ×2 4V 1629 TA01 Figure 1. High Current Dual Phase Step-Down Converter 1 LTC1629/LTC1629-PG U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage (VIN).........................36V to – 0.3V Topside Driver Voltages (BOOST1,2) .........42V to – 0.3V Switch Voltage (SW1, 2) .............................36V to – 5 V SENSE1+, SENSE2 +, SENSE1–, SENSE2 – Voltages ........................ (1.1)INTVCC to – 0.3V EAIN, VOS+, VOS–, EXTVCC, INTVCC, RUN/SS, AMPMD, PGOOD Voltages ............7V to – 0.3V Boosted Driver Voltage (BOOST-SW) ..........7V to – 0.3V PLLFLTR, PLLIN, CLKOUT, PHASMD, VDIFFOUT Voltages ................................ INTVCC to – 0.3V ITH Voltage ................................................2.7V to – 0.3V Peak Output Current fOSC – 15 15 µA µA RRELPHS Controller 2-Controller 1 Phase VPHASMD = 0V, Open VPHASMD = 5V 180 240 Deg Deg CLKOUT Phase (Relative to Controller 1) VPHASMD = 0V VPHASMD = Open VPHASMD = 5V 60 90 120 Deg Deg Deg CLKHIGH Clock High Output Voltage CLKLOW Clock Low Output Voltage 4 V 0.2 V 0.3 V ±1 µA PGOOD Output (LTC1629-PG Only) VPGL PGOOD Voltage Low IPGOOD = 2mA IPGOOD PGOOD Leakage Current VPGOOD = 5V VPG PGOOD Trip Level, Either Controller VEAIN with Respect to Set Output Voltage VEAIN Ramping Negative VEAIN Ramping Positive 0.1 –6 6 – 7.5 7.5 – 9.5 9.5 % % 0.995 1 1.005 V/V 46 55 dB 80 kΩ Differential Amplifier/Op Amp Gain Block (Note 5) ADA Gain Differential Amp Mode CMRRDA Common Mode Rejection Ratio Differential Amp Mode; 0V < VCM < 5V RIN Input Resistance Differential Amp Mode; Measured at VOS + Input 3 LTC1629/LTC1629-PG ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage Op Amp Mode; VCM = 2.5V; LTC1629 Only VDIFFOUT = 5V; IDIFFOUT = 1mA MIN TYP MAX IB Input Bias Current Op Amp Mode; LTC1629 Only AOL Open Loop DC Gain Op Amp Mode; 0.7V ≤ VDIFFOUT < 10V; LTC1629 Only VCM Common Mode Input Voltage Range Op Amp Mode; LTC1629 Only 0 CMRROA Common Mode Rejection Ratio Op Amp Mode; 0V < VCM < 3V; LTC1629 Only 70 90 dB PSRROA Power Supply Rejection Ratio Op Amp Mode; 6V < VIN < 30V; LTC1629 Only 70 90 dB ICL Maximum Output Current Op Amp Mode; VDIFFOUT = 0V; LTC1629 Only 10 35 mA 10 6 30 200 5000 UNITS mV nA V/mV 3 V VOMAX Maximum Output Voltage Op Amp Mode; IDIFFOUT = 1mA; LTC1629 Only 11 V GBW Gain-Bandwidth Product Op Amp Mode; IDIFFOUT = 1mA; LTC1629 Only 2 MHz SR Slew Rate Op Amp Mode; RL = 2k; LTC1629 Only 5 V/µs Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC1629/LTC1629-PG: TJ = TA + (PD • 95°C/W) Note 3: The LTC1629/LTC1629-PG are tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VEAIN. Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 5: When the AMPMD pin is high, the IC pins are connected directly to the internal op amp inputs. When the AMPMD pin is low, internal MOSFET switches connect four 40k resistors around the op amp to create a standard unity-gain differential amp. Note 6: The minimum on-time condition corresponds to the on inductor peak-to-peak ripple current ≥ 40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Output Current (Figure 12) Efficiency vs Output Current (Figure 12) 100 Efficiency vs Input Voltage (Figure 12) 100 100 VOUT = 3.3V VEXTVCC = 5V IOUT = 20A VEXTVCC = 5V 80 90 VIN = 12V VIN = 20V 40 VOUT = 3.3V VEXTVCC = 5V IOUT = 20A 20 1 10 OUTPUT CURRENT (A) 70 90 80 VOUT = 3.3V 100 1629 G01 4 80 60 0 0.1 VEXTVCC = 0V EFFICIENCY (%) VIN = 8V 60 EFFICIENCY (%) EFFICIENCY (%) VIN = 5V 50 70 1 10 OUTPUT CURRENT (A) 100 5 10 15 20 VIN (V) 1629 G02 1629 G03 LTC1629/LTC1629-PG U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Input Voltage and Mode 1000 250 600 ON 400 200 5.05 INTVCC AND EXTVCC SWITCH VOLTAGE (V) EXTVCC VOLTAGE DROP (mV) 800 SUPPLY CURRENT (µA) INTVCC and EXTVCC Switch Voltage vs Temperature EXTVCC Voltage Drop 200 LTC1629 150 LTC1629-PG 100 50 SHUTDOWN 0 0 20 15 10 25 INPUT VOLTAGE (V) 5 30 0 35 10 0 30 20 CURRENT (mA) 40 1629 G04 4.85 4.80 EXTVCC SWITCHOVER THRESHOLD 4.75 50 25 75 0 TEMPERATURE (°C) 100 125 1629 G06 Maximum Current Sense Threshold vs Percent of Nominal Output Voltage (Foldback) Maximum Current Sense Threshold vs Duty Factor 75 80 ILOAD = 1mA 70 60 4.8 4.7 50 VSENSE (mV) 4.9 VSENSE (mV) INTVCC VOLTAGE (V) 4.90 4.70 – 50 – 25 50 5.0 25 4.6 50 40 30 20 4.5 10 0 4.4 0 20 15 25 10 INPUT VOLTAGE (V) 5 30 0 35 20 40 60 DUTY FACTOR (%) 80 Maximum Current Sense Threshold vs VRUN/SS (Soft-Start) 80 0 100 50 100 0 25 75 PERCENT ON NOMINAL OUTPUT VOLTAGE (%) 1629 G08 1629 G07 1629 G09 Current Sense Threshold vs ITH Voltage Maximum Current Sense Threshold vs Sense Common Mode Voltage 80 VSENSE(CM) = 1.6V 90 80 70 76 60 40 VSENSE (mV) 60 VSENSE (mV) VSENSE (mV) 4.95 1629 G05 Internal 5V LDO Line Reg 5.1 INTVCC VOLTAGE 5.00 72 68 50 40 30 20 10 20 0 64 –10 –20 60 0 0 1 2 3 4 5 6 VRUN/SS (V) 1629 G10 0 1 3 4 2 COMMON MODE VOLTAGE (V) 5 1629 G11 –30 0 0.5 1 1.5 VITH (V) 2 2.5 1629 G12 5 LTC1629/LTC1629-PG U W TYPICAL PERFOR A CE CHARACTERISTICS Load Regulation VITH vs VRUN/SS 2.5 FCB = 0V VIN = 15V FIGURE 1 100 VOSENSE = 0.7V 2.0 –0.2 50 ISENSE (µA) –0.1 VITH (V) NORMALIZED VOUT (%) 0.0 SENSE Pins Total Source Current 1.5 1.0 –0.3 0 –50 0.5 –0.4 1 0 3 2 LOAD CURRENT (A) 0 4 5 0 1 2 3 4 5 –100 6 VRUN/SS (V) 2 0 4 1629 G14 1629 G13 Maximum Current Sense Threshold vs Temperature 1629 G15 RUN/SS Current vs Temperature 80 1.8 78 1.4 RUN/SS CURRENT (µA) VSENSE (mV) 1.6 76 74 72 1.2 1.0 0.8 0.6 0.4 0.2 70 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 1629 G17 125 Load Step (Figure 12) IOUT O/30A VITH 1V/DIV VOUT 2V/DIV VOUT 200mV/DIV VRUNSS 2V/DIV 100ms/DIV 6 100 1629 G19 Soft-Start Up (Figure 12) VITH 1V/DIV 1629 G20 6 VSENSE COMMON MODE VOLTAGE (V) 10µs/DIV 1629 G21 LTC1629/LTC1629-PG U W TYPICAL PERFOR A CE CHARACTERISTICS Current Sense Pin Input Current vs Temperature EXTVCC Switch Resistance vs Temperature 10 350 VOUT = 5V VFREQSET = 5V 33 31 29 27 25 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 300 8 LTC1629 6 4 LTC1629-PG VFREQSET = OPEN 200 VFREQSET = 0V 150 100 50 50 25 0 75 TEMPERATURE (°C) 1629 G23 100 0 – 50 – 25 125 50 25 75 0 TEMPERATURE (°C) 1629 G24 Undervoltage Lockout vs Temperature 100 125 1629 G25 Shutdown Latch Thresholds vs Temperature 4.5 SHUTDOWN LATCH THRESHOLDS (V) 3.50 UNDERVOLTAGE LOCKOUT (V) 250 2 0 –50 –25 125 FREQUENCY (kHz) EXTVCC SWITCH RESISTANCE (Ω) CURRENT SENSE INPUT CURRENT (µA) 35 Oscillator Frequency vs Temperature 3.45 3.40 3.35 3.30 3.25 3.20 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1629 G26 LATCH ARMING 4.0 3.5 3.0 LATCHOFF THRESHOLD 2.5 2.0 1.5 1.0 0.5 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1629 G27 U U U PI FU CTIO S RUN/SS (Pin 1): Combination of Soft-Start, Run Control Input and Short-Circuit Detection Timer. A capacitor to ground at this pin sets the ramp time to full current output. Forcing this pin below 0.8V causes the IC to shut down all internal circuitry. All functions are disabled in shutdown. SENSE1+, SENSE2+ (Pins 2,14): The (+) Input to the Differential Current Comparators. The ITH pin voltage and built-in offsets between SENSE– and SENSE+ pins in conjunction with RSENSE set the current trip threshold. SENSE1–, SENSE2– (Pins 3, 13): The (–) Input to the Differential Current Comparators. EAIN (Pin 4): Input to the Error Amplifier that compares the feedback voltage to the internal 0.8V reference voltage. This pin is normally connected to a resistive divider from the output of the differential amplifier (DIFFOUT). PLLFLTR (Pin 5): The Phase-Locked Loop’s Low Pass Filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. 7 LTC1629/LTC1629-PG U U U PI FU CTIO S PLLIN (Pin 6): External Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 50kΩ. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal. PHASMD (Pin 7): Control Input to Phase Selector which determines the phase relationships between controller 1, controller 2 and the CLKOUT signal. ITH (Pin 8): Error Amplifier Output and Switching Regulator Compensation Point. Both current comparator’s thresholds increase with this control voltage. The normal voltage range of this pin is from 0V to 2.4V. SGND (Pin 9): Signal Ground, common to both controllers, must be routed separately from the input switched current ground path to the common (–) terminal(s) of the COUT capacitor(s). VDIFFOUT (Pin 10): Output of a Differential Amplifier that provides true remote output voltage sensing. This pin normally drives an external resistive divider that sets the output voltage. VOS–, VOS+ (Pins 11, 12): Inputs to an Operational Amplifier. Internal precision resistors capable of being electronically switched in or out can configure it as a differential amplifier or an uncommitted Op Amp. SW2, SW1 (Pins 17, 26): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. BOOST2, BOOST1 (Pins 18, 25): Bootstrapped Supplies to the Topside Floating Drivers. Capacitors are connected between the Boost and Switch pins and Schottky diodes are tied between the Boost and INTVCC pins. Voltage swing at the Boost pins is from INTVCC to (VIN + INTVCC). BG2, BG1 (Pins 19, 23): High Current Gate Drives for Bottom Synchronous N-Channel MOSFETS. Voltage swing at these pins is from ground to INTVCC. PGND (Pin 20): Driver Power Ground. Connect to sources of bottom N-channel MOSFETS and the (–) terminals of CIN. INTVCC (Pin 21): Output of the Internal 5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver and control circuits are powered from this voltage source. Decouple to power ground with a 1µF ceramic capacitor placed directly adjacent to the IC and minimum of 4.7µF additional tantalum or other low ESR capacitor. EXTVCC (Pin 22): External Power Input to an Internal Switch . This switch closes and supplies INTVCC, bypassing the internal low dropout regulator whenever EXTVCC is higher than 4.7V. See EXTVCC Connection in the Applications Information section. Do not exceed 7V on this pin and ensure VEXTVCC ≤ VINTVCC. AMPMD (Pin 15) (LTC1629 Only): This Logic Input pin controls the connections of internal precision resistors that configure the operational amplifier as a unity-gain differential amplifier. VIN (Pin 24): Main Supply Pin. Should be closely decoupled to the IC’s signal ground pin. PGOOD (Pin 15) (LTC1629-PG Only): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on the EAIN pin is not within ±7.5% of its set point. CLKOUT (Pin 28): Output Clock Signal available to daisychain other controller ICs for additional MOSFET driver stages/phases. TG2, TG1 (Pins 16, 27): High Current Gate Drives for Top N-Channel MOSFETS. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. 8 LTC1629/LTC1629-PG W FU CTIO AL DIAGRA U U LTC1629-PG PGOOD CONNECTION DIFFOUT PGOOD VOS – – 0.86V + A1 VOS + EAIN – – + + 0.74V THE AMPMD PIN ON THE LTC1629 IS REPLACED BY A PGOOD PIN IN THE LTC1629-PG PLLIN VIN INTVCC PHASE DET FIN 50k DUPLICATE FOR SECOND CONTROLLER CHANNEL PLLLPF DB BOOST RLP CLKOUT CLP DROP OUT DET CLK1 OSCILLATOR CLK2 PHASMD ±2µA S Q R Q BOT CB TG TOP + CIN FCB SW FORCE BOT SWITCH LOGIC PHASE LOGIC INTVCC BOT BG PGND LTC1629 ONLY VOS – SHDN A1 VOS + – I1 + INTVCC – + – + L + 30k SENSE 0.86V 4(VFB) SLOPE COMP 0V POSITION DIFFOUT – 30k SENSE RSENSE COUT + AMPMD 45k 45k VOUT 2.4V EAIN 0.80V VIN – EA + VREF VIN OV 4.7V EXTVCC 5V + – 5V LDO REG INTERNAL SUPPLY R2 + – 6V SGND 0.80V 0.86V ITH CC 1.2µA INTVCC + R1 SHDN RST 4(VFB) RUN SOFT START RC RUN/SS CSS 1629 FBD 9 LTC1629/LTC1629-PG U OPERATIO (Refer to Functional Diagram) Main Control Loop Low Current Operation The LTC1629 uses a constant frequency, current mode step-down architecture. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The differential amplifier, A1, produces a signal equal to the differential voltage sensed across the output capacitor but re-references it to the internal signal ground (SGND) reference. The EAIN pin receives a portion of this voltage feedback signal at the DIFFOUT pin which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in the EAIN pin voltage relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on for the rest of the period. The LTC1629 operates in a continuous, PWM control mode. The resulting operation at low output currents optimizes transient response at the expense of substantial negative inductor current during the latter part of the period. The level of ripple current is determined by the inductor value, input voltage, output voltage, and frequency of operation. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external Schottky diode. When VIN decreases to a voltage close to VOUT, however, the loop may enter dropout and attempt to turn on the top MOSFET continuously. A dropout detector detects this condition and forces the top MOSFET to turn off for about 400ns every 10th cycle to recharge the bootstrap capacitor. The main control loop is shut down by pulling Pin 1 (RUN/ SS) low. Releasing RUN/SS allows an internal 1.2µA current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled with the ITH voltage clamped at approximately 30% of its maximum value. As CSS continues to charge, ITH is gradually released allowing normal operation to resume. When the RUN/SS pin is low, all LTC1629 functions are shut down. If VOUT has not reached 70% of its nominal value when CSS has charged to 4.1V, an overcurrent latchoff can be invoked as described in the Applications Information section. 10 Frequency Synchronization The phase-locked loop allows the internal oscillator to be synchronized to an external source via the PLLIN pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator that operates over a 140kHz to 310kHz range corresponding to a DC voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal. When PLLIN is left open, the PLLFLTR pin goes low, forcing the oscillator to minimum frequency. The internal master oscillator runs at a frequency twelve times that of each controller’s frequency. The PHASMD pin determines the relative phases between the internal controllers as well as the CLKOUT signal as shown in Table␣ 1. The phases tabulated are relative to zero phase being defined as the rising edge of the top gate (TG1) driver output of controller 1. Table 1. VPHASMD GND OPEN INTVCC Controller 2 180° 180° 240° CLKOUT 60° 90° 120° The CLKOUT signal can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or separate outputs. Input capacitance ESR requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the RMS current squared. A two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input capacitor(s). LTC1629/LTC1629-PG U OPERATIO (Refer to Functional Diagram) INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most of the IC circuitry is derived from INTVCC. When the EXTVCC pin is left open, an internal 5V low dropout regulator supplies INTVCC power. If the EXTVCC pin is taken above 4.7V, the 5V regulator is turned off and an internal switch is turned on connecting EXTVCC to INTVCC. This allows the INTVCC power to be derived from a high efficiency external source such as the output of the regulator itself or a secondary winding, as described in the Applications Information section. An external Schottky diode can be used to minimize the voltage drop from EXTVCC to INTVCC in applications requiring greater than the specified INTVCC current. Voltages up to 7V can be applied to EXTVCC for additional gate drive capability. Differential Amplifier This amplifier provides true differential output voltage sensing. Sensing both VOUT + and VOUT – benefits regulation in high current applications and/or applications having electrical interconnection losses. The AMPMD pin (available on the LTC1629 only) allows selection of internal precision feedback resistors for high common mode rejection differencing applications, or direct access to the actual amplifier inputs without these internal feedback resistors for other applications. The AMPMD pin is grounded to connect the internal precision resistors in a unity-gain differencing application or tied to the INTVCC pin to bypass the internal resistors and make the amplifier inputs directly available. The amplifier is a unity-gain stable, 2MHz gain-bandwidth, >120dB open-loop gain design. The amplifier has an output slew rate of 5V/µs and is capable of driving capacitive loads with an output RMS current typically up to 25mA. The amplifier is not capable of sinking current and therefore must be resistively loaded to do so. The differential amplifier is configured as a unitygain differencing amplifier in the LTC1629-PG. Power Good (PGOOD) (LTC1629-PG Only) The PGOOD pin is connected to the drain of an internal MOSFET. The MOSFET turns on when the output is not within ±7.5% of its nominal output level as determined by the feedback divider. When the output is within ±7.5% of its nominal value, the MOSFET is turned off within 10µs and the PGOOD pin should be pulled up by an external resistor to a source of up to 7V. Short-Circuit Detection The RUN/SS capacitor is used initially to limit the inrush current from the input power source. Once the controllers have been given time, as determined by the capacitor on the RUN/SS pin, to charge up the output capacitors and provide full load current, the RUN/SS capacitor is then used as a short-circuit timeout circuit. If the output voltage falls to less than 70% of its nominal output voltage the RUN/SS capacitor begins discharging assuming that the output is in a severe overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overidden by providing a >5µA pull-up current at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. U W U U APPLICATIO S I FOR ATIO The basic LTC1629 application circuit is shown in Figure␣ 1 on the first page. External component selection is driven by the load requirement, and begins with the selection of RSENSE1, 2. Once RSENSE1, 2 are known, L1 and L2 can be chosen. Next, the power MOSFETs and D1 and D2 are selected. The operating frequency and the inductor are chosen based mainly on the amount of ripple current. Finally, CIN is selected for its ability to handle the input ripple current (that PolyPhase operation minimizes) and COUT is chosen with low enough ESR to meet the output ripple voltage and load step specifications (also minimized with PolyPhase). The circuit shown in Figure␣ 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). 11 LTC1629/LTC1629-PG U W U U APPLICATIO S I FOR ATIO 2.5 RSENSE Selection For Output Current PLLFLTR PIN VOLTAGE (V) RSENSE1, 2 are chosen based on the required output current. The LTC1629 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.5( INTVCC). The current comparator threshold sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL. Allowing a margin for variations in the LTC1629 and external component values yields: The LTC1629 uses a constant frequency, phase-lockable architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to Phase-Locked Loop and Frequency Synchronization in the Applications Information section for additional information. A graph for the voltage applied to the PLLFLTR pin vs frequency is given in Figure␣ 2. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 310kHz. Inductor Value Calculation and Output Ripple Current The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of 12 1.0 0.5 170 220 270 OPERATING FREQUENCY (kHz) 320 1629 F02 Figure 2. Operating Frequency vs VPLLFLTR where N = number of stages. Operating Frequency 1.5 0 120 RSENSE = (50mV/IMAX)N When using the controller in very low dropout conditions, the maximum output current level will be reduced due to internal slope compensation required to meet stability criterion for buck regulators operating at greater than 50% duty factor. A curve is provided to estimate this reduction in peak output current level depending upon the operating duty factor. 2.0 MOSFET gate charge and transition losses. In addition to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be considered. The PolyPhase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL per individual section, N, decreases with higher inductance or frequency and increases with higher VIN or VOUT: ∆IL = VOUT  VOUT   1−  fL  VIN  where f is the individual output stage operating frequency. In a PolyPhase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to the ripple cancellation. The details on how to calculate the net output ripple current can be found in Application Note 77. Figure 3 shows the net ripple current seen by the output capacitors for the different phase configurations. The output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. The output ripple current is normalized against the inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations. As shown in Figure␣ 3, the zero output ripple current is obtained when: LTC1629/LTC1629-PG U W U U APPLICATIO S I FOR ATIO VOUT k = VIN N where k = 1, 2, …, N – 1 So the number of phases used can be selected to minimize the output ripple current and therefore the output ripple voltage at the given input and output voltages. In applications having a highly varying input voltage, additional phases will produce the best results. Accepting larger values of ∆IL allows the use of low inductances, but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is ∆IL = 0.4(IOUT)/N, where N is the number of channels and IOUT is the total load current. Remember, the maximum ∆IL occurs at the maximum input voltage. The individual inductor ripple currents are constant determined by the inductor, input and output voltages. 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.9 0.8 0.7 Two external power MOSFETs must be selected for each controller with the LTC1629: One N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. 0.6 VO/fL ∆IO(P-P) Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which do not increase the height significantly. Power MOSFET, D1 and D2 Selection 1.0 0.5 0.4 0.3 0.2 0.1 0 Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 1629 F03 Figure 3. Normalized Peak Output Current vs Duty Factor [IRMS ≈ 0.3 (∆IO(P–P))] Inductor Core Selection Once the values for L1 and L2 are known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Kool Mµ is a registered trademark of Magnetics, Inc. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sublogic-level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), reverse transfer capacitance CRSS, input voltage, and maximum output current. When the LTC1629 is operating in continuous mode the duty factors for the top and bottom MOSFETs of each output stage are given by: Main Switch Duty Cycle = VOUT VIN V –V  Synchronous Switch Duty Cycle =  IN OUT    VIN 13 LTC1629/LTC1629-PG U U W U APPLICATIO S I FOR ATIO  2 I k( VIN )  MAX  (CRSS )( f)  N  2 I  V –V PSYNC = IN OUT  MAX  1 + δ RDS(ON) VIN  N  ( ) where δ is the temperature dependency of RDS(ON), k is a constant inversely related to the gate drive current and N is the number of stages. Both MOSFETs have I2R losses but the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actual provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs. Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. The Schottky diodes, D1 and D2 shown in Figure 1 conduct during the dead-time between the conduction of the two large power MOSFETs. This helps prevent the body diode of the bottom MOSFET from turning on, storing charge during the dead-time, and requiring a reverse recovery period which would reduce efficiency. A 1A to 3A (depending on output current) Schottky diode is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in 14 CIN and COUT Selection In continuous mode, the source current of each top N-channel MOSFET is a square wave of duty cycle VOUT/ VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a close form equation can be found in Application Note 77. Figure 4 shows the input capacitor ripple current for different phase configurations with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the product of phase number and output voltage, N(VOUT), is approximately equal to the input voltage VIN or: VOUT k = VIN N where k = 1, 2, …, N – 1 So the phase number can be chosen to minimize the input capacitor size for the given input and output voltages. In the graph of Figure 4, the local maximum input RMS capacitor currents are reached when: VOUT 2k − 1 = VIN 2N where k = 1, 2, …, N 0.6 0.5 DC LOAD CURRENT 2 V I  PMAIN = OUT  MAX  (1 + δ )RDS(ON) + VIN  N  additional transition losses due to their larger junction capacitance. RMS INPUT RIPPLE CURRNET The MOSFET power dissipations at maximum output current are given by: 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 1629 F04 Figure 4. Normalized Input RMS Ripple Current vs Duty Factor for 1 to 6 Output Stages LTC1629/LTC1629-PG U W U U APPLICATIO S I FOR ATIO These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question. The graph shows that the peak RMS input current is reduced linearly, inversely proportional to the number, N of stages used. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 2-stage implementation results in 75% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a PolyPhase system. The required amount of input capacitance is further reduced by the factor, N, due to the effective increase in the frequency of the current pulses. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirements. The steady state output ripple (∆VOUT) is determined by:  1  ∆VOUT ≈ ∆IRIPPLE  ESR +   8NfCOUT  Where f = operating frequency of each stage, N is the number of phases, COUT = output capacitance, and ∆IRIPPLE = combined inductor ripple currents. The output ripple varies with input voltage since ∆IL is a function of input voltage. The output ripple will be less than 50mV at max VIN with ∆IL = 0.4IOUT(MAX)/N assuming: COUT required ESR < 2N(RSENSE) and COUT > 1/(8Nf)(RSENSE) The emergence of very low ESR capacitors in small, surface mount packages makes very physically small implementations possible. The ability to externally compensate the switching regulator loop using the ITH pin(OPTI- LOOP compensation) allows a much wider selection of output capacitor types. OPTI-LOOP compensation effectively removes constraints on output capacitor ESR. The impedance characteristics of each capacitor type are significantly different than an ideal capacitor and therefore require accurate modeling or bench evaluation during design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo and the Panasonic SP surface mount types have the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON type capacitors is recommended to reduce the inductance effects. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. A combination of capacitors will often result in maximizing performance and minimizing overall cost and size. INTVCC Regulator An internal P-channel low dropout regulator produces 5V at the INTVCC pin from the VIN supply pin. The INTVCC regulator powers the drivers and internal circuitry of the LTC1629. The INTVCC pin regulator can supply up to 50mA peak and must be bypassed to power ground with a minimum of 4.7µF tantalum or electrolytic capacitor. An additional 1µF ceramic capacitor placed very close to the IC is recommended due to the extremely high instantaneous currents required by the MOSFET gate drivers. 15 LTC1629/LTC1629-PG U W U U APPLICATIO S I FOR ATIO High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1629 to be exceeded. The supply current is dominated by the gate charge supply current, in addition to the current drawn from the differential amplifier output. The gate charge is dependent on operating frequency as discussed in the Efficiency Considerations section. The supply current can either be supplied by the internal 5V regulator or via the EXTVCC pin. When the voltage applied to the EXTVCC pin is less than 4.7V, all of the INTVCC load current is supplied by the internal 5V linear regulator. Power dissipation for the IC is higher in this case by (IIN)(VIN – INTVCC) and efficiency is lowered. The junction temperature can be estimated by using the equations given in Note 1 of the Electrical Characteristics. For example, the LTC1629 VIN current is limited to less than 24mA from a 24V supply: TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C Use of the EXTVCC pin reduces the junction temperature to: TJ = 70°C + (24mA)(5V)(95°C/W) = 81.4°C The input supply current should be measured while the controller is operating in continuous mode at maximum VIN and the power dissipation calculated in order to prevent the maximum junction temperature from being exceeded. EXTVCC Connection The LTC1629 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. When the voltage applied to EXTVCC rises above 4.7V, the internal regulator is turned off and the switch closes, connecting the EXTVCC pin to the INTVCC pin thereby supplying internal and MOSFET gate driving power. The switch remains closed as long as the voltage applied to EXTVCC remains above 4.5V. This allows the MOSFET driver and control power to be derived from the output during normal operation (4.7V < VEXTVCC < 7V) and from the internal regulator when the output is out of regulation (start-up, short-circuit). Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC < VIN + 0.3V when using the application circuits shown. If an external voltage source is applied to the EXTVCC pin when the VIN supply is 16 not present, a diode can be placed in series with the LTC1629’s VIN pin and a Schottky diode between the EXTVCC and the VIN pin, to prevent current from backfeeding VIN. Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by the ratio: (Duty Factor)/(Efficiency). For 5V regulators this means connecting the EXTVCC pin directly to VOUT. However, for 3.3V and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5V regulator resulting in a significant efficiency penalty at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If an external supply is available in the 5V to 7V range, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. VIN must be greater than or equal to the voltage applied to the EXTVCC pin. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an outputderived voltage which has been boosted to greater than 4.7V but less than 7V. This can be done with either the inductive boost winding as shown in Figure 5a or the capacitive charge pump shown in Figure 5b. The charge pump has the advantage of simple magnetics. Topside MOSFET Driver Supply (CB,DB) (Refer to Functional Diagram) External bootstrap capacitors CB1 and CB2 connected to the BOOST1 and BOOST2 pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though diode DB from INTVCC when the SW pin is low. When the topside MOSFET turns on, the driver places the CB voltage across the gate- LTC1629/LTC1629-PG U W U U APPLICATIO S I FOR ATIO OPTIONAL EXTVCC CONNECTION 5V < VSEC < 7V + CIN + VIN VIN LTC1629 VIN 1N4148 TG1 EXTVCC 6.8V N-CH VSEC N-CH LTC1629 1µF T1 BAT85 0.22µF BAT85 BAT85 VN2222LL EXTVCC RSENSE VOUT SW1 COUT BG1 VOUT L1 + + BG1 + CIN TG1 + RSENSE SW1 VIN CIN COUT N-CH N-CH PGND PGND 1629 F05b 1629 F05a Figure 5a. Secondary Output Loop and EXTVCC Connection Figure 5b. Capacitive Charge Pump for EXTVCC source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin rises to VIN + VINTVCC. The value of the boost capacitor CB needs to be 30 to 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of DB must be greater than VIN(MAX). figuration is activated when the AMPMD pin is tied to ground and is the only configuration available for the LTC1629-PG. When the AMPMD pin is tied to INTVCC, the resistors are disconnected and the amplifier inputs are made directly available. The amplifier can then be used as a general purpose op amp. The amplifier has a 0V to 3V common mode input range limitation due to the internal switching of its inputs. The output is an NPN emitter follower without any internal pull-down current. A DC resistive load to ground is required in order to sink current. The output will swing from 0V to 10V. (VIN ≥ VDIFFOUT␣ +␣ 2V.) The final arbiter when defining the best gate drive amplitude level will be the input supply current. If a change is made that decreases input current, the efficiency has improved. If the input current does not change then the efficiency has not changed either. Output Voltage The LTC1629 has a true remote voltage sense capablity. The sensing connections should be returned from the load back to the differential amplifier’s inputs through a common, tightly coupled pair of PC traces. The differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback PC traces as well as ground loop disturbances. The differential amplifier output signal is divided down and compared with the internal precision 0.8V voltage reference by the error amplifier. The differential amplifier can be used in either of two configurations according to the voltage applied to the AMPMD pin. The first configuration, with the connections illustrated in the Functional Diagram, utilizes a set of internal precision resistors to enable precision instrumentation-type measurement of the output voltage. This con- Soft-Start/Run Function The RUN/SS pin provides three functions: 1) Run/Shutdown, 2) soft-start and 3) a defeatable short-circuit latchoff timer. Soft-start reduces the input power sources’ surge currents by gradually increasing the controller’s current limit ITH(MAX). The latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. A small pull-up current (>5µA) supplied to the RUN/ SS pin will prevent the overcurrent latch from operating. The following explanation describes how the functions operate. An internal 1.2µA current source charges up the CSS capacitor. When the voltage on RUN/SS reaches 1.5V, the controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3.0V, the internal current limit is increased from 25mV/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 1.4µs/µF to reach full current. The output cur- 17 LTC1629/LTC1629-PG U W U U APPLICATIO S I FOR ATIO rent thus ramps up slowly, reducing the starting surge current required from the input power supply. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately: tDELAY = ( ) 1.5V CSS = 1.25s / µF CSS 1.2µA The time for the output current to ramp up is then: tRAMP = 3V − 1.5V CSS = (1.25s / µF ) CSS 1.2µA By pulling the RUN/SS pin below 0.8V the LTC1629 is put into low current shutdown (IQ < 40µA). RUN/SS can be driven directly from logic as shown in Figure 6. Diode D1 in Figure 6 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. The RUN/SS pin has an internal 6V zener clamp (see Functional Diagram). Fault Conditions: Overcurrent Latchoff The RUN/SS pin also provides the ability to latch off the controllers when an overcurrent condition is detected. The RUN/SS capacitor, CSS, is used initially to limit the inrush current of both controllers. After the controllers have been started and been given adequate time to charge up the output capacitors and provide full load current, the RUN/ SS capacitor is used for a short-circuit timer. If the output voltage falls to less than 70% of its nominal value after CSS reaches 4.1V, CSS begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long enough period as determined by the size of CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. If the overload occurs during start-up, the time can be approximated by: tLO1 ≈ (CSS • 0.6V)/(1.2µA) = 5 • 105 (CSS) If the overload occurs after start-up, the voltage on CSS will continue charging and will provide additional time before latching off: tLO2 ≈ (CSS • 3V)/(1.2µA) = 2.5 • 106 (CSS) This built-in overcurrent latchoff can be overridden by providing a pull-up resistor, RSS, to the RUN/SS pin as 18 shown in Figure 6. This resistance shortens the soft-start period and prevents the discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. When deriving the 5µA current from VIN as in the figure, current latchoff is always defeated. Diodeconnecting this pull-up resistor to INTV CC, as in Figure␣ 6, eliminates any extra supply current during shutdown while eliminating the INTVCC loading from preventing controller start-up. Why should you defeat current latchoff? During the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off the controller. Defeating this feature allows troubleshooting of the circuit and PC layout. The internal short-circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. A decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. The value of the soft-start capacitor CSS may need to be scaled with output voltage, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: CSS > (COUT )(VOUT)(10-4)(RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1µF will be sufficient for most applications. INTVCC VIN 3.3V OR 5V D1 RUN/SS RSS* RSS* D1* RUN/SS CSS CSS *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF 1629 F06 Figure 6. RUN/SS Pin Interfacing Phase-Locked Loop and Frequency Synchronization The LTC1629 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is ±50% around the LTC1629/LTC1629-PG U W U U APPLICATIO S I FOR ATIO center frequency fO. A voltage applied to the PLLFLTR pin of 1.2V corresponds to a frequency of approximately 220kHz. The nominal operating frequency range of the LTC1629 is 140kHz to 310kHz. The phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range, ∆fH, is equal to the capture range, ∆fC: 2.4V PHASE DETECTOR RLP 10k CLP EXTERNAL OSC PLLFLTR PLLIN 50k DIGITAL PHASE/ FREQUENCY DETECTOR ∆fH = ∆fC = ±0.5 fO (150kHz-300kHz) The output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the PLLFLTR pin. A simplified block diagram is shown in Figure 7. If the external frequency (fPLLIN) is greater than the oscillator frequency f0SC, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than f0SC, current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is open and the filter capacitor CLP holds the voltage. The LTC1629 PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. When using multiple LTC1629’s for a phase-locked system, the PLLFLTR pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the master’s frequency. A DC voltage of 1.6V to 1.7V applied to the master oscillator’s PLLFLTR pin is recommended in order to meet this requirement. The resultant operating frequency will be approximately 300kHz. The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10kΩ and CLP is 0.01µF to 0.1µF. OSC 1629 F07 Figure 7. Phase-Locked Loop Block Diagram Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC1629 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT () VIN f If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC1629 will begin to skip cycles resulting in nonconstant frequency operation. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. The minimum on-time for the LTC1629 is generally less than 200ns. However, as the peak sense voltage decreases the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. If an application can operate close to the minimum ontime limit, an inductor must be chosen that has a low enough inductance to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule, keep the inductor ripple current of each phase equal to or greater than 15% of IOUT(MAX)/N at VIN(MAX). 19 LTC1629/LTC1629-PG U W U U APPLICATIO S I FOR ATIO Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1629 circuits: 1) LTC1629 VIN current (including loading on the differential amplifier output), 2) INTVCC regulator current, 3) I2R losses and 4) Topside MOSFET transition losses. 1) The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents; the second is the current drawn from the differential amplifier output. VIN current typically results in a small (