LTC1861CMS#TRPBF

LTC1860/LTC1861 µPower, 12-Bit, 250ksps 1- and 2-Channel ADCs in MSOP Features Description 12-Bit 250ksps ADCs in MSOP Package nn Single 5V Supply nn Low Supply Current: 850µA (Typ) nn Auto Shutdown Reduces Supply Current to 2µA at 1ksps nn True Differential Inputs nn 1-Channel (LTC1860) or 2-Channel (LTC1861) Versions nn SPI/MICROWIRETM Compatible Serial I/O nn High Speed Upgrade to LTC1286/LTC1298 nn Pin Compatible with 16-Bit LTC1864/LTC1865 nn Guaranteed Operation to 125°C (MSOP Package) The LTC®1860/LTC1861 are 12-bit A/D converters that are offered in MSOP and SO-8 packages and operate on a single 5V supply. At 250ksps, the supply current is only 850µA. The supply current drops at lower speeds because the LTC1860/LTC1861 automatically power down to a typical supply current of 1nA between conversions. These 12-bit switched capacitor successive approximation ADCs include sample-and-holds. The LTC1860 has a differential analog input with an adjustable reference pin. The LTC1861 offers a software-selectable 2-channel MUX and an adjustable reference pin on the MSOP version. nn Applications High Speed Data Acquisition Portable or Compact Instrumentation nn Low Power Battery-Operated Instrumentation nn Isolated and/or Remote Data Acquisition nn nn The 3-wire, serial I/O, MSOP or SO-8 package and extremely high sample rate-to-power ratio make these ADCs ideal choices for compact, low power, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans down to 1V full scale, allow direct connection to signal sources in many applications, eliminating the need for external gain stages. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application Single 5V Supply, 250ksps, 12-Bit Sampling ADC Supply Current vs Sampling Frequency 1000 1µF 5V LTC1860 1 ANALOG INPUT 0V TO 5V 2 3 4 VREF VCC IN+ SCK IN– SDO GND CONV 8 7 6 5 1860 TA01 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS SUPPLY CURRENT (µA) 100 10 1 0.1 0.01 0.01 0.1 10 100 1 SAMPLING FREQUENCY (kHz) 1000 1860 TA02 18601fb For more information www.linear.com/LTC1860 1 LTC1860/LTC1861 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage (VCC) ..................................................7V Ground Voltage Difference AGND, DGND LTC1861 MSOP Package..............±0.3V Analog Input .....................(GND – 0.3V) to (VCC + 0.3V) Digital Input ..................................... (GND – 0.3V) to 7V Digital Output .................... (GND – 0.3V) to (VCC + 0.3V) Power Dissipation............................................... 400mW Operating Temperature Range LTC1860C/LTC1861C................................0°C to 70°C LTC1860I/LTC1861I ........................... – 40°C to 85°C LTC1860H/LTC1861H..........................–40°C to 125°C Storage Temperature Range....................–65°C to 150°C Lead Temperature (Soldering, 10 sec)...................300°C Pin Configuration LTC1860 LTC1861 TOP VIEW VREF IN+ IN¯ GND 8 7 6 5 1 2 3 4 TOP VIEW CONV CH0 CH1 AGND DGND VCC SCK SDO CONV MS8 PACKAGE 8-LEAD PLASTIC MSOP VREF 1 IN+ TJMAX = 150°C, θJA = 210°C/W LTC1861 TOP VIEW TOP VIEW 8 VCC CONV 1 8 VCC 2 7 SCK CH0 2 7 SCK IN– 3 6 SDO CH1 3 6 SDO GND 4 5 CONV GND 4 5 SDI S8 PACKAGE 8-LEAD PLASTIC SO S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W 2 VREF VCC SCK SDO SDI MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 210°C/W LTC1860 10 9 8 7 6 1 2 3 4 5 TJMAX = 150°C, θJA = 175°C/W 18601fb For more information www.linear.com/LTC1860 LTC1860/LTC1861 order information http://www.linear.com/product/LTC1860#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1860CMS8#PBF LTC1860CMS8#TRPBF LTWR 8-Lead Plastic MSOP 0°C to 70°C LTC1860IMS8#PBF LTC1860IMS8#TRPBF LTWS 8-Lead Plastic MSOP –40°C to 85°C LTC1860HMS8#PBF LTC1860HMS8#TRPBF LTWS 8-Lead Plastic MSOP –40°C to 125°C LTC1860CS8#PBF LTC1860CS8#TRPBF 1860 8-Lead Plastic SO 0°C to 70°C LTC1860IS8#PBF LTC1860IS8#TRPBF 1860I 8-Lead Plastic SO –40°C to 85°C LTC1861CMS#PBF LTC1861CMS#TRPBF LTWT 10-Lead Plastic MSOP 0°C to 70°C LTC1861IMS#PBF LTC1861IMS#TRPBF LTWU 10-Lead Plastic MSOP –40°C to 85°C LTC1861HMS#PBF LTC1861HMS#TRPBF LTWU 10-Lead Plastic MSOP –40°C to 125°C LTC1861CS8#PBF LTC1861CS8#TRPBF 1861 8-Lead Plastic SO 0°C to 70°C LTC1861IS8#PBF LTC1861IS8#TRPBF 1861I 8-Lead Plastic SO –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 18601fb For more information www.linear.com/LTC1860 3 LTC1860/LTC1861 CONVERTER AND MULTIPLEXER CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. SYMBOL CONDITIONS MIN TYP MAX UNITS Resolution l 12 Bits No Missing Codes Resolution l 12 Bits INL (Note 3) ±1 l Transition Noise 0.07 Gain Error l Offset Error LTC1860 SO-8 and MSOP, LTC1861 MSOP LTC1861 SO-8 l l Input Differential Voltage Range VIN = IN+ – IN– l Absolute Input Range IN+ Input IN– Input VREF Input Range LTC1860 SO-8 and MSOP, LTC1861 MSOP Analog Input Leakage Current (Note 4) CIN Input Capacitance In Sample Mode During Conversion LSB LSBRMS ±2 ±3 ±20 mV ±5 ±7 mV mV 0 VREF V –0.05 –0.05 VCC + 0.05 VCC/2 V V 1 VCC V ±1 µA l 12 5 pF pF dynamic accuracy TA = 25°C. VCC = 5V, fSAMPLE = 250kHz, unless otherwise specified. SYMBOL PARAMETER SNR Signal-to-Noise Ratio CONDITIONS S/(N + D) Signal-to-Noise Plus Distortion Ratio THD Total Hamonic Distortion Up to 5th Harmonic MIN MAX UNITS 72 dB 100kHz Input Signal 71 dB 100kHz Input Signal 77 dB 20 MHz 125 kHz Full Power Bandwidth Full Linear Bandwidth TYP S/(N + D) ≥ 68dB The l denotes specifications which apply digital and dc electrical characteristics over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VCC = 5.25V l VIL Low Level Input Voltage VCC = 4.75V l 0.8 V IIH High Level Input Current VIN = VCC l 2.5 µA IIL Low Level Input Current VIN = 0V l –2.5 µA VOH High Level Output Voltage VCC = 4.75V, IO = 10µA VCC = 4.75V, IO = 360µA l l VOL Low Level Output Voltage VCC = 4.75V, IO = 1.6mA l 4 MIN TYP MAX 2.4 4.5 2.4 UNITS V 4.74 4.72 V V 0.4 V 18601fb For more information www.linear.com/LTC1860 LTC1860/LTC1861 The l denotes specifications which apply digital and dc electrical characteristics over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS IOZ Hi-Z Output Leakage CONV = VCC MIN TYP MAX ±3 l UNITS µA ISOURCE Output Source Current VOUT = 0V –25 mA ISINK Output Sink Current VOUT = VCC 20 mA IREF Reference Current (LTC1860 SO-8, MSOP and LTC1861 MSOP) CONV = VCC fSMPL = fSMPL(MAX) l l 0.001 0.05 3 0.1 µA mA ICC Supply Current CONV = VCC After Conversion CONV = VCC After Conversion, H-Grade fSMPL = fSMPL(MAX) l l l 0.001 0.001 0.85 3 5 1.3 µA µA mA PD Power Dissipation fSMPL = fSMPL(MAX) 1.25 mV The l denotes specifications which apply over recommended operating conditions the full operating temperature range, otherwise specifications are TA = 25°C. SYMBOL PARAMETER VCC Supply Voltage fSCK Clock Frequency tCYC Total Cycle Time tSMPL Analog Input Sampling Time tsuCONV CONDITIONS MIN TYP 4.75 H-Grade l l 12 • SCK + tCONV MAX UNITS 5.25 V 20 16.7 MHz MHz µs LTC1860 (Note 5) LTC1861 (Note 5) 12 10 SCK SCK Setup Time CONV↓ Before First SCK↑, (See Figure 1) H-Grade 60 65 thDI Holdtime SDI After SCK↑ LTC1861 15 ns tsuDI Setup Time SDI Stable Before SCK↑ LTC1861 15 ns tWHCLK SCK High Time fSCK = fSCK(MAX) 40% 1/fSCK tWLCLK SCK Low Time fSCK = fSCK(MAX) 40% 1/fSCK tWHCONV CONV High Time Between Data Transfer Cycles (Note 5) tCONV µs tWLCONV CONV Low Time During Data Transfer (Note 5) 12 thCONV Hold Time CONV Low After Last SCK↑ 30 30 ns ns SCK 13 ns 18601fb For more information www.linear.com/LTC1860 5 LTC1860/LTC1861 The l denotes specifications which apply over the full operating temperature timing characteristics range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. SYMBOL PARAMETER tCONV Conversion Time (See Figure 1) CONDITIONS fSMPL(MAX) Maximum Sampling Frequency tdDO Delay Time, SCK↓ to SDO Data Valid MIN H-Grade l l H-Grade l l CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF, H-Grade l l H-Grade MAX 3.2 3.3 250 248 UNITS µs µs kHz kHz 15 20 25 30 ns ns ns l l 30 30 60 65 ns ns 30 30 60 65 ns ns tdis Delay Time, CONV↑ to SDO Hi-Z ten Delay Time, CONV↓ to SDO Enabled CLOAD = 20pF CLOAD = 20pF, H-Grade l l thDO Time Output Data Remains Valid After SCK↓ CLOAD = 20pF l tr SDO Rise Time tf SDO Fall Time 10 ns CLOAD = 20pF 8 ns CLOAD = 20pF 4 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. 6 TYP 2.75 2.75 5 Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 4: Channel leakage current is measured while the part is in sample mode. Note 5: Guaranteed by design, not subject to test. 18601fb For more information www.linear.com/LTC1860 LTC1860/LTC1861 Typical Performance Characteristics Supply Current vs Sampling Frequency CONV LOW = 800ns TA = 25°C VCC = 5V 800 1 600 400 CONV HIGH = 3.2µS fSMPL = 250kHz VCC = 5V VREF = 5V 200 0.1 0.01 0.01 0.1 10 100 1.0 SAMPLING FREQUENCY (kHz) 0 –50 1000 –25 50 0 75 25 TEMPERATURE (°C) Reference Current vs Sample Rate 20 10 100 150 200 SAMPLE RATE (kHz) 40 50 49 –1.0 20 48 47 10 –25 50 25 0 75 TEMPERATURE (°C) 100 0 125 512 1024 1536 2048 2560 3072 3584 4096 CODE 1860/61 G07 0 1 2 3 VREF (V) Analog Input Leakage vs Temperature 100 TA = 25°C VCC = 5V VREF = 5V 0.5 0 –0.5 –1.0 0 5 4 1860/61 G06 ANALOG INPUT LEAKAGE (nA) INL COC ERROR (LSBs) 1.0 DNL EOC ERROR (LSBs) 0 30 1860/61 G05 TA = 25°C VCC = 5V VREF = 5V 125 fS = 250kHz TA = 25°C 50 VCC = 5V Typical DNL Curve –0.5 100 60 51 Typical INL Curve 0 50 25 0 75 TEMPERATURE (°C) Reference Current vs Reference Voltage 52 45 –50 250 0.5 –25 1860/61 G03 fS = 250kHz 54 VCC = 5V = 5V V 53 REF 1860/61 G04 1.0 300 0 –50 125 46 50 400 100 IREF (µA) REFERENCE CURRENT (µA) 30 0 500 200 55 40 0 600 Reference Current vs Temperature CONV IS LOW FOR 800ns TA = 25°C VCC = 5V VREF = 5V 50 100 700 1860/61 G02 1860/61 G01 60 CONV = VCC = 5V 800 SLEEP CURRENT (nA) 10 REFERENCE CURRENT (µA) Sleep Current vs Temperature 1000 900 SUPPLY CURRENT (µA) 100 SUPPLY CURRENT (µA) Supply Current vs Temperature 1000 1000 512 1024 1536 2048 2560 3072 3584 4096 CODE 1860/61 G07 VCC = 5V VREF = 5V CONV = 0V 75 50 25 0 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 1860/61 G09 18601fb For more information www.linear.com/LTC1860 7 LTC1860/LTC1861 Typical Performance Characteristics Change in Offset Error vs Reference Voltage 4 CHANGE IN OFFSET ERROR (LSB) 1.0 TA = 25°C VCC = 5V CHANGE IN OFFSET (LSB) 3 2 1 0 –1 –2 –3 0.4 0.2 0 –0.2 –0.4 –0.6 –1.0 –50 3 4 2 REFERENCE VOLTAGE (V) 5 –25 50 25 0 75 TEMPERATURE (°C) Change in Gain Error vs Temperature 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 50 25 0 75 TEMPERATURE (°C) –25 100 50 SINAD 40 30 20 10 10 100 fIN (kHz) 1000 10000 8 1 4 3 2 REFERENCE VOLTAGE(V) 5 4096 Point FFT fS = 204.1kHz fIN = 99.5kHz TA = 25°C VCC = 5V –20 50 40 30 –40 –60 –80 20 –100 10 –5 0 –120 0 10 20 30 40 50 60 70 80 90 100 f (kHz) 1860/61 G15 Total Harmonic Distortion vs fIN Spurious Free Dynamic Range vs fIN 100 TA = 25°C VCC = 5V VIN = 0dB –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 1 10 100 1000 fIN (kHz) 1860/61 G16 0 1860/61 G12 SPURIOUS FREE DYNAMIC RANGE (dB) 60 1 –3 1195 G20 TOTAL HARMONIC DISTORTION (dB) SIGNAL-TO-(NOISE + DISTORTION) (dB) SNR 70 0 –2 60 0 TA = 25°C VCC = 5V VIN = 0dB 80 –1 –5 125 fIN = 10kHz TA = 25°C VCC = 5V 70 0 –40 –35 –30 –25 –20 –15 –10 INPUT LEVEL (dB) 125 Signal-to-(Noise + Distortion) vs fIN 90 0 0 1860/61 G13 100 100 AMPLITUDE (dB) SIGNAL-TO-(NOISE + DISTORTION) (dB) CHANGE IN GAIN ERROR (LSB) 80 0.6 –1.0 –50 1 Signal-to-(Noise + Distortion) vs Input Level VCC = 5V VREF = 5V 0.8 2 1860/61 G11 1860/61 G10 1.0 3 –4 –0.8 –5 1 VCC = 5V 4 TA = 25°C 0.6 –4 0 5 VCC = 5V 0.8 CHANGE IN GAIN ERROR (LSB) 5 Change in Gain Error vs Reference Voltage Change in Offset vs Temperature 1860/61 G17 90 80 70 60 50 40 30 20 TA = 25°C VCC = 5V VIN = 0dB 10 0 1 10 100 1000 fIN (kHz) 1860/61 G18 18601fb For more information www.linear.com/LTC1860 LTC1860/LTC1861 Pin Functions LTC1860 VREF (Pin 1): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. SDI (Pin 6): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 7): Digital Data Output. The A/D conversion result is shifted out of this output. IN +, IN– (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. SCK (Pin 8): Shift Clock Input. This clock synchronizes the serial data transfer. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. VCC (Pin 9): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. CONV (Pin 5): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this pin. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. LTC1861 (MSOP Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to AGND. AGND (Pin 4): Analog Ground. AGND should be tied directly to an analog ground plane. DGND (Pin 5): Digital Ground. DGND should be tied directly to an analog ground plane. VREF (Pin 10): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to AGND. LTC1861 (SO-8 Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. SDI (Pin 5): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin. 18601fb For more information www.linear.com/LTC1860 9 LTC1860/LTC1861 functional Block Diagram CONV (SDI) SCK VCC PIN NAMES IN PARENTHESES REFER TO LTC1861 CONVERT CLK SDO SERIAL PORT BIAS AND SHUTDOWN DATA IN 12-BITS IN+ (CH0) + IN– – (CH1) 12-BIT SAMPLING ADC DATA OUT 1860/61 BD VREF GND test circuits Load Circuit for tdDO, tr, tf, tdis and ten Voltage Waveforms for SDO Rise and Fall Times, tr, tf TEST POINT VOH SDO VOL VCC tdis WAVEFORM 2, ten 3k SDO tr tdis WAVEFORM 1 20pF tf 1860 TC04 1860 TC01 Voltage Waveforms for ten Voltage Waveforms for tdis CONV SDO 1860 TC03 ten Voltage Waveforms for SDO Delay Times, tdDO and thDO SCK VIH CONV SDO WAVEFORM 1 (SEE NOTE 1) SDO WAVEFORM 2 (SEE NOTE 2) 90% tdis 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL VIL tdDO thDO 1860 TC05 VOH SDO VOL 1860 TC02 10 18601fb For more information www.linear.com/LTC1860 LTC1860/LTC1861 applications information tsuCONV CONV tSMPL SLEEP MODE tCONV 1 2 3 4 5 6 7 8 9 10 11 12 SCK SDO B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Figure 1. LTC1860 Operating Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY Sequence 1860 F01 1µF 111111111111 111111111110 VCC • • • LTC1860 000000000001 000000000000 1 VIN* VREF *VIN = IN+ – IN– VREF – 1LSB VREF – 2LSB 1LSB 0V VIN = 0V TO VCC Figure 2. LTC1860 Transfer Curve 2 3 4 VREF VCC IN+ SCK IN– SDO GND CONV 8 7 6 5 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS 1860 F03 1860 F02 Figure 3. LTC1860 with Rail-to-Rail Input Span LTC1860 OPERATION Analog Inputs Operating Sequence The LTC1860 has a unipolar differential analog input. The converter will measure the voltage between the “IN + ” and “IN–” inputs. A zero code will occur when IN+ minus IN– equals zero. Full scale occurs when IN+ minus IN– equals VREF minus 1LSB. See Figure 2. Both the “IN+” and “IN–” inputs are sampled at the same time, so common mode noise on the inputs is rejected by the ADC. If “IN–” is grounded and VREF is tied to VCC, a rail-to-rail input span will result on “IN+” as shown in Figure 3. The LTC1860 conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1860 goes into sleep mode drawing only leakage current. On the falling edge of CONV, the LTC1860 goes into sample mode and SDO is enabled. SCK synchronizes the data transfer with each bit being transmitted from SDO on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 1. Reference Input The voltage on the reference input of the LTC1860 (and the LTC1861 MSOP package) defines the full-scale range of the A/D converter. These ADCs can operate with reference voltages from VCC to 1V. 18601fb For more information www.linear.com/LTC1860 11 LTC1860/LTC1861 Applications Information CONV SDI tSMPL SLEEP MODE tCONV S/D O/S DON’T CARE 1 2 DON’T CARE 3 4 5 6 7 8 9 10 11 12 SCK SDO B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1860 F04 Figure 4. LTC1861 Operating Sequence 111111111111 111111111110 • • • Table 1. Multiplexer Channel Selection VIN* 000000000001 000000000000 VCC VCC – 1LSB VCC – 2LSB 1LSB 0V *VIN = (SELECTED “+” CHANNEL) – (SELECTED “–” CHANNEL) REFER TO TABLE 1 1860 F05 SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE MUX ADDRESS SGL/DIFF ODD/SIGN 0 1 1 1 0 0 1 0 CHANNEL # 0 1 + + + – – + GND – – 186465 TBL1 Figure 5. LTC1861 Transfer Curve LTC1861 OPERATION Analog Inputs Operating Sequence The two bits of the input word (SDI) assign the MUX configuration for the next requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of the following table. In single‑ended mode, all input channels are measured with respect to GND (or AGND). A zero code will occur when the “+” input minus the “–” input equals zero. Full scale occurs when the “+” input minus the “–” input equals VREF minus 1LSB. See Figure 5. Both the “+” and “–” inputs are sampled at the same time so common mode noise is rejected. The input span in the SO-8 package is fixed at VREF = VCC. If the “–” input in differential mode is grounded, a rail-to-rail input span will result on the “+” input. The LTC1861 conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1861 goes into sleep mode. The LTC1861’s 2-bit data word is clocked into the SDI input on the rising edge of SCK after CONV goes low. Additional inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 4. 12 18601fb For more information www.linear.com/LTC1860 LTC1860/LTC1861 Applications Information Reference Input Bypassing The reference input of the LTC1861 SO-8 package is internally tied to VCC. The span of the A/D converter is therefore equal to VCC. The voltage on the reference input of the LTC1861 MSOP package defines the span of the A/D converter. The LTC1861 MSOP package can operate with reference voltages from 1V to VCC. For good performance, the VCC and VREF pins must be free of noise and ripple. Any changes in the VCC/VREF voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a minimum of 1µF tantalum. Keep the bypass capacitor leads as short as possible. GENERAL analog considerations Analog Inputs Grounding Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1860/ LTC1861 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if source resistances are less than 200Ω or high speed op amps are used (e.g., the LT®1211, LT1469, LT1807, LT1810, LT1630, LT1226 or LT1215). But if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins. The LTC1860/LTC1861 should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a printed circuit board. The ground pins (AGND and DGND for the LTC1861 MSOP package and GND for the LTC1860 and LTC1861 SO-8 package) should be tied directly to the analog ground plane with minimum lead length. 18601fb For more information www.linear.com/LTC1860 13 LTC1860/LTC1861 Package Description Please refer to http://www.linear.com/product/LTC1860#packaging for the most recent package drawings. MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.254 (.010) 8 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.52 (.0205) REF 0° – 6° TYP GAUGE PLANE 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC 0.53 ± 0.152 (.021 ± .006) DETAIL “A” RECOMMENDED SOLDER PAD LAYOUT 1 1.10 (.043) MAX 2 3 4 0.86 (.034) REF 0.18 (.007) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 14 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.1016 ± 0.0508 (.004 ± .002) MSOP (MS8) 0307 REV F 18601fb For more information www.linear.com/LTC1860 LTC1860/LTC1861 Package Description Please refer to http://www.linear.com/product/LTC1861#packaging for the most recent package drawings. MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 0.254 (.010) 3.20 – 3.45 (.126 – .136) 10 9 8 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.497 ± 0.076 (.0196 ± .003) REF 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.1016 ± 0.0508 (.004 ± .002) MSOP (MS) 0307 REV E 18601fb For more information www.linear.com/LTC1860 15 LTC1860/LTC1861 Package Description Please refer to http://www.linear.com/product/LTC1860#packaging for the most recent package drawings. S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610 Rev G) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 .245 MIN .160 ±.005 .010 – .020 × 45° (0.254 – 0.508) 2 .053 – .069 (1.346 – 1.752) 0°– 8° TYP .016 – .050 (0.406 – 1.270) .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE 16 5 .150 – .157 (3.810 – 3.988) NOTE 3 1 RECOMMENDED SOLDER PAD LAYOUT .008 – .010 (0.203 – 0.254) 6 .228 – .244 (5.791 – 6.197) .030 ±.005 TYP NOTE: 1. DIMENSIONS IN 7 3 4 .004 – .010 (0.101 – 0.254) .050 (1.270) BSC SO8 REV G 0212 18601fb For more information www.linear.com/LTC1860 LTC1860/LTC1861 Revision History (Revision history begins at Rev B) REV DATE DESCRIPTION B 05/16 Corrected Order Information PAGE NUMBER 3 18601fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC1860 17 LTC1860/LTC1861 Typical Application Sample Two Channels Simultaneously with a Single Input ADC f1 (0V TO 0.66V) 5V 0.1µF + 4.096V REF 5k – 100pF 20k 28.7k 5pF 10k 10k 2 1µF 5V 5k f2 (0V TO 2V) 4.096V REF 100Ω 1/2 LT1492 0.1µF + – 8 3 1µF 0.1µF 1µF 8 VCC IN+ IN– 0.1µF 1 REF 7 SCK 6 LTC1860 SDO 5 CONV GND 4 100Ω 1/2 LT1492 4 0.1µF 100pF 1860 TA03 Related Parts PART NUMBER SAMPLE RATE POWER DISSIPATION DESCRIPTION 12-Bit Serial I/O ADCs LTC1286/LTC1298 12.5ksps/11.1ksps 1.3mW/1.7mW 1-Channel with Ref. Input (LTC1286), 2-Channel (LTC1298), 5V LTC1400 400ksps 75mW 1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V LTC1401 200ksps 15mW SO-8 with Internal Reference, 3V LTC1402 2.2Msps 90mW Serial I/O, Bipolar or Unipolar, Internal Reference LTC1404 600ksps 25mW SO-8 with Internal Reference, Bipolar or Unipolar, 5V LTC1417 400ksps 20mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V LTC1418 200ksps 15mW Serial/Parallel I/O, Internal Reference, 5V LTC1609 200ksps 65mW Configurable Bipolar or Unipolar Input Ranges, 5V LTC1864/LTC1865 250ksps 4.25mW SO-8, MS8, 1-Channel, 5V/SO-8, MS10, 2-Channel, 5V 14-Bit Serial I/O ADCs 16-Bit Serial I/O ADCs References LT1460 Micropower Precision Series Reference Bandgap, 130µA Supply Current, 10ppm/°C, Available in SOT-23 LT1790 Micropower Low Dropout Reference 60µA Supply Current, 10ppm/°C, SOT-23 18 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC1860 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC1860 18601fb LT 0516 REV B • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 2007