LTC1922EG-1#TRPBF

LTC1922-1 Synchronous Phase Modulated Full-Bridge Controller DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Adaptive DirectSenseTM Zero Voltage Switching Integrated Synchronous Rectification Control for Highest Efficiency Output Power Levels from 50W to Kilowatts Very Low Start-Up and Quiescent Currents Compatible with Voltage Mode and Current Mode Topologies Programmable Slope Compensation Undervoltage Lockout Circuitry with 4.2V Hysteresis and Integrated 10.3V Shunt Regulator Fixed Frequency Operation to 1MHz 50mA Outputs for Bridge Drive and Secondary Side Synchronous Rectifiers Soft-Start, Cycle-by-Cycle Current Limiting and Hiccup Mode Short-Circuit Protection 5V, 15mA Low Dropout Regulator 20-Pin PDIP and SSOP Packages U APPLICATIO S ■ ■ ■ Telecommunications, Infrastructure Power Systems Distributed Power Architectures Server Power Supplies High Density Power Modules The LTC1922-1 also provides secondary side synchronous rectifier control. The device uses peak current mode control with programmable slope comp and leading edge blanking. The LTC1922-1 features extremely low operating and start-up currents to simplify off-line start-up and bias circuitry. The LTC1922-1 also includes a full range of protection features and is available in 20-pin through hole (N) and surface mount (G) packages. , LTC and LT are registered trademarks of Linear Technology Corporation. DirectSense is a trademark of Linear Technology Corporation. U ■ The LTC®1922-1 phase shift PWM controller provides all of the control and protection functions necessary to implement a high performance, zero voltage switched, phase shift, full-bridge power converter with synchronous rectification. The part is ideal for developing isolated, low voltage, high current outputs from a high voltage input source. The LTC1922-1 combines the benefits of the fullbridge topology with fixed frequency, zero voltage switching operation (ZVS). Adaptive ZVS circuity controls the turn-on signals for each MOSFET independent of internal and external component tolerances for optimal performance. TYPICAL APPLICATIO VIN 48V BIAS SUPPLY Efficiency 100 VOUT 3.3V EFFICIENCY (%) 90 VIN = 48V VIN = 36V 80 70 LTC1922-1 ISOLATED FEEDBACK 60 0 10 20 30 40 LOAD CURRENT (A) 1922 • TA01b 1922 TA01a 1 LTC1922-1 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) ORDER PART NUMBER TOP VIEW VCC to GND Low Impedance Source ......................... –0.3V to 10V (Chip Self Regulates at 10.3V) All Other Pins to GND (Low Impedance Source) ..................... –0.3V to 5.5V VCC (Current Fed) .................................................. 25mA VREF Output Current ................................ Self Regulated Outputs (A, B, C, D, E, F) Current ..................... ±100mA Operating Temperature Range (Note 5) LTC1922E ........................................... – 40°C to 85°C LTC1922I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 125°C Lead Temperature (Soldering, 10 sec).................. 300°C SYNC 1 20 CT RAMP 2 19 GND CS 3 18 OUTA COMP 4 17 OUTB RLEB 5 16 OUTC FB 6 15 VCC SS 7 14 OUTD PDLY 8 13 OUTE SBUS 9 12 OUTF ADLY 10 11 VREF G PACKAGE 20-LEAD PLASTIC SSOP LTC1922EG-1 LTC1922IG-1 LTC1922EN-1 LTC1922IN-1 N PACKAGE 20-LEAD PDIP TJMAX = 125°C, θJA = 110°C/W (G) TJMAX = 125°C,θJA = 62°C/W (N) Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at VCC = 9.5V, CT = 180pF, TA = TMIN to TMAX unless other wise noted. SYMBOL PARAMETER CONDITIONS UVLO Undervoltage Lockout Measured on VCC UVHY UVLO Hysteresis Measured on VCC ICCST Start-Up Current VCC = VUVLO – 0.3V ICCRN Operating Current VSHUNT Shunt Regulator Voltage RSHUNT MIN TYP MAX UNITS 10.25 10.7 V Input Supply 3.8 4.2 V 145 250 µA 4 7 mA Current Into VCC = 10mA 10.2 10.8 V Shunt Resistance Current Into VCC = 7mA to 17mA –1.5 2 Ω DTHR Delay Pin Threshold ADLY and PDLY SBUS = 1.5V SBUS = 2.25V 1.38 2.08 1.50 2.25 1.62 2.42 V V DHYS Delay Hysteresis Current ADLY and PDLY SBUS = 1.5V, ADLY/PDLY = 1.6V 1.1 1.3 1.45 mA DTMO Delay Time-Out SBUS = 1.5V SBUS = 2.25V DZRT Zero Delay Threshold Measured on SBUS ● Delay Blocks 600 900 3 4.15 ns ns 5 V Phase Modulator ROS RAMP Offset Voltage Measured on COMP, RAMP = 0V 0.4 V IRMP RAMP Discharge Current RAMP = 1V, COMP = 0V 30 50 mA ISLP Slope Compensation Current Measured on CS, CT = 1.5V CT = 3V 35 70 55 110 DCMX Maximum Phase Shift COMP = 4V ● 95 99.5 DCMN Minimum Phase Shift COMP = 0V ● 2 0.1 75 150 µA µA % 0.6 % LTC1922-1 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at VCC = 9.5V, CT = 180pF, TA = TMIN to TMAX unless other wise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS OSCT Total Variation VCC = 6.5V to 9.5V 236 277 319 kHz OSCV CT RAMP Amplitude OSYT SYNC Threshold Measured on CT 3.6 3.85 4.2 V Measured on SYNC 1.6 1.8 2.2 V OSYW Minimum SYNC Pulse Width Measured at Outputs (Note 2) OSYWX Maximum SYNC Pulse Width Measured on Outputs, CT = 180pF OSOP SYNC Output Pulse Width Measured on SYNC, RSYNC = 5.1k Oscillator ● 6 ns 1.3 170 µs ns Error Amplifier VFB FB Input Voltage COMP = 2.5V (Note 3) 1.179 FBI FB Input Range Measured on FB (Note 4) –0.3 1.204 AVOL Open-Loop Gain COMP = 1V to 3V (Note 3) 70 90 IIB Input Bias Current COMP = 2.5V (Note 3) VOH Output High Load on COMP = –100µA 4.7 4.92 VOL Output Low Load on COMP = 100µA ISOURCE Output Source Current COMP = 2.5V – 400 – 800 µA ISINK Output Sink Current COMP = 2.5V 3 7 mA VREF Initial Accuracy TA = 25°C, Measured on VREF 4.925 5 5.075 V REFTV Total Variation Line, Load and Temperature 4.9 5 5.1 V REFLD Load Regulation Load on VREF = 100µA to 5mA 2 15 mV REFLN Line Regulation VCC = 6.5V to 9.5V 0.1 10 mV REFSC Short-Circuit Current VREF Shorted to GND 18 30 45 mA OUTH(X) Output High Voltage IOUT(X) = –50mA 7.9 8.4 OUTL(X) Output Low Voltage IOUT(X) = 50mA 0.6 1 V RHI(X) Pull-Up Resistance IOUT(X) = –50mA to –10mA 22 30 Ω RLO(X) Pull-Down Resistance IOUT(X) = –50mA to –10mA 12 20 Ω tr(X) Rise Time COUT(X) = 50pF 5 15 ns tf(X) Fall Time COUT(X) = 50pF 5 15 ns 5 0.18 1.229 V 2.5 V dB 50 nA V 0.4 V Reference ● Outputs V Current Limit and Shutdown CLPP Pulse-by-Pulse Current Limit Threshold Measured on CS 0.34 0.415 0.48 V CLSD Shutdown Current Limit Threshold Measured on CS 0.55 0.64 0.73 V SSI Soft-Start Current SS = 2.5V 7 12 17 µA SSR Soft-Start Reset Threshold Measured on SS 0.7 0.4 0.1 V FLT FAULT Reset Threshold Measured on SS 4.4 4.1 3.8 V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: SYNC pulse width is valid from >20ns and 1/2 • 2 • COSS • VIN2 — the worst case occurs when the load current is zero. This condition is usually easy to meet. The magnetizing current is virtually constant during this transition because the magnetizing inductance has positive voltage applied across it throughout the low to high transition. Since the leg is actively driven by this “current source,” it is called the active or linear transition. When the voltage on the active leg has 9 LTC1922-1 U OPERATIO .and must be considered when specifying the power transformer. If ZVS is required over the entire range of loads, a small commutating inductor is added in series with the primary to aid with the passive leg transition, since the leakage inductance alone is usually not sufficient and predictable enough to guarantee ZVS over the full load range. State 1. State 4 (Power Pulse 2) During power pulse 2, current builds up in the primary winding in the opposite direction as power pulse 1. The primary current consists of reflected output inductor current and current due to the primary magnetizing inductance. At the end of State 4, MOSFET MC turns off and an active transition, essentially similar to State 2, but opposite in direction (high to low) takes place. POWER PULSE 1 VIN VOUT L1 MA MC MB MD N:1 LOAD L2 + MF ME IP ≈ IL01/N + (VIN • TOVL)/LMAG PRIMARY AND SECONDARY SHORTED State 2. ACTIVE TRANSITION MA FREEWHEEL INTERVAL MC VOUT MA MC LOAD MB MD MB MD MF State 3. PASSIVE TRANSITION MA MC MB MD State 4. MA POWER PULSE 2 VOUT MC LOAD MB + MD MF ME 1922 F01 Figure 1. ZVS Operation 10 ME LTC1922-1 U OPERATIO Zero Voltage Switching (ZVS) Adaptive Mode A lossless switching transition requires that the respective full-bridge MOSFETs be switched to the “ON” state at the exact instant their drain to source voltage is zero. Delaying the turn-on results in lower efficiency due to circulating current flowing in the body diode of the primary side MOSFET rather than its low resistance channel. Premature turn-on produces hard switching of the MOSFETs, increasing noise and power dissipation. Previous solutions have attempted to meet these requirements with fixed or first order (linear) variable open-loop time delays. Openloop methods typically set the turn-on delay to the worst case longest bridge transition time expected plus the tolerances of all the internal and external delay timing circuitry. These error tolerances can be quite significant, while the optimal transition times over the load current range vary nonlinearly. In a volume production environment, these factors can necessitate an external trim to guarantee ZVS operation, adding cost to the final product. An additional side effect of longer than required delays is a decrease in the effective maximum duty cycle. Reduced duty cycle range can mandate a lower transformer turns ratio, impacting efficiency or requiring a lower switching frequency, impacting size. The LTC1922-1 is configured for adaptive delay sensing with three pins, ADLY, PDLY and SBUS. ADLY and PDLY sense the active and passive delay legs respectively via a voltage divider network as shown in Figure 2. LTC1922-1 Adaptive Delay Circuitry The LTC1922-1 addresses the issue of nonideal switching delays with novel DirectSense circuitry that intelligently monitors both the input supply and instantaneous bridge leg voltages, and commands a switching transition when the expected zero voltage condition is reached. In effect, the LTC1922-1 “closes the loop” on the ZVS turn-on delay requirements. DirectSense technology provides optimal turn-on delay timing, regardless of input voltage, output load, or component tolerances and greatly simplifies the power supply design process. The DirectSense technique requires only a simple voltage divider sense network to implement. If there is not enough energy to fully commutate the bridge leg to a ZVS condition, the LTC1922-1 automatically overrides the DirectSense circuitry and forces a transition. The LTC1922-1 delay circuitry can also be overridden, by tying SBUS to VREF. VIN A R2 C ADLY SBUS R5 R6 PDLY B R1 D R3 1k R4 1k RCS 1922 F02 Figure 2. Adaptive Mode The threshold voltage on PDLY and ADLY for both the rising and falling transitions is set by the voltage on SBUS. A buffered version of this voltage is used as the threshold level for the internal DirectSense circuitry. At nominal VIN, the voltage on SBUS is set to 1.5V by an external voltage divider between VIN and GND, making this voltage directly proportional to VIN. The LTC1922-1 DirectSense circuitry uses this characteristic to zero voltage switch all of the external power MOSFETs, independent of input voltage. ADLY and PDLY are connected through voltage dividers to the active and passive bridge legs respectively. The lower resistor in the divider is set to 1k. The upper resistor in the divider is divided into one, two or three equal value resistors to reduce its overall capacitance. In off-line applications, this is usually required anyway to stay within the maximum voltage ratings of the resistors. One or two resistor segments will work for most nominal 48V or lower VIN applications. To set up the ADLY and PDLY resistors, first determine at what drain to source voltage to turn-on the MOSFETs. Finite delays exist between the time at which the LTC1922-1 controller output transitions, to the time at which the power MOSFET switches on due to MOSFET turn on delay and external driver circuit delay. Ideally, we want the power MOSFET to switch at the instant there is zero volts across it. By setting a threshold voltage for ADLY and 11 LTC1922-1 U OPERATIO PDLY corresponding to several volts across the MOSFET, the LTC1922-1 can “anticipate” a zero voltage VDS and signal the external driver and switch to turn-on. The amount of anticipation can be tailored for any application by modifying the upper divider resistor(s). The LTC1922-1 DirectSense circuitry sources a trimmed current out of PDLY and ADLY after a low to high level transition occurs. This provides hysteresis and noise immunity for the PDLY and ADLY circuitry, and sets the high to low threshold on ADLY or PDLY to nearly the same level as the low to high threshold, thereby making the upper and lower MOSFET VDS switch points virtually identical, independent of VIN. to VCC as well as signaling that the chip’s bias voltage is sufficient to begin switching operation (under voltage lockout). With its typical 10.2V turn-on voltage and 4.2V UVLO hysteresis, the LTC1922-1 is tolerant of loosely regulated input sources such as an auxiliary transformer winding. The VCC shunt is capable of sinking up to 25mA of externally applied current. The UVLO turn-on and turnoff thresholds are derived from an internally trimmed reference making them extremely accurate. In addition, the LTC1922-1 exhibits very low (145µA typ) start-up current that allows the use of 1/8W to 1/4W trickle charge start-up resistors. Example: VIN = 48V nominal (36V to 72V) The trickle charge resistor should be selected as follows: 1. Set up SBUS: 1.5V is desired on SBUS with VIN = 48V. Set divider current to 100µA. RSTART(MAX) = VIN(MIN) – 10.7V/250µA R1 = 1.5V/100µA = 15k. Adding a small safety margin and choosing standard values yields: R2 = (48V – 1.5V)/100µA = 465k. APPLICATION VIN RANGE RSTART DC/DC 36V to 72V 100k Off-Line 85V to 270VRMS 430k 390VDC 1.4M An optional small capacitor (0.001µF) can be added across R1 to decouple noise from this input. 2. Set up ADLY and PDLY: 7V of “anticipation” are required in this circuit to account for the delays of the external MOSFET driver and gate drive components. R3, R4 = 1k, sets a nominal 1.5mA in the divider chain at the threshold. R5, R6 = (48V – 7V – 1.5V)/1.5mA = 26.3k, use (2) equal 13k segments. PFC Preregulator VCC should be bypassed with a 0.1µF to 1µF multilayer ceramic capacitor to decouple the fast transient currents demanded by the output drivers and a bulk tantalum or electrolytic capacitor to hold up the VCC supply before the bootstrap winding, or an auxiliary regulator circuit takes over. CHOLDUP = (ICC + IDRIVE) • tDELAY/3.8V (minimum UVLO hysteresis) Zero Delay Mode The LTC1922-1 provides the flexibility through the SBUS pin to disable the DirectSense delay circuitry. See Figure␣ 3 for details. Regulated bias supplies as low as 7V can be utilized to provide bias to the LTC1922-1. Refer to Figure 4 for various bias supply configurations. VREF VIN SBUS 12V ±10% VBIAS < VUVLO ADLY PDLY 1922 F03 1.5k 1N5226 3V 1N914 RSTART + Figure 3. Zero Delays 0.1µF 0.1µF CHOLD Powering the LTC1922-1 The LTC1922-1 utilizes an integrated VCC shunt regulator to serve the dual purposes of limiting the voltage applied 12 VCC VCC Figure 4. Bias Configurations 1922 F04 LTC1922-1 U OPERATIO Off-Line Bias Supply Generation If a regulated bias supply is not available to provide VCC voltage to the LTC1922-1 and supporting circuitry, one must be generated. Since the power requirement is small, approximately 1W, and the regulation is not critical, a simple open-loop method is usually the easiest and lowest cost approach. One method that works well is to add a winding to the main power transformer, and post regulate the resultant square wave with an L-C filter (see Figure␣ 5a). The advantage of this approach is that it maintains decent regulation as the supply voltage varies, and it does not require full safety isolation from the input winding of the transformer. Some manufacturers include a primary winding for this purpose in their standard product offerings as well. A different approach is to add a winding to the output inductor and peak detect and filter the square wave signal (see Figure 5b). The polarity of this winding is designed so that the positive voltage square wave is produced while the output inductor is freewheeling. An advantage of this technique over the previous is that it does not require a separate filter inductor and since the voltage is derived from the well-regulated output voltage, it is also well controlled. One disadvantage is that this winding will require the same safety isolation that is required for the main transformer. Another disadvantage is that a much larger VCC filter capacitor is needed, since it does not VIN 2k + 0.1µF CHOLD 1922 F05a *OPTIONAL Figure 5a. Auxiliary Winding Bias Supply VIN VOUT LOUT RSTART ISO BARRIER Programming the LTC1922-1 Oscillator The high accuracy LTC1922-1 oscillator circuit provides flexibility to program the switching frequency, slope compensation, and synchronization with minimal external components. The LTC1922-1 oscillator circuitry produces a 3.8V peak-to-peak amplitude ramp waveform on CT and a narrow pulse on SYNC that can be used to synchronize other PWM chips. Typical maximum duty cycles of 99% are obtained at 300kHz and 97% at 1MHz. The large amplitude ramp provides a high degree of noise margin. A compensating slope current is derived from the oscillator ramp waveform and sourced out of CS. The desired amount of slope compensation is selected with single external resistor (or no resistor), if not required. A capacitor to GND on CT programs the switching frequency. The CT ramp discharge current is internally set to a high value (>10mA). The dedicated SYNC I/O pin easily achieves synchronization. The LTC1922-1 can be set up to either synchronize other PWM chips or be synchronized by another chip or external clock source. The 1.8V SYNC threshold allows the LTC1922-1 to be synchronized directly from all standard 3V and 5V logic families. Design Procedure: VCC RSTART 15V* generate a voltage as the output is first starting up, or during short-circuit conditions. + 1. Choose CT for the desired oscillator frequency. The switching frequency selected must be consistent with the power magnetics and output power level. This is detailed in the Transformer Design section. In general, increasing the switching frequency will decrease the maximum achievable output power, due to limitations of maximum duty cycle imposed by transformer core reset and ZVS. Remember that the output frequency is 1/2 that of the oscillator. CT = 1/(20k • fOSC) Example: Desired fOSC = 330kHz 0.1µF VCC CHOLD 1922 F05b Figure 5b. Output Inductor Bias Supply CT = 1/(20k • 330kHz) = 152pF, choose closest standard value of 150pF. A 5% or better tolerance multilayer NPO or X7R ceramic capacitor is recommended for best performance. 13 LTC1922-1 U OPERATIO 2. The LTC1922-1 can either synchronize other PWMs, or be synchronized to an external frequency source or PWM chip. See Figure 6 for details. CT OF SLAVE(S) IS 1.25 CT OF MASTER. LTC1922-1 CT 5.1k MASTER CT SYNC CT 5.1k SYNC CT LTC1922-1 1k 1k SYNC • • 5.1k • UP TO 5 SLAVES LTC1922-1 CT CT (33µA/V(CT)). Thus, at the peak of CT, this current is approximately 125µA and is output from the CS pin. A resistor connected between CS and the external current sense resistor sums in the required amount of slope compensation. The value of this resistor is dependent on several factors including minimum VIN, VOUT, switching frequency, current sense resistor value and output inductor value. An illustrative example with the design equation is provided below. Example: VIN = 36V to 72V SLAVES VOUT = 3.3V 1922 F06a Figure 6a. SYNC Output (Master Mode) IOUT = 40A L = 2.2µH AMPLITUDE > 1.8V 12.5ns < PW < 0.4/ƒ EXTERNAL FREQUENCY SOURCE 1k SYNC 5.1k LTC1922-1 CT Transformer turns ratio (N) = VIN(MIN) • DMAX/ VOUT␣ =␣ 3 RCS = 0.025Ω CT 1922 F06b fSW = 300kHz, i.e., transformer f = fSW/2 = 150kHz Figure 6b. SYNC Input from an External Source RSLOPE = VO • RCS/(2 • L • fT • 125µA • N) = 3.3V • 0.025/ (2 • 2.2µA • 100k • 125µA • 3) 3. Slope compensation is required for most peak current mode controllers in order to prevent subharmonic oscillation of the current control loop. In general, if the system duty cycle exceeds 50% in a fixed frequency, continuous current mode converter, an unstable condition exists within the current control loop. Any perturbation in the current signal is amplified by the PWM modulator resulting in an unstable condition. Some common manifestations of this include alternate pulse nonuniformity and pulse width jitter. Fortunately, this can be addressed by adding a corrective slope to the current sense signal or by subtracting the same slope from the current command signal (error amplifier output). In theory, the current doubler output configuration does not require slope compensation since the output inductor duty cycles only approach 50%. However, transient conditions can momentarily cause higher duty cycles and therefore, the possibility for unstable operation. The exact amount of required slope compensation is easily programmed by the LTC1922-1 with the addition of a single external resistor (see Figure 7). The LTC1922-1 generates a current that is proportional to the instantaneous voltage on C T , RSLOPE = 500Ω, choose the next higher standard value to account for tolerances in ISLOPE, RCS, N and L. 14 LTC1922-1 CT I= 33k V(CT) 33k BRIDGE CURRENT CS RSLOPE ADDED SLOPE CURRENT SENSE WAVEFORM RCS 1922 F07 Figure 7. Slope Compensation Circuitry Current Sensing and Overcurrent Protection Current sensing provides feedback for the current mode control loop and protection from overload conditions. The LTC1922-1 is compatible with either resistive sensing or current transformer methods. Internally connected to the LTC1922-1 CS pin are two comparators that provide pulse-by-pulse and overcurrent shutdown functions respectively. (See Figure 8) LTC1922-1 U OPERATIO PULSE BY PULSE CURRENT LIMIT φMOD + Q S Q S – R OVERLOAD CURRENT LIMIT + S Q – UVLO ENABLE 4.1V R 12µA SS 0.4V + 600mV PWM LOGIC – RCS 400mV Q H = SHUTDOWN OUTPUTS UVLO ENABLE + CS PWM LATCH CSS – Q 1922 F08 Figure 8. Current Sense/Fault Circuitry Detail The pulse-by-pulse comparator has a 400mV nominal threshold, which can reduce sense resistor losses by 67% compared to previous solutions. This corresponds to 3W in a 200W, 48V to 3.3V converter. If the 400mV threshold is exceeded, the PWM cycle is terminated. The overcurrent comparator is set approximately 50% higher than the pulse-by-pulse level. If the current signal exceeds this level, the PWM cycle is terminated, the soft-start capacitor is quickly discharged and a soft-start cycle is initiated. If the overcurrent condition persists, the LTC1922-1 halts PWM operation and waits for the soft-start capacitor to charge up to approximately 4V before a retry is allowed. The soft-start capacitor is charged by an internal 12µA current source. If the fault condition has not cleared when soft-start reaches 4V, the soft-start pin is again discharged and a new cycle is initiated. This is referred to as hiccup mode operation. In normal operation and under most abnormal conditions, the pulse-by-pulse comparator is fast enough to prevent hiccup mode operation. In severe cases, however, with high input voltage, very low RDS(ON) MOSFETs and a shorted output, or with saturating magnetics, the overcurrent comparator provides a means of protecting the power converter. Leading Edge Blanking The LTC1922-1 provides programmable leading edge blanking to prevent nuisance tripping of the current sense circuitry. Although the ZVS full-bridge topology is somewhat more immune to leading edge noise spikes than other types of converters, they are not totally eliminated. Leading edge blanking relieves the filtering requirements for the CS pin, greatly improving the response to real overcurrent conditions. It also allows the use of a ground referenced current sense resistor or transformer(s), further simplifying the design. With a single 10k to 100k resistor from RLEB to GND, blanking times of approximately 40ns to 320ns are programmed. If not required, connecting RLEB to VREF can disable leading edge blanking. Keep in mind that the use of leading edge blanking will set a minimum linear control range for the phase modulation circuitry. Resistive Sensing A resistor connected between input common and the sources of MB and MD is the simplest, fastest and most accurate method of current sensing for the full-bridge converter. This is the preferred method for low to moderate power levels. A graph of resistive sense power losses vs output power is shown Figure 9. The sense resistor should be chosen such that the maximum rated output current for the converter can be delivered at the lowest expected VIN. Use the following formula to calculate the optimal value for RCS. 15 LTC1922-1 U OPERATIO POWER LOSS (W) 2.0 RS = 0.025 1.8 VIN = 48V VO = 3.3V 1.6 LO = 2.2µH 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 5 10 15 20 25 30 OUTPUT CURRENT (A) 35 40 1922 • F09 Figure 9. RSENSE Power Loss vs IOUT If RAMP and CS are connected together: RCS = 0.4V – (125µA • RSLOPE) IP (PEAK) IP (PEAK) = IO(MAX) + VIN(MAX) • 2 • DMIN LMAG • f CLK 2 • N • EFF VO (1 – DMIN ) LOUT • f CLK• N + where: N = Transformer turns ratio If RAMP and CS are separated RCS 0.4V = IP (PEAK) include, higher cost and complexity, lower accuracy, core reset/max duty cycle limitations and lower speed. Nevertheless, for very high power applications, this method is preferred. The sense transformer primary is placed in the same location as the ground referenced sense resistor, or between the upper MOSFET drains in the (MA, MC) and VIN. The advantage of the high side location is a greater immunity to leading edge noise spikes, since gate charge current and reflected rectifier recovery current are largely eliminated. Figure 10 illustrates a typical current sense transformer based sensing scheme. RS in this case is calculated the same as in the resistive case, only its value is increased by the sense transformer turns ratio. At high duty cycles, it may become difficult or impossible to reset the current transformer. This is because the required transformer reset voltage increases as the available time for reset decreases to equalize the (volt • seconds) applied. The interwinding capacitance and secondary inductance of the current sense transformer form a resonant circuit that limits the dV/dT on the secondary of the CS transformer. This in turn limits the maximum achievable duty cycle for the CS transformer. Attempts to operate beyond this limit will cause the transformer core to “walk” and eventually saturate, opening up the current feedback loop. Common methods to address this limitation include: 1. Reducing the maximum duty cycle by lowering the power transformer turns ratio. 2. Reducing the switching frequency of the converter. 3. Employ external active reset circuitry. 4. Using two CS transformers summed together. Current Transformer Sensing A current sense transformer can be used in lieu of resistive sensing with the LTC1922-1. Current sense transformers are available in many styles from several manufacturers. A typical sense transformer for this application will use a 1:50 turns ratio (N), so that the sense resistor value is N times larger, and the secondary current N times smaller than in the resistive sense case. Therefore, the sense resistor power loss is about N times less with the transformer method, neglecting the transformers core and copper losses. The disadvantages of this approach 16 5. Choose a CS transformer optimized for high frequency applications. MD SOURCE MB SOURCE RSLOPE N:1 RAMP RS CURRENT TRANSFORMER CS OPTIONAL FILTERING Figure 10. Current Transformer Sense Circuitry 1922 F10 LTC1922-1 U OPERATIO Phase Modulator (MA-MD or MB-MC) conduct and cause current in an output inductor to increase. This current is seen on the primary of the power transformer divided by the turns ratio. Since the current sense resistor is connected between GND and the two bottom bridge transistors, a voltage proportional to the output inductor current will be seen across RSENSE. The high side of RSENSE is also connected to RAMP and CS, usually through a small resistor (RSLOPE). When the voltage on RAMP/CS exceeds either COMP/5.2 – 400mV, or 400mv, the overlap conduction period will terminate. During normal operation, the attenuated COMP voltage will determine the RAMP/CS trip point. During start-up, or slewing conditions following a large load step, the 400mV CS threshold will terminate the cycle, as COMP will be driven high, such that the attenuated version exceeds the 400mV threshold. In extreme conditions, the 600mV threshold on CS will be exceeded, invoking a soft-start/restart cycle. The LTC1922-1 phase modulation control circuitry is comprised of the phase modulation comparator and logic, the error amplifier, and the soft-start amplifier (see Figure␣ 11). Together, these elements develop the required phase overlap (duty cycle) required to keep the output voltage in regulation. In isolated applications, the sensed output voltage error signal is fed back to COMP across the input to output isolation boundary by an optical coupler and shunt reference/error amplifier (LT®1431) combination. The FB pin is connected to GND, forcing COMP high. The collector of the optoisolator is connected to COMP directly. The voltage COMP is internally attenuated by the LTC1922-1. The attenuated COMP voltage provides one input to the phase modulation comparator. This is the current command. The other input to the phase modulation comparator is the RAMP voltage, level shifted by approximately 400mV. This is the current loop feedback. During every switching cycle, alternate diagonal switches FB + 1.2V TOGGLE F/F Q ERROR AMPLIFIER – 50k PHASE MODULATION COMPARATOR COMP VREF SS Q – PHASE MODULATION LOGIC + S Q + 12µA + A CLK CLK 400mV SOFT-START AMPLIFIER – B C D R FROM CURRENT LIMIT COMPARATOR – 14.9k RLEB RAMP BLANKING Q S R CLK 1922 F11 Figure 11. Phase Modulation Circuitry 17 LTC1922-1 U OPERATIO Selecting the Power Stage Components Perhaps the most critical part of the overall design of the converter is selecting the power MOSFETs, transformer, inductors and filter capacitors. Tremendous gains in efficiency, transient performance and overall operation can be obtained as long as a few simple guidelines are followed with the phase shifted full-bridge topology. Power Transformer This guide is aimed at selecting readily available standard “off the shelf” transformers. The basic requirements, however, apply to custom transformer designs as well. Switching frequency, core material characteristics, series resistance and input/output voltages all play an important role in transformer selection. Close attention also needs to be paid to leakage and magnetizing inductances as they play an important role in how well the converter will achieve ZVS. Planar magnetics are very well suited to these applications because of their excellent control of these parameters. Turns Ratio impact on efficiency. Other factors to consider are switching frequency and required maximum duty cycle. A lower value of magnetizing inductance will require a longer time to reset the core, cutting into the available duty cycle range. As switching frequencies increase, this becomes more significant. In general, the magnetizing inductance value should be the lowest value required in order to achieve the necessary maximum duty cycle at the chosen switching frequency. Output inductor value determines the magnitude of output ripple current and therefore the ripple voltage along with the output capacitors. Generally speaking, the output inductance should be minimized as much as possible in order to improve transient response. In addition, output capacitance ESR should be minimized as much as possible. Using the equations below, plug in the manufacturers magnetizing inductance value and a “starting value” of commutating inductance (1% of LMAG) to verify that a sufficient max duty cycle can be achieved at the desired switching frequency. Next, use equation (2) to determine what the absolute minimum required LCOM is to guarantee ZVT over the entire load range. One or two iterations may be required in order to arrive at the final selections. The required turns ratio for a current doubler secondary is given below. Depending on the magnetics selected, this value may need to be reduced slightly. MAX DC vs LCOM at fSW Turns ratio formula: MAX DC ≥ N = 2• 2 – f SW • TR ; 2 (1) VIN(MIN) • DMAX VOUT where: VIN(MIN) = Minimum VIN for operation DMAX = Maximum duty cycle of controller where: TR = transformer reset time (worst case) = IO(MAX) • f SW • LMAG + VIN • 2 • D • N  LCOM + LL    f SW • LMAG • N VIN   Magnetizing, Output, and Leakage Inductors A lower value of magnetizing and output inductance will improve the ability of the converter to achieve ZVS over the full range of loads and reduce the size of the external commutating inductor. One of the trade-offs is increased primary referred ripple current which has a small negative 18 LCOM vs ZVS vs Load 2 LCOM + LL = 2 4 / 3 C OSS • LMAG • f SW 2 • D2 (2) LTC1922-1 U OPERATIO where: COSS = MOSFET D-S capacitance lMAG = magnetizing inductance fSW = switching frequency D = duty cycle LL = leakage inductance For a 48V to 3.3V/5V, 200W converter, the following values were derived: fSW LMAG LCOM LOUT : 300kHz : 100µH : 0.9µH : 2.2µH Turns Ratio (N) = 2.5 Output Capacitors Output capacitor selection has a dramatic impact on ripple voltage, dynamic response to transients and stability. Capacitor ESR along with output inductor ripple current will determine the peak-to-peak voltage ripple on the output. The current doubler configuration is advantageous because it has inherent ripple current reduction. The dual output inductors deliver current to the output capacitor 180 degrees out of phase, in effect, partially canceling each other’s ripple current. This reduction is maximized at high duty cycle and decreases as the duty cycle reduces. This means that a current doubler converter requires less output capacitance for the same performance as a conventional converter. By determining the minimum duty cycle for the converter, worse-case VOUT ripple can be derived by the formula given below. VORIPPLE = IRIPPLE • ESR = VO • ESR (1 – D)(1 – 2D) LO • 2 • f SW where: D = minimum duty cycle fSW = oscillator frequency LO = output inductance ESR = output capacitor series resistance The amount of bulk capacitance required is usually system dependent, but has some relationship to output inductance value, switching frequency, load power and dynamic load characteristics. Polymer electrolytic capacitors are the preferred choice for their combination of low ESR, small size and high reliability. For less demanding applications, or those not constrained by size, aluminum electrolytic capacitors are commonly applied. Most DC/DC converters in the 100kHz to 300kHz range use 20µF to 25µF of bulk capacitance per watt of output power. Converters switching at higher frequencies can usually use less bulk capacitance. In systems where dynamic response is critical, additional high frequency capacitors, such as ceramics, can substantially reduce voltage transients, Power converter stability is, to a large extent, determined by the choice of output capacitor. A zero in the converter’s transfer function is given by 1/(2π • ESR • CO). Aluminum electrolytic ESR is highly variable with temperature, increasing by about 4× at cold temperatures, making the ESR zero frequency highly variable. Polymer electrolytic ESR is essentially flat with temperature. This characteristic simplifies loop compensation and allows for a much faster responding power supply compared to one with aluminum electrolytic capacitors. Specific details on loop compensation are given in the Compensation section of the data sheet. Power MOSFETs The full-bridge power MOSFETs should be selected for their RDS(ON) and BVDSS ratings. Select the lowest BVDSS rated MOSFET available for a given input voltage range leaving at least a 20% voltage margin. Conduction losses are directly proportional to RDS(ON). Since the full-bridge has two MOSFETs in the power path most of the time, conduction losses are approximately equal to: 2 • RDS(ON) • I2, where I = IO/2N Switching losses in the MOSFETs are dominated by the power required to charge their gates, and turn-on and turn-off losses. At higher power levels, gate charge power is seldom a significant contributor to efficiency loss. ZVS operation virtually eliminates turn-on losses. Turn-off losses are reduced by the use of an external drain to source 19 LTC1922-1 U OPERATIO snubber capacitor and/or a very low resistance turn-off driver. If synchronous rectifier MOSFETs are used on the secondary, the same general guidelines apply. Keep in mind, however, that the BVDSS rating needed for these can be greater than VIN(MAX)/N, depending on how well the secondary is snubbed. Without snubbing, the secondary voltage can ring to levels far beyond what is expected due to the resonant tank circuit formed between the secondary leakage inductance and the COSS (output capacitance) of the synchronous rectifier MOSFETs. Switching Frequency Selection Closing the Feedback Loop Closing the feedback loop with the full-bridge converter involves identifying where the power stage and other system poles/zeroes are located and then designing a compensation network around the converters error amplifier to shape the frequency response to insure adequate phase margin and transient response. Additional modifications will sometimes be required in order to deal with parasitic elements within the converter that can alter the feedback response. The compensation network will vary depending on the load current range and the type of output capacitors used. In isolated applications, the compensation network is generally located on the secondary side of the power supply, around the error amplifier of the optocoupler driver, usually an LT1431or equivalent. In nonisolated systems, the compensation network is located around the LTC1922-1’s error amplifier. Unless constrained by other system requirements, the power converter’s switching frequency is usually set as high as possible while staying within the desired efficiency target. The benefits of higher switching frequencies are many including smaller size, weight and reduced bulk capacitance. In the full-bridge phase shift converter, these principles are generally the same with the added complication of maintaining zero voltage transitions, and therefore, higher efficiency. ZVS is achieved in a finite time during the switching cycle. During the ZVS time, power is not delivered to the output; the act of ZVS reduces the maximum available duty cycle. This reduction is proportional to maximum output power since the parasitic capacitive element (MOSFETs) that increase ZVS time get larger as power levels increase. This implies an inverse relationship between output power level and switching frequency. Table 1 displays recommended maximum switching frequency vs power level for a 30V/75V in to 3.3V/5V out converter. Higher switching frequencies can be used if the input voltage range is limited, the output voltage is lower and/or lower efficiency can be tolerated. In current mode control, the dominant system pole is determined by the load resistance (VO/IO) and the output capacitor 1/(2π • RO • CO). The output capacitors ESR 1/(2π • ESR • CO) introduces a zero. Excellent DC line and load regulation can be obtained if there is high loop gain at DC. This requires an integrator type of compensator around the error amplifier. A procedure is provided for deriving the required compensation components. More complex types of compensation networks can be used to obtain higher bandwidth if necessary. Table 1.Switching Frequency vs Power Level Step 2. Calculate ESR zero location: 20