LTC1955
Dual Smart Card Interface
with Serial Control
Features
Description
Compatible with ISO7816-3 and EMV Electrical
Specifications
n Power Management and Control for Two Smart Cards
n Control/Status Serial Port May Be Daisychained for
Multicard Applications
n Automatic Shutdown on Electrical Faults
n Buck/Boost Charge Pump Generates 5V, 3V or 1.8V
Outputs (Smart Card Classes A, B and C)
n Independent 5V/3V/1.8V Level Control for Both Cards
n Automatic Level Translation
n Supervisory Functions Prevent Smart Card Faults
n Low Operating Current: 250µA Typical
n Ultralow Shutdown Current
n >10kV ESD on Smart Card Pins
n Small 32-Lead 5mm × 5mm QFN Package
The LTC®1955 provides all necessary supervisory and
power control functions for two smart cards, two S.A.M.
cards or a combination of S.A.M. and smart cards. It
provides a charge pump for battery-powered applications
as well as all necessary level shifting circuitry.
n
Applications
n
n
n
n
n
n
Handheld Payment Terminals
Pay Telephones
ATM Machines
POS Terminals
Computer Keyboards
Multiple S.A.M. Sockets
The card voltages can be independently set to 1.8V, 3V or
5V. Both card interfaces include a card detection channel
with automatic debounce circuitry. To reduce wiring costs,
the LTC1955 interfaces to a microcontroller via a simple
4-wire serial interface. Multiple devices may be connected
in daisychain fashion so that the number of wires to the
card socket board is independent of the number of sockets.
Status data is returned over the same interface.
Extensive security features ensure proper deactivation
sequencing in the event of a supply fault or a smart card
electrical fault. The smart card pins can withstand greater
than 10kV ESD in-situ with no additional components.
The LTC1955 is available in a low profile (0.75mm) 5mm
× 5mm QFN package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6356140, 6411531.
Typical Application
23
1
Deactivation Sequence
INPUT
POWER
12,13
0.1µF
4.7µF
9, 10
24
RST A
5V/DIV
27
CLK A
5V/DIV
4-WIRE
COMMAND
INTERFACE
I/O A
5V/DIV
VCCA
5V/DIV
28
26
25
29
10µs/DIV
1955 TA01a
180k
240k
4-WIRE
CARD
INTERFACE
30
32
31
22
DVCC
UNDERV
2
PRES A
CARD
DETECT
VBATT
LTC1955
GND
C8A
C4A
I/O A
FAULT
RST A
CLK A
DIN
VCCA
DOUT
SCLK
PRES B
LD
I/O B
DATA
RIN
RST B
SYNC
CLK B
ASYNC
VCCB
NC/NO
C+
14
1µF
C–
11
3
4
5
6
7
SMART CARD
8
21
1µF
20
19
18
VENDOR CARD
17
1µF
CPO
1955 TA01b
15
4.7µF
1955fd
For more information www.linear.com/LTC1955
1
LTC1955
Absolute Maximum Ratings
Pin Configuration
(Note 1)
VBATT, DVCC, CPO, FAULT,
UNDERV to GND........................................ –0.3V to 6.0V
PRES A/PRES B, DATA, RIN, SYNC, ASYNC,
LD, DIN, SCLK to GND..................–0.3V to (DVCC + 0.3V)
I/O A............................................. –0.3V to (VCCA + 0.3V)
I/O B............................................. –0.3V to (VCCB + 0.3V)
IVCCA/IVCCB.............................................................80mA
VCCA/VCCB Short-Circuit Duration...................... Indefinite
Operating Temperature Range (Note 4).... –40°C to 85°C
Junction Temperature............................................ 125°C
Storage Temperature Range.................... –65°C to 125°C
LD
SCLK
DIN
DOUT
DATA
RIN
ASYNC
SYNC
TOP VIEW
32 31 30 29 28 27 26 25
DVCC 1
24 FAULT
PRES A 2
23 UNDERV
C8A 3
22 NC/NO
C4A 4
21 PRES B
33
SGND
I/O A 5
20 I/O B
RST A 6
19 RST B
CLK A 7
18 CLK B
VCCA 8
17 VCCB
NC
CPO
C+
PVBATT
SVBATT
C–
PGND
SGND
9 10 11 12 13 14 15 16
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1955EUH#PBF
LTC1955EUH#TRPBF
1955
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
LTC1955IUH#PBF
LTC1955IUH#TRPBF
1955
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1955EUH
LTC1955EUH#TR
1955
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
LTC1955IUH
LTC1955IUH#TR
1955
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPVBATT = VSVBATT = 3.3V, DVCC = 3.3V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Power Supply
VBATT Operating Voltage
l
2.7
5.5
V
IPVBATT + ISVBATT Operating Current
VCCA = 5V, VCCB = 0V, ICCA = 0µA
VCCA = VCCB = 5V, ICCA = ICCB = 0µA
l
l
250
350
400
500
µA
µA
IPVBATT + ISVBATT Shutdown Current
No Cards Present. VCPO = 0V
l
0.75
1.75
µA
5.5
V
DVCC Operating Voltage
l
1.7
1955fd
2
For more information www.linear.com/LTC1955
LTC1955
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPVBATT = VSVBATT = 3.3V, DVCC = 3.3V, unless otherwise noted.
TYP
MAX
IDVCC Operating Current
PARAMETER
CONDITIONS
l
MIN
10
25
UNITS
µA
IDVCC Shutdown Current
l
0.5
1.5
µA
ROLCP 5V Mode Open-Loop Output Resistance
VBATT = 3.075V, ICPO = ICCA + ICCB = 120mA (Note 3) l
5.7
8.5
Ω
CPO Turn-On Time
ICCA/B = 0mA, 10% to 90%
l
0.6
1.5
ms
VCCA/B Output Voltage
5V Mode, 0 < ICCA/B < 60mA
3V Mode, 0 < ICCA/B < 50mA
1.8V Mode, 0 < ICCA/B < 30mA
l
l
l
5
3
1.8
5.35
3.25
1.95
V
V
V
VCCA/B Turn-On Time
ICCA/B = 0mA, 10% to 90%
l
0.8
1.5
ms
Undervoltage Detection
Relative to Nominal Output
l
–9
–5
–2.5
%
Overcurrent Detection
5V Mode
l
65
100
135
mA
VNC/NO = 0V
l
20
35
60
ms
PRES A, PRES B Pull-Up Current
VPRESA/B = 0
l
1.25
2.5
µA
Deactivation Time (
ICCA/B = 0mA, CVCCA/B = 1µF
l
20
250
µs
Low Level Output Voltage (VOL), (Note 2)
Sink Current = –200µA
l
0.2
V
High Level Output Voltage (VOH), (Note 2)
Source Current = 200µA
l
Rise/Fall Time (Note 2)
Loaded with 50pF, 10% to 90%
l
Charge Pump
Smart Card Supplies VCCA, VCCB
4.65
2.75
1.65
Smart Card Detection
Debounce Time (
PRES A/B to
D15/D7)
RST to VCC = 0.4V)
CLK A, CLK B
CLK A, CLK B Frequency (Note 2)
l
VCCA/B – 0.2
V
16
10
ns
MHz
RST A, RST B, C4A, C8A
Low Level Output Voltage (VOL), (Note 2)
Sink Current = –200µA
l
High Level Output Voltage (VOH), (Note 2)
Source Current = 200µA
l
0.2
Rise/Fall Time (Note 2)
Loaded with 50pF, 10% to 90%
l
100
ns
Low Level Output Voltage (VOL), (Note 2)
Sink Current = –1mA (VDATA = 0V)
l
0.3
V
High Level Output Voltage (VOH), (Note 2)
Source Current = 20µA (VDATA = VDVCC)
l
Rise/Fall Time (Note 2)
Loaded with 50pF, 10% to 90%
l
500
ns
Short-Circuit Current (Note 2)
VDATA = 0V
l
10
mA
Low Level Output Voltage (VOL)
Sink Current = –500µA (VI/OA/B = 0V)
l
0.3
V
High Level Output Voltage (VOH)
Source Current = 20µA (VI/OA/B = VCCA/B)
l
Rise/Fall Time
Loaded with 50pF, 10% to 90%
l
500
ns
Low Input Threshold (VIL)
l
0.15 • DVCC
V
High Input Threshold (VIH)
l
0.85 • DVCC
Input Current (IIH/IIL)
l
–1
VCCA/B – 0.2
V
V
I/O A, I/O B
0.85 • VCCA/B
V
5
DATA
0.8 • DVCC
V
RIN, DIN, SCLK, LD, SYNC, ASYNC, NC/NO
V
1
µA
1955fd
For more information www.linear.com/LTC1955
3
LTC1955
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VPVBATT = VSVBATT = 3.3V, DVCC = 3.3V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DOUT
Low Level Output Voltage (VOL)
Sink Current = –200µA
l
0.3
High Level Output Voltage (VOH)
Source Current = 200µA
l
DVCC – 0.3
l
1.17
V
V
UNDERV
Threshold
VUNDERV = 3.3V
l
Low Level Output Voltage (VOL)
Sink Current = –200µA
l
Leakage Current
VFAULT = 5.5V
l
Leakage Current
1.23
1.29
V
50
nA
0.3
V
1
µA
FAULT
SYMBOL
PARAMETER
CONDITIONS
0.005
MIN
TYP
MAX
UNITS
Serial Port Timing
tDS
DIN Valid to SCLK Setup
l
8
ns
tDH
DIN Valid to SCLK Hold
l
8
ns
tDD
DOUT Output Delay
l
15
tL
SCLK Low Time
l
50
ns
tH
SCLK High Time
l
50
ns
tCL
SCLK to LD
l
50
ns
tLC
LD to SCLK
l
0
ns
tLFC
LD Falling to SCLK
l
50
ns
CLOAD = 15pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This specification applies to all three smart card voltage classes:
1.8V, 3V and 5V.
Note 3: ROLCP @ (2VBATT – VCPO)/ICPO; VCPO will depend upon total load
(ICCA + ICCB) and minimum supply voltage VBATT. See Figure 5.
60
ns
Note 4: The LTC1955E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
ambient temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC1955I is guaranteed to
meet performance specifications over the full –40°C to 85°C temperature
range.
1955fd
4
For more information www.linear.com/LTC1955
LTC1955
Typical Performance Characteristics
6.0
400
VCCA = 1.8V, VCCB = 0V
300
200
100
0
2.7
3.1
3.5 3.9 4.3 4.7
SUPPLY VOLTAGE (V)
5.1
5.5
5.0
4.5
4.0
3.5
–40
5.5
–15
10
35
TEMPERATURE (°C)
60
1955 G01
60
VBATT = 3.3V
VCPO = 5.75V
DEBOUNCE TIME (ms)
LOAD CURRENT (mA)
160
140
VCCX = 3V
120
100
–15
10
35
TEMPERATURE (°C)
60
TA = 25°C
45
40
TA = –40°C
35
25
2.7
85
3.1
1955 G04
3.0
VBATT = 3.1V
TA = 25°C
3.5
3.9 4.3 4.7 5.1
VBATT SUPPLY VOLTAGE (V)
5.5
0.14
6
5
4
3
2
10
35
TEMPERATURE (°C)
VDATA = 0V
IOL = –1mA
VBATT = 2.7V
60
85
VCCX = 1.8V
VCCX = 3V
0.12
VCCX = 5V
0.10
0.08
0.06
–40
–15
1955 G05
10
35
TEMPERATURE (°C)
60
85
1955 G06
DVCC Shutdown Current
vs Supply Voltage
1.0
VDVCC = VBATT
2.5
8
7
–15
1955 G03
VBATT Shutdown Current
vs Supply Voltage
SUPPLY CURRENT (µA)
VBATT QUIESCENT CURRENT (mA)
9
5.0
0.16
TA = 85°C
50
VBATT Quiescent Current
[IBATT – 2 (ICCA + ICCB)]
vs Load Current
10
5.5
Bidirectional Channel (I/O A, I/O B)
Low Output Level vs Temperature
30
VCCX = 5V
80
–40
6.0
4.5
–40
Card Detection Debounce Time
vs VBATT Supply Voltage
55
VCCX = 1.8V
VIN = 2.7V
VCPO = 4.9V
1955 G02
VCCX Overcurrent Shutdown
Threshold vs Temperature
180
Charge Pump Open-Loop Output
Resistance vs Temperature
(2VIN – VCPO) / ILOAD(MAX)
6.5
85
I/O A, I/O B LOW OUTPUT VOLTAGE (V)
VCCA = VCCB = 5V
7.0
DVCC = VBATT = 5.5V
VCCX = 5V
OUTPUT RESISTANCE (Ω)
TA = 25°C
ICCA = ICCB = 0µA
VDVCC = VBATT
0.8
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
500
No Load Supply Current vs VBATT
SHORT-CIRCUIT CURRENT (mA)
600
I/O X Short-Circuit Current
vs Temperature
TA = –40°C
2.0
TA = 25°C
1.5
1.0
TA = 85°C
TA = –40°C
0.6
0.4
TA = 25°C, 85°C
0.2
0.5
1
0
10µ
100µ
1m
10m
LOAD CURRENT (A)
100m
1955 G07
0
2.7
3.1
3.5
3.9 4.3 4.7 5.1
VBATT SUPPLY VOLTAGE (V)
5.5
1955 G08
For more information www.linear.com/LTC1955
0
2.7
3.1
3.5 3.9 4.3 4.7 5.1
VDVCC SUPPLY VOLTAGE (V)
5.5
1955 G09
1955fd
5
LTC1955
Typical Performance Characteristics
Charge Pump and LDO Activation
Deactivation Sequence
Data – I/O Channel, CL = 50pF
RST A
5V/DIV
VCPO
5V/DIV
I/O A
2V/DIV
CLK A
5V/DIV
VCCA
5V/DIV
I/O A
5V/DIV
I/O A
5V/DIV
DATA
2V/DIV
VCCA
5V/DIV
1ms/DIV
1955 G10
10µs/DIV
1955 G11
100ns/DIV
1955 G12
Pin Functions
SVBATT: Power. Supply voltage for analog sections of the
LTC1955.
and C8A synchronous card pins can be selected to connect
to the DATA pin via the serial port (see Table 4).
PVBATT: Power. Supply voltage for the charge pump.
RIN: Input. The RIN pin supplies the RST signal to both
smart cards. It is level shifted and transmitted directly
to the RST pin of a selected card socket. When a card is
deselected, the RST A/RST B pin for that channel is latched
at its current state.
DVCC: Power. Reference voltage for the control logic.
SGND: Ground. Signal ground for analog sections of the
LTC1955. The Exposed Pad must be soldered to PCB
ground.
PGND: Ground. Power ground for the charge pump. This
pin should be connected directly to a low impedance
ground plane.
CPO: Charge Pump. CPO is the output of the charge pump.
When one or both of the smart cards requires power, the
charge pump will charge CPO to either 3.7V or 5.35V
depending on what smart card voltages are required. A
low impedance 4.7µF X5R or X7R ceramic capacitor is
required on CPO.
C +, C –: Charge Pump. Charge pump flying capacitor pins.
A 1µF X5R or X7R ceramic capacitor should be connected
from C+ to C –.
DATA: Input/Output. Microcontroller side data I/O pin. The
DATA pin provides the bidirectional communication path
to both smart cards. One, both or neither of the cards may
be selected to communicate via the DATA pin. If several
LTC1955s are connected in parallel, the DATA pin can be
made high impedance by selecting neither card. The C4A
6
SYNC: Input. The SYNC pin provides the clock input for
synchronous smart cards. When a synchronous card
is selected, its CLK pin follows SYNC directly. When a
synchronous card is deselected, the CLK A/CLK B pin for
that channel is latched at its current state.
ASYNC: Input. The ASYNC pin provides the clock input
for asynchronous cards and should be connected to a free
running clock. The clock signal to the smart card can be
a ÷1, ÷2, ÷4 or ÷8 version of the signal on ASYNC. Asynchronous cards can also be placed in clock stop mode
with the clock stopped either high or low.
DIN: Input. Input for the serial port. Command data is
shifted into DIN synchronously with SCLK. DIN can be
connected directly to a microcontroller or the DOUT pin of
another LTC1955 for daisychained operation.
DOUT: Output. Output for the serial port. Smart card status
data is shifted out of DOUT synchronously with SCLK. DOUT
can be connected directly to a microcontroller or the DIN
pin of another LTC1955 for daisychained operation.
For more information www.linear.com/LTC1955
1955fd
LTC1955
Pin Functions
SCLK: Input. The SCLK pin clocks the serial port. Each
new data bit is received on the rising edge of SCLK. SCLK
should be left high during idle times and should not be
clocked when LD is low.
LD: Input. The falling edge of this pin loads the current
state of the shift register into the command register.
Command changes to both smart card channels will be
updated on the falling edge of LD. The rising edge of LD
latches status information from the smart card channels
into the shift register for the next read/write cycle.
NC/NO: Input. This pin controls the activation level of the
PRES A/PRES B pins. When it is high (DVCC), the PRES
pins are active high. When it is low (GND), the PRES pins
are active low. When a ground side N.O. switch is used,
the NC/NO pin should be grounded. When a ground side
N.C. switch is used, the NC/NO pin should be connected
to DVCC.
Note: If an N.C. switch is used, a small current (several
microamperes) will flow through the switch whenever a
smart card is not present. For ultralow power consumption
in shutdown, an N.O. switch is optimum.
PRES A/PRES B: Card Socket. The PRES A/PRES B pins
are used to detect the presence of the smart cards. They
can be connected to either normally open or normally
closed detection switches on the smart card acceptor’s
sockets. The NC/NO pin should be set appropriately. These
pins have a pull-up current source on-chip so no external
components are required.
C4A/C8A: Card Socket. These pins connect to the C4
and C8 pins of synchronous memory cards on smart
card socket A. The signal for these pins is unidirectional
and can only be sent to the card. Data for C4A and C8A
is transmitted via the DATA pin and may be selected
in place of I/OA via the serial port (see Table 4). When
either C4A or C8A is selected, it will follow the DATA
pin. When it is deselected, it will remain latched at its
current state.
I/O A/I/O B: Card Socket. The I/O A/I/O B pins connect to
the I/O pins of the respective smart card sockets. When
a smart card is selected, its I/O pin connects to the DATA
pin. When a smart card is deselected, its I/O A/I/O B pin
returns to the idle state (H).
RST A/RST B: Card Socket. These pins should be connected
to the RST pins of the respective smart card sockets. The
RST A/RST B signals are derived from the RIN pin. When
a card is selected, its RST pin follows RIN. When a card
is deselected, the RST A/RST B pin for that channel holds
the current value on RIN.
CLK A/CLK B: Card Socket. The CLK A/CLK B pins should
be connected to the CLK pins of the respective smart card
sockets. The CLK A/CLK B signals can be derived from
either the SYNC input or the ASYNC input depending on
which type of card is being accessed. The card type is
selected via the serial port (see Tables 1 and 3).
VCCA, VCCB: Card Socket. The VCCA/VCCB pins should be
connected to the VCC pins of the respective smart card
sockets. The activation of a VCCA/VCCB pin is controlled by
the serial port (see Tables 1 and 2) and can be set to 0V,
1.8V, 3V or 5V. The voltage levels of the two card sockets
are controlled independently for maximum flexibility.
FAULT: Output. The FAULT pin can be used as an interrupt
to a microcontroller to indicate when a fault has occurred.
It is an open-drain output, which is logically equivalent to
D4 + D5 + D12 + D13. (See Table 1)
UNDERV: Input. The UNDERV pin provides security by
supplying a precision undervoltage threshold for external supply monitoring. An external resistive voltage
divider programs the desired undervoltage threshold.
Once UNDERV falls below 1.23V, the LTC1955 automatically begins the deactivation sequence on any channel
that is active.
If external supply monitoring is not required, the UNDERV
pin should be connected to either SVBATT or DVCC.
1955fd
For more information www.linear.com/LTC1955
7
LTC1955
Block Diagram
CHARGE PUMP
C+
C–
PGND
14
11
10
SVBATT PVBATT
12
13
CPO
15
CHARGE
PUMP
VCCB 17
LDO B
8 VCCA
LDO A
I/O B 20
SMART
CARD
SOCKET B
5 I/O A
CLOCK
CONTROL
LOGIC
CLK B 18
RST B 19
PRES B 21
τ
4 C4A
7 CLK A
6 RST A
DATA 29
SMART
CARD
COMMUNICATIONS
SMART
CARD
SOCKET A
3 C8A
RESET
CONTROL
LOGIC
ASYNC 31
τ
2 PRES A
SYNC 32
22 NC/NO
RIN 30
24
FAULT
STATUS DATA
9 SGND
DIN 27
SERIAL PORT
COMMAND/STATUS
DATA
DOUT 28
SCLK 26
DIGITAL
SUPPLY
1 DVCC
SHIFT REGISTER
LD 25
–
23 UNDERV
COMMAND LATCH
+
1.23V
+
–
1955 BD
1955fd
8
For more information www.linear.com/LTC1955
LTC1955
Operation
Serial Port
• Operating mode of asynchronous cards (clock stop
high, low, ÷1, ÷2, ÷4 or ÷8)
The microcontroller compatible serial port provides all
of the command and control inputs for the LTC1955, as
well as the status of the two smart cards. Data on the DIN
input is loaded on the rising edge of SCLK. D15 is loaded
first and D0 last. At the same time, the command bits are
being shifted into the DIN input, the status bits are being
shifted out of the DOUT output. The status bits are presented
to DOUT on the rising edge of SCLK. Once all bits have
been clocked into the shift register, the command data is
loaded into the command latch by bringing LD low. At this
time, the command latch is updated and the LTC1955 will
begin to act on the new command set. The status data
is latched into the shift register on the rising edge of LD.
SCLK should be low when LD is brought low and should
be high when LD is brought high. This requires a 9th clock
cycle per transaction. Figure 1 shows the recommended
operation of the serial port.
• Selection of the I/O, C4 or C8 pins for card socket A
The serial port provides the following status data:
• It indicates the presence or absence of the smart
cards.
• It indicates the readiness of the smart card VCC supplies.
Communication with a smart card is disabled until its
power supply voltage has reached the final value.
• It indicates fault status. In the event of an electrical or
ATR fault, the fault is reported. For electrical faults, the
LTC1955 will automatically deactivate the smart card.
Table 1 illustrates the command inputs and status outputs
associated with each bit of the serial data word.
Three voltage options are available from the LTC1955: 5V,
3V and 1.8V. Bits D0, D1 (card B) and D8, D9 (card A)
determine which voltage is selected. Setting both control
bits of a channel to 0 deactivates that channel and sets
the smart card supply voltage to 0V. If both channels are
deactivated, the LTC1955 is in shutdown. Table 2 shows
the operation of the supply control bits.
Multiple LTC1955s may be daisychained together by
connecting the DOUT pin of one LTC1955 to the DIN pin of
another. Figure 6 shows an example of multiple LTC1955s
daisychained together.
The maximum clock rate for the serial port is 10MHz.
The CLK A/CLK B pins to the smart cards can be programmed for various modes. Both synchronous and asynchronous cards are supported. There are several options
available with asynchronous cards. Table 3 shows how
all clock options are obtained using bits D5–D7 (card B)
and D13–D15 (card A). The default state of the LTC1955
on power up is synchronous mode.
The serial port controls the following parameters of each
smart card socket:
• Selection/deselection of a smart card
• VCC voltage level of each card (5V/3V/1.8V/0V)
• Clock mode of each card (synchronous or asynchronous)
READ/WRITE CYCLE
tLC
tDS
tDH
tH
tDD
tL
tCL
tLFC
tCL
SCLK
DIN
X
D15
D14
D2
D1
D0
X
LD
DOUT
D15
D14
D5
D1
D0
D15 FROM
INPUT
D15
1955 F01
Figure 1. Serial Port Timing Diagram
1955fd
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9
LTC1955
Operation
Table 1. Serial Port Comand
CARD B
CARD A
STATUS OUTPUT
BIT
COMMAND INPUT
0
D0
0
D1
VCCB Options
(See Table 2)
0
D2
Card B Select/Deselect
0
D3
Data Pull-Up Defeat
Card B Electrical Fault
D4
Reserved (Always Set to “0”)
Card B ATR Fault
D5
Card B Clock Options
(See Table 3)
Card B VCC Ready
D6
Card B Present
D7
0
D8
VCCA Options
(See Table 2)
0
D9
0
D10 Card A Select/Deselect
0
D11 Card A Communications
D12 Options (See Table 4)
Card A Electrical Fault
Card A ATR Fault
Card A VCC Ready
D13 Card A Clock Options
D14 (See Table 3)
Card A Present
D15
Table 2. VCC and Shutdown Options
D9
D1
0
0
1
1
D8
D0
0
1
0
1
STATUS (CARD A)
STATUS (CARD B)
VCC = 0V (Shutdown)
VCC = 1.8V
VCC = 3V
VCC = 5V
Table 3. Clock Options
D7
D15
0
0
0
0
1
1
1
1
D6
D14
0
0
1
1
0
0
1
1
D5
D13
0
1
0
1
0
1
0
1
CLOCK MODE (CARD B)
CLOCK MODE (CARD A)
Synchronous Mode
Unused
Asynchronous Stop Low
Asynchronous Stop High
Asynchronous ÷1
Asynchronous ÷2
Asynchronous ÷4
Asynchronous ÷8
To receive status data from the serial port, a read/write operation must be performed. When polling for the presence
of a smart card on both channels, the input word should
be set to $0000 since this is the shutdown command for
the LTC1955. However, consider the example where some
operation is already being performed on channel A. If, for
example, the previous command was $BE00 (VCCA set to
3V, card selected, I/O A connected to DATA and CLK A set
to ASYNC÷2), then the commands for this channel must
be rewritten to the serial port each time. To poll for the
presence of a card on channel B, or even the VCCA ready
status, then $BE00 should be rewritten on each new read/
write cycle. Once a card is detected on channel B, the
commands for channel B can be changed but the $BExx
should continue to be rewritten for channel A.
Bidirectional Channels
The bidirectional channels are level shifted to the appropriate VCCA/B voltages at the I/O A/I/O B pins.
An NMOS pass transistor performs the level shifting. The
gate of the NMOS transistor is biased such that the transistor is completely off when both sides have relinquished
the channel. If one side of the channel asserts an L, then
the transistor will convey the L to the other side. Note that
current passes from the receiving side of the channel to the
transmitting side. The low output voltage of the receiving
side will be dependent upon the voltage at the transmitting
side plus the I • R drop of the pass transistor.
When a card socket is selected, it becomes a candidate
to drive data on the DATA pin, and likewise, receive data
from the DATA pin. When a card socket is deselected, the
voltage on its I/O A/I/O B pin will return to the idle state
(H), and the DATA side of that channel will become high
impedance. If both cards are deselected, the DATA pin
will be high impedance.
Both cards may be deselected at the same time to allow
communication with a second LTC1955.
Card channel A includes provision for unidirectional
communication with the C4 and C8 pins of the smart
card. The C4, C8 and I/O pins of card A are individually
multiplexed to the DATA pin using bits D11 and D12, as
shown in Table 4.
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LTC1955
Operation
Table 4. Card A Communications Options
D12
0
0
1
1
D11
0
1
0
1
CARD A COMMUNICATION MODE
Nothing Selected
C4A Connected to DATA Pin
C8A Connected to DATA Pin
I/O A Connected to DATA Pin
Note that if a reset is initiated with both cards selected,
then both may give an answer to reset and collide on the
DATA line. No damage will occur but data could be lost
or corrupted.
Dynamic Pull-Up Current Sources
The current sources on the bidirectional pins (DATA, I/O
A/I/O B) are dynamically activated to achieve a fast rise time
with a relatively small static current.* Once a bidirectional
pin is relinquished, a small start-up current begins to
charge the node. An edge rate detector determines if the
pin is released by comparing its slew rate with an internal
reference value. If a valid transition is detected, a large
pull-up current enhances the edge rate on the node. The
higher slew rate corroborates the decision to charge the
node thereby affecting a dynamic form of hysteresis.
LOCAL
SUPPLY
+
ISTART
BIDIRECTIONAL
PIN
VREF
–
dv
dt
1955 F02
Figure 2. Dynamic Pull-Up Current Sources
Clock Channels
As described in the section Serial Port, the LTC1955 supports both synchronous and asynchronous smart cards.
On start-up, or when bits D13-D15 for card A and bits
D5-D7 for card B are set to 0s, the clock channel is in
synchronous mode. The remaining modes are used for
asynchronous cards.
In synchronous mode, the CLK A/CLK B pins follow the
SYNC pin for a channel that is selected. If a channel is
deselected (via the serial port), the CLK A/CLK B line for
that channel is latched at its current value.
In asynchronous mode, the CLK A/CLK B pins follow either
the ASYNC pin (÷1 mode) or a divided version of this pin.
The CLK A/CLK B pins can also be stopped high or low.
The available divider ratios include ÷2, ÷4 and ÷8. When
switching between divider ratios, the internal selection
circuitry ensures that no spikes or glitches appear on the
CLK A/CLK B pins. Consequently, it may take up to 8 clock
pulses for the clock frequency change command to take
affect. Synchronization circuitry ensures that no glitches
occur when entering or exiting one of the stop modes.
For example, when entering stop low mode, the selection
circuitry waits for the next falling edge of the respective
CLK A/CLK B signal to make the change. Likewise, if stop
high is selected, it will occur on the next rising edge.
Deselection of an asynchronous card does not affect its
CLK A/CLK B pin. Its clock can be started, stopped or its
divider ratio changed at any time.
To clean up the duty cycle of the incoming clock in asynchronous applications, any of the clock divider modes ÷2,
÷4 or ÷8 will yield a very nearly 50% duty cycle.
Additional synchronization circuitry prevents glitches from
occurring when switching between synchronous mode and
asynchronous mode. Because of this circuitry, two edges
(a falling edge followed by a rising edge) are necessary
at the CLK pin to switch modes from asynchronous to
synchronous. For example, if clock stop mode is engaged,
the clock channel will not change modes until clock stop
mode is disengaged.
Any combination of cards, synchronous or asynchronous,
can be used as both channels can be set to any of the
clock modes or divider ratios independently.
Both SYNC and ASYNC inputs are independently level
shifted to the appropriate voltage for the CLK A/CLK B
pins (5V, 3V, 1.8V).
Reset Channels
When a card is selected, the reset channels provide a level
shifted path from the RIN pin to the RST A/RST B pins.
When a card is deselected, its RST A/RST B pin is latched
at the current value of RIN.
* U.S. Patent No. 6,356,140
For more information www.linear.com/LTC1955
1955fd
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LTC1955
Operation
Smart Card Detection Circuits
Automatic Deactivation
The PRES A/PRES B pins are used to detect the presence
of a smart card. An automatic debounce circuit waits until
a smart card has been present for a continuous period
of typically 35ms. Once a valid card indication exists,
the status bit for that channel is updated and may be
polled by cycling data through the serial port. The DOUT
pin (equivalent to D15) of the serial port can be used to
indicate the presence of a card on channel A in real time
if LD is held low.
The built-in deactivation sequence can be executed via the
serial port simply by setting the appropriate control bits
(D0 and D1 or D8 and D9) to 0. The deactivation sequence
is outlined below.
The PRES A/PRES B pins have built-in pull-up current
sources, so no external components are required for
switch detection. The pull-up current sources are designed
to have a small current when the pin voltage is below approximately 1V, but somewhat higher current when the
pin voltage reaches 1V. This helps maintain low power
dissipation when a card is present and yet fast response
time to a card removal.
If the smart card was set to asynchronous mode, then
the CLK A/CLK B pin will be latched low on its next
falling edge. If no falling edges occur within 5µs (min),
then the CLK A/CLK B line is forced low.
The PRES A/PRES B pins can be configured to respond
to either normally open or normally closed switches via
the NC/NO pin.
1. The RST A/RST B pin for that channel is immediately
brought low.
2. The deactivation of the CLK A/CLK B pins depends upon
which type of card is used:
If the smart card was set to synchronous mode, then the
CLK A/CLK B pin is immediately latched at its current
value (either high or low) and then forced low after a
duration of 5µs (min). During the 5µs timeout period,
changes on SYNC will be ignored.
3. The I/O A/I/O B, C4A and C8A pins for that channel are
brought low.
Activation/Deactivation
4. The VCCA/VCCB pin is brought low.
For maximum flexibility, the activation sequencing of the
smart card is left to the application programmer. Upon
activation, to comply with relevant smart card standards,
none of the smart card signal pins will be allowed to go
high before the smart card supply voltage (VCCA/VCCB) has
reached its final value. Deactivation can be achieved either
manually or automatically. An electrical fault condition will
trigger the automatic deactivation.
If an error occurs on one smart card, operation of the
other card is unaffected.
Manual deactivation may be performed under software
control by setting the smart card pins to 0V in the desired
sequence via the control pins (SYNC, ASYNC, RIN, DATA
and the serial port). For most applications, this will be
cumbersome and the built-in deactivation will be used
instead.
Electrical Fault Detection
Several types of faults are detected by the LTC1955. They
include VCCA/VCCB undervoltage, VCCA/VCCB overcurrent,
CLK A/CLK B, RST A/RST B, C8A, C4A short-circuit, card
removal during a transaction, failed answer to reset (ATR),
supply undervoltage or UNDERV and chip overtemperature.
To prevent false errors from plaguing the microcontroller,
the electrical faults are acted upon only after a 5µs (min)
timeout period. Card removal during transaction faults
initiate the deactivation sequence immediately.
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LTC1955
Operation
VCCA/VCCB undervoltage faults are determined by comparing the actual output voltage with the internal reference
voltage. If the output is more than ~5% below its set point
for the entire timeout period, the fault is reported and the
deactivation sequence is initiated.
VCCA/VCCB overcurrent faults are detected by comparing
the output current of the LDOs with an internal reference
level. If the current of an LDO is more than 100mA (typ)
for the entire timeout period, the fault is reported and the
deactivation sequence is initiated.
CLK A/CLK B and RST A/RST B faults are detected by
comparing the outputs of these pins with their expected
signals. If the signal on a pin is incorrect for the entire
timeout period, the fault is reported and the deactivation
sequence is initiated.
The clock channels are a special case. Since they can have
a free running clock, the error indication is accumulated
over a longer period of time without being cleared. Even
though the clock may be running, an error will still be
detected.
An overtemperature fault is detected by sensing the junction
temperature of the IC. If the junction temperature exceeds
approximately 150°C for the entire timeout period, the
fault is reported by setting both fault bits (D4 and D12)
and the deactivation sequence is initiated.
A card removal fault is determined as soon as the PRES A/
PRES B pin is high (for NC/NO = 0). Once this occurs,
the fault is reported and the deactivation sequence is
initiated.
If no card is present, and the application software attempts
to power-up a card socket, an automatic fault will result
on that channel.
Short-circuits on the I/O A/I/O B lines will not be detected
by the fault detection hardware; however, a short-circuit
from these lines to their respective VCCA/VCCB pins will
be compliant with the maximum current limits set by applicable standards (
