LTC1983ES6-5#TRMPBF

LTC1983-3/LTC1983-5 100mA Regulated Charge-Pump Inverters in ThinSOT Description Features Fixed Output Voltages: –3V, –5V or Low Noise VIN to –VIN Inverted Output n ±4% Output Voltage Accuracy n Low Quiescent Current: 25µA n 100mA Output Current Capability n 2.3V to 5.5V Operating Voltage Range n Internal 900kHz Oscillator n “Zero Current” Shutdown n Short-Circuit and Over-Temperature Protected n Low Profile (1mm) ThinSOTTM Package n Applications n n n n –3V Generation in Single-Supply Systems Portable Equipment LCD Bias Supplies GaAs FET Bias Supplies The LTC®1983-3 and LTC1983-5 are inverting charge pump DC/DC converters that produce negative regulated outputs. The parts require only three tiny external capacitors and can provide up to 100mA of output current. The devices can operate in open loop mode (creating a –VIN supply) or regulated output mode depending on the input supply voltage and the output current. The LTC1983-3/LTC1983-5 have many useful features for portable applications including very low quiescent current (25µA typical) and a zero current shutdown mode programmed through the SHDN pin. The LTC1983-3/LTC1983-5 are over-temperature and short-circuit protected. The parts are available in a 6-pin low profile (1mm) ThinSOT package. L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application –3V at 100mA DC/DC Converter OFF ON VIN VOUT LTC1983-3 SHDN C+ VOUT = –3V IOUT = UP TO 100mA –3.3 COUT 10µF –3.2 GND –3.1 VOUT (V) VIN 3V TO 5.5V CIN 10µF VOUT vs IOUT C– VIN = 5V –3.0 1983-3 TA01 CFLY 1µF CFLY: TAIYO YUDEN LMK212BJ105 CIN, COUT: TAIYO YUDEN JMK316BJ106ML –2.9 VIN = 3.3V –2.8 –2.7 0 20 40 60 IOUT (mA) 80 100 1983 TA02 1983fc For more information www.linear.com/LTC1983-3 1 LTC1983-3/LTC1983-5 Absolute Maximum Ratings Pin Configuration (Note 1) VIN to GND.................................................... –0.3V to 6V SHDN Voltage............................................... –0.3V to 6V VOUT to GND (LTC1983-3).................... 0.2V to VOUT Max VOUT to GND (LTC1983-5)................... 0.2V to VOUT Max IOUT Max...............................................................125mA Output Short-Circuit Duration........................... Indefinite Operating Temperature Range (Note 2)....–40°C to 85°C Storage Temperature Range................... – 65°C to 125°C Lead Temperature (Soldering, 10 sec).................... 300°C Order Information TOP VIEW VCC 1 6 SHDN VOUT 2 5 GND C+ 3 4 C– S6 PACKAGE 6-LEAD PLASTIC SOT-23 TJMAX = 125°C, θJA = 256°C/W http://www.linear.com/product/LTC1983-3#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1983ES6-3#PBF LTC1983ES6-3#TRPBF LTPC 6-Lead Plastic TSOT-23 –40°C to 85°C LTC1983ES6-5#PBF LTC1983ES6-5#TRPBF LTYB 6-Lead Plastic TSOT-23 –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, CFLY = 1µF, COUT = 10µF unless otherwise noted. PARAMETER CONDITIONS VIN Operating Voltage (Regulated Output Mode) (LTC1983-3) (LTC1983-5) MIN l VIN Minimum Startup Voltage TYP 3.0 5.0 MAX 5.5 5.5 2.3 UNITS V V V VOUT (LTC1983-3) VIN ≥ 3.3V, IOUT ≤ 25mA VIN ≥ 5V, IOUT ≤ 100mA l l –2.88 –2.88 –3 –3 –3.12 –3.12 V V VOUT (LTC1983-5) VIN ≥ 5V, VIN –5V ≥ IOUT • ROUT l –4.8 –5 –5.2 V l 25 60 VIN Operating Current VIN ≤ 5.5V, IOUT = 0µA, SHDN = VIN VIN Operating Current (Open-Loop Mode) (LTC1983-5) VIN = 3.3V VIN = 4.75V VIN Shutdown Current SHDN = 0V, VIN ≤ 5.5V Output Ripple 3.3 ≤ VIN ≤ 5.5 60 mVP-P Open-Loop Output Impedance (LTC1983-3): ROUT VIN = 3.3V, VOUT = –3V 11 Ω 2 2.5 4 l 0.1 µA mA mA 1 µA 1983fc For more information www.linear.com/LTC1983-3 LTC1983-3/LTC1983-5 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, CFLY = 1µF, COUT = 10µF unless otherwise noted. PARAMETER CONDITIONS MIN Open-Loop Output Impedance (LTC1983-5): ROUT VIN = 3.3V, IOUT ≈ 50mA VIN = 5V, IOUT ≈ 60mA Oscillator Frequency (Non Burst Mode® Operation) SHDN Input High l SHDN Input Low l VSHDN = 5.5V SHDN Input Current TYP MAX UNITS 11 8.5 Ω Ω 900 kHz 1.1 V 0.3 V 4 µA 2.2 l Note 2: The LTC1983E-3/LTC1983E-5 are guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Typical Performance Characteristics 70 60 11.0 50 40 10.5 10.0 30 9.5 20 9.0 10 8.5 0 TA = 25°C 0 20 ROUT –2.1 0 20 50 –3VOUT vs IOUT Over Temperature 3.3 100 80°C –2.9 IOUT (mA) 1983 GO4 –3.5 VIN = 5V 3.2 –40°C 0°C 3.0 40°C 2.9 –40°C, 0°C, 40°C 80°C 2.8 –3.3 10 –3VOUT vs IOUT Over Temperature (VIN = 5V) 3.1 –2.7 –3.1 25 100 80 60 40 IOUT (mA) 1983 G03 –2.5 VIN = 5V VOUT (V) EFFICIENCY (%) 5.35 4.35 –2.3 VIN = 3.3V 1 VIN = 3.3V 5 3.35 120°C 0.1 15 1983 TA02 75 0 0.01 20 VIN (V) Efficiency vs I­OUT VOUT = –3V TA = 25°C VIN = 2.3V VIN = 5V 1983 G01 100 TA = 25°C 10 8.0 2.35 100 80 60 40 IOUT (mA) Output Impedance vs IOUT (LTC1983-5) 25 11.5 VIN = 3.3V VIN = 2.3V ROUT (Ω) EFFICIENCY (%) 12.0 VIN = 5V 30 IOUT = 25mA TA = 25°C ROUT (Ω) 80 12.5 VOUT (–V) 90 Output Impedance vs Input Voltage Efficiency vs IOUT (LTC1983-5) 0 20 80 60 100 40 OUTPUT CURRENT (mA) 120 1983 G05 2.7 0 20 100 40 60 80 OUTPUT CURRENT (mA) 120 1983 G06 1983fc For more information www.linear.com/LTC1983-3 3 LTC1983-3/LTC1983-5 Typical Performance Characteristics Open-Loop Current vs Temperature (LTC1983-5) 4.5 VIN = 5V 4.7 50 TA = 25°C 40 3.5 IIN (mA) 4.3 4.1 35 3.0 20 2.0 3.7 3.5 –40 60 10 TEMPERATURE (°C) 1.5 110 15 2.3 3.3 2.8 3.3 VIN (V) 16 INPUT CURRENT (µA) ROUT vs Temperature (IOUT = 10mA) 29.5 ROUT (Ω) 1.0 0.9 0.8 VIN = 3V 12 10 VIN = 5V 8 0.7 0.6 0.5 0.4 28.0 6 27.5 4 0.2 27.0 2 0.1 26.5 0 –50 3.6 4.6 4.1 VIN (V) 5.1 5.5 0 50 150 100 TEMPERATURE (°C) 3.5 140 3.0 120 2.5 100 2.0 80 ROUT (Ω) ISHDN (µA) SHDN Pin Input Current vs Temperature 40 0.5 20 0 50 100 TEMPERATURE (°C) 0 50 100 TEMPERATURE (°C) 150 150 1983 G12 ROUT vs CFLY (VIN = 5V) VIN = 5V TA = 25°C 0 0.01 0.1 1 CFLY (µF) 1983 G13 4 0 –50 60 1.0 0 –50 0.3 1983 G11 1983 G10 1.5 110 SHDN Pin Threshold Voltage vs Temperature IOUT = 10mA 14 30.0 3.1 60 1983 G08 VTHRESHOLD (V) 18 TA = 25°C 28.5 10 TEMPERATURE (°C) 1983 G09 Burst Mode Input Current vs VIN (LTC1983-3) 29.0 10 –40 4.8 4.3 1983 G07 30.5 30 25 2.5 3.9 31.0 VIN = 5V 45 4.0 4.5 IIN (mA) Burst Mode Current vs Temperature (LTC1983-3) IIN (µA) 4.9 Open-Loop Input Current vs VIN (LTC1983-5) 1983 G14 1983fc For more information www.linear.com/LTC1983-3 LTC1983-3/LTC1983-5 Typical Performance Characteristics VOUT Start-Up into 100mA Resistive Load VOUT Ripple at 100mA Load VOUT 1V VOUT 20mV VIN 5V 50µs/DIV 1µs/DIV 1983 G15 1983 G16 VOUT Load Step Response from IOUT = 0 to IOUT = 100mA VOUT Ripple at 30mA Load VOUT 20mV VOUT 20mV IOUT 100mA 2.5µs/DIV 1983 G17 100µs/DIV 1983 G18 1983fc For more information www.linear.com/LTC1983-3 5 LTC1983-3/LTC1983-5 Pin Functions VIN (Pin 1): Charge Pump Input Voltage. May be between 2.3V and 5.5V. VIN should be bypassed with a ≥4.7µF low ESR capacitor as close as possible to the pin for best performance. VOUT (Pin 2): Regulated Output Voltage for the IC. VOUT should be bypassed with a ≥4.7µF low ESR capacitor as close as possible to the pin for best performance. C+ (Pin 3): Charge Pump Flying Capacitor Positive Terminal. This node is switched between VIN and GND (It is connected to VCC during shutdown). C– (Pin 4): Charge Pump Flying Capacitor Negative Terminal. This node is switched between GND and VOUT (It is connected to GND during shutdown). GND (Pin 5): Signal and Power Ground for the 6-Pin SOT‑23 package. This pin should be tied to a ground plane for best performance. SHDN (Pin 6): Shutdown. Grounding this pin shuts down the IC. Tie to VIN to enable. This pin should not be pulled above the VIN voltage or below GND. Block Diagram LTC1983-X VIN CFLY 1µF CIN 10µF S1A S2A C– S1B VOUT S2B CLOCK1 SHDN CONTROL LOGIC VREF + C+ CLOCK2 – CHARGE PUMP COUT 10µF COMP1 1µA 1983 BD 6 1983fc For more information www.linear.com/LTC1983-3 LTC1983-3/LTC1983-5 Operation (Refer to Block Diagram) The LTC1983-3/LTC1983-5 use a switched capacitor charge pump to invert a positive input voltage to a regulated –3V ±4% (LTC1983-3) or ­–5 ±4% (LTC1983-5) output voltage. Regulation is achieved by sensing the output voltage through an internal resistor divider and enabling the charge pump when the output voltage droops above the upper trip point of COMP1. When the charge pump is enabled, a 2-phase, nonoverlapping clock controls the charge pump switches. Clock 1 closes the S1 switches which enables the flying capacitor to charge up to the VIN voltage. Clock 2 closes the S2 switches that invert the VIN voltage and connect the bottom plate of CFLY to the output capacitor at VOUT. This sequence of charging and discharging continues at a free-running frequency of 900kHz (typ) until the output voltage has been pumped down to the lower trip point of COMP1 and the charge pump is disabled. When the charge pump is disabled, the LTC1983 draws only 25µA (typ) from VIN which provides high efficiency at low load conditions. In shutdown mode, all circuitry is turned off and the part draws less than 1µA from the VIN supply. VOUT is also disconnected from VIN and CFLY. The SHDN pin has a threshold of approximately 0.7V. The part enters shutdown when a low is applied to the SHDN pin. The SHDN pin should not be floated; it must be driven with a logic high or low. Open-Loop Operation The LTC1983-3/LTC1983-5 inverting charge pumps regulate at –3V/–5V respectively, unless the input voltage is too low or the output current is too high. The equations for output voltage regulation are as follows: VIN –5.06V > IOUT • ROUT (LTC1983-5) VIN –3.06V > IOUT • ROUT (LTC1983-3) If this condition is not met, then the part will run in open loop mode and act as a low output impedance inverter for which the output voltage will be: VOUT = –[VIN –(IOUT • ROUT)] For all ROUT values, check the corresponding curves in the Typical Performance Characteristics section (Note: CFLY = 1µF for all ROUT curves). The ROUT value will be different for different flying caps, as shown in the following equation: ⎛ ⎞ 1 ROUT = ROUT (curve) – 1.11Ω + ⎜ ⎝ fOSC • CFLY ⎟⎠ Short-Circuit/Thermal Protection During short-circuit conditions, the LTC1983 will draw several hundred milliamps from VIN causing a rise in the junction temperature. On-chip thermal shutdown circuitry disables the charge pump once the junction temperature exceeds ≈155°C, and re-enables the charge pump once the junction temperature falls back to ≈145°C. The LTC1983 will cycle in and out of thermal shutdown indefinitely without latchup or damage until the VOUT short is removed. Capacitor Selection For best performance, it is recommended that low ESR capacitors be used for both CIN and COUT to reduce noise and ripple. The CIN and COUT capacitors should be either ceramic or tantalum and should be 4.7µF or greater. Aluminum electrolytic are not recommended because of their high equivalent series resistance (ESR). If the source impedance is very low, CIN may not be needed. Increasing the size of COUT to 10µF or greater will reduce output voltage ripple. The flying capacitor and COUT should also have low equivalent series inductance (ESL). The board layout is critical as well for inductance for the same reason (the suggested board layout should be used). A ceramic capacitor is recommended for the flying capacitor with a value in the range of 0.1µF to 4.7µF. Note that a large value flying cap (>1µF) will increase output ripple unless COUT is also increased. For very low load applications, C1 may be reduced to 0.01µF to 0.047µF. This will reduce output ripple at the expense of efficiency and maximum output current. 1983fc For more information www.linear.com/LTC1983-3 7 LTC1983-3/LTC1983-5 Operation (Refer to Block Diagram) There are many aspects of the capacitors that must be taken into account. First, the temperature stability of the dielectric is a main concern. For ceramic capacitors, a three character code specifies the temperature stability (e.g. X7R, Y5V, etc.). The first two characters represent the temperature range that the capacitor is specified and the third represents the absolute tolerance that the capacitor is specified to over that temperature range. The ceramic capacitor used for the flying and output capacitors should be X5R or better. Second, the voltage coefficient of capacitance for the capacitor must be checked and the actual value usually needs to be derated for the operating voltage (the actual value has to be larger than the value needed to take into account the loss of capacitance due to voltage bias across the capacitor). Third, the frequency characteristics need to be taken into account because capacitance goes down as the frequency of oscillation goes up. Typically, the manufacturers have capacitance vs frequency curves for their products. This curve must be referenced to be sure the capacitance will not be too small for the application. Finally, the capacitor ESR and ESL must be low for reasons mentioned in the following section. Output Ripple Normal LTC1983 operation produces voltage ripple on the VOUT pin. Output voltage ripple is required for the LTC1983 to regulate. Low frequency ripple exists due to the hysteresis in the sense comparator and propagation delays in the charge pump enable/disable circuits. High frequency ripple is also present mainly due to ESR of the output capacitor. Typical output ripple under maximum load is 60mVP-P with a low ESR 10µF output capacitor. The magnitude of the ripple voltage depends on several factors. High input voltage to negative output voltage differentials [(VIN + VOUT) >1V] increase the output ripple since more charge is delivered to COUT per clock cycle. A large flying capacitor (>1µF) also increases ripple for the same reason. Large output current load and/or a small output capacitor ( 0.1Ω) on the output pin cause high frequency voltage spikes on VOUT with every clock cycle. There are several ways to reduce the output voltage ripple. A larger COUT capacitor (22µF or greater) will reduce both the low and high frequency ripple due to the lower COUT charging and discharging dV/dt and the lower ESR typically found with higher value (larger case size) capacitors. A low ESR ceramic output capacitor will minimize the high frequency ripple, but will not reduce the low frequency ripple unless a high capacitance value is chosen. A reasonable compromise is to use a 10µF to 22µF tantalum capacitor in parallel with a 1µF to 4.7µF ceramic capacitor on VOUT to reduce both the low and high frequency ripple. However, the best solution is to use 10µF to 22µF, X5R ceramic capacitors which are available in 1206 package sizes. An RC filter may also be used to reduce high frequency voltage spikes (see Figure 1). In low load or high VIN applications, smaller values for CFLY may be used to reduce output ripple. A smaller flying capacitor (0.01µF to 0.047µF) delivers less charge per clock cycle to the output capacitor resulting in lower output ripple. However, the smaller value flying caps also reduce the maximum IOUT capability as well as efficiency. LTC1983-X VOUT 3.9Ω 10µF TANTALUM VOUT 10µF TANTALUM 15µF TANTALUM VOUT 1µF CERAMIC LTC1983-X VOUT 1983 F01 Figure 1. Output Ripple Reduction Techniques 1983fc For more information www.linear.com/LTC1983-3 LTC1983-3/LTC1983-5 Operation (Refer to Block Diagram) Inrush Currents During normal operation, VIN will experience current transients in the several hundred milliamp range whenever the charge pump is enabled. During start-up, these inrush currents may approach 1 to 2 amps. For this reason, it is important to minimize the source resistance between the input supply and the VIN pin. Too much source resistance may result in regulation problems or even prevent startup. One way that this can be avoided (especially when the source impedance can’t be lowered due to system constraints) is to use a large VIN capacitor with low ESR right at the VIN pin. If ceramic capacitors are used, you may need to add 1µF to 10µF tantalum capacitor in parallel to limit input voltage transients. Input voltage transients will occur if VIN is applied via a switch or a plug. One example of this situation is in USB applications. Ultralow Quiescent Current Regulated Supply The LTC1983 contains an internal resistor divider (refer to the Block Diagram) that draws only 1µA (typ for the 3V version) from VOUT during normal operation. During shutdown, the resistor divider is disconnected from the output and the part draws only leakage current from the output. During no-load conditions, applying a 1Hz to 100Hz, 2% to 5% duty cycle signal to the SHDN pin ensures that the circuit of Figure 2 comes out of shutdown frequently enough to maintain regulation even under lowload conditions. Since the part spends nearly all of its time in shutdown, the no-load quiescent current is essentially zero. However, the part will still be in operation during the time the SHDN pin is high, so the current will not be zero and can be calculated using the following equations to determine the approximate maximum current: IIN(MAX) = [(Time out of shutdown) • (Burst Mode operation quiescent current) + (Normal operating IIN) • (Time output is being charged before the LTC1983 enters Burst Mode operation)]/(Period of SHDN signal). This number will be highly dependent on the amount of board leakage current and how many devices are connected to VOUT (each will draw some leakage current) and must be calculated and verified for each different board design. 3.3V TO 5.5V VIN CIN 10µF TANTALUM LTC1983-3 VIN SHDN GND C+ VOUT FROM MPU SHDN –3V ± 4% C– COUT 10µF CERAMIC CFLY 1µF CERAMIC SHDN PIN WAVEFORMS: LOW IQ MODE (IOUT ≤ 100µA) VOUT LOAD ENABLE MODE (IOUT = 100µA TO 100mA) (1Hz TO 100Hz, 2% TO 5% DUTY CYCLE) 1983 F02 Figure 2. Ultralow Quiescent Current Regulated Supply The LTC1983 must be out of shutdown for a minimum duration of 200µs to allow enough time to sense the output and keep it in regulation. A 1Hz, 2% duty cycle signal will keep VOUT in regulation under no-load conditions. Even though the term no-load is used, there will always be board leakage current and leakage current drawn by anything connected to VOUT. This is why it is necessary to wake the part up every once in a while to verify regulation. As the VOUT load current increases, the frequency with which the part is taken out of shutdown must also be increased to prevent VOUT from drooping below the – 2.88V (for the 3V version) during the OFF phase (see Figure 3). A 100Hz, 2% duty cycle signal on the SHDN pin ensures proper regulation with load currents as high as 100µA. When load current greater than 100µA is needed, the SHDN pin must be forced high as in normal operation. Each time the LTC1983 comes out of shutdown, the part delivers a minimum of one clock cycle worth of charge to the output. Under high VIN (>4V) and/or low IOUT (