LTC2066/LTC2067/LTC2068
10µA Supply Current,
Low IB, Zero-Drift Operational Amplifier
FEATURES
DESCRIPTION
Low Supply Current: 10μA Maximum (per Amplifier)
n Offset Voltage: 5μV Maximum
n Offset Voltage Drift: 0.02μV/°C Maximum
n Input Bias Current:
n 5pA Typical
n 50pA Maximum, –40°C to 85°C
n 150pA Maximum, –40°C to 125°C
n Integrated EMI Filter (90dB Rejection at 1.8GHz)
n Shutdown Current: 170nA Maximum (per Amplifier)
n Rail-to-Rail Input and Output
n 1.7V to 5.25V Operating Supply Range
n A
VOL: 140dB Typical
n Low-Charge Power-Up for Duty Cycled Applications
n Specified Temperature Ranges:
n –40°C to 85°C
n –40°C to 125°C
n SC70, TSOT23, MS8, DFN10, TSSOP14 and
QFN16 Packages
The LTC®2066/LTC2067/LTC2068 are single, dual,
and quad low power, zero-drift, 100kHz amplifiers. The
LTC2066/LTC2067/LTC2068 enable high resolution measurement at extremely low power levels.
n
APPLICATIONS
Signal Conditioning in Wireless Mesh Networks
Portable Instrumentation Systems
n Low-Power Sensor Conditioning
n Gas Detection
n Temperature Measurement
n Medical Instrumentation
n Energy Harvesting Applications
n Low Power Current Sensing
n
n
Typical supply current is 7.5µA per amplifier with a maximum of 10µA. The available shutdown mode has been
optimized to minimize power consumption in duty-cycled
applications and features low charge loss during powerup, reducing total system power.
The LTC2066/LTC2067/LTC2068’s self-calibrating circuitry results in very low input offset (5µV max) and offset
drift (0.02µV/°C). The maximum input bias current is only
35pA and does not exceed 150pA over the full specified
temperature range. The extremely low input bias current
of the LTC2066/LTC2067/LTC2068 allows the use of high
value power-saving resistors in the feedback network.
With its ultralow quiescent current and outstanding precision, the LTC2066/LTC2067/LTC2068 can serve as a
signal chain building block in portable, energy harvesting and wireless sensor applications.
The LTC2066 is available in 6-lead SC70 and 5-lead TSOT23 packages. The LTC2067 is available in 8-lead MSOP
and 10-lead DFN packages. The LTC2068 is available in
14-lead TSSOP and 16-lead 3mm × 3mm QFN packages.
These devices are fully specified over the –40°C to 85°C
and –40°C to 125°C temperature ranges.
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
Output Voltage vs Sense Current
2.5
Precision Micropower Low Side Current Sense
VIN
100µA TO 250mA
3.3V
–
LOAD
ISENSE
1M
0.1%
10k*
0.1%
100mΩ
0.1%
LTC2066
VOUT = 10 • ISENSE
1mV TO 2.5V
+
1
OUTPUT VOLTAGE, VOUT (V)
10k
0.1%
0.1
0.01
2066 TA01a
*RESISTOR CANCELS OUT PARASITIC SEEBECK EFFECT VOLTAGE
0.001
0.1
1
10
ISENSE (mA)
100
250
2066 TA01b
Rev. B
Document Feedback
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1
LTC2066/LTC2067/LTC2068
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage (V+ to V–).................................5.5V
Differential Input Current (+IN to –IN) (Note 2)..... ±10mA
Differential Input Voltage (+IN to –IN).......................5.5V
Input Voltage +IN, –IN, SHDN........(V–) – 0.3V to (V+) + 0.3V
Input Current +IN, –IN, SHDN (Note 2)................... ±10mA
Output Short-Circuit Duration (Note 3)......Thermally Limited
Operating and Specified Temperature Range (Note 4)
LTC2066I/LTC2067I/LTC2068I.............–40°C to 85°C
LTC2066H/LTC2067H/LTC2068H....... –40°C to 125°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
LTC2066
LTC2067
LTC2068
TOP VIEW
TOP VIEW
4 OUT
SC6 PACKAGE
6-LEAD PLASTIC SC70
θJA = 265°C/W (Note 5)
8
7
6
5
A
B
16 15 14 13
V+
OUTB
–INB
+INB
12 –IND
–INA 1
+INA 2
11 +IND
10 V–
17
V+ 3
+INB 4
MS8 PACKAGE
8-LEAD PLASTIC MSOP
θJA = 163°C/W, θJC = 40°C/W (Note 5)
9
5
6
7
8
–INC
–IN 3
1
2
3
4
OUTC
OUTA
–INA
+INA
V–
5 SHDN
–INB
+
–
V– 2
OUTB
6 V+
+IN 1
SHDN
OUTA
OUTD
NC
TOP VIEW
+INC
QFN16 PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
θJA = 68°C/W (NOTE 5)
EXPOSED PAD (PIN 17) MUST BE CONNECTED TO V–(PIN 10)
LTC2066
LTC2067
TOP VIEW
5 V+
OUT 1
+IN 3
+
–
V– 2
TOP VIEW
OUTA
1
10 V+
–INA
2
9 OUTB
+INA
3
V–
4
NC
5
4 –IN
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
θJA = 215°C/W (Note 5)
LTC2068
TOP VIEW
A
11
B
8 –INB
7 +INB
6 SHDN
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
θJA = 43°C/W, θJC = 5.5°C/W (Note 5)
EXPOSED PAD (PIN 11) IS CONNECTED
TO V– (PIN 4) (PCB CONNECTION OPTIONAL)
OUTA 1
–INA 2
+INA 3
14 OUTD
A
D
V+ 4
+INB 5
–INB 6
OUTB 7
13 –IND
12 +IND
11 V–
B
C
10 +INC
9 –INC
8 OUTC
TSSOP14 PACKAGE
14-LEAD PLASTIC TSSOP
θJA = 100°C/W (NOTE 5)
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2066ISC6#TRMPBF
LTC2066ISC6#TRPBF
LHDB
6-Lead Plastic SC70
–40°C to 85°C
LTC2066HSC6#TRMPBF
LTC2066HSC6#TRPBF
LHDB
6-Lead Plastic SC70
–40°C to 125°C
LTC2066IS5#TRMPBF
LTC2066IS5#TRPBF
LTHCZ
5-Lead Plastic TSOT-23
–40°C to 85°C
LTC2066HS5#TRMPBF
LTC2066HS5#TRPBF
LTHCZ
5-Lead Plastic TSOT-23
–40°C to 125°C
LTC2067IMS8#PBF
LTC2067IMS8#TRPBF
LTHDC
8-Lead Plastic MSOP
–40°C to 85°C
LTC2067HMS8#PBF
LTC2067HMS8#TRPBF
LTHDC
8-Lead Plastic MSOP
–40°C to 125°C
LTC2067IDD#PBF
LTC2067IDD#TRPBF
LHDD
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC2067HDD#PBF
LTC2067HDD#TRPBF
LHDD
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC2068IUD#PBF
LTC2068IUD#TRPBF
LHKV
16-Lead (3mm × 3mm) Plastic QFN
–40°C to 85°C
LTC2068HUD#PBF
LTC2068HUD#TRPBF
LHKV
16-Lead (3mm × 3mm) Plastic QFN
–40°C to 125°C
LTC2068IF#PBF
LTC2068IF#TRPBF
LTC2068
14-Lead TSSOP
–40°C to 85°C
LTC2068HF#PBF
LTC2068HF#TRPBF
LTC2068
14-Lead TSSOP
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Parts ending with PBF are RoHS and WEEE compliant.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
2
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VS = 1.8V, VCM = VOUT = VS/2, VSHDN = 1.8V,
RL to VS/2.
SYMBOL PARAMETER
CONDITIONS
VOS
VS = 1.7V
Input Offset Voltage (Note 6)
TYP
MAX
UNITS
1
l
±5
±10
μV
μV
l
l
±0.03
±0.05
ΔVOS/ΔT
Input Offset Voltage Drift (Note 6)
IB
Input Bias Current (Note 7)
±2
pA
IOS
Input Offset Current (Note 7)
±4
pA
in
Input Noise Current Spectral Density
f ≤ 100Hz
35
fA/√Hz
en
Input Noise Voltage Spectral Density
f ≤ 100Hz
90
nV/√Hz
en P-P
Input Noise Voltage
DC to 10Hz
1.9
μVP–P
CIN
Input Capacitance
Differential
Common Mode
3.3
3.5
pF
pF
VCMR
Input Voltage Range
Guaranteed by CMRR
CMRR
PSRR
–40°C to 85°C
–40°C to 125°C
MIN
l
(V–) – 0.1
VCM
RL = 499k
103
100
123
l
dB
dB
VS = 1.7V to 5.25V
RL = 499k
108
106
126
l
dB
dB
= (V–) – 0.1V to (V+) + 0.1V
Common Mode Rejection Ratio (Note 8)
Power Supply Rejection Ratio
(V+) + 0.1
μV/°C
µV/°C
V
AVOL
Open Loop Gain
VOUT = (V–) + 0.1V to (V+) – 0.1V, RL = 499k
135
dB
VOL
Output Voltage Swing Low (VOUT – V–)
RL = 499k
0.05
mV
RL = 10k
3
l
VOH
Output Voltage Swing High (V+ – VOUT)
RL = 499k
0.1
RL = 10k
4.5
l
ISC
Output Short Circuit Current
10
20
Sourcing
mV
mV
mV
10
50
mV
mV
5.8
4
7.5
l
mA
mA
10.4
5
13
l
mA
mA
Sinking
SR
Slew Rate
AV = +1
17.5
V/ms
GBW
Gain Bandwidth Product
RL = 499k
100
kHz
tON
Power-Up Time
0.4
ms
fC
Internal Chopping Frequency
25
kHz
VS
Supply Voltage Range
Guaranteed by PSRR
IS
Supply Current per Amplifier
No Load
–40°C to 85°C
–40°C to 125°C
l
l
In Shutdown (SHDN = V–)
–40°C to 85°C
–40°C to 125°C
l
l
l
VH
SHDN Pin Threshold, Logic High (Referred to V–)
l
VL
SHDN Pin Threshold, Logic Low (Referred to V–)
l
ISHDN
SHDN Pin Current
VSHDN = 0V
l
1.7
5.25
V
7.4
10
12.5
20
μA
μA
µA
90
170
250
500
nA
nA
nA
1.0
–150
V
0.65
V
–20
nA
Rev. B
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3
LTC2066/LTC2067/LTC2068
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VS = 5V, VCM = VOUT = VS/2, VSHDN = 5V,
RL to VS/2.
SYMBOL PARAMETER
CONDITIONS
VOS
VS = 5.25V
Input Offset Voltage (Note 6)
ΔVOS/ΔT
Input Offset Voltage Drift (Note 6)
IB
Input Bias Current
IOS
Input Offset Current
TYP
MAX
UNITS
1
l
±5
±10
μV
μV
–40°C to 85°C
–40°C to 125°C
l
l
±0.02
±0.04
μV/°C
µV/°C
–40°C to 85°C
–40°C to 125°C
±5
l
l
±35
±50
±150
pA
pA
pA
LTC2066, LTC2067
–40°C to 85°C
–40°C to 125°C
±10
l
l
±35
±50
±150
pA
pA
pA
LTC2068
–40°C to 85°C
–40°C to 125°C
±10
l
l
±65
±70
±170
pA
pA
pA
in
Input Noise Current Spectral Density
f ≤ 100Hz
en
Input Noise Voltage Spectral Density
en P–P
Input Noise Voltage
CIN
VCMR
CMRR
PSRR
MIN
35
fA/√Hz
f ≤ 100Hz
80
nV/√Hz
DC to 10Hz
1.7
μVP–P
Input Capacitance
Differential
Common Mode
3.3
3.5
pF
pF
Input Voltage Range
Guaranteed by CMRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
l
(V–) – 0.1
VCM
RL = 499k
111
108
134
l
dB
dB
VS = 1.7V to 5.25V
RL = 499k
108
106
126
l
dB
dB
66
79
90
76
dB
dB
dB
dB
140
dB
dB
0.1
mV
= (V–) – 0.1V to (V+) + 0.1V
EMIRR
EMI Rejection Ratio
VRF = 100mVPK
EMIRR = 20 • log(VRF/∆VOS)
f = 400MHz
f = 900MHz
f = 1800MHz
f = 2400MHz
AVOL
Open Loop Gain
VOUT = (V–) + 0.1V to (V+) – 0.1V, RL = 499k
l
VOL
Output Voltage Swing Low (VOUT – V–)
112
110
RL = 499k
RL = 10k
(V+) + 0.1
5.5
l
VOH
Output Voltage Swing High (V+ – VOUT)
RL = 499k
0.15
RL = 10k
7
l
ISC
Output Short Circuit Current
Sourcing
15
20
V
mV
mV
mV
15
20
mV
mV
30
16
51
l
mA
mA
20
5
48
l
mA
mA
Sinking
SR
Slew Rate
AV = +1
17.5
V/ms
GBW
Gain Bandwidth Product
RL = 499k
100
kHz
tON
Power-Up Time
0.4
ms
fC
Internal Chopping Frequency
25
kHz
VS
Supply Voltage Range
Guaranteed by PSRR
IS
Supply Current per Amplifier
No Load
–40°C to 85°C
–40°C to 125°C
4
l
1.7
7.5
l
l
5.25
V
10
12.5
20
μA
μA
µA
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VS = 5V, VCM = VOUT = VS/2, VSHDN = 5V,
RL to VS/2.
SYMBOL PARAMETER
CONDITIONS
MIN
In Shutdown (SHDN = V–)
–40°C to 85°C
–40°C to 125°C
l
l
VH
SHDN Pin Threshold, Logic High (Referred to V–)
l
VL
SHDN Pin Threshold, Logic Low (Referred to V–)
l
ISHDN
SHDN Pin Current
VSHDN = 0V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs are protected by two series connected ESD protection
diodes to each power supply. The input current should be limited to less than
10mA. The input voltage should not exceed 300mV beyond the power supply.
Note 3: A heat sink may be required to keep the junction temperature below
the absolute maximum rating when the output is shorted indefinitely.
Note 4: The LTC2066I/LTC2067I/LTC2068I is guaranteed to meet specified
performance from –40°C to 85°C. The LTC2066H/LTC2067H/LTC2068H is
guaranteed to meet specified performance from –40°C to 125°C.
l
TYP
MAX
UNITS
90
170
250
500
nA
nA
nA
1.8
–150
V
0.8
V
–20
nA
Note 5: Thermal resistance varies with the amount of PC board metal
connected to the package. The specified values are for short traces
connected to the leads.
Note 6: These parameters are guaranteed by design. Thermocouple effects
preclude measurements of these voltage levels during automated testing.
VOS is measured to a limit determined by test equipment capability.
Note 7: Input Bias Current, Input Offset Current and Open Loop Gain are
only production tested at 5V. Input Bias Current and Input Offset Current
at 1.8V are expected to meet 5V specifications.
Note 8: Minimum specifications for these parameters are limited by noise
and the capabilities of the automated test system.
Rev. B
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5
LTC2066/LTC2067/LTC2068
TYPICAL PERFORMANCE CHARACTERISTICS
80
70
260 TYPICAL UNITS
70 VS = 5V
60
NUMBER OF AMPLIFIERS
50
40
30
20
40
30
20
10
0
0
3
4
5
2066 G01
Input Offset Voltage Drift
Distribution (H-Grade)
120
80
60
40
–5 –4 –3 –2 –1 0 1
VOS (µV)
0
5
60
50
40
30
20
0
5
120
40
5
4
3
100
80
60
40
20
0
5
0
10 15 20 25 30 35 40 45 50
VOS TC (nV/°C)
6
1
2
VOS (µV)
1
0
–1
0
–2
–2
–4
–3
–3
–6
–4
–4
–8
–5
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCM (V)
–5
–0.5
0.5
5 TYPICAL UNITS
VCM = VS/2
TA = 25°C
8
4
0
10 15 20 25 30 35 40 45 50
VOS TC (nV/°C)
10
5 TYPICAL UNITS
VS = 1.8V
TA = 25°C
–2
6
5
Input Offset Voltage vs
Supply Voltage
2
2066 G07
0
2066 G06
2
–1
260 TYPICAL UNITS
VS = 1.8V
TA = –40°C TO 85°C
2066 G05
5 TYPICAL UNITS
VS = 5V
TA = 25°C
10 15 20 25 30 35 40 45 50
VOS TC (nV/°C)
2066 G03
Input Offset Voltage vs
Input Common Mode Voltage
0
5
Input Offset Voltage Drift
Distribution (I-Grade)
60
0
10 15 20 25 30 35 40 45 50
VOS TC (nV/°C)
0
2066 G02
20
VOS (µV)
VOS (µV)
3
4
80
Input Offset Voltage vs
Input Common Mode Voltage
4
3
100
2066 G04
5
2
260 TYPICAL UNITS
VS = 5V
TA = –40°C TO 85°C
120
20
0
70
10
140
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
100
80
Input Offset Voltage Drift
Distribution (I-Grade)
260 TYPICAL UNITS
VS = 1.8V
TA = –40°C TO 125°C
260 TYPICAL UNITS
VS = 5V
TA = –40°C TO 125°C
90
50
10
2
100
260 TYPICAL UNITS
VS = 1.8V
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
60
–5 –4 –3 –2 –1 0 1
VOS (µV)
Input Offset Voltage Drift
Distribution (H-Grade)
Input Offset Voltage Distribution
NUMBER OF AMPLIFIERS
Input Offset Voltage Distribution
1
VCM (V)
1.5
2
2.5
2066 G08
–10
1
1.5
2
2.5
3 3.5
VS (V)
4
4.5
5
5.5
2066 G09
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bias Current Distribution
1500
6276 TYPICAL UNITS
VS = 5V
TA = 25°C
6276 TYPICAL UNITS
VS = 1.8V
TA = 25°C
1250
NUMBER OF AMPLIFIERS
1250
NUMBER OF AMPLIFIERS
Input Bias Current Distribution
1500
1000
750
500
1000
250
750
500
250
0
–20 –16 –12 –8 –4 0 4 8 12 16 20
INPUT BIAS CURRENT (pA)
0
–10 –8 –6 –4 –2 0 2 4 6
INPUT BIAS CURRENT (pA)
2066 G10
Input Bias Current vs
Input Common Mode Voltage
20
VS = 5V
10
15
IB (–IN)
10
IB (+IN)
5
IB (+IN)
IB (pA)
IB (pA)
VS = 5V
TA = 25°C
15
20
5
0
IB (–IN)
–5
0
–10
–5
–15
–10
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
–20
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCM (V)
125
2066 G13
2066 G12
Input Bias Current vs
Input Common Mode Voltage
10
8
Input Bias Current vs
Supply Voltage
10
VS = 1.8V
TA = 25°C
6
4
IB (pA)
0
IB (+IN)
–2
IB (+IN)
4
IB (–IN)
2
2
0
–4
–6
–6
–8
IB (–IN)
–2
–4
–10
–0.5
VCM = VS/2
TA = 25°C
8
6
IB (pA)
10
2066 G11
Input Bias Current vs Temperature
25
8
–8
0
0.5
1
1.5
VCM (V)
2
2.5
–10
1
1.5
2066 G14
2
2.5
3 3.5
VS (V)
4
4.5
5
5.5
2066 G15
Rev. B
For more information www.analog.com
7
LTC2066/LTC2067/LTC2068
TYPICAL PERFORMANCE CHARACTERISTICS
10
Input Offset and Average Current
vs Input Common Mode Voltage
5
VS = 5V
TA = 25°C
8
3
IB (pA)
IB (pA)
0
–2
–4
1
0
–1
–2
IOS
–6
IAVG
2
IAVG
2
VS = 1.8V
TA = 25°C
4
6
4
IOS
–3
–4
–8
–5
–0.5
–10
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCM (V)
0
0.5
1
1.5
VCM (V)
2
Input Referred Voltage Noise
Density
1k
VS = ± 0.9V
VS = ± 2.5V
1
10
100
1k
FREQUENCY (Hz)
10k
VS = 5V
VCM = 2.5V
40
1
10
100 1k 10k 100k
FREQUENCY (Hz)
120
0
0.1
–PSRR
20
1
10
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
2066 G22
1
RF FREQUENCY (GHz)
4
2066 G21
0
70
50
40
30
20
10
0
AV = +100
AV = +10
AV = +1
–10
AV = –1
–20
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
2066 G23
VS = 5V
RL = 499kΩ
RF = 1MΩ
AV = +1000
60
CLOSED LOOP GAIN (dB)
+PSRR
60
40
20
0.1
Closed Loop Gain vs Frequency
80
PSRR (dB)
CMRR (dB)
VS = 5V
40
20
0.05
1M
VS = 5V
RL = 499kΩ
100
VS = 1.8V
60
100
Power Supply Rejection Ratio
vs Frequency
RL = 499kΩ
60
80
2066 G20
120
80
VIN = 100mVPK
EMIRR = 20log(100mV/∆VOS)
1k
10
0.1
100k
EMI Rejection vs Frequency
100
Common Mode Rejection Ratio
vs Frequency
100
2066 G18
120
2066 G19
140
TIME (1s/DIV)
EMIRR (dB)
CURRENT NOISE DENSITY (fA/√Hz)
VOLTAGE NOISE DENSITY (nV/√Hz)
10k
10
0.1
2.5
Input Referred Current Noise
Density
10k
100
VS = ± 2.5V
2066 G17
2066 G16
8
DC to 10Hz Voltage Noise
INPUT REFERRED VOLTAGE NOISE (0.5µV/DIV)
Input Offset and Average Current
vs Input Common Mode Voltage
–30
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
2066 G24
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
TYPICAL PERFORMANCE CHARACTERISTICS
0
140
120
PHASE
VS = 5V
RL = 499kΩ –45
80
60
–180
60
40
–225
20
–270
0
–20
CL = 0pF
CL = 47pF
CL = 100pF
–40
–60
1m 10m100m 1
GAIN (dB)
100
–135
0
–20
–405
–40
–450
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
–150
GAIN
20
–360
–90
–120
40
–315
–60
PHASE
–180
–210
CL = 0pF
CL = 47pF
CL = 100pF
–60
1m 10m 100m 1
–240
–270
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
2066 G25
150
–40
OPEN LOOP GAIN (dB)
CROSSTALK (dB)
–20
–60
–80
–100
–140
100
B to A
A to B
1k
10k
100k
FREQUENCY (Hz)
1M
Shutdown Transient with
Sinusoidal Input
VS = 5V
135
VOUT, VIN
0.1V/DIV
130
400µs/DIV
1
2066 G28
Shutdown Transient with
Sinusoidal Input
10
RLOAD (kΩ)
100
500
2066 G30
Enable Transient with
Sinusoidal Input
VSHDN
5V/DIV
IS
5µA/DIV
VSHDN
2V/DIV
IS
5µA/DIV
IS
5µA/DIV
VOUT, VIN
0.1V/DIV
2066 G29
VS = ±2.5V
AV = +1
Enable Transient with
Sinusoidal Input
VSHDN
2V/DIV
1M
2066 G27
IS
5µA/DIV
120
VOUT, VIN
0.2V/DIV
VOUT, VIN
1V/DIV
VS = ±0.9V
AV = +1
–120
140
–140
100
400µs/DIV
–100
VSHDN
5V/DIV
125
10k
100k
FREQUENCY (Hz)
–80
145
–120
1k
–60
Open Loop Gain vs Load
ADJACENT CHANNELS
DIAGONAL CHANNELS
RL = 10k
–40
2066 G26
LTC2068 Crosstalk vs Frequency
0
RL = 10k
–20
PHASE (°)
–90
80
GAIN
V = 1.8V
RSL = 499kΩ –30
120
100
LTC2067 Crosstalk vs Frequency
0
0
140
PHASE (°)
GAIN (dB)
Open Loop Gain and Phase
vs Frequency
CROSSTALK (dB)
Open Loop Gain and Phase
vs Frequency
2066 G31
400µs/DIV
VS = ±2.5V
AV = +1
2066 G32
400µs/DIV
2066 G33
VS = ±0.9V
AV = +1
Rev. B
For more information www.analog.com
9
LTC2066/LTC2067/LTC2068
TYPICAL PERFORMANCE CHARACTERISTICS
Closed Loop Output Impedance
vs Frequency
1M
Output Impedance in Shutdown
vs Frequency
1G
VS = 5V
AV = +1
100k
100M
10M
1k
ZOUT (Ω)
ZOUT (Ω)
10k
100
1M
100k
10
10k
1
0.1
VS = 5V
AV = +1
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
1k
10M
10
100
1k
10k 100k
FREQUENCY (Hz)
AV = +1
VS = ±2.5V
VOUT = ±2V
–40
–60
–80
–100
–120
RL = 10k
RL = 499k
20
100
FREQUENCY (Hz)
1k
2k
Maximum Undistorted Output
Amplitude vs Frequency
Supply Current vs Supply Voltage
6
12.5
5
10.0
4
3
2
AV = +1
VS = ±2.5V
THD < –40dB
RL = 499k
1
0
100
1k
FREQUENCY (Hz)
2066 G37
10
9
8
7
6
5
–50
VS = 5V
Supply Current vs SHDN Pin
Voltage
60
40
30
20
10
–25
0
25
50
75
TEMPERATURE (°C)
100
125
0
VS = 1.8V
14
50
12
125°C
85°C
25°C
–40°C
10
8
6
4
2
0
0.5
1
1.5 2 2.5 3 3.5 4
SHDN PIN VOLTAGE (V)
4.5
2066 G39
10
16
125°C
85°C
25°C
–40°C
70
IS PER AMPLIFIER (µA)
IS PER AMPLIFIER (µA)
80
VS = 1.8V
VS = 5V
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
2066 G38
Supply Current vs SHDN Pin
Voltage
Supply Current vs Temperature
11
5.0
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VS (V)
10k
2066 G36
12
7.5
2.5
IS PER AMPLIFIER (µA)
TOTAL HARMONIC DISTORTION (dB)
–20
10M
2066 G35
IS PER AMPLIFIER (µA)
THD vs Frequency
MAXIMUM UNDISTORTED OUTPUT VOLTAGE (VP–P)
2066 G34
1M
5
2066 G40
0
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
SHDN PIN VOLTAGE (V)
2066 G41
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
TYPICAL PERFORMANCE CHARACTERISTICS
SHDN Pin Pull-Up Current vs
SHDN Pin Voltage
20
VS = 5V
0
–10
–20
0
–20
–50
–40
–50
–60
–60
–70
–70
–80
–80
–90
–90
0
1
2
3
VSHDN (V)
4
5
–100
6
–1
0.5
1
1.5
–80
–50
2
100
250
200
150
100
10
125°C
85°C
25°C
–40°C
VS = 1.8V
VS = 5V
–25
0
25
50
75
TEMPERATURE (°C)
100
0.1
0.01
125
0.1
2066 G46
Output Voltage Swing Low
vs Load Current
4000
VS = ± 0.9V
125
VS = ± 2.5V
1
2066 G45
Output Voltage Swing High
vs Load Current
100
1000
50
–50
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VS (V)
0
25
50
75
TEMPERATURE (°C)
Output Voltage Swing High
vs Load Current
4000
100
50
–25
2066 G44
300
150
VS = 1.8V
VS = 5V
2066 G43
350
200
1000
–60
Shutdown Supply Current vs
Temperature
250
0
0
VSHDN (V)
IS PER AMPLIFIER (nA)
IS PER AMPLIFIER (nA)
300
–0.5
2066 G42
125°C
85°C
25°C
–40°C
350
–50
–70
Shutdown Supply Current vs
Supply Voltage
400
VSHDN = 0V
–40
–30
ISHDN (nA)
ISHDN (nA)
–40
–1
125°C
85°C
25°C
–40°C
–10
–30
–100
VS = 1.8V
10
125°C
85°C
25°C
–40°C
ISHDN (nA)
10
SHDN Pin Current vs Temperature
–30
V+ – VOH (mV)
20
SHDN Pin Pull-Up Current vs
SHDN Pin Voltage
1
ISOURCE (mA)
10
100
2066 G47
Output Voltage Swing Low
vs Load Current
1000
VS = ± 2.5V
VS = ± 0.9V
1000
100
10
1
0.1
0.01
125°C
85°C
25°C
–40°C
0.1
1
ISOURCE (mA)
10
100
2066 G48
100
VOL – V– (mV)
VOL – V- (mV)
V+ – VOH (mV)
100
10
125°C
85°C
25°C
–40°C
1
0.1
0.01
0.1
1
ISINK (mA)
10
100
2066 G49
10
1
0.1
0.01
125°C
85°C
25°C
–40°C
0.1
1
ISINK (mA)
10
100
2066 G50
Rev. B
For more information www.analog.com
11
LTC2066/LTC2067/LTC2068
TYPICAL PERFORMANCE CHARACTERISTICS
Output Short Circuit Current
vs Temperature
No Phase Reversal
90
AV = +1
VS = ±2.5V
VIN = 5.6VP–P
Output Short Circuit Current
vs Temperature
20
VS = ± 2.5V
80
70
VS = ± 0.9V
15
ISC (mA)
ISC (mA)
VOLTAGE (1V/DIV)
60
50
40
10
30
5
20
SOURCING
SINKING
10
VOUT
VIN
0
–50
–25
1ms/DIV
0
25
50
75
TEMPERATURE (°C)
100
0
–50
125
SINKING
SOURCING
–25
0
25
50
75
TEMPERATURE (°C)
2066 G52
2066 G51
Large Signal Response
Small Signal Response
VS = ±2.5V
VIN = 40mVP–P
AV = +1
VOUT (0.5V/DIV)
VOUT (10mV/DIV)
VS = ±0.9V
AV = +1
VOUT (1V/DIV)
125
2066 G53
Large Signal Response
VS = ±2.5V
AV = +1
100
CL = 3.9pF
CL = 100pF
200µs/DIV
200µs/DIV
20µs/DIV
2066 G54
2066 G55
2066 G56
Small Signal Overshoot
vs Load Capacitance
Small Signal Response
80
VS = ±0.9V
VIN = 40mVP–P
AV = +1
Small Signal Overshoot
vs Load Capacitance
60
VS = ±2.5V
VIN = 40mVP–P
AV = +1
70
VS = ±0.9V
VIN = 40mVP–P
AV = +1
50
OVERSHOOT (%)
OVERSHOOT (%)
VOUT (10mV/DIV)
60
50
40
30
40
30
20
20
10
CL = 3.9pF
CL = 100pF
0
20µs/DIV
2066 G57
12
+OS
–OS
1
10
100
CL (pF)
1000
2066 G58
10
0
+OS
–OS
1
10
100
CL (pF)
1000
2066 G59
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
TYPICAL PERFORMANCE CHARACTERISTICS
Positive Output Overload
Recovery
VOUT
0.5V/DIV
VOUT
1V/DIV
VIN
50mV/DIV
VOUT
1V/DIV
VIN
50mV/DIV
VIN
50mV/DIV
200µs/DIV
Negative Output Overload
Recovery
Positive Output Overload Recovery
2066 G60
2066 G61
400µs/DIV
200µs/DIV
2066 G62
VS = ±2.5V
AV = –100
VS = ±0.9V
AV = –100
VS = ±2.5V
AV = –100
Negative Output Overload
Recovery
Positive Input Overload Recovery
Positive Input Overload Recovery
VOUT
0.5V/DIV
VIN
50mV/DIV
400µs/DIV
VIN
1V/DIV
VIN
0.5V/DIV
VOUT
1V/DIV
VOUT
0.5V/DIV
2066 G63
VS = ±0.9V
AV = –100
2066 G64
100µs/DIV
VS = ±2.5V
AV = +1
40µs/DIV
2066 G65
VS = ±0.9V
AV = +1
Negative Input Overload Recovery
Negative Input Overload Recovery
VIN
0.5V/DIV
VIN
1V/DIV
VOUT
0.5V/DIV
VOUT
1V/DIV
100µs/DIV
VS = ±2.5V
AV = +1
2066 G66
40µs/DIV
2066 G65
VS = ±0.9V
AV = +1
Rev. B
For more information www.analog.com
13
LTC2066/LTC2067/LTC2068
PIN FUNCTIONS
V–: Negative Power Supply. A bypass capacitor should be
used between supply pins and ground.
OUT: Amplifier Output
–IN: Inverting Amplifier Input
+IN: Noninverting Amplifier Input
V+: Positive Power Supply. A bypass capacitor should be
used between supply pins and ground.
SHDN: Shutdown Control Pin. The SHDN pin threshold is
referenced to V–. If tied to V+, the part is enabled. If tied
to V–, the part is disabled and draws less than 170nA of
supply current per amplifier. It is recommended not to
float this pin.
BLOCK DIAGRAM
Amplifier
Shutdown Circuit
V+
V+
V+
50nA
10k
SHDN
+IN
V–
7k
V–
V+
EMI
FILTER
7k
SHDN
V+
V+
2066 BDb
V–
+
OUT
–
2066 BDa
V–
V–
–IN
V–
14
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
APPLICATIONS INFORMATION
Using the LTC2066/LTC2067/LTC2068
The LTC2066/LTC2067/LTC2068 are single, dual, and
quad zero-drift operational amplifiers with the open-loop
voltage gain and bandwidth characteristics of a conventional operational amplifier. Advanced circuit techniques
allow the LTC2066/LTC2067/LTC2068 to operate continuously through its entire bandwidth while self-calibrating
unwanted errors.
Input Voltage Noise
Zero-drift amplifiers like the LTC2066/LTC2067/LTC2068
achieve low input offset voltage and 1/f noise by heterodyning DC and flicker noise to higher frequencies. In early
zero-drift amplifiers, this process resulted in idle tones
at the self-calibration frequency, often referred to as the
chopping frequency. These artifacts made early zero-drift
amplifiers difficult to use. The advanced circuit techniques
used by the LTC2066/LTC2067/LTC2068 suppress these
spurious artifacts, allowing for trouble-free use.
Input Current Noise
For applications with high source and feedback impedances, input current noise can be a significant contributor
to total output noise. For this reason, it is important to
consider noise current interaction with circuit elements
placed at the amplifier’s inputs.
CURRENT NOISE DENSITY (fA/√Hz)
10k
VS = 5V
VCM = 2.5V
1k
100
10
0.1
1
10
100 1k 10k 100k
FREQUENCY (Hz)
1M
2066 F01
Figure 1. Input Current Noise Spectrum
The current noise spectrum of the LTC2066/LTC2067/
LTC2068 is shown in Figure 1. Low input current noise
is achieved through the use of MOSFET input devices and
self-calibration techniques to eliminate 1/f current noise.
As with all zero-drift amplifiers, there is an increase in
current noise at the offset-nulling frequency. This phenomenon is discussed in the Input Bias Current and Clock
Feedthrough section.
Input current noise also rises with frequency due to
capacitive coupling of MOSFET channel thermal noise.
Input Bias Current and Clock Feedthrough
The input bias current of zero-drift amplifiers has different characteristics than that of a traditional operational
amplifier. The specified input bias current is the DC average of transient currents which conduct due to the input
stage’s switching circuitry. In addition to this, junction
leakages can contribute additional input bias current at
elevated temperatures. Through careful design and the
use of an innovative boot-strap circuit, the input bias current of the LTC2066/LTC2067/LTC2068 does not exceed
35pA at room and 150pA over the full temperature range.
This minimizes bias current induced errors even in high
impedance circuits.
Transient switching currents at the input interact with
source and feedback impedances, producing error voltages which are indistinguishable from a valid input signal.
The resulting error voltages are amplified by the amplifier’s closed-loop gain, which acts as a filter, attenuating
frequency components above the circuit bandwidth. This
phenomenon is known as clock feedthrough and is present in all zero-drift amplifiers. Understanding the cause
and effect of clock feedthrough is important when using
zero-drift amplifiers.
For zero-drift amplifiers, clock feedthrough is proportional
to source and feedback impedances, as well as the magnitude of the transient currents. These transient currents
have been minimized in the LTC2066/LTC2067/LTC2068
to allow use with high source and feedback impedances.
Many circuit designs require high feedback impedances
Rev. B
For more information www.analog.com
15
LTC2066/LTC2067/LTC2068
APPLICATIONS INFORMATION
In order to achieve accuracy on the microvolt level, thermocouple effects must be considered. Any connection
of dissimilar metals forms a thermoelectric junction and
generates a small temperature-dependent voltage. Also
known as the Seebeck Effect, these thermal EMFs can be
the dominant error source in low-drift circuits.
Connectors, switches, relay contacts, sockets, resistors,
and solder are all candidates for significant thermal EMF
generation. Even junctions of copper wire from different
manufacturers can generate thermal EMFs of 200nV/°C,
which significantly exceeds the maximum drift specification of the LTC2066/LTC2067/LTC2068. Figures 2 and 3
illustrate the potential magnitude of these voltages and
their sensitivity to temperature.
In order to minimize thermocouple-induced errors, attention must be given to circuit board layout and component
selection. It is good practice to minimize the number of
junctions in the amplifier’s input signal path and avoid connectors, sockets, switches, and relays whenever possible.
If such components are required, they should be selected
for low thermal EMF characteristics. Furthermore, the number, type, and layout of junctions should be matched for
both inputs with respect to thermal gradients on the circuit board. Doing so may involve deliberately introducing
dummy junctions to offset unavoidable junctions.
Air currents can also lead to thermal gradients and cause
significant noise in measurement systems. It is important
to prevent airflow across sensitive circuits. Doing so will
often reduce thermocouple noise substantially. A summary of techniques can be found in Figure 4.
16
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
MICROVOLTS REFERRED TO 25°C
Thermocouple Effects
25
35
30
40
45
TEMPERATURE (°C)
2066 F02
Figure 2. Thermal EMF Generated by Two Copper
Wires from Different Manufacturers
THERMALLY PRODUCED VOLTAGE IN MICROVOLTS
to minimize power consumption and/or require a sensor
which is intrinsically high impedance. In these cases, a
capacitor can be used, either at the input or across the
feedback resistor, to limit the bandwidth of the closedloop system. Doing so will effectively filter out the clock
feedthrough signal.
100
SLOPE ≈ 1.5µV/°C
BELOW 25°C
50
0
64% SN/36% Pb
60% Cd/40% SN
SLOPE ≈ 160nV/°C
BELOW 25°C
–50
–100
10
30
0
40
50
20
SOLDER-COPPER JUNCTION DIFFERENTIAL TEMPERATURE
SOURCE: NEW ELECTRONICS 02-06-77
2066 F03
Figure 3. Solder-Copper Thermal EMFs
Leakage Effects
Leakage currents into high impedance signal nodes can
easily degrade measurement accuracy of sub-nanoamp
signals. High voltage and high temperature applications
are especially susceptible to these issues. Quality insulation materials should be used, and insulating surfaces
should be cleaned to remove fluxes and other residues.
For humid environments, surface coating may be necessary to provide a moisture barrier.
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
APPLICATIONS INFORMATION
HEAT SOURCE/
POWER DISSIPATOR
RG**
+–
VIN
THERMAL
GRADIENT
+IN
OUT
LTC2066
†
NC
‡
VTHERMAL
RL§
–IN
RG
+–
VTHERMAL
RF§
RELAY
**
#
RF
MATCHING RELAY
#
*
2066 F04
* CUT SLOTS IN PCB FOR THERMAL ISOLATION.
** INTRODUCE DUMMY JUNCTIONS AND COMPONENTS TO OFFSET UNAVOIDABLE JUNCTIONS OR CANCEL THERMAL EMFs.
† ALIGN INPUTS SYMMETRICALLY WITH RESPECT TO THERMAL GRADIENTS.
‡ INTRODUCE DUMMY TRACES AND COMPONENTS FOR SYMMETRICAL THERMAL HEAT SINKING.
§ LOADS AND FEEDBACK CAN DISSIPATE POWER AND GENERATE THERMAL GRADIENTS. BE AWARE OF THEIR THERMAL EFFECTS.
# COVER CIRCUIT TO PREVENT AIR CURRENTS FROM CREATING THERMAL GRADIENTS.
Figure 4. Techniques for Minimizing Thermocouple-Induced Errors
NO SOLDER MASK
OVER GUARD RING
GUARD
RING
LEAKAGE
CURRENT
VBIAS
‡
–IN
HIGH-Z
SENSOR
RF
+IN
V–
§
V+
V–
OUT
VOUT
V+
‡ NO LEAKAGE CURRENT, V–IN = V+IN
§ AVOID DISSIPATING SIGNIFICANT AMOUNTS OF POWER IN THIS RESISTOR.
IT WILL GENERATE THERMAL GRADIENTS WITH RESPECT TO THE INPUT
PINS AND LEAD TO THERMOCOUPLE-INDUCED ERROR. THERMALLY
ISOLATE OR ALIGN WITH INPUTS IF RESISTOR WILL CAUSE HEATING.
GUARD RING
VBIAS
RF
HIGH-Z SENSOR
VIN
–+
V+
RIN
–
LEAKAGE
CURRENT
LTC2066
VOUT
+
V–
LEAKAGE CURRENT IS ABSORBED BY GROUND INSTEAD OF
CAUSING A MEASUREMENT ERROR.
2066 F05
Figure 5. Example Layout of Inverting Amplifier with Leakage Guard Ring
Rev. B
For more information www.analog.com
17
LTC2066/LTC2067/LTC2068
APPLICATIONS INFORMATION
Board leakage can be minimized by encircling the input
connections with a guard ring operated at a potential very
close to that of the inputs. The ring must be tied to a low
impedance node. For inverting configurations, the guard
ring should be tied to the potential of the positive input
(+IN). For noninverting configurations, the guard ring
should be tied to the potential of the negative input (–IN).
In order for this technique to be effective, the guard ring
must not be covered by solder mask. Ringing both sides
of the printed circuit board may be required. See Figure 5
for an example of proper layout.
Shutdown Mode
The LTC2066 in the SC70 package, the LTC2067 in the
DFN package, and the LTC2068 in the QFN package feature a shutdown mode for low-power applications. In the
OFF state, each amplifier draws less than 170nA of supply current and the outputs present a high impedance to
external circuitry.
Shutdown operation is accomplished by tying SHDN
below VL. If the shutdown feature is not required, it
is recommended that SHDN be tied to V+. A current
source pulls the SHDN pin high to keep the amplifier in
the ON state when the pin is floated, however this may
not be reliable at elevated temperatures due to board
leakage (see SHDN Circuit Block Diagram, page 14).
For operation in noisy environments, a capacitor between
SHDN and V+ is recommended to prevent noise from
changing the shutdown state. When there is a danger of
SHDN being pulled beyond the supply rails, resistance
in series with the SHDN pin is recommended to limit the
resulting current.
In the worst case, there may not be enough supply current available to take the system up to nominal voltages.
In other cases, this transient power-up current will lead
to added power loss in duty-cycled applications.
A way to quantify the transient current loss is to integrate
the supply current during power-up to examine the total
charge loss. If there were no additional transient current,
the integrated supply current would appear as a smooth,
straight line with a slope equal to the DC supply current
of the part. Any deviation from a straight line indicates
additional transient current that is drawn from the supply.
The LTC2066/LTC2067/LTC2068 have been designed to
minimize this charge loss during power-up so that power
can be conserved in duty-cycled applications. Figure 6
shows the integrated supply current (i.e. charge) of the
LTC2066 during power-up. Likewise, Figure 7 shows the
charge loss due to enabling and disabling the part via
the SHDN pin.
V–
5V/DIV
VOUT
2V/DIV
QV+
10nC/DIV
500µs/DIV
Figure 6. LTC2066 Charge Loss During Power-Up
VSHDN
5V/DIV
Start-Up Characteristics
Micropower op amps are often not micropower during
start-up, which can cause problems when used on low
current supplies. Large transient currents can conduct
during power-up until the internal bias nodes settle to
their final values. A large amount of current can be drawn
from the supplies during this transient, which can sustain
for several milliseconds in the case of a micropower part.
18
2066 F06
1V/µs V– EDGE RATE
V+ = 5V
VOUT
2V/DIV
QV+
10nC/DIV
500µs/DIV
2066 F07
Figure 7. LTC2066 Charge Loss Due to
Enabling and Disabling via SHDN Pin
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
APPLICATIONS INFORMATION
There are benefits when the SHDN pin is used to disable
and enable the part in duty-cycled applications, rather
than powering down the external supply voltage (V+).
Powering up and powering down the external supply will
tend to waste charge due to charging and discharging the
external decoupling capacitors. For these power-cycled
applications, a relay or MOS device can be located after
the decoupling capacitors to alleviate this; however there
are drawbacks to this approach. The LTC2066 draws an
initial charge of approximately 3nC when powered up.
This recurring charge loss is unavoidable in power-cycled
applications. Additionally, if the supply ramp rate exceeds
0.4V/µs, an internal transient ESD clamp will trigger, conducting additional current from V+ to V–. This will waste
charge and can make insignificant any savings that may
have been expected by power-cycling the supply. Figure 8
shows the charge loss at power-up.
The shutdown pin can be used to overcome these limitations in duty-cycled applications. The typical charge loss
transitioning into and out of shutdown is only 2.3nC.
Since the supply is not transitioned, the external decoupling capacitors do not draw charge from the supply.
CHARGE CONSUMED TO
0.1% SETTLED POINT (nC)
100
10
Gas Sensor
This low power precision gas sensor circuit operates in
an oxygen level range of 0% to 30%, with a nominal output of 1V in normal atmospheric oxygen concentrations
(20.9%) when the gas sensor has been fully initialized.
Total active power consumption is less than 10.1μA on a
single rail supply.
Since this gas sensor produces 100μA in a normal oxygen environment and requires a 100Ω load resistor, the
resulting input signal is typically around 10mV. The
LTC2066’s rail-to-rail input means no additional DC level
shifting is necessary, all the way down to very low oxygen
concentrations.
Due to the extremely low input offset voltage of the
LTC2066, which is 1μV typically and 5μV maximum, it is
possible to gain up the mV-scale input signal substantially
without introducing significant error. In the configuration
shown in Figure 9, with a noninverting gain of 101V/V, the
worst-case input offset results in a maximum of 0.5mV
offset on the 1V output, or 0.05% error.
Although the 100kΩ resistor in series with the gas sensor does not strictly have the same precision requirement
as the 10MΩ and 100kΩ resistors that set the gain, it is
important to use a similar resistor at both input terminals.
This helps to minimize additional offset voltage at the inputs
due to thermocouple effects and bias current, hence the
similar 0.1% precision requirement.
10M
0.1%
1
0.1
1
SUPPLY EDGE RATE (V/µs)
2
OXYGEN SENSOR
CITY TECHNOLOGY
40XV
2066 F08
100k
0.1%
100k*
0.1%
100Ω
0.1%
Figure 8. LTC2066 Power-Up Charge vs Supply Edge Rate
www.citytech.com
1.8V
–
LTC2066
+
VOUT = 1V IN AIR
ISUPPLY = 7.5µA (ENABLED)
90nA (SHUTDOWN)
VSHDN
2066 F09
*RESISTOR CANCELS OUT PARASITIC SEEBECK EFFECT VOLTAGE
Figure 9. Micropower Precision Oxygen Sensor
Rev. B
For more information www.analog.com
19
LTC2066/LTC2067/LTC2068
APPLICATIONS INFORMATION
RTD Sensor
This low power platinum resistance temperature detector
(RTD) sensor circuit draws only 43μA total supply current on a minimum 2.6V rail, and is accurate to within
±1°C at room temperature, including all error intrinsic
to the Vishay PTS Class F0.3 Variant RTD. It covers the
temperature range from –40°C to 85°C in 10mV/°C increments and produces an output of 1V at nominal room
temperature of 25°C.
The LTC2066’s extremely low typical offset of 1μV and
typical input bias current of 5pA allows for the use of a
very low excitation current in the RTD. Thus, self-heating
is negligible, improving accuracy.
The LT5400-3, B-grade, is used to provide a ±0.025%
matched resistor network that is effectively a precision
131:1 voltage divider. This precision divider forms one
half of a bridge circuit, with the 0.1% 110kΩ and RTD in
the other branch. Note that the 110kΩ’s precision requirement is to ensure matching with the RTD. The 11kΩ R2
serves to provide a DC offset for the entire bridge so
IN
2.6V ≤ VSUPPLY ≤ 18V
+
–
C1
0.1µF
LT6656-2.048
GND
that the output is 1V at room temperature. Since bridge
imbalances can lead to error, it is recommended to minimize the length of the leads connecting the RTD to reduce
additional lead resistance.
The LT6656-2.048 reference helps create a known excitation current in the RTD at each temperature of operation,
and also acts as a supply for the LTC2066, all while using
less than 1μA itself. The LT6656 can accept input voltages
anywhere between 2.6V and 18V, allowing for flexibility
in selection of supply voltage while maintaining a fixed
output range. The LT6656 reference can easily source
the 43μA required to run the entire circuit, thanks to the
LTC2066’s 10μA maximum supply current and ability to
handle microvolt signals produced by the RTD under low
excitation current.
Care should be taken to minimize thermocouple effects by
preventing significant thermal gradients between the two
op amp inputs. It is also important to choose feedback
and series resistors that are low-tempco to minimize error
due to drift over the entire temperature range.
OUT
C2
10µF
VISHAY PTS SERIES
1kΩ PtRTD, CLASS F0.3
PTS12061B1K00P100
www.vishay.com
110k
0.1%
±2ppm/°C
VOUT SCALE 10mV/°C
1V AT 25°C ROOM TEMP
ISUPPLY = 43µA
100k
RTD
1k
10k
10k
R2
11k
100k
+
OUT
LTC2066
–
RFB
1.58M
2066 F10
LT5400-3
131:1 VOLTAGE DIVIDER
Figure 10. RTD Sensor
20
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
APPLICATIONS INFORMATION
VIN
4.5V TO 90V
RIN
49.9Ω
0.1%
ISENSE
100µA to 250mA
RSENSE
0.1Ω
C1
3.3µF
R1
49.9Ω
0.1%
REF
LT1389-4.096
C2
10µF
–
D1
1N4148
LOAD
BSP322P
M1
LTC2066
+
C3
100nF
C4
22µF
BSP322P
M2
R3
499k
VOUT = 10 • ISENSE
1mV TO 2.5V
ROUT
4.99k
0.1%
2066 F11
Figure 11. High Side Current Sense
90V High Side Current Sense
This micropower precision LTC2066 high side current
sense circuit measures currents from 100μA to 250mA
over a 4.5V to 90V input voltage range.
The output of this circuit is:
R
•R
VOUT = OUT SENSE ISENSE = 10 •ISENSE
RIN
The LTC2066’s low typical input offset voltage of 1μV and
low input bias current of 5pA contribute output errors
that are much smaller than the error due to precision
limitations of the resistors used. Thus, output accuracy
is mainly set by the accuracy of the resistors RSENSE, RIN,
and ROUT. R1 helps cancel out parasitic Seebeck effect
voltages at –IN by balancing with an identical voltage
at +IN.
The LT1389-4.096 reference, along with the bootstrap
circuit composed of M2, R3, and D1, establishes a very
low power isolated 3V rail that protects the LTC2066 from
reaching its absolute maximum voltage of 5.5V while
allowing for much higher input voltages.
Since the LTC2066’s gain-bandwidth product is 100kHz,
it is recommended to use this circuit to measure currents
that do not change faster than 10kHz. Note that the output
filter as drawn will limit the frequency to 1.5Hz, which
optimizes for lowest noise. If this output filter bandwidth
is too narrow, removing C4 leads to an output filter with
318Hz bandwidth, created by C3 and ROUT.
Rev. B
For more information www.analog.com
21
LTC2066/LTC2067/LTC2068
APPLICATIONS INFORMATION
Parallel LTC2067 Amplifiers to Reduce Noise by √2
R2
909k
R1
100k
1.5V
–
1/2 LTC2067
+
R3
100Ω
–1.5V
IN
OUT
1.5V
R4
100Ω
+
R5
100k
1/2 LTC2067
–
–1.5V
R6
909k
2066 F12
Precision, Micropower Carbon Monoxide Detector
C2
100nF
R3
35.7k
4CM CARBON MONOXIDE SENSOR
CITY TECHNOLOGY
70nA/ppm CO TYP
2.5V
–
2.5V
R1
402k
R2
100k
1/2 LTC2067
+
C1
100nF
4CM COUNTER ELECTRODE (CE)
SELF-BIASES BELOW WE POTENTIAL
VWE – VCE = –0.3V TO –0.4V TYP
CE
2.5V
RE
4CM
WE
J1
MMBFJ270
RBURDEN
5Ω
2.5V
R6
402k
R7
100k
TYPICAL GAIN:
2.5mV/ppm CO
C4
100nF
R4
1M
INPUT RANGE:
0ppm TO 500ppm CO
R5
35.7k
OUTPUT:
1.7V (TYP)
2.0V (MAX) AT 500ppm CO
2.5V
–
1/2 LTC2067
R8
100k
OUT
C5
10µF
+
C3
100nF
2066 F13
22
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
PACKAGE DESCRIPTION
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638 Rev B)
0.47
MAX
0.65
REF
1.80 – 2.20
(NOTE 4)
1.00 REF
INDEX AREA
(NOTE 6)
1.80 – 2.40 1.15 – 1.35
(NOTE 4)
2.8 BSC 1.8 REF
PIN 1
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.10 – 0.40
0.65 BSC
0.15 – 0.30
6 PLCS (NOTE 3)
0.80 – 1.00
1.00 MAX
0.00 – 0.10
REF
GAUGE PLANE
0.15 BSC
0.26 – 0.46
0.10 – 0.18
(NOTE 3)
SC6 SC70 1205 REV B
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB
Rev. B
For more information www.analog.com
23
LTC2066/LTC2067/LTC2068
PACKAGE DESCRIPTION
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635 Rev B)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
1.4 MIN
3.85 MAX 2.62 REF
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
24
0.01 – 0.10
1.00 MAX
DATUM ‘A’
1.90 BSC
S5 TSOT-23 0302 REV B
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev G)
0.889 ±0.127
(.035 ±.005)
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ±.0015)
TYP
8
7 6 5
0.52
(.0205)
REF
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1
2 3
4
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS8) 0213 REV G
Rev. B
For more information www.analog.com
25
LTC2066/LTC2067/LTC2068
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
R = 0.125
TYP
6
0.40 ±0.10
10
1.65 ±0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
5
0.75 ±0.05
0.00 – 0.05
1
(DD) DFN REV C 0310
0.25 ±0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
26
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1782 Rev Ø)
Exposed Pad Variation BB
BOTTOM VIEW—EXPOSED PAD
3.00 ±0.10
(4 SIDES)
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ±0.05
15
16
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
1.60 ±0.10
(4-SIDES)
(UD16 VAR BB) QFN 0119 REV Ø
0.25 ±0.05
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-4)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. NiPdAu PPF TERMINAL FINISH
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.50 BSC
0.70 ±0.05
3.50 ±0.05
1.60 ±0.05
2.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
Rev. B
For more information www.analog.com
27
LTC2066/LTC2067/LTC2068
PACKAGE DESCRIPTION
F Package
14-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1650)
4.90 – 5.10*
(.193 – .201)
14 13 12 11 10 9 8
1.05 ±0.10
6.60 ±0.10
6.40
(.252)
BSC
4.50 ±0.10
0.45 ±0.05
0.65 BSC
1 2 3 4 5 6 7
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50**
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
1.10
(.0433)
MAX
0° – 8°
0.65
(.0256)
BSC
0.19 – 0.30
(.0075 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
F14 TSSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
28
Rev. B
For more information www.analog.com
LTC2066/LTC2067/LTC2068
REVISION HISTORY
REV
DATE
DESCRIPTION
A
07/18
Adding LTC2067 to data sheet
PAGE NUMBER
All Pages
B
06/20
Added LTC2068 to data sheet
All Pages
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
29
LTC2066/LTC2067/LTC2068
TYPICAL APPLICATION
Battery Powered Current Sense Amplifier Floats with Sense Resistor Voltage
IN
BAT
>3.1V
12V
LT6656-3
OUT
10µF
2M
2M
10µF
2M
14k
ILOAD CURRENT
TO BE MEASURED
(BI-DIRECTIONAL)
RSENSE
10mΩ
2M
VREF
+
LTC2066
14k
–
VOUT = VREF/2 ±ILOAD × RSENSE × GAIN
GAIN = 2M/14k
2M
2066 TA03
0.1% RESISTORS TO MAINTAIN OFFSET ACCURACY
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
ADA4051-1/ADA4051-2
Micropower, Single/Dual, Zero-Drift Operational Amplifiers
7μA IS, 15μV VOS, 11.8V to 5.5V VS, 115kHz, RRIO
LTC2063/LTC2064/
LTC2065
Micropower, Low IB Single/Dual/Quad, Zero-Drift Op Amps
2μA IS, 5μV VOS, 1.7V to 5.25V VS, 20kHz, RRIO
LTC2054/LTC2055
Micropower, Single/Dual, Zero-Drift Operational Amplifier
130μA IS, 5μV VOS, 2.7V to 11 V VS, 500kHz, RR Output
ADA4522-1/ADA4522-2/ 55V, Low Noise Zero-Drift Operational Amplifier
ADA4522-4
900μA IS, 5.8nV/�Hz, 5μV VOS, 4.5V to 55V VS, 3MHz, RR Output
LTC2057/LTC2057HV
High Voltage-Low Noise Zero-Drift Operational Amplifier
4μV VOS, 1.2mA IS, 4.75V to 60V VS, 1.5MHz, RR Output
LTC2058
36V, Low Noise Zero-Drift Operational Amplifier
5μV VOS, 1.2mA IS, 4.75V to 36V VS, 2.5MHz, RR Output
LTC2050/LTC2050HV
Zero-Drift Operational Amplifier
3μV VOS, 1.5mA IS, 2.7V to 12V VS, 3MHz, RR Output
LTC2051/LTC2052
Dual/Quad Zero-Drift Operational Amplifier
3μV VOS, 1.5mA IS, 2.7V to 12V VS, 3MHz, RR Output
ADA4528-1/ADA4528-2
5V Ultra Low Noise Zero-Drift Op Amps
5μV VOS, 5.6nV/√Hz, 1.7mA IS, 2.2V to 5.5V VS, 4MHz, RRIO
LT®1494/LT1495/
LT1496
1.5μA Max, Over-The-Top Precision Operational Amplifier
1.5μA IS, 375μV VOS, 2.2V to 36V VS, 2.7kHz, RRIO
LT6003/LT6004/LT6005 1.6V, 1μA Precision Rail-to-Rail Input and Output Op Amps 1μA IS, 500μV VOS, 1.6V to 16V VS, 2kHz, RRIO
LT6023
Micropower, Enhanced Slew Op Amp
20μA IS, 20μV VOS, 3V to 30V VS, 40kHz
LTC2053
Precision, Rail-to-Rail, Zero-Drift, PGIA
1.3mA IS, 10μV VOS, 2.7V to 12V VS, 200kHz, RRIO
LT5400
Quad Matched Resistor Network
0.01% Matching, 8ppm/°C Temp Drift , 0.2ppm/°C Temp Matching
30
Rev. B
D16885-0-6/20
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