LTC2224IUK#PBF

LTC2224 12-Bit, 135Msps ADC U FEATURES DESCRIPTIO ■ The LTC®2224 is a 135Msps, sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2224 is perfect for demanding communications applications with AC performance that includes 67.3dB SNR and 80dB spurious free dynamic range for signals up to 150MHz. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Sample Rate: 135Msps 67.3dB SNR up to 140MHz Input 80dB SFDR up to 150MHz Input 775MHz Full Power Bandwidth S/H Single 3.3V Supply Low Power Dissipation: 630mW CMOS Outputs Selectable Input Ranges: ±0.5V or ±1V No Missing Codes Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Data Ready Output Clock Pin Compatible Family 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) 48-Pin 7mm × 7mm QFN Package U APPLICATIO S ■ ■ ■ ■ Wireless and Wired Broadband Communication Cable Head-End Systems Power Amplifier Linearization Communications Test Equipment DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.5LSBRMS. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC – inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U TYPICAL APPLICATIO 3.3V VDD REFL FLEXIBLE REFERENCE + ANALOG INPUT INPUT S/H – 12-BIT PIPELINED ADC CORE CORRECTION LOGIC 0.5V TO 3.6V 90 OVDD 85 D11 • • • D0 OUTPUT DRIVERS 4th OR HIGHER SFDR (dBFS) REFH SFDR vs Input Frequency 95 80 75 2nd OR 3rd 70 65 60 OGND CLOCK/DUTY CYCLE CONTROL 50 0 2224 TA01 ENCODE INPUT 55 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 2224 TA01b 2224fa 1 LTC2224 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO OVDD = VDD (Notes 1, 2) TOP VIEW 48 GND 47 VDD 46 VDD 45 GND 44 VCM 43 SENSE 42 MODE 41 OF 40 D11 39 D10 38 OGND 37 OVDD Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ............... –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2224C ............................................... 0°C to 70°C LTC2224I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C AIN+ 1 AIN– 2 REFHA 3 REFHA 4 REFLB 5 REFLB 6 REFHB 7 REFHB 8 REFLA 9 REFLA 10 VDD 11 VDD 12 36 D9 35 D8 34 D7 33 OVDD 32 OGND 31 D6 30 D5 29 D4 28 OVDD 27 OGND 26 D3 25 D2 GND 13 VDD 14 GND 15 ENC + 16 ENC – 17 SHDN 18 OE 19 CLOCKOUT 20 DO 21 OGND 22 OVDD 23 D1 24 49 UK PACKAGE 48-LEAD (7mm × 7mm) PLASTIC QFN EXPOSED PAD IS GND (PIN 49), MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 29°C/W ORDER PART NUMBER LTC2224CUK LTC2224IUK UK PART* MARKING LTC2224UK LTC2224UK Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. U CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS ● 12 Integral Linearity Error Differential Analog Input (Note 5) ● –1 ±0.4 1 LSB Differential Linearity Error Differential Analog Input ● –1 ±0.3 1 LSB Integral Linearity Error Single-Ended Analog Input (Note 5) Differential Linearity Error Single-Ended Analog Input Offset Error (Note 6) ● –35 ±3 35 Gain Error External Reference ● –2.5 ±0.5 2.5 Resolution (No Missing Codes) Offset Drift Bits ±1 LSB ±0.3 LSB mV %FS ±10 µV/C Full-Scale Drift Internal Reference External Reference ±30 ±15 ppm/C ppm/C Transition Noise SENSE = 1V 0.5 LSBRMS 2224fa 2 LTC2224 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ – AIN–) 3.1V < VDD < 3.5V ● VIN, CM Analog Input Common Mode (AIN+ Differential Input Single Ended Input (Note 7) ● ● 1 0.5 IIN Analog Input Leakage Current 0 < AIN+, AIN– < VDD ● ISENSE SENSE Input Leakage 0V < SENSE < 1V ● IMODE MODE Pin Pull-Down Current to GND 10 µA tAP Sample and Hold Acquisition Delay Time 0 ns tJITTER Sample and Hold Acquisition Delay Time Jitter CMRR + AIN–)/2 MIN MAX UNITS 1.6 1.6 V 1.9 2.1 V V –1 1 µA –1 1 µA 0.15 Analog Input Common Mode Rejection Ratio Full Power Bandwidth TYP ±0.5 to ±1 Figure 8 Test Circuit psRMS 80 dB 775 MHz W U DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 30MHz Input (1V Range) 30MHz Input (2V Range) SFDR SFDR S/(N+D) Spurious Free Dynamic Range Spurious Free Dynamic Range 4th Harmonic or Higher Signal-to-Noise Plus Distortion Ratio MIN TYP 66.5 62.8 67.6 dB dB 70MHz Input (1V Range) 70MHz Input (2V Range) 62.8 67.6 dB dB 140MHz Input (1V Range) 140MHz Input (2V Range) 62.5 67.3 dB dB 250MHz Input (1V Range) 250MHz Input (2V Range) 61.8 65.9 dB dB 84 84 dB dB 70MHz Input (1V Range) 70MHz Input (2V Range) 84 84 dB dB 140MHz Input (1V Range) 140MHz Input (2V Range) 84 84 dB dB 250MHz Input (1V Range) 250MHz Input (2V Range) 77 77 dB dB 30MHz Input (1V Range) 30MHz Input (2V Range) 90 90 dB dB 70MHz Input (1V Range) 70MHz Input (2V Range) 90 90 dB dB 140MHz Input (1V Range) 140MHz Input (2V Range) 90 90 dB dB 250MHz Input (1V Range) 250MHz Input (2V Range) 90 90 dB dB 62.8 67.4 dB dB 62.8 67.2 dB dB 81 dBc 30MHz Input (1V Range) 30MHz Input (2V Range) 30MHz Input (1V Range) 30MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) IMD Intermodulation Distortion fIN1 = 138MHz, fIN2 = 140MHz ● ● ● 72 66 MAX UNITS 2224fa 3 LTC2224 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX VCM Output Voltage IOUT = 0 1.575 1.600 1.625 ±25 VCM Output Tempco UNITS V ppm/°C VCM Line Regulation 3.1V < VDD < 3.5V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 2.5 V V ENCODE INPUTS (ENC +, ENC –) VID Differential Input Voltage VICM Common Mode Input Voltage RIN Input Resistance CIN Input Capacitance ● Internally Set Externally Set (Note 7) ● 0.2 1.1 (Note 7) V 1.6 1.6 6 kΩ 3 pF LOGIC INPUTS (OE, SHDN) VIH High Level Input Voltage VDD = 3.3V ● VIL Low Level Input Voltage VDD = 3.3V ● IIN Input Current VIN = 0V to VDD ● CIN Input Capacitance (Note 7) 2 V –10 0.8 V 10 µA 3 pF LOGIC OUTPUTS OVDD = 3.3V COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF ISOURCE Output Source Current VOUT = 0V 50 mA ISINK Output Sink Current VOUT = 3.3V 50 mA VOH High Level Output Voltage IO = –10µA IO = –200µA ● IO = 10µA IO = 1.6mA ● VOL Low Level Output Voltage 3.1 3.295 3.29 0.005 0.09 V V 0.4 V V OVDD = 2.5V VOH High Level Output Voltage IO = –200µA 2.49 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V VOH High Level Output Voltage IO = –200µA 1.79 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V OVDD = 1.8V 2224fa 4 LTC2224 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) SYMBOL PARAMETER VDD Analog Supply Voltage OVDD IVDD CONDITIONS MIN TYP MAX UNITS ● 3.1 3.3 3.5 V Output Supply Voltage ● 0.5 3.3 3.6 V Analog Supply Current ● 191 206 mA PDISS Power Dissipation ● 630 680 mW PSHDN Shutdown Power SHDN = High, OE = High, No CLK 2 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 35 mW WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fS Sampling Frequency ● 1 tL ENC Low Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On ● ● 135 MHz 3.5 2 3.7 3.7 500 500 ns ns tH ENC High Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On ● ● 3.5 2 3.7 3.7 500 500 ns ns tAP Sample-and-Hold Aperture Delay tOE Output Enable Delay (Note 7) ● 5 10 ns tD ENC to DATA Delay (Note 7) ● 1.3 2.1 3.5 ns tC ENC to CLOCKOUT Delay (Note 7) ● 1.3 2.1 3.5 ns DATA to CLOCKOUT Skew (tC - tD) (Note 7) ● –0.6 0 0.6 0 Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. 5 ns ns Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a “best straight line” fit to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF. 2224fa 5 LTC2224 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2224: Shorted Input Noise Histogram LTC2224: DNL, 2V Range 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0 –0.2 100000 0.2 0 –0.4 –0.6 –0.6 –0.8 –0.8 60000 40000 –0.2 –0.4 29529 21767 20000 –1.0 –1.0 0 2048 1024 3072 4096 79331 80000 COUNT ERROR (LSB) ERROR (LSB) LTC2224: INL, 2V Range 2048 1024 OUTPUT CODE 3072 2057 4096 OUTPUT CODE 2224 G01 322 123 0 0 2058 2059 2060 2061 CODE 2224 G02 2224 G03 LTC2224: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 2V Range LTC2224: SNR vs Input Frequency, –1dB, 1V Range LTC2224: SNR vs Input Frequency, –1dB, 2V Range 69 69 67 67 65 65 95 90 63 61 SFDR (dBFS) SNR (dBFS) SNR (dBFS) 85 63 61 59 59 57 57 80 75 70 65 60 55 55 55 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 50 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 2224 G04 0 90 90 90 85 85 85 80 80 80 SFDR (dBFS) 95 SFDR (dBFS) 95 75 70 75 70 65 65 65 60 60 60 55 55 55 50 50 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 2224 G07 600 LTC2224: SFDR (HD4+) vs Input Frequency, –1dB, 1V Range 95 70 200 300 400 500 INPUT FREQUENCY (MHz) 2224 G06 LTC2224: SFDR (HD4+) vs Input Frequency, –1dB, 2V Range 75 100 2224 G05 LTC2224: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 1V Range SFDR (dBFS) 600 50 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 2224 G08 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 2224 G09 2224fa 6 LTC2224 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2224: SFDR and SNR vs Sample Rate, 1V Range, fIN = 30MHz, –1dB LTC2224: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 100 100 220 95 95 210 SFDR 85 80 75 70 SNR 65 90 80 75 40 60 80 100 120 140 160 SAMPLE RATE (Msps) 150 0 20 40 60 80 100 120 140 160 SAMPLE RATE (Msps) 2224 G10 0 20 40 60 80 100 120 140 160 180 SAMPLE RATE (Msps) 2224 G12 2224 G11 LTC2224: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V LTC2224: SFDR vs Input Level, f IN = 70MHz, 2V Range 20 100 90 dBFS 80 SFDR (dBc AND dBFS) 20 1V RANGE 180 160 SNR 60 0 2V RANGE 190 170 70 65 60 200 SFDR 85 IVDD (mA) SFDR AND SNR (dBFS) 90 IOVDD (mA) SFDR AND SNR (dBFS) LTC2224: SFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, –1dB 10 70 60 dBc 50 40 30 20 10 0 0 20 40 60 80 100 120 140 160 180 SAMPLE RATE (Msps) 2224 G13 0 – 60 – 50 –30 –20 –40 INPUT LEVELS (dBFS) –10 0 2224 G14 2224fa 7 LTC2224 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2224: 8192 Point FFT, f IN = 30MHz, –1dB, 1V Range 0 0 – 10 – 10 – 20 – 20 – 20 – 30 – 30 – 30 – 40 – 40 – 40 – 50 – 60 – 70 – 80 – 50 – 60 – 70 – 80 – 50 – 60 – 70 – 80 – 90 – 90 – 90 – 100 – 100 – 100 – 110 – 110 – 110 – 120 – 120 – 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 0 5 10 15 20 25 30 35 40 45 50 55 60 65 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 2224 G15 2224 G16 LTC2224: 8192 Point FFT, f IN = 140MHz, –1dB, 2V Range 0 0 – 10 – 10 – 20 – 20 – 20 – 30 – 30 – 30 – 40 – 40 – 40 – 60 – 70 – 80 AMPLITUDE (dB) 0 – 50 – 50 – 60 – 70 – 80 – 50 – 60 – 70 – 80 – 90 – 90 – 90 – 100 – 100 – 100 – 110 – 110 – 110 – 120 – 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) FREQUENCY (MHz) 2224 G18 – 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) 2224 G19 LTC2224: 8192 Point FFT, f IN = 250MHz, –1dB, 1V Range LTC2224: 8192 Point FFT, f IN = 250MHz, –1dB, 2V Range 0 – 10 – 20 – 20 – 20 – 30 – 30 – 30 – 40 – 40 – 40 – 60 – 70 – 80 AMPLITUDE (dB) 0 – 10 AMPLITUDE (dB) 0 – 50 – 60 – 70 – 80 2224 G20 LTC2224: 8192 Point FFT, f IN = 500MHz, –6dB, 1V Range – 10 – 50 2224 G17 LTC2224: 8192 Point FFT, f IN = 140MHz, –1dB, 1V Range – 10 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 0 LTC2224: 8192 Point FFT, f IN = 70MHz, –1dB, 1V Range AMPLITUDE (dB) LTC2224: 8192 Point FFT, f IN = 70MHz, –1dB, 2V Range – 10 AMPLITUDE (dB) AMPLITUDE (dB) LTC2224: 8192 Point FFT, f IN = 30MHz, –1dB, 2V Range – 50 – 60 – 70 – 80 – 90 – 90 – 90 – 100 – 100 – 100 – 110 – 110 – 110 – 120 – 120 – 120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 0 5 10 15 20 25 30 35 40 45 50 55 60 65 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 2224 G21 2224 G22 2224 G23 2224fa 8 LTC2224 U U U PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. AIN– (Pin 2): Negative Differential Analog Input. OE (Pin 19): Output Enable Pin. Refer to SHDN pin function. REFHA (Pins 3, 4): ADC High Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor, to Pins 9, 10 with a 2.2µF ceramic capacitor and to ground with a 1µF ceramic capacitor. CLOCKOUT (Pin 20): Data Valid Output. Latch data on the falling edge of CLOCKOUT. REFLB (Pins 5, 6): ADC Low Reference. Bypass to Pins 3, 4 with 0.1µF ceramic chip capacitor. Do not connect to Pins 9, 10. OGND (Pins 22, 27, 32, 38): Output Driver Ground. REFHB (Pins 7, 8): ADC High Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor. Do not connect to Pins 3, 4. REFLA (Pins 9, 10): ADC Low Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 3, 4 with a 2.2µF ceramic capacitor and to ground with a 1µF ceramic capacitor. VDD (Pins 11, 12, 14, 46, 47): 3.3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. Adjacent pins can share a bypass capacitor. GND (Pins 13, 15, 45, 48): ADC Power Ground. ENC + (Pin 16): Encode Input. The input is sampled on the positive edge. ENC – (Pin 17): Encode Complement Input. The input is sampled on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended ENCODE signal. SHDN (Pin 18): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. D0 – D11 (Pins 21, 24, 25, 26, 29, 30, 31, 34, 35, 36, 39, 40): Digital Outputs. D11 is the MSB. OVDD (Pins 23, 28, 33, 37): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitors. OF (Pin 41): Over/Under Flow Output. High when an over or under flow has occurred. MODE (Pin 42): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 43): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 44): 1.6V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Exposed Pad (Pin 49): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. 2224fa 9 LTC2224 W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE 1.6V REFERENCE 2.2µF SHIFT REGISTER AND CORRECTION RANGE SELECT REFH SENSE FIFTH PIPELINED ADC STAGE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER DIFF REF AMP CONTROL LOGIC • • • OUTPUT DRIVERS D11 D0 CLOCKOUT REFLB REFHA 2.2µF 0.1µF 1µF 2224 F01 REFLA REFHB OGND + ENC – ENC M0DE SHDN OE 0.1µF 1µF Figure 1. Functional Block Diagram 2224fa 10 LTC2224 W UW TI I G DIAGRA S Timing Diagram tAP ANALOG INPUT N+4 N+2 N N+3 tH N+1 tL ENC – ENC + tD N–5 D0-D11, OF N–4 N–3 N–2 N–1 tC 2224 TD01 CLOCKOUT OE t OE DATA t OE OF, D0-D11, CLOCKOUT 2224fa 11 LTC2224 U W U U APPLICATIO S I FOR ATIO The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Signal-to-Noise Ratio Spurious Free Dynamic Range (SFDR) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. Full Power Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) 2224fa 12 LTC2224 U W U U APPLICATIO S I FOR ATIO CONVERTER OPERATION As shown in Figure 1, the LTC2224 is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The encode input is differential for improved common mode noise immunity. The LTC2224 has two phases of operation, determined by the state of the differential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. stage residue that is sent to the fifth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2224 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. LTC2224 VDD AIN+ CSAMPLE 1.6pF 15Ω CPARASITIC 1pF VDD When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth AIN– CSAMPLE 1.6pF 15Ω CPARASITIC 1pF VDD 1.6V 6k ENC+ ENC– 6k 1.6V 2224 F02 Figure 2. Equivalent Input Circuit 2224fa 13 LTC2224 U W U U APPLICATIO S I FOR ATIO During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.6V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.6V. The VCM output pin (Pin 44) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2224 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC, the sampleand-hold circuit will connect the 1.6pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2224 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω AIN+ LTC2224 0.1µF 12pF 25Ω 25Ω T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 2224 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer 2224fa 14 LTC2224 U W U U APPLICATIO S I FOR ATIO signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. For input frequencies above 100MHz the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.6V. In Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. Figure 9 shows the LTC2224 reference circuitry consisting of a 1.6V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; typing the SENSE pin to VCM selects the 1V range. Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss. Reference Operation The 1.6V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.6V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. VCM VCM HIGH SPEED DIFFERENTIAL AMPLIFIER 25Ω ANALOG INPUT + 2.2µF AIN+ LTC2224 ANALOG INPUT 2.2µF 1k 25Ω 12pF – AIN+ LTC2224 3pF + CM – 1k 0.1µF 12pF 25Ω LTC6600-20 OR LT1993 3pF 25Ω AIN– 2224 F04 Figure 4. Differential Drive with an Amplifier 0.1µF AIN– 2224 F05 Figure 5. Single-Ended Drive 2224fa 15 LTC2224 U W U U APPLICATIO S I FOR ATIO and REFLB for the low reference. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. VCM 2.2µF 0.1µF AIN+ 12Ω ANALOG INPUT 25Ω T1 0.1µF LTC2224 0.1µF 8pF 25Ω 12Ω AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 2224 F06 Figure 6. Recommended Front End Circuit for Input Frequencies Between 100MHz and 250MHz Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. VCM LTC2224 2.2µF 0.1µF AIN+ ANALOG INPUT 25Ω LTC2224 4Ω VCM 1.6V 1.6V BANDGAP REFERENCE 2.2µF 0.1µF 1V 0.5V T1 0.1µF 25Ω RANGE DETECT AND CONTROL AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 2224 F07 Figure 7. Recommended Front End Circuit for Input Frequencies Between 250MHz and 500MHz TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V SENSE REFLB BUFFER INTERNAL ADC HIGH REFERENCE 0.1µF REFHA 1µF VCM 2.2µF DIFF AMP 2.2µF 0.1µF 25Ω 1µF LTC2224 REFLA 0.1µF T1 0.1µF AIN+ 4.7nH ANALOG INPUT 0.1µF 2pF 25Ω INTERNAL ADC LOW REFERENCE REFHB 4.7nH 2224 F09 AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE 2224 F08 Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz Figure 9. Equivalent Reference Circuit 1.6V VCM 2.2µF 12k The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has four pins: two each of REFHA and REFHB for the high reference and two each of REFLA 0.8V 12k SENSE LTC2224 1µF 2224 F10 Figure 10. 1.6V Range ADC 2224fa 16 LTC2224 U W U U APPLICATIO S I FOR ATIO Input Range 1. Differential drive should be used. The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5dB. See the Typical Performance Characteristics section. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. Driving the Encode Inputs The noise performance of the LTC2224 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration: VDD LTC2224 TO INTERNAL ADC CIRCUITS VDD 1.6V BIAS 6k ENC+ 0.1µF 1:4 CLOCK INPUT VDD 50Ω 1.6V BIAS 6k ENC– 2224 F11 Figure 11. Transformer Driven ENC+/ENC– 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.1V to 2.5V. Each input may be driven from ground to VDD for single-ended drive. Maximum and Minimum Encode Rates The maximum encode rate for the LTC2224 is 135Msps. For the ADC to operate properly, the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 3.5ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2224 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2224 is 1Msps. 2224fa 17 LTC2224 U W U U APPLICATIO S I FOR ATIO DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits and the overflow bit. Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) OF D11 – D0 (Offset Binary) D11 – D0 (2’s Complement) >+1.000000V +0.999512V +0.999024V 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 0111 1111 1111 0111 1111 1110 +0.000488V 0.000000V –0.000488V –0.000976V 0 0 0 0 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 –0.999512V –1.000000V