LTC2249CUH#PBF

LTC2249 14-Bit, 80Msps Low Power 3V ADC U FEATURES DESCRIPTIO ■ The LTC®2249 is a 14-bit 80Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2249 is perfect for demanding imaging and communications applications with AC performance that includes 73dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Sample Rate: 80Msps Single 3V Supply (2.7V to 3.4V) Low Power: 222mW 73dB SNR at 70MHz Input 90dB SFDR at 70MHz Input No Missing Codes Flexible Input: 1VP-P to 2VP-P Range 575MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit) 105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit) 80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit) 65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit) 40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit) 25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit) 10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit) 32-Pin (5mm × 5mm) QFN Package DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U APPLICATIO S ■ ■ ■ ■ ■ Wireless and Wired Broadband Communication Imaging Systems Ultrasound Spectral Analysis Portable Instrumentation U TYPICAL APPLICATIO REFH REFL SNR vs Input Frequency, –1dB, 2V Range 75 FLEXIBLE REFERENCE 74 73 OVDD INPUT S/H – 14-BIT PIPELINED ADC CORE CORRECTION LOGIC D13 • • • D0 OUTPUT DRIVERS OGND SNR (dBFS) + ANALOG INPUT 72 71 70 69 68 67 CLOCK/DUTY CYCLE CONTROL 66 65 0 2229 TA01 CLK 100 50 150 INPUT FREQUENCY (MHz) 200 2249 G09 2249fa 1 LTC2249 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2249C ............................................... 0°C to 70°C LTC2249I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C D11 D12 D13 OF MODE SENSE VCM VDD TOP VIEW 32 31 30 29 28 27 26 25 AIN+ 1 24 D10 AIN– 2 23 D9 REFH 3 22 D8 REFH 4 21 OVDD 33 REFL 5 20 OGND REFL 6 19 D7 VDD 7 18 D6 GND 8 17 D5 D4 D3 D2 D1 D0 OE CLK SHDN 9 10 11 12 13 14 15 16 UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD IS GND (PIN 33) MUST BE SOLDERED TO PCB QFN PART MARKING* 2249 ORDER PART NUMBER LTC2249CUH LTC2249IUH Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. U CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS ● 14 Integral Linearity Error Differential Analog Input (Note 5) ● –4 ±1 4 LSB Differential Linearity Error Differential Analog Input ● –1 ±0.5 1 LSB Offset Error (Note 6) ● –12 ±2 12 mV Gain Error External Reference ● –2.5 ±0.5 2.5 %FS Resolution (No Missing Codes) Offset Drift Bits ±10 µV/°C Full-Scale Drift Internal Reference External Reference ±30 ±5 ppm/°C ppm/°C Transition Noise SENSE = 1V 1.2 LSBRMS 2249fa 2 LTC2249 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS +– AIN–) MIN TYP MAX UNITS ±0.5 to ±1 2.7V < VDD < 3.4V (Note 7) ● Differential Input (Note 7) Single Ended Input (Note 7) ● ● 1 0.5 Analog Input Leakage Current 0V < AIN+, AIN– < VDD ● ISENSE SENSE Input Leakage 0V < SENSE < 1V IMODE MODE Pin Leakage tAP Sample-and-Hold Acquisition Delay Time tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2 psRMS CMRR Analog Input Common Mode Rejection Ratio 80 dB VIN Analog Input Range (AIN VIN,CM Analog Input Common Mode (AIN+ IIN + AIN–)/2 1.5 1.5 V 1.9 2 V V –1 1 µA ● –3 3 µA ● –3 3 µA 0 ns W U DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER SNR Signal-to-Noise Ratio CONDITIONS MIN TYP 73 dB 70.8 73 dB 70MHz Input 73 dB 140MHz Input 72.6 dB 90 dB 90 dB 70MHz Input 90 dB 140MHz Input 85 dB 5MHz Input 95 dB 5MHz Input ● 40MHz Input SFDR SFDR S/(N+D) Spurious Free Dynamic Range 2nd or 3rd Harmonic Spurious Free Dynamic Range 4th Harmonic or Higher Signal-to-Noise Plus Distortion Ratio 5MHz Input ● 40MHz Input ● 40MHz Input 81 UNITS 95 dB 70MHz Input 95 dB 140MHz Input 90 dB 5MHz Input 72.9 dB 72.8 dB 70MHz Input 72.8 dB 140MHz Input ● 40MHz Input IMD 75 MAX 70.2 72.1 dB Intermodulation Distortion fIN1 = 28.2MHz, fIN2 = 26.8MHz 90 dB Full Power Bandwidth Figure 8 Test Circuit 575 MHz U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V ±25 VCM Output Tempco ppm/°C VCM Line Regulation 2.7V < VDD < 3.4V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω 2249fa 3 LTC2249 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS (CLK, OE, SHDN) VIH High Level Input Voltage VDD = 3V ● VIL Low Level Input Voltage VDD = 3V ● IIN Input Current VIN = 0V to VDD ● CIN Input Capacitance (Note 7) 2 V –10 0.8 V 10 µA 3 pF LOGIC OUTPUTS OVDD = 3V COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF ISOURCE Output Source Current VOUT = 0V 50 mA ISINK Output Sink Current VOUT = 3V 50 mA VOH High Level Output Voltage IO = –10µA IO = –200µA ● IO = 10µA IO = 1.6mA ● VOL Low Level Output Voltage 2.7 2.995 2.99 0.005 0.09 V V V V 0.4 OVDD = 2.5V VOH High Level Output Voltage IO = –200µA 2.49 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V VOH High Level Output Voltage IO = –200µA 1.79 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V OVDD = 1.8V U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Analog Supply Voltage (Note 9) ● 2.7 3 3.4 V OVDD Output Supply Voltage (Note 9) IVDD Supply Current ● ● 0.5 3 3.6 V 74 86 mA PDISS Power Dissipation ● 222 258 mW PSHDN Shutdown Power SHDN = H, OE = H, No CLK 2 mW PNAP Nap Mode Power SHDN = H, OE = L, No CLK 15 mW 2249fa 4 LTC2249 WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN fs Sampling Frequency (Note 9) ● 1 tL CLK Low Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 5.9 5 tH CLK High Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● tAP Sample-and-Hold Aperture Delay tD CLK to DATA Delay CL = 5pF (Note 7) ● Data Access Time After OE↓ CL = 5pF (Note 7) BUS Relinquish Time (Note 7) TYP MAX UNITS 80 MHz 6.25 6.25 500 500 ns ns 5.9 5 6.25 6.25 500 500 ns ns 1.4 2.7 5.4 ns ● 4.3 10 ns ● 3.3 8.5 0 Pipeline Latency ns 5 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 80MHz, input range = 2VP-P with differential drive, unless otherwise noted. ns Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 80MHz, input range = 1VP-P with differential drive. Note 9: Recommended operating conditions. U W TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range Typical DNL, 2V Range Typical INL, 2V Range 2.0 1.5 1.0 0 0.8 –10 –20 0.6 0.5 0 –0.5 –1.0 0.4 0.2 0 –0.2 –0.4 8192 12288 16384 CODE –120 0 4096 8192 12288 16384 CODE 2249 G01 –80 –110 –1.0 4096 –60 –70 –100 –0.8 0 –40 –50 –90 –0.6 –1.5 –2.0 –30 AMPLITUDE (dB) DNL ERROR (LSB) INL ERROR (LSB) 1.0 2249 G02 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 2249 G03 2249fa 5 LTC2249 U W TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range 0 0 0 –10 –10 –20 –20 –20 –30 –30 –30 –60 –70 –80 –40 AMPLITUDE (dB) –40 –50 –90 –50 –60 –70 –80 –90 –40 –50 –60 –70 –80 –90 –100 –100 –100 –110 –110 –110 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 –120 40 5 0 10 15 20 25 30 FREQUENCY (MHz) 35 2249 G04 0 50000 45000 –20 40000 –30 COUNT –80 15000 25292 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 69 66 1987 178 26 552 8203 70 67 6150 5194 8201 71 68 12558 5000 0 8205 8207 CODE 65 8209 2249 G09 SNR and SFDR vs Clock Duty Cycle SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 95 100 100 200 100 50 150 INPUT FREQUENCY (MHz) 0 2249 G08 2249 G07 SFDR vs Input Frequency, –1dB, 2V Range 40 72 10000 –110 35 73 35969 25000 20000 –100 15 20 25 30 FREQUENCY (MHz) 74 30000 –70 –90 10 75 43161 SNR (dBFS) –40 –60 5 SNR vs Input Frequency, –1dB, 2V Range 35000 –50 0 2249 G06 Grounded Input Histogram –10 –120 –120 40 2249 G05 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range AMPLITUDE (dB) 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range –10 AMPLITUDE (dB) AMPLITUDE (dB) 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range SFDR: DCS ON 95 90 SFDR (dBFS) 85 80 75 SNR AND SFDR (dBFS) SNR AND SFDR (dBFS) 90 90 SFDR 80 SNR 70 SFDR: DCS OFF 85 80 75 60 SNR: DCS ON 70 SNR: DCS OFF 65 0 50 100 150 INPUT FREQUENCY (MHz) 200 2249 G10 50 70 0 10 20 30 40 50 60 70 80 90 100 110 SAMPLE RATE (Msps) 2249 G11 30 35 40 45 50 55 60 CLOCK DUTY CYCLE (%) 65 70 2249 G12 2249fa 6 LTC2249 U W TYPICAL PERFOR A CE CHARACTERISTICS SNR vs Input Level, fIN = 70MHz, 2V Range 80 SFDR vs Input Level, fIN = 70MHz, 2V Range 120 dBFS 100 60 SFDR (dBc AND dBFS) SNR (dBc AND dBFS) 70 50 40 dBc 30 20 90 80 70 dBc 60 50 100dBc SFDR REFERENCE LINE 40 30 20 10 10 0 –70 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 –80 0 2249 G13 –40 –60 –20 INPUT LEVEL (dBFS) 0 2249 G14 IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 85 7 80 6 IOVDD (mA) IVDD (mA) dBFS 110 75 2V RANGE 70 1V RANGE 5 4 65 3 60 2 55 1 50 0 0 10 20 30 40 50 60 70 80 90 100 SAMPLE RATE (Msps) 2249 G15 0 10 20 30 40 50 60 70 80 90 100 SAMPLE RATE (Msps) 2249 G16 2249fa 7 LTC2249 U U U PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. AIN- (Pin 2): Negative Differential Analog Input. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pin 8): ADC Power Ground. CLK (Pin 9): Clock Input. The input sample starts on the positive edge. SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 11): Output Enable Pin. Refer to SHDN pin function. D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D13 is the MSB. OGND (Pin 20): Output Driver Ground. OVDD (Pin 21): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OF (Pin 28): Over/Under Flow Output. High when an over or under flow has occurred. MODE (Pin 29): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 30): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 31): 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad) (Pin 33): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. 2249fa 8 LTC2249 W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE 1.5V REFERENCE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D13 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 0.1µF 2249 F01 REFL OGND CLK MODE SHDN OE 2.2µF 1µF 1µF Figure 1. Functional Block Diagram 2249fa 9 LTC2249 WU W TI I G DIAGRA tAP ANALOG INPUT N+4 N+2 N N+3 tH N+5 N+1 tL CLK tD D0-D13, OF N–5 N–4 N–3 N–2 N–1 N 2249 TD01 2249fa 10 LTC2249 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Signal-to-Noise Ratio Spurious Free Dynamic Range (SFDR) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when CLK reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) 2249fa 11 LTC2249 U W U U APPLICATIO S I FOR ATIO CONVERTER OPERATION As shown in Figure 1, the LTC2249 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2249 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2249 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. LTC2249 VDD CSAMPLE 4pF 15Ω AIN+ CPARASITIC 1pF VDD AIN– CSAMPLE 4pF 15Ω CPARASITIC 1pF VDD CLK 2249 F02 Figure 2. Equivalent Input Circuit 2249fa 12 LTC2249 U W U U APPLICATIO S I FOR ATIO Single-Ended Input Input Drive Circuits For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.5V or VCM. Figure 3 shows the LTC2249 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin (Pin 31) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2249 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 AIN+ 25Ω LTC2249 25Ω 0.1µF 12pF 25Ω AIN– T1 = MA/COM ETC1-1T 25Ω RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 2249 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT + AIN+ LTC2249 + CM – 2.2µF 12pF – 25Ω AIN– 2249 F04 Figure 4. Differential Drive with an Amplifier 2249fa 13 LTC2249 U W U U APPLICATIO S I FOR ATIO Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth. Reference Operation Figure 9 shows the LTC2249 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. VCM VCM 1k 0.1µF 25Ω ANALOG INPUT 2.2µF 0.1µF 2.2µF 1k ANALOG INPUT AIN+ LTC2249 25Ω LTC2249 25Ω 2249 F05 LTC2249 VCM 2.2µF 12Ω ANALOG INPUT 1.5V AIN+ 4Ω 1.5V BANDGAP REFERENCE 1V 0.1µF T1 0.1µF VCM 2.2µF LTC2249 25Ω 2249 F08 Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz Figure 5. Single-Ended Drive 0.1µF AIN– 6.8nH T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE AIN– 0.1µF 0.1µF T1 0.1µF 12pF 25Ω AIN+ 6.8nH 0.5V 8pF 25Ω 12Ω AIN– T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE RANGE DETECT AND CONTROL 2249 F06 Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V SENSE BUFFER INTERNAL ADC HIGH REFERENCE 1µF VCM REFH 2.2µF 0.1µF AIN+ ANALOG INPUT LTC2249 25Ω 0.1µF 2.2µF 0.1µF DIFF AMP T1 0.1µF 25Ω T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 1µF AIN– REFL 2249 F07 INTERNAL ADC LOW REFERENCE Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz 2249 F09 Figure 9. Equivalent Reference Circuit 2249fa 14 LTC2249 U W U U APPLICATIO S I FOR ATIO The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5.7dB. Driving the Clock Input The CLK input can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low-jitter squaring circuit before the CLK pin (see Figure 11). The noise performance of the LTC2249 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source. CLEAN SUPPLY 4.7µF 1.5V FERRITE BEAD VCM 0.1µF 2.2µF 12k 0.75V 12k SENSE LTC2249 SINUSOIDAL CLOCK INPUT 0.1µF CLK 50Ω 1µF 2249 F10 Figure 10. 1.5V Range ADC 1k 1k LTC2249 NC7SVU04 2249 F11 Figure 11. Sinusoidal Single-Ended CLK Drive 2249fa 15 LTC2249 U W U U APPLICATIO S I FOR ATIO Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact. The transformer in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10Ω to 20Ω ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2249 is 80Msps. For the ADC to operate properly, the CLK signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 5.9ns for the ADC internal circuitry to have enough settling time for proper operation. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2249 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2249 is 1Msps. CLEAN SUPPLY 4.7µF FERRITE BEAD 0.1µF ETC1-1T CLK 100Ω CLK LTC2249 5pF-30pF LTC2249 DIFFERENTIAL CLOCK INPUT 2249 F13 2249 F12 IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter 0.1µF FERRITE BEAD VCM Figure 13. LVDS or PECL CLK Drive Using a Transformer 2249fa 16 LTC2249 U W U U APPLICATIO S I FOR ATIO DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) OF D13 – D0 (Offset Binary) D13 – D0 (2’s Complement) >+1.000000V +0.999878V +0.999756V 1 0 0 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 +0.000122V 0.000000V –0.000122V –0.000244V 0 0 0 0 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 –0.999878V –1.000000V