LTC2262-14
14-Bit, 150Msps
Ultralow Power 1.8V ADC
FEATURES
DESCRIPTION
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The LTC®2262-14 is a sampling 14-bit A/D converter
designed for digitizing high frequency, wide dynamic
range signals. The LTC2262-14 is perfect for demanding
communications applications with AC performance that
includes 72.8dB SNR and 88dB spurious free dynamic
range (SFDR). Ultralow jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance.
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72.8dB SNR
88dB SFDR
Low Power: 149mW
Single 1.8V Supply
CMOS, DDR CMOS or DDR LVDS Outputs
Selectable Input Ranges: 1VP-P to 2VP-P
800MHz Full-Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm × 6mm) QFN Package
DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typical) and no missing codes over temperature. The transition
noise is a low 1.2LSBRMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
APPLICATIONS
The ENC+ and ENC– inputs may be driven differentially
or single ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of
clock duty cycles.
Communications
Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multi-Channel Data Acquisition
n Nondestructive Testing
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L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
LTC2262-14 2-Tone FFT,
fIN = 68MHz and 69MHz
1.8V
0
1.2V
TO 1.8V
VDD
–10
–20
OVDD
–
INPUT
S/H
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
D13
CMOS
•
OR
•
LVDS
•
D0
OUTPUT
DRIVERS
OGND
CLOCK/DUTY
CYCLE
CONTROL
150MHz
–30
AMPLITUDE (dBFS)
ANALOG
INPUT
+
–40
–50
–60
–70
–80
–90
–100
–110
–120
GND
226214 TA01a
0
10
20
30 40
50
FREQUENCY (MHz)
60
70
226214 TA01b
CLOCK
226214fc
For more information www.linear.com/LTC2262-14
1
LTC2262-14
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages (VDD, OVDD)........................ –0.3V to 2V
Analog Input Voltage (AIN+, AIN–,
PAR/SER, SENSE) (Note 3)............–0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC–, CS,
SDI, SCK) (Note 4)..................................... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage................. –0.3V to (OVDD + 0.3V)
Operating Temperature Range:
LTC2262C................................................. 0°C to 70°C
LTC2262I.............................................. –40°C to 85°C
Storage Temperature Range.................... –65°C to 150°C
PIN CONFIGURATIONS
DNC
D10_11
DNC
D12_13
DNC
OF
VCM
VREF
VDD
D10
D11
D12
D13
DNC
OF
VCM
VREF
SENSE
VDD
40 39 38 37 36 35 34 33 32 31
SENSE
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
FULL-RATE CMOS OUTPUT MODE
TOP VIEW
40 39 38 37 36 35 34 33 32 31
AIN+ 1
30 D9
AIN– 2
AIN+ 1
30 D8_9
29 D8
29 DNC
GND 3
28 CLKOUT+
AIN– 2
GND 3
28 CLKOUT+
REFH 4
27 CLKOUT–
REFH 4
27 CLKOUT–
REFH 5
26 OVDD
REFH 5
25 OGND
REFL 6
REFL 7
24 D7
REFL 7
PAR/SER 8
23 D6
PAR/SER 8
VDD 9
22 D5
VDD 9
22 D4_5
VDD 10
21 D4
VDD 10
21 DNC
41
26 OVDD
41
25 OGND
24 D6_7
D2_3
DNC
DNC
SDO
SDI
SCK
CS
D0_1
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
ENC–
D3
D2
D1
D0
SDO
SDI
SCK
CS
11 12 13 14 15 16 17 18 19 20
ENC–
11 12 13 14 15 16 17 18 19 20
ENC+
23 DNC
ENC+
REFL 6
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
D10_11–
D10_11+
D12_13–
D12_13+
OF–
OF+
VCM
VREF
SENSE
VDD
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
40 39 38 37 36 35 34 33 32 31
AIN+ 1
30 D8_9+
AIN– 2
29 D8_9–
GND 3
28 CLKOUT+
REFH 4
27 CLKOUT–
REFH 5
26 OVDD
41
REFL 6
25 OGND
REFL 7
24 D6_7+
PAR/SER 8
23 D6_7–
VDD 9
22 D4_5+
VDD 10
21 D4_5–
D2_3+
D2_3–
D0_1+
D0_1–
SDO
SDI
SCK
CS
ENC–
ENC+
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
226214fc
2
For more information www.linear.com/LTC2262-14
LTC2262-14
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2262CUJ-14#PBF
LTC2262CUJ-14#TRPBF
LTC2262UJ-14
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2262IUJ-14#PBF
LTC2262IUJ-14#TRPBF
LTC2262UJ-14
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER
CHARACTERISTICS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
MIN
l
14
TYP
MAX
UNITS
Bits
Integral Linearity Error
Differential Analog Input (Note 6)
l
–4
±1
4
LSB
Differential Linearity Error
Differential Analog Input
l
–1
±0.3
1
LSB
Offset Error
(Note 7)
l
–9
±1.5
9
mV
Gain Error
Internal Reference
External Reference
l
–1.5
±1.5
±0.4
1.5
%FS
%FS
±20
µV/°C
Full-Scale Drift
Offset Drift
Internal Reference
External Reference
±30
±10
ppm/°C
ppm/°C
Transition Noise
External Reference
1.2
LSBRMS
ANALOG
INPUT
The
l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN
Analog Input Range (AIN+ – AIN–)
1.7V < VDD < 1.9V
l
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Analog Input (Note 8)
l
VCM – 100mV
VCM
VCM + 100mV
VSENSE
External Voltage Reference Applied to SENSE External Reference Mode
l
0.625
1.250
1.300
IINCM
Analog Input Common Mode Current
Per Pin, 150Msps
IIN1
Analog Input Leakage Current
0 < AIN+, AIN– < VDD, No Encode
l
–1
1
µA
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–3
3
µA
IIN3
SENSE Input Leakage Current
0.625 < SENSE < 1.3V
l
–6
6
µA
tAP
Sample-and-Hold Acquisition Delay Time
0
tJITTER
Sample-and-Hold Acquisition Delay Jitter
0.17
CMRR
Analog Input Common Mode Rejection Ratio
BW-3B
Full-Power Bandwidth
1 to 2
VP-P
185
Figure 6 Test Circuit
V
V
µA
ns
psRMS
80
dB
800
MHz
226214fc
For more information www.linear.com/LTC2262-14
3
LTC2262-14
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
30MHz Input
70MHz Input
140MHz Input
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic
S/(N+D)
5MHz Input
30MHz Input
70MHz Input
140MHz Input
MIN
l
l
TYP
70.4
74
MAX
UNITS
72.8
72.7
72.5
72.1
dB
dB
dB
dB
88
88
82
81
dB
dB
dB
dB
Spurious Free Dynamic Range
4th Harmonic or Higher
5MHz Input
30MHz Input
70MHz Input
140MHz Input
90
90
90
90
dB
dB
dB
dB
Signal-to-Noise Plus Distortion Ratio
5MHz Input
30MHz Input
70MHz Input
140MHz Input
72.7
72.5
72
71.6
dB
dB
dB
dB
l
69.3
INTERNAL
REFERENCE CHARACTERISTICS l denotes the specifications which apply over the
The
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.5 • VDD – 25mV
0.5 • VDD
0.5 • VDD + 25mV
VCM Output Temperature Drift
UNITS
±25
VCM Output Resistance
–600µA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
4
1.225
Ω
1.250
VREF Output Temperature Drift
1.275
V
±25
VREF Output Resistance
–400µA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
V
ppm/°C
ppm/°C
7
Ω
0.6
mV/V
DIGITAL
INPUTS AND OUTPUTS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC– )
Differential Encode Mode (ENC– Not Tied to GND)
VID
Differential Input Voltage
(Note 8)
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
l
0.2
l
0.2
V
1.2
1.6
V
V
3.6
V
VIN
Input Voltage Range
ENC+, ENC– to GND
RIN
Input Resistance
(See Figure 10)
10
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
Single-Ended Encode Mode (ENC– Tied to GND)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
1.2
V
VIN
Input Voltage Range
ENC+ to GND
l
RIN
Input Resistance
(See Figure 11)
30
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
0
0.6
V
3.6
V
226214fc
4
For more information www.linear.com/LTC2262-14
LTC2262-14
DIGITAL
INPUTS AND OUTPUTS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CS, SDI, SCK)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
IIN
Input Current
VIN = 0V to 3.6V
l
CIN
Input Capacitance
(Note 8)
1.3
V
–10
0.6
V
10
µA
3
pF
200
Ω
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
ROL
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
(Note 8)
l
–10
10
µA
4
pF
1.790
V
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OVDD = 1.8V
VOH
High Level Output Voltage
IO = –500µA
l
VOL
Low Level Output Voltage
IO = 500µA
l
1.750
0.010
0.050
V
OVDD = 1.5V
VOH
High Level Output Voltage
IO = –500µA
1.488
V
VOL
Low Level Output Voltage
IO = 500µA
0.010
V
OVDD = 1.2V
VOH
High Level Output Voltage
IO = –500µA
1.185
V
VOL
Low Level Output Voltage
IO = 500µA
0.010
V
DIGITAL DATA OUTPUTS (LVDS MODE)
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
247
350
175
454
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
1.125
1.250
1.250
1.375
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
mV
mV
V
V
100
Ω
POWER
REQUIREMENTS l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
1.8
1.9
UNITS
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
Analog Supply Voltage
(Note 10)
l
1.7
OVDD
Output Supply Voltage
(Note 10)
l
1.1
IVDD
Analog Supply Current
DC Input
Sine Wave Input
l
IOVDD
Digital Supply Current
Sine Wave Input, OVDD=1.2V
PDISS
Power Dissipation
DC Input
Sine Wave Input, OVDD=1.2V
82.7
84.5
1.9
V
95
mA
mA
5.5
l
149
159
V
mA
171
mW
mW
226214fc
For more information www.linear.com/LTC2262-14
5
LTC2262-14
POWER
REQUIREMENTS l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.8
1.9
V
1.9
V
LVDS Output Mode
VDD
Analog Supply Voltage
(Note 10)
l
1.7
OVDD
Output Supply Voltage
(Note 10)
l
1.7
IVDD
Analog Supply Current
Sine Wave Input
l
88.1
101.3
mA
IOVDD
Digital Supply Current
(0VDD = 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
l
20.7
40.5
23
44
mA
mA
PDISS
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
l
196
231
224
262
mW
mW
All Output Modes
PSLEEP
Sleep Mode Power
0.5
mW
PNAP
Nap Mode Power
9
mW
10
mW
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
PDIFFCLK
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
fS
Sampling Frequency
(Note 10)
l
1
tL
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.17
2.0
tH
ENC High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.17
2.0
tAP
Sample-and-Hold Acquisition Delay
Time
SYMBOL
PARAMETER
TYP
MAX
UNITS
150
MHz
3.33
3.33
500
500
ns
ns
3.33
3.33
500
500
ns
ns
0
CONDITIONS
ns
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.7
3.1
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.4
2.6
ns
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
Pipeline Latency
Full Data Rate Mode
Double Data Rate Mode
tSKEW
5.0
5.5
ns
Cycles
Cycles
Digital Data Outputs (LVDS Mode)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.8
3.2
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.5
2.7
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
5.5
Cycles
226214fc
6
For more information www.linear.com/LTC2262-14
LTC2262-14
TIMING
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SPI Port Timing (Note 8)
tSCK
SCK Period
tS
Write Mode
Readback Mode, CSDO = 20pF, RPULLUP = 2k
l
l
40
250
ns
ns
CS to SCK Setup Time
l
5
ns
tH
SCK to CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
tDO
SCK Falling to SDO Valid
Readback Mode, CSDO = 20pF, RPULLUP = 2k
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
ns
125
l
ns
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 150MHz, LVDS outputs with
internal termination disabled, differential ENC+/ENC– = 2VP-P sine wave,
input range = 2VP-P with differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and 11 1111 1111
1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = 1.8V, fSAMPLE = 150MHz, ENC+ = single-ended 1.8V square
wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on
each digital output unless otherwise noted.
Note 10: Recommended operating conditions.
TIMING DIAGRAMS
Full-Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
tL
N+1
ENC–
ENC+
tD
N–5
D0-D13, OF
CLKOUT +
N–4
N–3
N–2
N–1
tC
CLKOUT –
226214 TD01
226214fc
For more information www.linear.com/LTC2262-14
7
LTC2262-14
TIMING DIAGRAMS
Double Data Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
tL
N+1
ENC–
ENC+
tD
D0_1
tD
D0N-5
D1N-5
D0N-4
D1N-4
D0N-3
D1N-3
D0N-2
D1N-2
D12N-5
D13N-5
D12N-4
D13N-4
D12N-3
D13N-3
D12N-2
D13N-2
••
•
D12_13
OFN-5
OF
OFN-4
OFN-2
tC
tC
CLKOUT+
OFN-3
CLKOUT –
226214 TD02
Double Data Rate LVDS Output Mode Timing
All Outputs are Differential and Have LVDS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
tL
N+1
ENC–
ENC+
D0_1+
D0_1–
tD
tD
D0N-5
D1N-5
D0N-4
D1N-4
D0N-3
D1N-3
D0N-2
D1N-2
D12N-5
D13N-5
D12N-4
D13N-4
D12N-3
D13N-3
D12N-2
D13N-2
••
•
D12_13+
D12_13–
OF+
OF–
CLKOUT+
OFN-5
tC
OFN-4
OFN-3
OFN-3
tC
CLKOUT –
226214 TD03
226214fc
8
For more information www.linear.com/LTC2262-14
LTC2262-14
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
A6
R/W
SDO
A5
A4
A3
A2
A1
A0
XX
D7
HIGH IMPEDANCE
XX
XX
D6
D5
XX
XX
D4
XX
D3
XX
D2
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
R/W
SDO
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
226214 TD04
HIGH IMPEDANCE
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2262-14: Integral
Non-Linearity (INL)
LTC2262-14: Differential
Non-Linearity (DNL)
2.0
1.0
0
1.5
0.8
–10
0
–0.5
–1.0
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
0.5
0.2
0
–0.2
–0.4
–0.8
0
4096
8192
12288
OUTPUT CODE
16384
226214 G01
–1.0
–40
–50
–60
–70
–80
–90
–100
–0.6
–1.5
–2.0
–20
0.6
1.0
INL ERROR (LSB)
LTC2262-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 150Msps
0
4096
8192
12288
OUTPUT CODE
16384
226214 G02
–110
–120
0
10
20
30 40
50
FREQUENCY (MHz)
60
70
226214 G03
226214fc
For more information www.linear.com/LTC2262-14
9
LTC2262-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2262-14: 8k Point FFT, fIN = 70MHz
–1dBFS, 150Msps
LTC2262-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 150Msps
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2262-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 150Msps
–40
–50
–60
–70
–80
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
10
20
30 40
50
FREQUENCY (MHz)
60
70
0
10
20
30 40
50
FREQUENCY (MHz)
60
70
20
30 40
50
FREQUENCY (MHz)
60
6000
–20
70
226214 G06
LTC2262-14: Shorted Input
Histogram
0
74
73
5000
–30
72
–40
–50
SNR (dBFS)
4000
COUNT
–60
3000
–70
–80
2000
–90
–100
1000
71
70
69
68
0
10
20
30 40
50
FREQUENCY (MHz)
60
67
0
8177
70
8179
8181
8183
OUTPUT CODE
226214 G07
66
8185
100
90
SFDR (dBc AND dBFS)
90
75
dBFS
85
80
LVDS OUTPUTS
70
60
50
350
90
dBc
40
30
80
75
CMOS OUTPUTS
70
20
70
100 150 200 250 300
INPUT FREQUENCY (MHz)
LTC2262-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
110
95
80
50
226214 G09
LTC2262-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 150Msps
85
0
226214 G08
LTC2262-14: SFDR vs Input
Frequency, –1dB, 2V Range,
150Msps
IVDD (mA)
AMPLITUDE (dBFS)
10
LTC2262-14: SNR vs Input
Frequency, –1dB, 2V Range,
150Msps
–10
–110
–120
0
226214 G05
226214 G04
LTC2262-14: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
150Msps
SFDR (dBFS)
–40
–50
10
65
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
350
226214 G10
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
226214 G12
65
0
25
50
75
100
125
SAMPLE RATE (Msps)
150
226214 G13
226214fc
10
For more information www.linear.com/LTC2262-14
LTC2262-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2262-14: IOVDD vs Sample
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
45
74
3.5mA LVDS
40
LVDS
CMOS
72
1.75mA LVDS
20
15
72
71
SNR (dBFS)
25
SNR (dBFS)
30
IOVDD (mA)
73
73
35
70
69
68
10
1.8V CMOS
5
0
LTC2262-14: SNR vs Sample Rate
and Digital Output Mode, 30MHz Sine
Wave Input, –1dB
LTC2262-14: SNR vs SENSE,
fIN = 5MHz, –1dB
70
67
1.2V CMOS
0
DDR CMOS
71
50
100
SAMPLE RATE (Msps)
150
66
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
226214 G14
1.2
1.3
226214 G15
69
0
25
50
75
100
SAMPLE RATE (Msps)
125
150
226214 G18
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
AIN+ (Pin 1): Positive Differential Analog Input.
AIN– (Pin 2): Negative Differential Analog Input.
GND (Pin 3): ADC Power Ground.
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2µF ceramic capacitor and to ground with a
0.1µF ceramic capacitor.
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2µF ceramic capacitor and to ground with a
0.1µF ceramic capacitor.
PAR/SER (Pin 8): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
operating modes. PAR/SER should be connected directly
to ground or the VDD of the part and not be driven by a
logic signal.
VDD (Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
to ground with 0.1µF ceramic capacitors. Pins 9 and 10
can share a bypass capacitor.
ENC+ (Pin 11): Encode Input. Conversion starts on the
rising edge.
ENC – (Pin 12): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = VDD), CS controls the clock duty cycle
stabilizer. When CS is low, the clock duty cycle stabilizer is
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 14): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK controls the
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
226214fc
For more information www.linear.com/LTC2262-14
11
LTC2262-14
PIN FUNCTIONS
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. When SDI
is low, the part operates normally. When SDI is high, the
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
CLKOUT– (Pin 27): Inverted version of CLKOUT+.
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessary and SDO can be left unconnected. In the parallel
programming mode (PAR/SER = VDD), SDO is not used
and should not be connected.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
OGND (Pin 25): Output Driver Ground.
OVDD (Pin 26): Output Driver Supply. Bypass to ground
with a 0.1µF ceramic capacitor.
VCM (Pin 37): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1µF
ceramic capacitor.
VREF (Pin 38): Reference Voltage Output. Bypass to ground
with a 1µF ceramic capacitor, nominally 1.25V.
SENSE (Pin 39): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0 to D13 (Pins 17-24, 29-34): Digital Outputs. D13 is
the MSB.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
DNC (Pin 35): Do not connect this pin.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0_1 to D12_13 (Pins 18, 20, 22, 24, 30, 32, 34): Double
Data Rate Digital Outputs. Two data bits are multiplexed onto
each output pin. The even data bits (D0, D2, D4, D6, D8, D10,
D12) appear when CLKOUT+ is low. The odd data bits (D1,
D3, D5, D7, D9, D11, D13) appear when CLKOUT+ is high.
CLKOUT– (Pin 27): Inverted version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 19, 21, 23, 29, 31, 33, 35): Do not connect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1–/D0_1+ to D12_13 –/D12_13+ (Pins 17/18, 19/20,
21/22, 23/24, 29/30, 31/32, 33/34): Double Data Rate
Digital Outputs. Two data bits are multiplexed onto each
226214fc
12
For more information www.linear.com/LTC2262-14
LTC2262-14
PIN FUNCTIONS
differential output pair. The even data bits (D0, D2, D4,
D6, D8, D10, D12) appear when CLKOUT+ is low. The odd
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
CLKOUT+ is high.
CLKOUT–/CLKOUT+
(Pins 27/28): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
OF–/OF+ (Pins 35/36): Over/Under Flow Digital Output. OF+
is high when an overflow or underflow has occurred.
FUNCTIONAL BLOCK DIAGRAM
AIN+
–
AIN
VCM
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
VDD
FIFTH PIPELINED
ADC STAGE
GND
VDD/2
0.1µF
VREF
1µF
1.25V
REFERENCE
SHIFT REGISTER
AND CORRECTION
RANGE
SELECT
SENSE
REFH
REF
BUF
REFL INTERNAL CLOCK SIGNALS
OVDD
OF
DIFF
REF
AMP
MODE
CONTROL
REGISTERS
CLOCK/DUTY
CYCLE
CONTROL
•
•
•
OUTPUT
DRIVERS
D13
D0
CLKOUT +
CLKOUT –
REFH
0.1µF
REFL
OGND
ENC+
ENC–
226214 F01
PAR/SER CS SCK SDI SDO
2.2µF
0.1µF
0.1µF
Figure 1. Functional Block Diagram
226214fc
For more information www.linear.com/LTC2262-14
13
LTC2262-14
APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2262-14 is a low power 14-bit 150Msps A/D
converter that is powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially, or single ended for lower
power consumption. The digital outputs can be CMOS,
double data rate CMOS (to halve the number of output
lines), or double data rate LVDS (to reduce digital noise in
the system.) Many additional features can be chosen by
programming the mode control registers through a serial
SPI port. See the Serial Programming Mode section.
ANALOG INPUT
The analog input is a differential CMOS sample-and-hold
circuit (Figure 2). The inputs should be driven differentially
around a common mode voltage set by the VCM output
pin, which is nominally VDD/2. For the 2V input range, the
LTC2262-14
VDD
AIN+
INPUT DRIVE CIRCUITS
Input filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
also limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
50Ω
RON
25Ω
10Ω
CSAMPLE
3.5pF
RON
25Ω
10Ω
T1
1:1
25Ω
25Ω
CSAMPLE
3.5pF
CPARASITIC
1.8pF
AIN+
LTC2262-14
0.1µF
12pF
25Ω
25Ω
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
VDD
VCM
0.1µF
0.1µF
ANALOG
INPUT
CPARASITIC
1.8pF
VDD
AIN–
inputs should swing from VCM – 0.5V to VCM + 0.5V. There
should be 180° phase difference between the inputs.
AIN–
226214 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
1.2V
10k
ENC+
ENC–
10k
1.2V
226214 F02
Figure 2. Equivalent Input Circuit
226214fc
14
For more information www.linear.com/LTC2262-14
LTC2262-14
APPLICATIONS INFORMATION
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is AC
coupled to the A/D so the amplifier’s output common mode
voltage can be optimally set to minimize distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures 4
to 6) should convert the signal to differential before driving the A/D.
50Ω
VCM
0.1µF
0.1µF
ANALOG
INPUT
AIN+
T2
T1
25Ω
LTC2262-14
0.1µF
1.8pF
50Ω
0.1µF
VCM
25Ω
AIN–
0.1µF
0.1µF
ANALOG
INPUT
T1
226214 F05
AIN+
T2
25Ω
LTC2262-14
0.1µF
4.7pF
0.1µF
25Ω
AIN–
226214 F04
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 5. Recommended Front-End Circuit for
Input Frequencies from 170MHz to 270MHz
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
50Ω
Figure 4. Recommended Front-End Circuit for
Input Frequencies from 70MHz to 170MHz
VCM
0.1µF
0.1µF
2.7nH
ANALOG
INPUT
AIN+
LTC2262-14
0.1µF
25Ω
T1
0.1µF
25Ω
2.7nH
AIN–
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
226214 F06
Figure 6. Recommended Front-End Circuit for
Input Frequencies Above 270MHz
226214fc
For more information www.linear.com/LTC2262-14
15
LTC2262-14
APPLICATIONS INFORMATION
Reference
The LTC2262-14 has an internal 1.25V voltage reference.
For a 2V input range using the internal reference, connect
SENSE to VDD. For a 1V input range using the internal
reference, connect SENSE to ground. For a 2V input range
with an external reference, apply a 1.25V reference voltage
to SENSE (Figure 9.)
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE.
ANALOG
INPUT
+
+
–
–
200Ω
200Ω
25Ω
0.1µF
AIN+
12pF
0.1µF
25Ω
VREF
1.25V
1.25V BANDGAP
REFERENCE
0.625V
RANGE
DETECT
AND
CONTROL
SENSE
BUFFER
INTERNAL ADC
HIGH REFERENCE
0.1µF
REFH
2.2µF
226214 F07
5Ω
1µF
LTC2262-14
AIN–
12pF
LTC2262-14
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • VSENSE FOR
0.65V < VSENSE < 1.300V
VCM
HIGH SPEED
DIFFERENTIAL
0.1µF
AMPLIFIER
The VREF , REFH and REFL pins should be bypassed as
shown in Figure 8. The 0.1µF capacitor between REFH and
REFL should be as close to the pins as possible (not on
the back side of the circuit board).
0.1µF
0.1µF
0.8x
DIFF AMP
REFL
INTERNAL ADC
LOW REFERENCE
Figure 7. Front-End Circuit Using a High
Speed Differential Amplifier
226214 F08
Figure 8. Reference Circuit
VREF
1µF
1.25V
EXTERNAL
REFERENCE
LTC2262-14
SENSE
1µF
226214 F09
Figure 9. Using an External 1.25V Reference
226214fc
16
For more information www.linear.com/LTC2262-14
LTC2262-14
APPLICATIONS INFORMATION
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10) and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinusoidal, PECL or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken
above VDD (up to 3.6V), and the common mode range
is from 1.1V to 1.6V. In the differential encode mode,
ENC– should stay at least 200mV above ground to avoid
falsely triggering the single-ended encode mode. For good
jitter performance ENC+ and ENC– should have fast rise
and fall times.
LTC2262-14
VDD
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50%(±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
by mode control register A2 (serial programming mode),
or by CS (parallel programming mode).
0.1µF
25Ω
DIFFERENTIAL
COMPARATOR
VDD
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC – is connected
to ground and ENC+ is driven with a square wave encode
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC+ threshold
is 0.9V. For good jitter performance ENC+ should have fast
rise and fall times.
ENC+
T1
1:4
100Ω
D1
LTC2262-14
100Ω
ENC–
15k
ENC+
0.1µF
226214 F12
T1: COILCRAFT WBC4 - 1WL
D1: AVAGO HSMS - 2822
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
ENC–
30k
226214 F10
Figure 12. Sinusoidal Encode Drive
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
0.1µF
LTC2262-14
1.8V TO 3.3V
0V
PECL OR
LVDS
CLOCK
ENC+
ENC–
30k
CMOS LOGIC
BUFFER
226214 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
ENC+
LTC2262-14
0.1µF
ENC–
226214 F13
Figure 13. PECL or LVDS Encode Drive
226214fc
For more information www.linear.com/LTC2262-14
17
LTC2262-14
APPLICATIONS INFORMATION
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50%(±5%) duty cycle. The
duty cycle stabilizer should not be used below 5Msps.
When using Double Data Rate CMOS at high sample rates
the SNR will degrade slightly (see Typical Performance
Characteristics section). DDR CMOS is not recommended
for sample frequencies above 100Msps.
DIGITAL OUTPUTS
In double data rate LVDS mode, two data bits are multiplexed and output on each differential output pair.
There are 7 LVDS output pairs (D0_1+/D0_1– through
D12_13+/D12_13–) for the digital output data. Overflow
(OF+/OF –) and the data output clock (CLKOUT+/CLKOUT–)
each have an LVDS output pair.
Digital Output Modes
The LTC2262-14 can operate in three digital output
modes: full rate CMOS, double data rate CMOS (to halve
the number of output lines), or double data rate LVDS
(to reduce digital noise in the system). The output mode
is set by mode control register A3 (serial programming
mode), or by SCK (parallel programming mode). Note that
double data rate CMOS cannot be selected in the parallel
programming mode.
Full-Rate CMOS Mode
In full-rate CMOS mode the 14 digital outputs (D0-D13),
overflow (OF), and the data output clocks (CLKOUT+,
CLKOUT–) have CMOS output levels. The outputs are
powered by OVDD and OGND which are isolated from the
A/D core power and ground. OVDD can range from 1.1V to
1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double Data Rate CMOS Mode
In double data rate CMOS mode, two data bits are multiplexed and output on each data pin. This reduces the
number of data lines by seven, simplifying board routing
and reducing the number of input pins needed to receive
the data. The 7 digital outputs (D0_1, D2_3, D4_5, D6_7,
D8_9, D10_11, D12_13), overflow (OF), and the data output
clocks (CLKOUT+, CLKOUT–) have CMOS output levels.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground. OVDD can
range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS
logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
18
Double Data Rate LVDS Mode
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground. In LVDS
mode, OVDD must be 1.8V.
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is increased by 1.6x to maintain about the same output
voltage swing.
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged.
The overflow bit has the same pipeline latency as the
data bits.
226214fc
For more information www.linear.com/LTC2262-14
LTC2262-14
APPLICATIONS INFORMATION
Phase Shifting the Output Clock
Table 1. Output Codes vs Input Voltage
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
setup-and-hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
AIN+ – AIN–
(2V Range)
OF
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>1.000000V
1
11 1111 1111 1111
01 1111 1111 1111
+0.999878V
0
11 1111 1111 1111
01 1111 1111 1111
+0.999756V
0
11 1111 1111 1110
01 1111 1111 1110
+0.000122V
0
10 0000 0000 0001
00 0000 0000 0001
+0.000000V
0
10 0000 0000 0000
00 0000 0000 0000
–0.000122V
0
01 1111 1111 1111
11 1111 1111 1111
–0.000244V
0
01 1111 1111 1110
11 1111 1111 1110
–0.999878V
0
00 0000 0000 0001
10 0000 0000 0001
–1.000000V
0
00 0000 0000 0000
10 0000 0000 0000
≤–1.000000V
1
00 0000 0000 0000
10 0000 0000 0000
CLKOUT+/
The LTC2262-14 can also phase shift the
CLKOUT– signals by serially programming mode control register A2. The output clock can be shifted by
0°, 45°, 90° or 135°. To use the phase shifting feature
the clock duty cycle stabilizer must be turned on.
Another control register bit can invert the polarity of
CLKOUT+ and CLKOUT–, independently of the phase shift.
The combination of these two features enables phase
shifts of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially programming mode control register A4
ENC+
D0-D13, OF
CLKOUT+
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
CLKPHASE1
CLKPHASE0
0°
0
0
0
45°
0
0
1
90°
0
1
0
135°
0
1
1
180°
1
0
0
225°
1
0
1
270°
1
1
0
315°
1
1
1
226214 F14
Figure 14. Phase Shifting CLKOUT
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is “randomized” by applying an exclusive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is applied—an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output randomizer is enabled by
serially programming mode control register A4.
Alternate Bit Polarity
Another feature that reduces digital feedback on the circuit
board is the alternate bit polarity mode. When this mode
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11,
D13) are inverted before the output buffers. The even bits
(D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are not
affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
When there is a very small signal at the input of the A/D
that is centered around midscale, the digital outputs toggle
between mostly 1s and mostly 0s. This simultaneous
For more information www.linear.com/LTC2262-14
226214fc
19
LTC2262-14
APPLICATIONS INFORMATION
switching of most of the bits will cause large currents in
the ground plane. By inverting every other bit, the alternate bit polarity mode makes half of the bits transition
high while half of the bits transition low. To first order,
this cancels current flow in the ground plane, reducing
the digital noise.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate
bit polarity mode is independent of the digital output randomizer—either, both or neither function can be on at the
same time. When alternate bit polarity mode is on, the data
format is offset binary and the 2’s complement control bit
has no effect. The alternate bit polarity mode is enabled
by serially programming mode control register A4.
The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including
OF and CLKOUT are disabled. The high impedance disabled
state is intended for long periods of inactivity—it is too
slow to multiplex a data bus between multiple converters
at full speed.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 101010101010101
to 010101010101010 on alternating samples
Output Disable
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down, resulting in 0.5mW power consumption. Sleep mode
is enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF ,
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
PC BOARD
CLKOUT FPGA
CLKOUT
CLKOUT
OF
OF
OF
D13/D0
RANDOMIZER
ON
D1
D12/D0
LTC2262-14
D12
D2
D13/D0
D13
D13
•
•
•
D12/D0
D2/D0
D2/D0
D12
D2
D1/D0
D1
D1/D0
D0
D0
•
•
•
D0
226214 F15
Figure 15. Functional Equivalent of Digital Output Randomizer
D0
226214 F16
Figure 16. Unrandomizing a Randomized Digital
Output Signal
226214fc
20
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LTC2262-14
APPLICATIONS INFORMATION
mode requires at least 100 clock cycles. If the application
demands very accurate DC settling then an additional
50µs should be allowed so the on-chip references can
settle from the slight temperature shift caused by the
change in supply current as the A/D leaves nap mode.
Nap mode is enabled by mode control register A1 in the
serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2262-14 can be programmed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V or 3.3V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Digital Output Mode Control Bit
0 = Full-Rate CMOS Output Mode
1 = Double Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required. If
serial data is only written and read back is not needed, then
SDO can be left floating and no pull-up resistor is needed.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
GROUNDING AND BYPASSING
The LTC2262-14 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with
an internal ground plane is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass
capacitors must be located as close to the pins as possible.
226214fc
For more information www.linear.com/LTC2262-14
21
LTC2262-14
APPLICATIONS INFORMATION
Of particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2µF capacitor
between REFH and REFL can be somewhat further away.
The VCM capacitor should be located as close to the pin
as possible. To make space for this the capacitor on VREF
can be further away or on the back of the PC board. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC2262-14 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board.
Table 3. Serial Programming Mode Register Map
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
X
X
X
X
X
X
RESET
Bit 7
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers are Reset to 00h. This Bit is Automatically Set Back to Zero at the end of the SPI write
command
The reset register is write only
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
PWROFF1
PWROFF0
Bits 7-2
Unused, Don’t Care Bits.
Bits 1-0
PWROFF1:PWROFF0
00 = Normal Operation
01 = Nap Mode
10 = Not Used
11 = Sleep Mode
Power Down Control Bits
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, Don’t Care Bits.
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– Delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– Delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– Delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT Phase Delay Feature is Used, the Clock Duty Cycle Stabilizer Must Also be Turned On
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
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22
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LTC2262-14
APPLICATIONS INFORMATION
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
D6
D5
D4
D3
D2
D1
D0
X
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE1
OUTMODE0
Bit 7
Unused, Don’t Care Bit.
Bits 6-4
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 1.6× the Current Set by ILVDS2:ILVDS0
Bit 2
OUTOFF
Output Disable Bit
0 = Digital Outputs are Enabled
1 = Digital Outputs are Disabled and Have High Output Impedance
Bits 1-0
OUTMODE1:OUTMODE0
Digital Output Mode Control Bits
00 = Full-Rate CMOS Output Mode
01 = Double Data Rate LVDS Output Mode
10 = Double Data Rate CMOS Output Mode
11 = Not Used
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
OUTTEST2
OUTTEST1
OUTTEST0
ABP
RAND
TWOSCOMP
Bit 7-6
Unused, Don’t Care Bits.
Bits 5-3
OUTTEST2:OUTTEST0
Digital Output Test Pattern Bits
000 = Digital Output Test Patterns Off
001 = All Digital Outputs = 0
011 = All Digital Outputs = 1
101 = Checkerboard Output Pattern. OF, D13-D0 Alternate Between 101 0101 0101 0101 and 010 1010 1010 1010
111 = Alternating Output Pattern. OF, D13-D0 Alternate Between 000 0000 0000 0000 and 111 1111 1111 1111
Note: Other Bit Combinations are not Used
Bit 2
ABP
Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
Bit 1
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Note: ABP = 1 Forces the Output Format to be Offset Binary
226214fc
For more information www.linear.com/LTC2262-14
23
LTC2262-14
TYPICAL APPLICATIONS
LTC2262 Evaluation Board Schematic
T2
MABAES0060
•
R9 10Ω
•
SENSE
R39
33.2Ω
1%
ANALOG INPUT
R10 10Ω
R40
33.2Ω
1%
C12
0.1µF
R14
1k
C51
4.7pF
C17
1µF
VDD
R15 100Ω
C23
1µF
C13
1µF
R16
100Ω
C19
0.1µF
40
39
38
37
VDD SENSE VREF VCM
R27 10Ω 1
R28 10Ω 2
3
4
C15
0.1µF
C20
2.2µF
5
6
7
C21
0.1µF
VDD
PAR/SER
8
9
10
C18
0.1µF
35
OF–
34
33
32
DIGITAL
OUTPUTS
31
D13 D12 D11 D10
30
AIN+
D9
AIN–
D8
GND
CLKOUT+
28
CLKOUT–
27
REFH
U2
REFH
LTC2262CUJ
OVDD
REFL
OGND
REFL
D7
PAR/SER
D6
VDD
D5
VDD
D4
GND
41
ENCODE CLOCK
36
OF+
ENC+ ENC–
11
12
CS
13
SCK
SDI SDO
14
15
16
D0
17
D1
18
D2
19
D3
20
29
26
25
C37
0.1µF
0VDD
24
23
22
21
DIGITAL
OUTPUTS
R13
100Ω
226214 TA02
SPI BUS
226214fc
24
For more information www.linear.com/LTC2262-14
LTC2262-14
TYPICAL APPLICATIONS
Silkscreen Top
Inner Layer 2 GND
Top Side
226214 TA04
226214 TA04
226214 TA03
Inner Layer 4
Inner Layer 3
226214 TA06
Inner Layer 5 Power
226214 TA07
Bottom Side
226214 TA08
226214 TA09
226214fc
For more information www.linear.com/LTC2262-14
25
LTC2262-14
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 ±0.05
6.50 ±0.05
5.10 ±0.05
4.42 ±0.05
4.50 ±0.05
(4 SIDES)
4.42 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 ±0.10
(4 SIDES)
0.75 ±0.05
R = 0.10
TYP
R = 0.115
TYP
39 40
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
4.50 REF
(4-SIDES)
4.42 ±0.10
2
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 ±0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
226214fc
26
For more information www.linear.com/LTC2262-14
LTC2262-14
REVISION HISTORY
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
B
08/12
Corrected IOVDD to IOVDD
11
Corrected RESET REGISTER A0, D7 description
21
Attached VDD to Pins 9, 10 and 40 on schematic
24
Corrected “external reference” to “internal reference” for 1V input range
16
C
01/14
PAGE NUMBER
226214fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
www.linear.com/LTC2262-14
27
LTC2262-14
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LT6604-10/
LT6604-15
Dual Matched 2.5MHz, 5MHz, 10MHz, 15MHz Filter
with ADC Driver
Dual Matched 4th Order LP Filters with Differential Drivers. Low Noise, Low
Distortion Amplifiers
226214fc
28
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2262-14
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(408) 432-1900 FAX: (408) 434-0507
www.linear.com/LTC2262-14
LT 0114 REV C • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2009
