LTC2295
Dual 14-Bit, 10Msps
Low Power 3V ADC
U
FEATURES
DESCRIPTIO
■
The LTC®2295 is a 14-bit 10Msps, low power dual 3V
A/D converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2295 is perfect for
demanding imaging and communications applications
with AC performance that includes 74.4dB SNR and 90dB
SFDR for signals well beyond the Nyquist frequency.
■
■
■
■
■
■
■
■
■
■
■
■
■
Integrated Dual 14-Bit ADCs
Sample Rate: 10Msps
Single 3V Supply (2.7V to 3.4V)
Low Power: 120mW
74.4dB SNR
90dB SFDR
110dB Channel Isolation
Multiplexed or Separate Data Bus
Flexible Input: 1VP-P to 2VP-P Range
575MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)
64-Pin (9mm × 9mm) QFN Package
DC specs include ±1.2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 1LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic. An optional multiplexer allows both channels to
share a digital output bus.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
APPLICATIO S
■
■
■
■
Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
U
TYPICAL APPLICATIO
Typical INL, 2V Range
ANALOG
INPUT A
INPUT
S/H
–
14-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
OVDD
2.0
D13A
1.5
••
•
D0A
OGND
CLK A
CLOCK/DUTY CYCLE
CONTROL
MUX
CLK B
INPUT
S/H
–
0
–0.5
–1.5
OVDD
ANALOG
INPUT B
0.5
–1.0
CLOCK/DUTY CYCLE
CONTROL
+
1.0
INL ERROR (LSB)
+
14-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
D13B
••
•
D0B
–2.0
0
4096
8192
CODE
12288
16384
2295 G02
OGND
2295 TA01
2295fa
1
LTC2295
U
W
U
PACKAGE/ORDER I FOR ATIO
U
W W
W
ABSOLUTE
AXI U RATI GS
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation ............................................ 1500mW
Operating Temperature Range
LTC2295C ............................................... 0°C to 70°C
LTC2295I .............................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
64 GND
63 VDD
62 SENSEA
61 VCMA
60 MODE
59 SHDNA
58 OEA
57 OFA
56 DA13
55 DA12
54 DA11
53 DA10
52 DA9
51 DA8
50 OGND
49 OVDD
TOP VIEW
AINA+ 1
AINA– 2
REFHA 3
REFHA 4
REFLA 5
REFLA 6
VDD 7
CLKA 8
CLKB 9
VDD 10
REFLB 11
REFLB 12
REFHB 13
REFHB 14
AINB– 15
AINB+ 16
48 DA7
47 DA6
46 DA5
45 DA4
44 DA3
43 DA2
42 DA1
41 DA0
40 OFB
39 DB13
38 DB12
37 DB11
36 DB10
35 DB9
34 DB8
33 DB7
GND 17
VDD 18
SENSEB 19
VCMB 20
MUX 21
SHDNB 22
OEB 23
DB0 24
DB1 25
DB2 26
DB3 27
DB4 28
DB5 29
DB6 30
OGND 31
OVDD 32
65
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 125°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB
ORDER PART
NUMBER
QFN PART*
MARKING
LTC2295CUP
LTC2295IUP
LTC2295UP
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
U
CO VERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
CONDITIONS
MIN
●
Differential Analog Input (Note 5)
Differential Analog Input
(Note 6)
External Reference
Internal Reference
External Reference
External Reference
SENSE = 1V
●
●
●
●
14
–5
–1
–12
–2.5
TYP
±1.2
±0.5
±2
±0.5
±10
±30
±5
±0.3
±2
1
MAX
5
1
12
2.5
UNITS
Bits
LSB
LSB
mV
%FS
µV/°C
ppm/°C
ppm/°C
%FS
mV
LSBRMS
2295fa
2
LTC2295
U
U
A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VIN
Analog Input Range (AIN+ –AIN–)
VIN,CM
Analog Input Common Mode (AIN+
CONDITIONS
+AIN
–)/2
MIN
2.7V < VDD < 3.4V (Note 7)
●
TYP
MAX
UNITS
±0.5 to ±1
V
Differential Input (Note 7)
●
1
1.5
1.9
V
Single Ended Input (Note 7)
●
0.5
1.5
2
V
0V < AIN+, AIN–
●
–1
1
µA
IIN
Analog Input Leakage Current
ISENSE
SENSEA, SENSEB Input Leakage
0V < SENSEA, SENSEB < 1V
●
–3
3
µA
IMODE
MODE Input Leakage Current
0V < MODE < VDD
●
–3
3
µA
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
0.2
psRMS
CMRR
Analog Input Common Mode Rejection Ratio
80
dB
575
MHz
Full Power Bandwidth
< VDD
0
Figure 8 Test Circuit
ns
W U
DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
●
MIN
TYP
71.6
74.4
dB
73.2
dB
90
dB
85
dB
70MHz Input
Spurious Free Dynamic Range
2nd or 3rd Harmonic
5MHz Input
SFDR
Spurious Free Dynamic Range
4th Harmonic or Higher
5MHz Input
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
5MHz Input
SFDR
75
Intermodulation Distortion
fIN = 4.3MHz, 4.6MHz
Crosstalk
fIN = 5MHz
UNITS
●
80
90
dB
90
dB
●
71
74.4
dB
73.1
dB
70MHz Input
70MHz Input
IMD
●
70MHz Input
MAX
90
dB
–110
dB
2295fa
3
LTC2295
U U
U
I TER AL REFERE CE CHARACTERISTICS
(Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCM Output Voltage
IOUT = 0
1.475
1.500
1.525
V
±25
VCM Output Tempco
ppm/°C
VCM Line Regulation
2.7V < VDD < 3.3V
3
mV/V
VCM Output Resistance
–1mA < IOUT < 1mA
4
Ω
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (CLK, OE, SHDN, MUX)
VIH
High Level Input Voltage
VDD = 3V
●
VIL
Low Level Input Voltage
VDD = 3V
●
IIN
Input Current
VIN = 0V to VDD
●
CIN
Input Capacitance
(Note 7)
2
V
–10
0.8
V
10
µA
3
pF
LOGIC OUTPUTS
OVDD = 3V
COZ
Hi-Z Output Capacitance
OE = High (Note 7)
3
pF
ISOURCE
Output Source Current
VOUT = 0V
50
mA
ISINK
Output Sink Current
VOUT = 3V
50
mA
VOH
High Level Output Voltage
IO = –10µA
IO = –200µA
●
IO = 10µA
IO = 1.6mA
●
VOL
Low Level Output Voltage
2.7
2.995
2.99
0.005
0.09
V
V
0.4
V
V
OVDD = 2.5V
VOH
High Level Output Voltage
IO = –200µA
2.49
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
VOH
High Level Output Voltage
IO = –200µA
1.79
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
OVDD = 1.8V
2295fa
4
LTC2295
U W
POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VDD
Analog Supply Voltage
(Note 9)
OVDD
Output Supply Voltage
IVDD
Supply Current
PDISS
UNITS
●
2.7
3
3.4
(Note 9)
●
0.5
3
3.6
V
Both ADCs at fS(MAX)
●
40
46
mA
Power Dissipation
Both ADCs at fS(MAX)
●
120
138
mW
PSHDN
Shutdown Power (Each Channel)
SHDN = H, OE = H, No CLK
2
mW
PNAP
Nap Mode Power (Each Channel)
SHDN = H, OE = L, No CLK
15
mW
V
WU
TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
ts
Sampling Frequency
(Note 9)
●
1
tL
CLK Low Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 7)
●
●
40
5
tH
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 7)
●
●
tAP
Sample-and-Hold Aperture Delay
tD
CLK to DATA Delay
CL = 5pF (Note 7)
tMD
MUX to DATA Delay
Data Access Time After OE↓
BUS Relinquish Time
TYP
MAX
UNITS
10
MHz
50
50
500
500
ns
ns
40
5
50
50
500
500
ns
ns
●
1.4
2.7
5.4
ns
CL = 5pF (Note 7)
●
1.4
2.7
5.4
ns
CL = 5pF (Note 7)
●
4.3
10
ns
(Note 7)
●
3.3
8.5
ns
0
Pipeline Latency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 10MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
5
ns
Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 10MHz, input range = 1VP-P with differential
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.
Note 9: Recommended operating conditions.
2295fa
5
LTC2295
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Typical INL, 2V Range
Crosstalk vs Input Frequency
Typical DNL, 2V Range
1.0
2.0
–100
0.8
1.5
–105
0.6
–110
–115
–120
DNL ERROR (LSB)
INL ERROR (LSB)
CROSSTALK (dB)
1.0
0.5
0
–0.5
–1.0
–125
–130
0
20
40
60
80
INPUT FREQUENCY (MHz)
–0.2
–0.4
–1.5
–0.8
–2.0
–1.0
4096
0
100
8192
CODE
16384
12288
0
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–80
AMPLITUDE (dB)
–40
AMPLITUDE (dB)
–60
–70
–50
–60
–70
–80
–90
–90
–40
–50
–60
–70
–80
–90
–100
–100
–100
–110
–110
–110
–120
–120
1
0
3
2
FREQUENCY (MHz)
4
5
1
0
3
2
FREQUENCY (MHz)
4
–120
5
25000
95
73
90
13373
10000
6919
0
SFDR (dBFS)
SNR (dBFS)
72
71
70
69
68
278
8179 8180 8181 8182 8183 8184 8185 8186
CODE
2295 G07
85
80
75
67
3227
43
5
100
74
18803
853
4
SFDR vs Input Frequency, –1dB,
2V Range
75
22016
5000
3
2
FREQUENCY (MHz)
2295 G06
SNR vs Input Frequency,
–1dB, 2V Range
Grounded Input Histogram
15000
1
0
2295 G05
2295 G04
20000
16384
12288
8192 Point 2-Tone FFT, fIN = 4.3MHz
and 4.6MHz, –1dB, 2V Range
–10
–40
8192
CODE
2295 G03
8192 Point FFT, fIN = 70.1MHz,
–1dB, 2V Range
–50
4096
0
2295 G02
8192 Point FFT, fIN = 5.1MHz,
–1dB, 2V Range
AMPLITUDE (dB)
0
–0.6
2295 G01
COUNT
0.4
0.2
70
66
65
65
0
10
40
30
20
50
60
INPUT FREQUENCY (MHz)
70
2295 G08
0
10
40
60
30
50
20
INPUT FREQUENCY (MHz)
70
2295 G09
2295fa
6
LTC2295
U W
TYPICAL PERFOR A CE CHARACTERISTICS
SNR vs Input Level, fIN = 5MHz,
2V Range
SNR and SFDR vs Sample Rate,
2V Range, fIN = 5MHz, –1dB
80
100
120
dBFS
80
SNR
70
100
60
SFDR (dBc AND dBFS)
SNR (dBc AND dBFS)
90
50
40
dBc
30
20
10
12
4
6
8
SAMPLE RATE (Msps)
14
dBc
80
70
60
100dBc SFDR
REFERENCE LINE
50
40
30
10
0
–70
–60
–50
–40 –30 –20
INPUT LEVEL (dBFS)
–10
0
0
–80
–40
–20
–60
INPUT LEVEL (dBFS)
2295 G11
2295 G10
IVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB
0
2295 G12
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB, OVDD = 1.8V
50
2.0
1.8
1.6
2V RANGE
1.4
40
IOVDD (mA)
2
IVDD (mA)
0
90
20
10
60
dBFS
110
70
SFDR
SNR AND SFDR (dBFS)
SFDR vs Input Level,
fIN = 5MHz, 2V Range
1V RANGE
30
1.2
1.0
0.8
0.6
0.4
0.2
0
20
0
2
4
6
8
10
SAMPLE RATE (Msps)
12
14
2295 G13
0
2
8
6
4
10
SAMPLE RATE (Msps)
12
14
2295 G14
2295fa
7
LTC2295
U
U
U
PI FU CTIO S
AINA+ (Pin 1): Channel A Positive Differential Analog
Input.
AINA– (Pin 2): Channel A Negative Differential Analog
Input.
REFHA (Pins 3, 4): Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
REFLA (Pins 5, 6): Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1µF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 13, 14 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1µF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.
AINB– (Pin 15): Channel B Negative Differential Analog
Input.
+
AINB (Pin 16): Channel B Positive Differential Analog
Input.
GND (Pins 17, 64): ADC Power Ground.
SENSEB (Pin 19): Channel B Reference Programming Pin.
Connecting SENSEB to VCMB selects the internal reference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of ±VSENSEB. ±1V is the largest valid input range.
VCMB (Pin 20): Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to VCMA.
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA13, OFA; Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together.
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to VDD results in normal operation with the outputs at high impedance. Connecting
SHDNB to VDD and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to VDD
and OEB to VDD results in sleep mode with the outputs at
high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
DB0 – DB13 (Pins 24 to 30, 33 to 39): Channel B Digital
Outputs. DB13 is the MSB.
OGND (Pins 31, 50): Output Driver Ground.
OVDD (Pins 32, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor.
OFB (Pin 40): Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DA0 – DA13 (Pins 41 to 48, 51 to 56): Channel A Digital
Outputs. DA13 is the MSB.
OFA (Pin 57): Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
2295fa
8
LTC2295
U
U
U
PI FU CTIO S
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting
SHDNA to VDD and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to VDD
and OEA to VDD results in sleep mode with the outputs at
high impedance.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects offset binary
output format and turns the clock duty cycle stabilizer off.
1/3 VDD selects offset binary output format and turns the
clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabi-
lizer on. VDD selects 2’s complement output format and
turns the clock duty cycle stabilizer off.
VCMA (Pin 61): Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to VCMB.
SENSEA (Pin 62): Channel A Reference Programming Pin.
Connecting SENSEA to VCMA selects the internal reference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of ±VSENSEA. ±1V is the largest valid input range.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
W
FUNCTIONAL BLOCK DIAGRA
U
U
AIN+
AIN–
VCM
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
1.5V
REFERENCE
SIXTH PIPELINED
ADC STAGE
SHIFT REGISTER
AND CORRECTION
2.2µF
RANGE
SELECT
REFH
SENSE
REFL
INTERNAL CLOCK SIGNALS
OVDD
REF
BUF
OF
D13
CLOCK/DUTY
CYCLE
CONTROL
DIFF
REF
AMP
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
D0
REFH
0.1µF
2295 F01
REFL
OGND
CLK
MODE
SHDN
OE
2.2µF
1µF
1µF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
2295fa
9
LTC2295
W
UW
TI I G DIAGRA S
Dual Digital Output Bus Timing
(Only One Channel is Shown)
tAP
N+4
N+2
N
ANALOG
INPUT
N+1
tH
N+3
N+5
tL
CLK
tD
N–4
N–5
D0-D13, OF
N–3
N–2
N–1
N
2295 TD01
Multiplexed Digital Output Bus Timing
tAPA
ANALOG
INPUT A
A+4
A+2
A
A+1
A+3
tAPB
ANALOG
INPUT B
B+4
B+2
B
B+1
tH
tL
A–5
B–5
B+3
CLKA = CLKB = MUX
D0A-D13A, OFA
A–4
tD
D0B-D13B, OFB
B–5
B–4
A–3
B–3
A–2
B–2
B–3
A–3
B–2
A–2
A–1
t MD
A–5
B–4
A–4
B–1
2295 TD02
2295fa
10
LTC2295
U
W
U U
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1)
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Aperture Delay Time
The time from when CLK reaches midsupply to the instant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
Intermodulation Distortion
Crosstalk
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
Crosstalk is the coupling from one channel (being driven
by a full-scale signal) onto the other channel (being driven
by a –1dBFS signal).
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
CONVERTER OPERATION
As shown in Figure 1, the LTC2295 is a dual CMOS
pipelined multistep converter. The converter has six
pipelined ADC stages; a sampled analog input will result in
a digitized value five cycles later (see the Timing Diagram
section). For optimal AC performance the analog inputs
should be driven differentially. For cost sensitive
2295fa
11
LTC2295
U
U
W
U
APPLICATIO S I FOR ATIO
applications, the analog inputs can be driven single-ended
with slightly worse harmonic distortion. The CLK input is
single-ended. The LTC2295 has two phases of operation,
determined by the state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2295
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (CSAMPLE) through
NMOS transistors. The capacitors shown attached to each
input (CPARASITIC) are the summation of all other capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when CLK is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As CLK transitions from
LTC2295
VDD
AIN+
CSAMPLE
4pF
15Ω
CPARASITIC
1pF
VDD
AIN–
CSAMPLE
4pF
15Ω
CPARASITIC
1pF
VDD
CLK
2295 F02
Figure 2. Equivalent Input Circuit
2295fa
12
LTC2295
U
W
U U
APPLICATIO S I FOR ATIO
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to VCM or a quiet reference voltage between
0.5V and 1.5V.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin may
be used to provide the common mode bias level. VCM can
be tied directly to the center tap of a transformer to set the
DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2295 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and reactance can
influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when CLK rises, holding the sampled input on
the sampling capacitor. Ideally the input circuitry should
be fast enough to fully charge the sampling capacitor
during the sampling period 1/(2FENCODE); however, this is
not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2295 being driven by an RF
transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
VCM
2.2µF
0.1µF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
AIN+
LTC2295
0.1µF
12pF
25Ω
T1 = MA/COM ETC1-1T 25Ω
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
2295 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
2295fa
13
LTC2295
U
W
U U
APPLICATIO S I FOR ATIO
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input
frequencies.
VCM
HIGH SPEED
DIFFERENTIAL
25Ω
AMPLIFIER
ANALOG
INPUT
+
AIN+
LTC2295
+
CM
–
2.2µF
12pF
–
25Ω
AIN–
2295 F04
Figure 4. Differential Drive with an Amplifier
Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
Reference Operation
Figure 6 shows the LTC2295 reference circuitry consisting
of a 1.5V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges
of 2V (±1V differential) or 1V (±0.5V differential). Tying the
SENSE pin to VDD selects the 2V range; tying the SENSE
pin to VCM selects the 1V range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
LTC2295
1.5V
VCM
4Ω
1.5V BANDGAP
REFERENCE
2.2µF
0.5V
1V
VCM
1k
0.1µF
ANALOG
INPUT
1k
25Ω
AIN+
LTC2295
12pF
25Ω
RANGE
DETECT
AND
CONTROL
2.2µF
AIN–
0.1µF
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
SENSE
BUFFER
INTERNAL ADC
HIGH REFERENCE
1µF
REFH
2295 F05
2.2µF
0.1µF
Figure 5. Single-Ended Drive
DIFF AMP
1µF
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
REFL
INTERNAL ADC
LOW REFERENCE
2295 F06
Figure 6. Equivalent Reference Circuit
2295fa
14
LTC2295
U
W
U U
APPLICATIO S I FOR ATIO
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 6. Each
ADC channel has an independent reference with its own
bypass capacitors. The two channels can be used with the
same or different input ranges.
Other voltage ranges between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 7. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
For the best channel matching, connect an external reference
to SENSEA and SENSEB.
1.5V
VCM
2.2µF
12k
0.75V
12k
Driving the Clock Input
The CLK inputs can be driven directly with a CMOS or TTL
level signal. A differential clock can also be used along with
a low jitter CMOS converter before the CLK pin (Figure 8).
CLEAN
SUPPLY
4.7µF
FERRITE
BEAD
0.1µF
CLK
LTC2295
100Ω
2295 F08
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter
The noise performance of the LTC2295 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
LTC2295
SENSE
1µF
2295 F7
Figure 7. 1.5V Range ADC
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this delay exceeds 1ns, the
performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 5.8dB.
2295fa
15
LTC2295
U
W
U U
APPLICATIO S I FOR ATIO
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2295 is 10Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (±10%) duty cycle. Each half cycle must have
at least 40ns for the ADC internal circuitry to have enough
settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The
input clock duty cycle can vary and the clock duty cycle
stabilizer will maintain a constant 50% internal duty cycle.
If the clock is turned off for a long period of time, the duty
cycle stabilizer circuit will require a hundred clock cycles
for the PLL to lock onto the input clock. To use the clock
duty cycle stabilizer, the MODE pin should be connected
to 1/3VDD or 2/3VDD using external resistors. The MODE
pin controls both Channel A and Channel B—the duty
cycle stabilizer is either on or off for both channels.
The lower limit of the LTC2295 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency for the LTC2295 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
OF
D13 – D0
(OFFSET BINARY)
D13 – D0
(2’s COMPLEMENT)
>+1.000000V
+0.999878V
+0.999756V
1
0
0
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
+0.000122V
0.000000V
–0.000122V
–0.000244V
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–0.999878V
–1.000000V