LTC2299IUP

LTC2299 Dual 14-Bit, 80Msps Low Power 3V ADC U FEATURES DESCRIPTIO ■ The LTC®2299 is a 14-bit 80Msps, low power dual 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2299 is perfect for demanding imaging and communications applications with AC performance that includes 73dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Integrated Dual 14-Bit ADCs Sample Rate: 80Msps Single 3V Supply (2.7V to 3.4V) Low Power: 444mW 73dB SNR at 70MHz Input 90dB SFDR at 70MHz Input 110dB Channel Isolation at 100MHz Multiplexed or Separate Data Bus Flexible Input: 1VP-P to 2VP-P Range 575MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit) 80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit) 65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit) 40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit) 25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit) 64-Pin (9mm × 9mm) QFN Package U APPLICATIO S ■ ■ ■ A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. An optional multiplexer allows both channels to share a digital output bus. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Wireless and Wired Broadband Communication Imaging Systems Spectral Analysis Portable Instrumentation U ■ DC specs include ±1.2LSB INL (typ), ±0.5LSB DNL (typ) and ±5LSB INL, ±1LSB DNL over temperature. The transition noise is a low 1.2LSBRMS. TYPICAL APPLICATIO + ANALOG INPUT A INPUT S/H – OVDD 14-BIT PIPELINED ADC CORE OUTPUT DRIVERS SNR vs Input Frequency, –1dB, 2V Range D13A •• • D0A 75 OGND 74 73 72 CLOCK/DUTY CYCLE CONTROL MUX CLK B CLOCK/DUTY CYCLE CONTROL SNR (dBFS) CLK A 71 70 69 68 OVDD + ANALOG INPUT B INPUT S/H – 14-BIT PIPELINED ADC CORE OUTPUT DRIVERS 67 D13B 66 •• • 65 D0B 0 100 50 150 INPUT FREQUENCY (MHz) 200 OGND 2299 TA02 2299 TA01 2299fa 1 LTC2299 U W U PACKAGE/ORDER I FOR ATIO U W W W ABSOLUTE AXI U RATI GS OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2299C ............................................... 0°C to 70°C LTC2299I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C 64 GND 63 VDD 62 SENSEA 61 VCMA 60 MODE 59 SHDNA 58 OEA 57 OFA 56 DA13 55 DA12 54 DA11 53 DA10 52 DA9 51 DA8 50 OGND 49 OVDD TOP VIEW AINA+ 1 AINA– 2 REFHA 3 REFHA 4 REFLA 5 REFLA 6 VDD 7 CLKA 8 CLKB 9 VDD 10 REFLB 11 REFLB 12 REFHB 13 REFHB 14 AINB– 15 AINB+ 16 48 DA7 47 DA6 46 DA5 45 DA4 44 DA3 43 DA2 42 DA1 41 DA0 40 OFB 39 DB13 38 DB12 37 DB11 36 DB10 35 DB9 34 DB8 33 DB7 GND 17 VDD 18 SENSEB 19 VCMB 20 MUX 21 SHDNB 22 OEB 23 DB0 24 DB1 25 DB2 26 DB3 27 DB4 28 DB5 29 DB6 30 OGND 31 OVDD 32 65 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 125°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB ORDER PART NUMBER QFN PART* MARKING LTC2299CUP LTC2299IUP LTC2299UP Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. U CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise CONDITIONS MIN ● Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference Internal Reference External Reference External Reference SENSE = 1V ● ● ● ● 14 –5 –1 –12 –2.5 TYP MAX ±1.2 ±0.5 ±2 ±0.5 ±10 ±30 ±5 ±0.3 ±2 1.2 5 1 12 2.5 UNITS Bits LSB LSB mV %FS µV/°C ppm/°C ppm/°C %FS mV LSBRMS 2299fa 2 LTC2299 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VIN Analog Input Range (AIN+ –AIN–) VIN,CM Analog Input Common Mode (AIN+ CONDITIONS +AIN –)/2 MIN 2.7V < VDD < 3.4V (Note 7) ● TYP MAX UNITS ±0.5 to ±1 V Differential Input (Note 7) ● 1 1.5 1.9 V Single Ended Input (Note 7) ● 0.5 1.5 2 V 0V < AIN+, AIN– ● –1 1 µA IIN Analog Input Leakage Current ISENSE SENSEA, SENSEB Input Leakage 0V < SENSEA, SENSEB < 1V ● –3 3 µA IMODE MODE Input Leakage Current 0V < MODE < VDD ● –3 3 µA tAP Sample-and-Hold Acquisition Delay Time tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2 psRMS CMRR Analog Input Common Mode Rejection Ratio 80 dB 575 MHz Full Power Bandwidth < VDD 0 Figure 8 Test Circuit ns W U DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input 40MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic MIN 73 ● 70.1 S/(N+D) Spurious Free Dynamic Range 4th Harmonic or Higher Signal-to-Noise Plus Distortion Ratio UNITS dB 73 dB 73 dB 140MHz Input 72.6 dB 5MHz Input 40MHz Input ● 74 90 dB 90 dB 90 dB 140MHz Input 85 dB 5MHz Input 90 dB 90 dB 70MHz Input 90 dB 140MHz Input 90 dB 72.9 dB 40MHz Input ● 80 5MHz Input 40MHz Input IMD MAX 70MHz Input 70MHz Input SFDR TYP ● 72.8 dB 70MHz Input 69.5 72.8 dB 140MHz Input 72.1 dB Intermodulation Distortion fIN = 40MHz, 41MHz 90 dB Crosstalk fIN = 100MHz –110 dB 2299fa 3 LTC2299 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V ±25 VCM Output Tempco ppm/°C VCM Line Regulation 2.7V < VDD < 3.4V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS (CLK, OE, SHDN, MUX) VIH High Level Input Voltage VDD = 3V ● VIL Low Level Input Voltage VDD = 3V ● IIN Input Current VIN = 0V to VDD ● CIN Input Capacitance (Note 7) 2 V –10 0.8 V 10 µA 3 pF LOGIC OUTPUTS OVDD = 3V COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF ISOURCE Output Source Current VOUT = 0V 50 mA ISINK Output Sink Current VOUT = 3V 50 mA VOH High Level Output Voltage IO = –10µA IO = –200µA ● IO = 10µA IO = 1.6mA ● VOL Low Level Output Voltage 2.7 2.995 2.99 0.005 0.09 V V 0.4 V V OVDD = 2.5V VOH High Level Output Voltage IO = –200µA 2.49 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V VOH High Level Output Voltage IO = –200µA 1.79 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V OVDD = 1.8V 2299fa 4 LTC2299 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Analog Supply Voltage (Note 9) ● 2.7 3 3.4 V OVDD Output Supply Voltage (Note 9) ● 0.5 3 3.6 V IVDD Supply Current Both ADCs at fS(MAX) ● 148 172 mA PDISS Power Dissipation Both ADCs at fS(MAX) ● 444 516 mW PSHDN Shutdown Power (Each Channel) SHDN = H, OE = H, No CLK 2 mW PNAP Nap Mode Power (Each Channel) SHDN = H, OE = L, No CLK 15 mW WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX fs Sampling Frequency (Note 9) ● 1 tL CLK Low Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 9) ● ● 80 MHz 5.9 5 6.25 6.25 500 500 ns ns tH CLK High Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 9) ● ● 5.9 5 6.25 6.25 500 500 ns ns tAP Sample-and-Hold Aperture Delay tD CLK to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns tMD MUX to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns Data Access Time After OE↓ CL = 5pF (Note 7) ● 4.3 10 ns BUS Relinquish Time (Note 7) ● 3.3 8.5 0 Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 80MHz, input range = 2VP-P with differential drive, unless otherwise noted. 5 UNITS ns ns Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 80MHz, input range = 1VP-P with differential drive. The supply current and power dissipation are the sum total for both channels with both channels active. Note 9: Recommended operating conditions. 2299fa 5 LTC2299 U W TYPICAL PERFOR A CE CHARACTERISTICS Crosstalk vs Input Frequency Typical INL, 2V Range, 80Msps –100 Typical DNL, 2V Range, 80Msps 1.0 2.0 0.8 1.5 –105 0.6 –110 –115 –120 0.4 DNL ERROR (LSB) INL ERROR (LSB) CROSSTALK (dB) 1.0 0.5 0 –0.5 0.2 0 –0.2 –0.4 –1.0 –125 –130 0 20 –0.8 –2.0 –1.0 100 40 60 80 INPUT FREQUENCY (MHz) –0.6 –1.5 0 4096 8192 2299 G03 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 80Msps 0 0 0 –10 –10 –10 –20 –20 –20 –30 –30 –30 –60 –70 –80 –90 –40 AMPLITUDE (dB) –40 –50 –50 –60 –70 –80 –90 –40 –50 –60 –70 –80 –90 –100 –100 –100 –110 –110 –110 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 –120 40 0 5 10 15 20 25 30 FREQUENCY (MHz) 2299 G04 35 –120 40 0 50000 –10 45000 –20 –20 –30 –30 –40 –40 –70 –90 –50 –60 –70 20000 –80 15000 –100 5000 –120 –120 0 35 40 2299 G07 12558 10000 –110 15 20 25 30 FREQUENCY (MHz) 25292 25000 –100 10 35969 30000 –110 5 40 35000 –90 0 35 43161 40000 COUNT AMPLITUDE (dB) 0 –80 15 20 25 30 FREQUENCY (MHz) Grounded Input Histogram, 80Msps –10 –60 10 2299 G06 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range –50 5 0 2299 G05 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 80Msps 16384 12288 CODE 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 80Msps AMPLITUDE (dB) AMPLITUDE (dB) 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 80Msps –120 8192 4096 2299 G02 2299 G01 AMPLITUDE (dB) 0 16384 12288 CODE 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 2299 G08 6150 5194 1987 178 26 552 8201 8203 8205 8207 CODE 8209 2299 G09 2299fa 6 LTC2299 U W TYPICAL PERFOR A CE CHARACTERISTICS SNR vs Input Frequency, –1dB, 2V Range, 80Msps SFDR vs Input Frequency, –1dB, 2V Range, 80Msps 75 SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 100 100 74 95 73 SFDR (dBFS) SNR (dBFS) SNR AND SFDR (dBFS) 90 90 72 71 70 69 68 85 80 75 67 80 SNR 70 60 70 66 65 65 200 100 50 150 INPUT FREQUENCY (MHz) 0 50 100 2299 G12 SNR vs Input Level, fIN = 70MHz, 2V Range, 80Msps SFDR vs Input Level, fIN = 70MHz, 2V Range, 80Msps 120 80 SFDR: DCS ON dBFS 110 70 100 60 90 85 80 SFDR (dBc AND dBFS) SNR (dBc AND dBFS) 90 SFDR: DCS OFF 50 40 dBc 30 10 70 40 45 60 dBc 50 40 100dBc SFDR REFERENCE LINE 10 SNR: DCS OFF 50 55 60 CLOCK DUTY CYCLE (%) 65 70 0 –70 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 0 –80 –40 –60 –20 INPUT LEVEL (dBFS) 0 2299 G15 2299 G13 2299 G14 IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 165 14 155 12 145 IOVDD (mA) IVDD (mA) 35 70 20 SNR: DCS ON 30 dBFS 80 30 20 75 0 10 20 30 40 50 60 70 80 90 100 110 SAMPLE RATE (Msps) 2299 G11 SNR and SFDR vs Clock Duty Cycle, 80Msps 95 50 200 150 INPUT FREQUENCY (MHz) 0 2299 G10 SNR AND SFDR (dBFS) SFDR 2V RANGE 135 1V RANGE 10 8 125 6 115 4 105 2 95 0 10 20 30 40 50 60 70 80 90 100 SAMPLE RATE (Msps) 2299 G16 0 0 10 20 30 40 50 60 70 80 90 100 SAMPLE RATE (Msps) 2299 G17 2299fa 7 LTC2299 U U U PI FU CTIO S AINA+ (Pin 1): Channel A Positive Differential Analog Input. AINA– (Pin 2): Channel A Negative Differential Analog Input. REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFLA (Pins 5, 6): Channel A Low Reference. Short together and bypass to Pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. CLKA (Pin 8): Channel A Clock Input. The input sample starts on the positive edge. CLKB (Pin 9): Channel B Clock Input. The input sample starts on the positive edge. REFLB (Pins 11, 12): Channel B Low Reference. Short together and bypass to Pins 13, 14 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 13, 14 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFHB (Pins 13, 14): Channel B High Reference. Short together and bypass to Pins 11, 12 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 11, 12 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. AINB– (Pin 15): Channel B Negative Differential Analog Input. + AINB (Pin 16): Channel B Positive Differential Analog Input. GND (Pins 17, 64): ADC Power Ground. SENSEB (Pin 19): Channel B Reference Programming Pin. Connecting SENSEB to VCMB selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSEB selects an input range of ±VSENSEB. ±1V is the largest valid input range. VCMB (Pin 20): Channel B 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to VCMA. MUX (Pin 21): Digital Output Multiplexer Control. If MUX is High, Channel A comes out on DA0-DA13, OFA; Channel B comes out on DB0-DB13, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0DB13, OFB; Channel B comes out on DA0-DA13, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together. SHDNB (Pin 22): Channel B Shutdown Mode Selection Pin. Connecting SHDNB to GND and OEB to GND results in normal operation with the outputs enabled. Connecting SHDNB to GND and OEB to VDD results in normal operation with the outputs at high impedance. Connecting SHDNB to VDD and OEB to GND results in nap mode with the outputs at high impedance. Connecting SHDNB to VDD and OEB to VDD results in sleep mode with the outputs at high impedance. OEB (Pin 23): Channel B Output Enable Pin. Refer to SHDNB pin function. DB0 – DB13 (Pins 24 to 30, 33 to 39): Channel B Digital Outputs. DB13 is the MSB. OGND (Pins 31, 50): Output Driver Ground. OVDD (Pins 32, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OFB (Pin 40): Channel B Overflow/Underflow Output. High when an overflow or underflow has occurred. DA0 – DA13 (Pins 41 to 48, 51 to 56): Channel A Digital Outputs. DA13 is the MSB. OFA (Pin 57): Channel A Overflow/Underflow Output. High when an overflow or underflow has occurred. OEA (Pin 58): Channel A Output Enable Pin. Refer to SHDNA pin function. 2299fa 8 LTC2299 U U U PI FU CTIO S SHDNA (Pin 59): Channel A Shutdown Mode Selection Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting SHDNA to VDD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to VDD and OEA to VDD results in sleep mode with the outputs at high impedance. MODE (Pin 60): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Note that MODE controls both channels. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabi- lizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. VCMA (Pin 61): Channel A 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to VCMB. SENSEA (Pin 62): Channel A Reference Programming Pin. Connecting SENSEA to VCMA selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSEA selects an input range of ±VSENSEA. ±1V is the largest valid input range. GND (Exposed Pad) (Pin 65): ADC Power Ground. The Exposed Pad on the bottom of the package needs to be soldered to ground. W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE 1.5V REFERENCE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D13 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 0.1µF 2299 F01 REFL OGND CLK MODE SHDN OE 2.2µF 1µF 1µF Figure 1. Functional Block Diagram (Only One Channel is Shown) 2299fa 9 LTC2299 W UW TI I G DIAGRA S Dual Digital Output Bus Timing (Only One Channel is Shown) tAP N+4 N+2 N ANALOG INPUT N+1 tH N+3 N+5 tL CLK tD N–4 N–5 D0-D13, OF N–3 N–2 N–1 N 2299 TD01 Multiplexed Digital Output Bus Timing tAPA ANALOG INPUT A A+4 A+2 A A+1 A+3 tAPB ANALOG INPUT B B+4 B+2 B B+1 tH tL A–5 B–5 B+3 CLKA = CLKB = MUX D0A-D13A, OFA A–4 tD D0B-D13B, OFB B–5 B–4 A–3 B–3 A–2 B–2 B–3 A–3 B–2 A–2 A–1 t MD A–5 B–4 A–4 B–1 2299 TD02 2299fa 10 LTC2299 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Aperture Delay Time The time from when CLK reaches midsupply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) Intermodulation Distortion Crosstalk If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. Crosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a –1dBFS signal). If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, CONVERTER OPERATION As shown in Figure 1, the LTC2299 is a dual CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive 2299fa 11 LTC2299 U U W U APPLICATIO S I FOR ATIO applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2299 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2299 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from LTC2299 VDD AIN+ CSAMPLE 4pF 15Ω CPARASITIC 1pF VDD AIN– CSAMPLE 4pF 15Ω CPARASITIC 1pF VDD CLK 2299 F02 Figure 2. Equivalent Input Circuit 2299fa 12 LTC2299 U W U U APPLICATIO S I FOR ATIO high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.5V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2299 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω AIN+ LTC2299 0.1µF 12pF Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2299 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may 25Ω T1 = MA/COM ETC1-1T 25Ω RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 2299 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. 2299fa 13 LTC2299 U W U U APPLICATIO S I FOR ATIO VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT + 2.2µF AIN+ 2.2µF 0.1µF LTC2299 12Ω ANALOG INPUT 25Ω + CM – VCM 25Ω 0.1µF AIN– LTC2299 0.1µF T1 12pF – AIN+ 8pF 25Ω 12Ω AIN– T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 2299 F04 2299 F06 Figure 4. Differential Drive with an Amplifier Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz VCM 2.2µF VCM 1k 0.1µF ANALOG INPUT 0.1µF 1k AIN+ ANALOG INPUT 2.2µF 25Ω 25Ω AIN+ T1 LTC2299 0.1µF 12pF 25Ω 25Ω T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 0.1µF LTC2299 0.1µF AIN– 2299 F07 2299 F05 Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz Figure 5. Single-Ended Drive The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth. VCM 2.2µF 0.1µF 6.8nH ANALOG INPUT 25Ω AIN+ LTC2299 0.1µF T1 0.1µF 25Ω 6.8nH – AIN T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE 2299 F08 Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz 2299fa 14 LTC2299 U W U U APPLICATIO S I FOR ATIO Reference Operation Figure 9 shows the LTC2299 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Each ADC channel has an independent reference with its own bypass capacitors. The two channels can be used with the same or different input ranges. Other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. For the best channel matching, connect an external reference to SENSEA and SENSEB. LTC2299 1.5V VCM 4Ω 1.5V 1.5V BANDGAP REFERENCE 2.2µF 2.2µF 12k 0.5V 1V 0.75V TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V RANGE DETECT AND CONTROL 12k BUFFER 0.1µF 1µF Figure 10. 1.5V Range ADC INTERNAL ADC HIGH REFERENCE Input Range REFH 2.2µF LTC2299 SENSE 2299 F10 SENSE 1µF VCM The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5.7dB. See the Typical Performance Characteristics section. DIFF AMP 1µF REFL INTERNAL ADC LOW REFERENCE 2299 F09 Figure 9. Equivalent Reference Circuit Driving the Clock Input The CLK inputs can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low jitter squaring circuit before the CLK pin (Figure 11). 2299fa 15 LTC2299 U W U U APPLICATIO S I FOR ATIO CLEAN SUPPLY 4.7µF SINUSOIDAL CLOCK INPUT 0.1µF CLEAN SUPPLY 4.7µF FERRITE BEAD FERRITE BEAD 0.1µF 0.1µF 1k CLK LTC2299 CLK LTC2299 100Ω 50Ω 1k NC7SVU04 2299 F11 Figure 11. Sinusoidal Single-Ended CLK Drive The noise performance of the LTC2299 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source. It is recommended that CLKA and CLKB are shorted together and driven by the same clock source. If a small time delay is desired between when the two channels sample the analog inputs, CLKA and CLKB can be driven by two different signals. If this delay exceeds 1ns, the performance of the part may degrade. CLKA and CLKB should not be driven by asynchronous signals. Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact. 2299 F12 IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter ETC1-1T CLK LTC2299 5pF-30pF DIFFERENTIAL CLOCK INPUT 2299 F13 0.1µF FERRITE BEAD VCM Figure 13. LVDS or PECL CLK Drive Using a Transformer The transformer in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10Ω to 20Ω ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections. 2299fa 16 LTC2299 Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2299 is 80Msps. For the ADC to operate properly, the CLK signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 5.9ns for the ADC internal circuitry to have enough settling time for proper operation. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The MODE pin controls both Channel A and Channel B—the duty cycle stabilizer is either on or off for both channels. The lower limit of the LTC2299 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2299 is 1Msps. DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V RANGE) OF D13 – D0 (OFFSET BINARY) D13 – D0 (2’s COMPLEMENT) >+1.000000V +0.999878V +0.999756V 1 0 0 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 +0.000122V 0.000000V –0.000122V –0.000244V 0 0 0 0 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 –0.999878V –1.000000V 70MHz C48 0.1µF EXT REF 5 6 3 1 C2 2.2µF C27 0.1µF JP3 SENSE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AINA+ AINA– REFHA REFHA REFLA REFLA VDD CLKA CLKB VDD REFLB REFLB REFHB REFHB AINB– AINB+ C1 0.1µF VDD C47 0.1µF C21 0.1µF C11 0.1µF C4 0.1µF VCMB 8 6 4 2 VCC GND C41 0.1µF T1, T2 ETC1-1T ETC1-1-13 C40 0.1µF R24 * C34 0.1µF R20 24.9Ω C23 1µF R22 24.9Ω R18 * 7 1/3VDD C20 2.2µF C18 1µF R39 OPT VDD 3 5 2/3VDD C10 2.2µF C9 1µF R3 1k R2 1k R1 1k C13 1µF 1 VDD C6 * •3 R23 51 T2 * R32 OPT C36 4.7µF VCMB C33 0.1µF C29 0.1µF R16 33Ω C17 0.1µF C14 0.1µF C8 0.1µF VDD R9 * R7 24.9Ω •3 2 R6 24.9Ω R5 * C44 0.1µF 1 C22 0.1µF • T1 * R5, R9, R18, R24 24.9Ω 12.4Ω C45 100µF 6.3V OPT J4 R17 ANALOG OPT INPUT B 4 VCMA C7 0.1µF U6 3 NC7SVU04 4 VCM VDD EXT REF 5 6 3 1 C3 0.1µF C15 0.1µF C12 4.7µF 6.3V R15 3 1k U3 NC7SVU04 *VERSION TABLE J3 CLOCK INPUT VDD L1 BEAD J2 ANALOG R4 INPUT A OPT VCMA E1 EXT REF A VDD JP2 SENSEA 1 VDD JP1 MODE 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 U1 LTC2299 C37 10µF 6.3V C35 0.1µF C28 2.2µF R25 105k R26 100k C38 0.01µF 4 BYP SHDN GND GND GND IN U8 LT1763 1 OUT 2 ADJ 3 VCC VCC DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 OFB DB13 DB12 DB11 DB10 DB9 DB8 DB7 GND VDD SENSEA VCMA MODE SHDNA OEA OFA DA13 DA12 DA11 DA10 DA9 DA8 OGND OVDD GND VDD SENSEB VCMB MUX SHDNB OEB DB0 DB1 DB2 DB3 DB4 DB5 DB6 OGND OVDD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 5 6 8 7 C25 0.1µF 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD VCC C5 0.1µF C39 1µF OE B0 GND T/R A0 OE GND 74VCX245BQX 19 T/R VCC 11 A7 B7 12 A6 B6 13 B5 A5 14 A4 B4 15 U11 B3 A3 16 A2 B2 17 A1 B1 18 B0 A0 20 VCC 74VCX245BQX 19 18 4 3 A2 A1 B2 B1 2 10 1 2 3 4 5 6 7 9 8 10 1 4 E4 GND U4 NC7SV86P5X RN8B 33Ω RN8A 33Ω RN7D 33Ω RN7B 33Ω RN7C 33Ω RN7A 33Ω RN6D 33Ω RN6C 33Ω RN6A 33Ω RN6B 33Ω 5 6 RN5C 33Ω RN5D 33Ω RN5B 33Ω RN5A 33Ω 7 17 9 8 20 VCC 11 A7 B7 12 A6 B6 13 B5 A5 14 A4 B4 15 U10 B3 A3 16 VCC 74VCX245BQX 20 VCC 11 9 A7 B7 12 8 A6 B6 13 7 B5 A5 14 6 A4 B4 15 5 U9 B3 A3 16 4 A2 B2 17 3 A1 B1 18 2 B0 A0 1 T/R 19 10 OE GND VCC 74VCX245BQX 20 VCC 11 9 A7 B7 12 8 A6 B6 13 7 B5 A5 14 6 A4 B4 15 5 U2 B3 A3 16 4 A2 B2 17 3 A1 B1 18 2 A0 B0 1 T/R 19 10 OE GND 3 5 VCC 1 2 RN4C 33Ω RN4B 33Ω RN4A 33Ω RN3D 33Ω RN3C 33Ω RN3B 33Ω RN2C 33Ω RN2D 33Ω RN3A 33Ω R35 100k U5 24LC025 21 23 33 35 59 61 68 70 1 A0 2 A1 3 A2 4 A3 C46 0.1µF R34 4.7k 100 98 94 96 92 84 86 88 90 76 78 80 82 72 74 8 VCC 7 WP 6 SCL 5 SDA R36 4.99k 99 97 93 95 91 83 85 87 89 75 77 79 81 71 73 67 69 63 65 60 64 66 62 53 55 57 54 56 58 45 47 49 51 46 48 50 52 37 39 41 43 34 36 38 40 42 44 29 31 25 27 30 32 22 24 26 28 RN1D 33Ω RN2A 33Ω RN2B 33Ω C24 0.1µF 15 16 17 19 7 9 11 13 8 10 12 14 18 20 1 3 5 RN1B 33Ω RN1C 33Ω RN1A 33Ω J1 EDGE-CON-100 2 4 6 VSS ENABLE SDA VCCIN SCL R38 4.99k R37 4.99k R33 4.7k VCC U U 20 W VDD APPLICATIO S I FOR ATIO 2299 AI01 SDA SCL VSS VCCIN U VCC LTC2299 2299fa LTC2299 U W U U APPLICATIO S I FOR ATIO Silkscreen Top Top Side 2299fa 21 LTC2299 U W U U APPLICATIO S I FOR ATIO Inner Layer 3 Power Inner Layer 2 GND Bottom Side 2299fa 22 LTC2299 U PACKAGE DESCRIPTIO UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ±0.05 7.15 ±0.05 8.10 ±0.05 9.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP 63 64 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER 7.15 ± 0.10 (4-SIDES) 0.25 ± 0.05 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE (UP64) QFN 1003 0.50 BSC BOTTOM VIEW—EXPOSED PAD 2299fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC2299 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2221 12-Bit, 135Msps ADC 630mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2222 12-Bit, 105Msps ADC 475mW, 67.9dB SNR, 7mm × 7mm QFN Package LTC2223 12-Bit, 80Msps ADC 366mW, 68dB SNR, 7mm × 7mm QFN Package LTC2224 12-Bit, 135Msps ADC 630mW, 67.5dB SNR, 7mm × 7mm QFN Package LTC2225 12-Bit, 10Msps ADC 60mW, 71.4dB SNR, 5mm × 5mm QFN Package LTC2226 12-Bit, 25Msps ADC 75mW, 71.4dB SNR, 5mm × 5mm QFN Package LTC2227 12-Bit, 40Msps ADC 120mW, 71.4dB SNR, 5mm × 5mm QFN Package LTC2228 12-Bit, 65Msps ADC 205mW, 71.3dB SNR, 5mm × 5mm QFN Package LTC2230 10-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2231 10-Bit, 135Msps ADC 630mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2232 10-Bit, 105Msps ADC 475mW, 61.3dB SNR, 7mm × 7mm QFN Package LTC2233 10-Bit, 80Msps ADC 366mW, 61.3dB SNR, 7mm × 7mm QFN Package LTC2245 14-Bit, 10Msps ADC 60mW, 74.4dB SNR, 5mm × 5mm QFN Package LTC2246 14-Bit, 25Msps ADC 75mW, 74.5dB SNR, 5mm × 5mm QFN Package LTC2247 14-Bit, 40Msps ADC 120mW, 74.4dB SNR, 5mm × 5mm QFN Package LTC2248 14-Bit, 65Msps ADC 205mW, 74.3dB SNR, 5mm × 5mm QFN Package LTC2249 14-Bit, 80Msps ADC 222mW, 73dB SNR, 5mm × 5mm QFN Package LTC2286 10-Bit, Dual, 25Msps ADC 150mW, 61.8dB SNR, 9mm × 9mm QFN Package LTC2287 10-Bit, Dual, 40Msps ADC 235mW, 61.8dB SNR, 9mm × 9mm QFN Package LTC2288 10-Bit, Dual, 65Msps ADC 400mW, 61.8dB SNR, 9mm × 9mm QFN Package LTC2289 10-Bit, Dual, 80Msps ADC 422mW, 61dB SNR, 9mm × 9mm QFN Package LTC2290 12-Bit, Dual, 10Msps ADC 120mW, 71.3dB SNR, 9mm × 9mm QFN Package LTC2291 12-Bit, Dual, 25Msps ADC 150mW, 74.5dB SNR, 9mm × 9mm QFN Package LTC2292 12-Bit, Dual, 40Msps ADC 235mW, 74.4dB SNR, 9mm × 9mm QFN Package LTC2293 12-Bit, Dual, 65Msps ADC 400mW, 74.3dB SNR, 9mm × 9mm QFN Package LTC2294 12-Bit, Dual, 80Msps ADC 422mW, 70.6dB SNR, 9mm × 9mm QFN Package LTC2295 14-Bit, Dual, 10Msps ADC 120mW, 74.4dB SNR, 9mm × 9mm QFN Package LTC2296 14-Bit, Dual, 25Msps ADC 150mW, 74.5dB SNR, 9mm × 9mm QFN Package LTC2297 14-Bit, Dual, 40Msps ADC 235mW, 74.4dB SNR, 9mm × 9mm QFN Package LTC2298 14-Bit, Dual, 65Msps ADC 400mW, 74.3dB SNR, 9mm × 9mm QFN Package 2299fa 24 Linear Technology Corporation RD/LT 0106 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005