LTC2309
8-Channel, 12-Bit SAR ADC
with I2C Interface
Features
Description
12-Bit Resolution
n Low Power: 1.5mW at 1ksps, 35µW Sleep Mode
n 14ksps Throughput Rate
n Low Noise: SNR = 73.4dB
n Guaranteed No Missing Codes
n Single 5V Supply
n 2-Wire I2C Compatible Serial Interface with Nine
Addresses Plus One Global for Synchronization
n Fast Conversion Time: 1.3µs
n Internal Reference
n Internal 8-Channel Multiplexer
n Internal Conversion Clock
n Unipolar or Bipolar Input Ranges (Software Selectable)
n Guaranteed Operation from –40°C to 125°C
(TSSOP Package)
n 24-Pin 4mm × 4mm QFN and 20-Pin TSSOP Packages
The LTC®2309 is a low noise, low power, 8-channel, 12-bit
successive approximation ADC with an I2C compatible
serial interface. This ADC includes an internal reference
and a fully differential sample-and-hold circuit to reduce
common mode noise. The LTC2309 operates from an
internal clock to achieve a fast 1.3µs conversion time.
n
Applications
n
n
n
n
n
n
Industrial Process Control
Motor Control
Accelerometer Measurements
Battery-Operated Instruments
Isolated and/or Remote Data Acquisition
Power Supply Monitoring
BLOCK DIAGRAM
The LTC2309 operates from a single 5V supply and
draws just 300µA at a throughput rate of 1ksps. The
ADC enters nap mode when not converting, reducing
the power dissipation.
The LTC2309 is available in both a small 24-pin 4mm ×
4mm QFN and a 20-pin TSSOP package. The internal 2.5V
reference and 8-channel multiplexer further reduce PCB
board space requirements.
The low power consumption and small size make the
LTC2309 ideal for battery-operated and portable applications, while the 2-wire I2C compatible serial interface makes
this ADC a good match for space-constrained systems.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Easy Drive is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
5V
0.1µF
Integral Nonlinearity
vs Output Code
10µF
1.00
VDD
CH0
CH1
0.75
AD1
AD0
LTC2309
0.50
CH3
ANALOG INPUTS
0V TO 4.096V UNIPOLAR CH4
±2.048V BIPOLAR
CH5
ANALOG
INPUT
MUX
+
–
I2C
12-BIT
SAR ADC
PORT
CH6
INL (LSB)
CH2
SCL
SDA
INTERNAL
2.5V REF
COM
0
–0.25
–0.50
VREF
CH7
0.25
2.2µF
–0.75
–1.00
REFCOMP
GND
0.1µF
10µF
0
1024
2048
3072
4096
OUTPUT CODE
2309 G01
2309 TA01
2309fd
LTC2309
Absolute Maximum Ratings (Notes 1, 2)
Supply Voltage
VDD........................................................... –0.3V to 6V
Analog Input Voltage (Note 3)
CH0-CH7, COM, VREF ,
REFCOMP..................... (GND – 0.3V) to (VDD + 0.3V)
Digital Input Voltage
(Note 3)............................. (GND – 0.3V) to (VDD + 0.3V)
Digital Output Voltage....... (GND – 0.3V) to (VDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC2309C................................................. 0°C to 70°C
LTC2309I..............................................–40°C to 85°C
LTC2309H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
TSSOP............................................................... 300°C
Pin Configuration
TOP VIEW
GND
GND
VDD
CH0
CH1
CH2
TOP VIEW
REFCOMP
1
20 VREF
GND
2
19 COM
VDD
3
18 CH7
16 SCL
AD0
4
17 CH6
15 AD1
AD1
5
16 CH5
14 AD0
SCL
6
15 CH4
13 VDD
SDA
7
14 CH3
GND
8
13 CH2
GND
9
12 CH1
VDD 10
11 CH0
24 23 22 21 20 19
CH3 1
18 GND
CH4 2
17 SDA
CH5 3
25
CH6 4
CH7 5
COM 6
VDD
GND
GND
9 10 11 12
GND
VREF
8
REFCOMP
7
UF PACKAGE
24-LEAD (4mm s 4mm) PLASTIC QFN
TJMAX = 150°C, θJA = 37°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
F PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 90°C/W, θJC = 20°C/W
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2309CUF#PBF
LTC2309CUF#TRPBF
2309
24-Lead (4mm × 4mm) Plastic QFN
0°C to 70°C
LTC2309IUF#PBF
LTC2309IUF#TRPBF
2309
24-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
LTC2309CF#PBF
LTC2309CF#TRPBF
LTC2309F
20-Lead Plastic TSSOP
0°C to 70°C
LTC2309IF#PBF
LTC2309IF#TRPBF
LTC2309F
20-Lead Plastic TSSOP
–40°C to 85°C
LTC2309HF#PBF
LTC2309HF#TRPBF
LTC2309F
20-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2309fd
LTC2309
CONVERTER
AND MULTIPLEXER CHARACTERISTICS
The l denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4, 5)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Bipolar Zero Error
Bipolar Zero Error Drift
Bipolar Zero Error Match
Unipolar Zero Error
Unipolar Zero Error Drift
Unipolar Zero Error Match
Bipolar Full-Scale Error
Bipolar Full-Scale Error Drift
Bipolar Full-Scale Error Match
Unipolar Full-Scale Error
Unipolar Full-Scale Error Drift
Unipolar Full-Scale Error Match
CONDITIONS
l
(Note 6)
MIN
12
l
l
(Note 7)
l
(Note 7)
l
External Reference (Note 8)
REFCOMP = 4.096V
External Reference
l
l
QFN External Reference (Note 8)
TSSOP External Reference (Note 8)
REFCOMP = 4.096V
External Reference
l
l
l
TYP
MAX
±0.45
±0.35
±1
0.002
±0.1
±0.4
0.002
±0.2
±0.5
±0.4
0.05
±0.4
±0.4
±0.5
±0.3
0.05
±0.3
±1
±1
±8
±3
±6
±1
±10
±9
±3
±10
±12
±6
±2
UNITS
Bits
LSB
LSB
LSB
LSB/°C
LSB
LSB
LSB/°C
LSB
LSB
LSB
LSB/°C
LSB
LSB
LSB
LSB
LSB/°C
LSB
ANALOG
INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
VIN+
VIN–
PARAMETER
Absolute Input Range (CH0 to CH7)
Absolute Input Range (CH0 to CH7, COM)
VIN+ – VIN– Input Differential Voltage Range
IIN
CIN
Analog Input Leakage Current
Analog Input Capacitance
CMRR
Input Common Mode Rejection Ratio
CONDITIONS
(Note 9)
Unipolar (Note 9)
Bipolar (Note 9)
VIN = VIN+ – VIN– (Unipolar)
VIN = VIN+ – VIN– (Bipolar)
MIN
–0.05
–0.05
–0.05
l
l
l
TYP
MAX
REFCOMP
0.25 • REFCOMP
0.75 • REFCOMP
0 to REFCOMP
±REFCOMP/2
l
l
±1
l
Sample Mode
Hold Mode
55
5
70
UNITS
V
V
V
V
V
µA
pF
pF
dB
DYNAMIC
ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 4, 10)
SYMBOL
SINAD
SNR
THD
SFDR
PARAMETER
Signal-to-(Noise + Distortion) Ratio
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range
Channel-to-Channel Isolation
Full Linear Bandwidth
–3dB Input Linear Bandwidth
Aperture Delay
Transient Response
CONDITIONS
fIN = 1kHz
fIN = 1kHz
fIN = 1kHz, First 5 Harmonics
fIN = 1kHz
fIN = 1kHz
(Note 11)
Full-Scale Step
l
l
MIN
71
71
l
l
79
TYP
73.3
73.4
–88
90
–109
700
25
13
240
MAX
–77
UNITS
dB
dB
dB
dB
dB
kHz
MHz
ns
ns
2309fd
LTC2309
INTERNAL
REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
VREF Output Voltage
VREF Output Tempco
VREF Output Impedance
VREFCOMP Output Voltage
VREF Line Regulation
CONDITIONS
IOUT = 0 (QFN)
IOUT = 0 (TSSOP)
IOUT = 0
–0.1mA ≤ IOUT ≤ 0.1mA
IOUT = 0
VDD = 4.75V to 5.25V
l
l
MIN
2.47
2.46
TYP
2.50
2.50
±25
8
4.096
0.8
MAX
2.53
2.54
UNITS
V
V
ppm/°C
kΩ
V
mV/V
I 2C INputs and digital outputs
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
VIH
VIL
VIHA
VILA
RINH
RINL
RINF
II
VHYS
VOL
tOF
tSP
CCAX
PARAMETER
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage for Address Pins A1, A0
Low Level Input Voltage for Address Pins A1, A0
Resistance from A1, A0, to VDD to Set Chip
Address Bit to 1
Resistance from A1, A0 to GND to Set Chip
Address Bit to 0
Resistance from A1, A0 to GND or VDD to Set
Chip Address Bit to Float
Digital Input Current
Hysteresis of Schmitt Trigger Inputs
Low Level Output Voltage (SDA)
Output Fall Time VH to VIL(MAX)
Input Spike Suppression
External Capacitance Load On-Chip Address Pins
(A1, A0) for Valid Float
CONDITIONS
l
MIN
2.85
TYP
1.5
l
l
4.75
l
0.25
10
l
10
l
VIN = VDD
(Note 9)
I = 3mA
(Note 12)
MAX
l
2
l
–10
0.25
l
kΩ
MΩ
10
0.4
250
50
10
l
l
UNITS
V
V
V
V
kΩ
20 + 0.1CB
l
l
µA
V
V
ns
ns
pF
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
VDD
IDD
PD
PARAMETER
Supply Voltage
Supply Current
Nap Mode
Sleep Mode
Power Dissipation
Nap Mode
Sleep Mode
CONDITIONS
l
14ksps Sample Rate
SLP Bit = 0, Conversion Done
SLP Bit = 1, Conversion Done
14ksps Sample Rate
SLP Bit = 0, Conversion Done
SLP Bit = 1, Conversion Done
l
l
l
l
l
l
MIN
4.75
TYP
5
2.3
210
7
11.5
1.05
35
MAX
5.25
3
350
15
15
1.75
75
UNITS
V
mA
µA
µA
mW
mW
µW
2309fd
LTC2309
I 2C TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fSCL
tHD(SDA)
tLOW
tHIGH
tSU(STA)
tHD(DAT)
tSU(DAT)
tr
tf
tSU(STO)
tBUF
PARAMETER
CONDITIONS
SCL Clock Frequency
Hold Time (Repeated) START Condition
LOW Period of the SCL Pin
HIGH Period of the SCL Pin
Set-Up Time for a Repeated START Condition
Data Hold Time
Data Set-Up Time
Rise Time for SDA/SCL Signals
(Note 12)
Fall Time for SDA/SCL Signals
(Note 12)
Set-Up Time for STOP Condition
Bus Free Time Between a STOP and START Condition
MIN
TYP
l
l
l
l
l
l
l
l
l
l
l
0.6
1.3
0.6
0.6
0
100
20 + 0.1CB
20 + 0.1CB
0.6
1.3
MAX
400
0.9
300
300
UNITS
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
ADC
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fSMPL
tCONV
tACQ
tREFWAKE
PARAMETER
Throughput Rate (Successive Reads)
Conversion Time
Acquisition Time
REFCOMP Wake-Up Time (Note 13)
CONDITIONS
MIN
TYP
l
(Note 9)
(Note 9)
CREFCOMP = 10µF, CREF = 2.2µF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above VDD,
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above VDD without latchup.
Note 4: VDD = 5V, fSMPL = 14ksps internal reference unless otherwise
noted.
Note 5: Linearity, offset and full-scale specifications apply for a
single-ended analog input with respect to COM.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and 1111 1111
l
1.3
l
200
MAX
14
1.8
240
UNITS
ksps
µs
ns
ms
1111. Unipolar zero error is the offset voltage measured from +0.5LSB
when the output code flickers between 0000 0000 0000 and 0000 0000
0001.
Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error. Unipolar full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 9: Guaranteed by design, not subject to test.
Note 10: All specifications in dB are referred to a full-scale ±2.048V input
with a 2.5V reference voltage.
Note 11: Full linear bandwidth is defined as the full-scale input frequency
at which the SINAD degrades to 60dB or 10 bits of accuracy.
Note 12: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).
Note 13: REFCOMP wake-up time is the time required for the REFCOMP
pin to settle within 0.5LSB at 12-bit resolution of its final value after
waking up from SLEEP mode.
2309fd
LTC2309
Typical Performance Characteristics
TA = 25°C, VDD = 5V, fSMPL = 14ksps, unless otherwise noted.
Differential Nonlinearity
vs Output Code
1kHz Sine Wave
8192 Point FFT Plot
1.00
1.00
0
0.75
0.75
–20
0.50
0.50
0.25
0.25
0
–0.25
0
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
0
1024
2048
4096
3072
–1.00
–60
–80
–100
–120
0
1024
OUTPUT CODE
2048
4096
3072
–140
0
1
OUTPUT CODE
2309 G01
6
Full-Scale Error vs Temperature
OFFSET ERROR (LSB)
0.5
FULL-SCALE ERROR (LSB)
1.5
2.0
7
4
2.0
1.0
5
4
3
FREQUENCY (kHz)
2309 G03
Offset Error vs Temperature
2.5
1.5
2
2309 G02
Supply Current
vs Sampling Frequency
SUPPLY CURRENT (mA)
SNR = 73.4dB
SINAD = 73.3dB
THD = –88dB
–40
MAGNITUDE (dB)
DNL (LSB)
INL (LSB)
Integral Nonlinearity
vs Output Code
1.0
0.5
0
UNIPOLAR
–0.5
–1.0
BIPOLAR
2
UNIPOLAR
0
BIPOLAR
–2
–4
–0.5
0
0.1
1
10
SAMPLING FREQUENCY (ksps)
–2.0
–50 –25
100
0
50
75
25
TEMPERATURE (°C)
100
3209 G04
–6
–50
125
125
100
2309 G06
Analog Input Leakage Current
vs Temperature
Sleep Current vs Temperature
3.0
10
1000
2.8
900
2.6
8
2.4
2.2
2.0
1.8
1.6
1.4
800
LEAKAGE CURRENT (nA)
SLEEP CURRENT (µA)
SUPPLY CURRENT (mA)
50
25
0
75
TEMPERATURE (°C)
2309 G05
Supply Current vs Temperature
6
4
2
1.2
1.0
–50
–25
700
600
500
400
CH (ON)
300
200
CH (OFF)
100
–25
50
25
0
75
TEMPERATURE (°C)
100
125
2309 G07
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
2309 G08
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
2309 G09
2309fd
LTC2309
Pin Functions (QFN)
CH3-CH7 (Pins 1-5): Channel 3 to Channel 7 Analog
Inputs. CH3-CH7 can be configured as single-ended
or differential input channels. See the Analog Input
Multiplexer section.
AD1 (Pin 15): Chip Address Control Pin. This pin is
configured as a three-state (LOW, HIGH, floating)
address control bit for the device I2C address. See
Table 2 for address selection.
COM (Pin 6): Common Input. This is the reference
point for all single-ended inputs. It must be free of
noise and should be connected to ground for unipolar
conversions and midway between GND and REFCOMP
for bipolar conversions.
SCL (Pin 16): Serial Clock Pin of the I2C Interface. The
LTC2309 can only act as a slave and the SCL pin only
accepts an external serial clock. Data is shifted into
the SDA pin on the rising edges of the SCL clock and
output through the SDA pin on the falling edges of the
SCL clock.
VREF (Pin 7): 2.5V Reference Output. Bypass to GND
with a minimum 2.2µF ceramic capacitor. The internal
reference may be overdriven by an external 2.5V reference at this pin.
REFCOMP (Pin 8): Reference Buffer Output. Bypass
to GND with 10µF and 0.1µF ceramic capacitors in
parallel. Nominal output voltage is 4.096V. The internal
reference buffer driving this pin is disabled by grounding VREF , allowing REFCOMP to be overdriven by an
external source.
GND (Pins 9-11, 18-20): Ground. All GND pins must
be connected to a solid ground plane.
VDD (Pins 12, 13, 21): 5V Supply. The range of VDD is
4.75V to 5.25V. Bypass VDD to GND with a 10µF ceramic
capacitor in parallel with three 0.1µF ceramic capacitors,
one located as close as possible to each pin.
SDA (Pin 17): Bidirectional Serial Data Line of the I2C
Interface. In transmitter mode (read), the conversion
result is output at the SDA pin, while in receiver mode
(write), the DIN word is input at the SDA pin to configure the ADC. The pin is high impedance during the
data input mode and is an open-drain output (requires
an appropriate pull-up device to VDD) during the data
output mode.
CH0-CH2 (Pins 22-24): Channel 0 to Channel 2 Analog
Inputs. CH0-CH2 can be configured as single-ended
or differential input channels. See the Analog Input
Multiplexer section.
Exposed Pad (Pin 25): Ground. Must be soldered
directly to ground plane.
AD0 (Pin 14): Chip Address Control Pin. This pin is
configured as a three-state (LOW, HIGH, floating) address control bit for the device I2C address. See Table 2
for address selection.
2309fd
LTC2309
Pin Functions (TSSOP)
REFCOMP (Pin 1): Reference Buffer Output. Bypass
to GND with 10µF and 0.1µF ceramic capacitors in
parallel. Nominal output voltage is 4.096V. The internal
reference buffer driving this pin is disabled by grounding VREF , allowing REFCOMP to be overdriven by an
external source.
GND (Pins 2, 8 , 9): Ground. All GND pins must be
connected to a solid ground plane.
VDD (Pins 3, 10): 5V Supply. The range of VDD is 4.75V
to 5.25V. Bypass VDD to GND with a 10µF ceramic capacitor in parallel with two 0.1µF ceramic capacitors,
one located as close as possible to each pin.
AD0 (Pin 4): Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, floating) address
control bit for the device I2C address. See Table 2 for
address selection.
AD1 (Pin 5): Chip Address Control Pin. This pin is
configured as a three-state (LOW, HIGH, floating)
address control bit for the device I2C address. See
Table 2 for address selection.
SCL (Pin 6): Serial Clock Pin of the I2C Interface. The
LTC2309 can only act as a slave and the SCL pin only
accepts an external serial clock. Data is shifted into
the SDA pin on the rising edges of the SCL clock and
output through the SDA pin on the falling edges of the
SCL clock.
SDA (Pin 7): Bidirectional Serial Data Line of the I2C
Interface. In transmitter mode (read), the conversion
result is output at the SDA pin, while in receiver mode
(write), the DIN word is input at the SDA pin to configure the ADC. The pin is high impedance during the
data input mode and is an open-drain output (requires
an appropriate pull-up device to VDD) during the data
output mode.
CH0-CH7 (Pins 11-18): Channel 0 to Channel 7 Analog
Inputs. CH0-CH7 can be configured as single-ended
or differential input channels. See the Analog Input
Multiplexer section.
COM (Pin 19): Common Input. This is the reference
point for all single-ended inputs. It must be free of
noise and should be connected to ground for unipolar
conversions and midway between GND and REFCOMP
for bipolar conversions.
VREF (Pin 20): 2.5V Reference Output. Bypass to GND
with a minimum 2.2µF ceramic capacitor. The internal
reference may be overdriven by an external 2.5V reference at this pin.
2309fd
LTC2309
FUNCTIONAL Block Diagram
VDD
LTC2309
CH0
AD1
AD0
CH1
CH2
CH3
CH4
ANALOG
INPUT
MUX
+
–
I2C
PORT
12-BIT
SAR ADC
SCL
SDA
CH5
CH6
CH7
INTERNAL
2.5V REF
COM
VREF
8k
GAIN = 1.6384x
REFCOMP
2308 BD
GND
TIMING DIAGRAM
Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
SDA
tLOW
tf
tSU(DAT)
tr
tHD(SDA)
tf
tBUF
tr
tSP
SCL
S
tHD(SDA)
tHD(DAT)
tHIGH
tSU(STA)
Sr
tSU(STO)
P
S
2309 TD
S = START, Sr = REPEATED START, P = STOP
2309fd
LTC2309
Applications Information
Overview
Programming the LTC2309
The LTC2309 is a low noise, 8-channel, 12-bit successive approximation register (SAR) A/D converter with an
I2C compatible serial interface. The LTC2309 includes a
precision internal reference and a configurable 8-channel analog input multiplexer (MUX). The ADC may be
configured to accept single-ended or differential signals
and can operate in either unipolar or bipolar mode. A
sleep mode option is also provided to further reduce
power during inactive periods.
The various modes of operation of the LTC2309 are
programmed by a 6-bit DIN word. The SDI input data
bits are loaded on the rising edge of SCL during a write
operation, with the S/D bit loaded on the first rising edge
and the SLP bit on the sixth rising edge (see Figure 8b
in the I2C Interface section). The input data word is
defined as follows:
The LTC2309 communicates through a 2-wire I2C
compatible serial interface. Conversions are initiated
by signaling a STOP condition after the part has been
successfully addressed for a read/write operation. The
device will not acknowledge (NACK) an external request
until the conversion is finished. After a conversion is
finished, the device is ready to accept a read/write
request. Once the LTC2309 is addressed for a read
operation, the device begins outputting the conversion result under the control of the serial clock (SCL).
There is no latency in the conversion result. There are
12 bits of output data followed by 4 trailing zeros. Data
is updated on the falling edges of SCL, allowing the
user to reliably latch data on the rising edge of SCL. A
write operation may follow the read operation by using
a repeat START or a STOP condition may be given to
start a new conversion. By selecting a write operation,
the ADC can be programmed with a 6-bit DIN word. The
DIN word configures the MUX and programs various
modes of operation of the ADC.
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
During a conversion, the internal 12-bit capacitive
charge redistribution DAC output is sequenced through
a successive approximation algorithm by the SAR starting from the most significant bit (MSB) to the least
significant bit (LSB). The sampled input is successively
compared with binary weighted charges supplied by
the capacitive DAC using a differential comparator. At
the end of a conversion, the DAC output balances the
analog input. The SAR contents (a 12-bit data word)
that represent the sampled analog input are loaded into
12 output latches that allow the data to be shifted out
via the I2C interface.
S/D O/S S1
S0 UNI SLP
O/S = ODD/SIGN BIT
S1 = CHANNEL SELECT BIT 1
S0 = CHANNEL SELECT BIT 0
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
Analog Input Multiplexer
The analog input MUX is programmed by the S/D,
O/S, S1 and S0 bits of the DIN word. Table 1 lists the
MUX configurations for all combinations of the configuration bits. Figure 1a shows several possible MUX
configurations and Figure 1b shows how the MUX can
be reconfigured from one conversion to the next.
Driving the Analog Inputs
The analog inputs of the LTC2309 are easy to drive.
Each of the analog inputs can be used as a single-ended
input relative to the COM pin (CH0-COM, CH1-COM,
etc.) or in differential input pairs (CH0 and CH1, CH2
and CH3, CH4 and CH5, CH6 and CH7). Figure 2 shows
how to drive COM for single-ended inputs in unipolar
and bipolar modes. Regardless of the MUX configuration, the “+” and “–” inputs are sampled at the same
instant. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection
of the sample-and-hold circuit. The inputs draw only
one small current spike while charging the sample-andhold capacitors during the acquire mode. In conversion
2309fd
10
LTC2309
Applications Information
4 Differential
+ (–)
– (+) {
+ (–)
– (+) {
CH0
CH1
+ (–)
– (+) {
+ (–)
– (+) {
CH4
CH5
8 Single-Ended
+
+
+
+
+
+
+
+
CH2
CH3
CH6
CH7
1st Conversion
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
+
–{
+
–{
2nd Conversion
CH2
CH3
–
+
{
CH2
CH3
CH4
CH5
+
+
{
CH4
CH5
COM
(UNUSED)
COM (–)
COM (–)
2328 F01b
Figure 1b. Changing the MUX Assignments “On the Fly”
Combinations of Differential
and Single-Ended
+
–{
CH0
CH1
–
+{
+
+
+
+
CH2
CH3
Unipolar Mode
Bipolar Mode
COM
CH4
CH5
CH6
CH7
COM (–)
REFCOMP/2
+
–
COM
2328 F02
Figure 2. Driving COM in Unipolar and Bipolar Modes
2309 F01a
Figure 1a. Example of MUX Configurations
Table 1. Channel Configuration
S/D O/S S1
S0
0
1
+
–
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
–
2
3
+
–
4
5
+
–
6
7
+
–
COM
Input Filtering
+
–
+
–
+
–
+
+
+
+
+
+
+
+
+
mode, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is
low, the ADC inputs can be driven directly. Otherwise,
more acquisition time should be allowed for a source
with higher impedance.
–
–
–
–
–
–
–
–
The noise and distortion of the input amplifier and
other circuitry must be considered since they will add
to the ADC noise and distortion. Therefore, noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient
for many applications.
The analog inputs of the LTC2309 can be modeled as
a 55pF capacitor (CIN) in series with a 100Ω resistor
(RON), as shown in Figure 3a. CIN gets switched to the
selected input once during each conversion. Large filter
RC time constants will slow the settling of the inputs.
It is important that the overall RC time constants be
short enough to allow the analog inputs to completely
settle to 12-bit resolution within the acquisition time
(tACQ) if DC accuracy is important.
2309fd
11
LTC2309
Applications Information
When using a filter with a large CFILTER value (e.g. 1µF),
the inputs do not completely settle and the capacitive
input switching currents are averaged into a net DC
current (IDC). In this case, the analog input can be modeled by an equivalent resistance (REQ = 1/(fSMPL • CIN))
in series with an ideal voltage source (VREFCOMP/2), as
shown in Figure 3b. The magnitude of the DC current
is then approximately IDC = (VIN – VREFCOMP/2)/REQ,
which is roughly proportional to VIN. To prevent large
DC drops across the resistor RFILTER, a filter with a small
resistor and large capacitor should be chosen. When
running at the maximum throughput rate of 14ksps,
the input current equals 1.5µA at VIN = 4.096V, which
amounts to a full-scale error of 0.5LSB when using a
filter resistor (RFILTER) of 333Ω. Applications requiring
lower sample rates can tolerate a larger filter resistor
for the same amount of full-scale error.
ANALOG
INPUT
50Ω
CH0
LTC2309
2000pF
COM
0.1µF
10µF
REFCOMP
2309 F04a
Figure 4a. Optional RC Input Filtering for Single-Ended Input
50Ω
DIFFERENTIAL
ANALOG
INPUTS
50Ω
1000pF
CH0
LTC2309
1000pF
CH1
1000pF
0.1µF
10µF
REFCOMP
2309 F04b
VIN
INPUT
CH0-CH7
RSOURCE
RON
100Ω
LTC2309
CIN
55pF
CFILTER
2309 F03a
Figure 3a. Analog Input Equivalent Circuit
VIN
RFILTER
IDC
Figure 4b. Optional RC Input Filtering for Differential Inputs
self heating and from damage that may occur during
soldering. Metal film surface mount resistors are much
less susceptible to both problems.
Dynamic Performance
INPUT
CH0-CH7
LTC2309
CFILTER
+
–
REQ
1/(fSMPL • CIN)
VREFCOMP/2
2309 F03b
Figure 3b. Analog Input Equivalent
Circuit for Large Filter Capacitances
Figures 4a and 4b show examples of input filtering for
single-ended and differential inputs. For the singleended case in Figure 4a, a 50Ω source resistor and a
2000pF capacitor to ground on the input will limit the
input bandwidth to 1.6MHz. High quality capacitors and
resistors should be used in the RC filter since these
components can add distortion. NPO and silver mica
type dielectric capacitors have excellent linearity. Carbon
surface mount resistors can generate distortion from
Fast Fourier Transform (FFT) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is
band-limited to frequencies from above DC and below
half the sampling frequency. Figure 5 shows a typical
SINAD of 73.3dB with a 14kHz sampling rate and a
1kHz input. An SNR of 73.4dB can be achieved with
the LTC2309.
2309fd
12
LTC2309
Applications Information
0
–20
MAGNITUDE (dB)
internal reference buffer can also be overdriven from
1V to VDD, as shown in Figure 6c. To do so, VREF must
be grounded to disable the reference buffer.
SNR = 73.4dB
SINAD = 73.3dB
THD = –88dB
–40
–60
–80
2.5V
BANDGAP
REFERENCE
2.2µF
–100
–120
–140
R1
8k
VREF
REFCOMP
4.096V
0
2
1
5
4
3
FREQUENCY (kHz)
6
7
REFERENCE
AMP
10µF
R2
0.1µF
2309 G03
GND
Figure 5. 1kHz Sine Wave 8192 Point FFT Plot
R3
LTC2309
2309 F06a
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the
RMS sum of all harmonics of the input signal to the
fundamental itself. The out-of-band harmonics alias into
the frequency band between DC and half the sampling
frequency (fSMPL/2). THD is expressed as:
THD = 20 log
Figure 6a. LTC2309 Reference Circuit
5V
0.1µF
VIN
LT1790A-2.5
VOUT
V22 + V32 + V42... + VN2
2.2µF
V1
The LTC2309 has an on-chip, temperature compensated bandgap reference that is factory trimmed to
2.5V (Refer to Figure 6a). It is internally connected to a
reference amplifier and is available at VREF . VREF should
be bypassed to GND with a 2.2μF ceramic capacitor to
minimize noise. An 8k resistor is in series with the output
so that it can be easily overdriven by an external reference if more accuracy and/or lower drift are required,
as shown in Figure 6b. The reference amplifier gains
the VREF voltage by 1.638 to 4.096V at REFCOMP. To
compensate the reference amplifier, bypass REFCOMP
with a 10μF ceramic capacitor in parallel with a 0.1μF
ceramic capacitor for best noise performance. The
LTC2309
REFCOMP
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
Internal Reference
VREF
10µF
0.1µF
GND
2309 F06b
Figure 6b. Using the LT®1790A-2.5 as an External Reference
5V
0.1µF
VREF
VIN
LTC2309
LT1790A-4.096
VOUT
REFCOMP
10µF
0.1µF
GND
2309 F06c
Figure 6c. Overdriving REFCOMP Using the LT1790A-4.096
2309fd
13
LTC2309
Applications Information
Internal Conversion Clock
The START and STOP Conditions
The internal conversion clock is factory trimmed to
achieve a typical conversion time (tCONV) of 1.3μs and
a maximum conversion time of 1.8μs over the full
operating temperature range.
Referring to Figure 7, a START (S) condition is generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The bus is considered to be busy after the
START condition. When the data transfer is finished, a
STOP (P) condition is generated by transitioning SDA
from LOW to HIGH while SCL is HIGH. The bus is free
after a STOP condition is generated. START and STOP
conditions are always generated by the master.
I2C Interface
The LTC2309 communicates through an I2C interface.
The I2C interface is a 2-wire open-drain interface supporting multiple devices and multiple masters on a
single bus. The connected devices can only pull the
serial data line (SDA) LOW and can never drive it HIGH.
SDA is required to be externally connected to the supply through a pull-up resistor. When the data line is not
being driven LOW, it is HIGH. Data on the I2C bus can
be transferred at rates up to 100kbits/s in the standard
mode and up to 400kbits/s in the fast mode. The VDD
power should not be removed from the LTC2309 when
the I2C bus is active to avoid loading the I2C bus lines
through the internal ESD protection diodes.
Each device on the I2C bus is recognized by a unique
address stored in the device and can only operate either
as a transmitter or receiver, depending on the function
of the device. A device can also be considered as a
master or a slave when performing data transfers. A
master is the device which initiates a data transfer on
the bus and generates the clock signals to permit the
transfer. Devices addressed by the master are considered slaves.
The LTC2309 can only be addressed as a slave (see
Table 2). Once addressed, it can receive configuration
bits (DIN word) or transmit the last conversion result. The
serial clock line (SCL) is always an input to the LTC2309
and the serial data line (SDA) is bidirectional. The device
supports the standard mode and the fast mode for data
transfer speeds up to 400kbits/s (see the Timing Diagram
section for definition of the I2C timing).
When the bus is in use, it stays busy if a repeated
START (Sr) is generated instead of a STOP condition.
The repeated START timing is functionally identical to
the START and is used for writing and reading from the
device before the initiation of a new conversion.
START Condition
STOP Condition
SDA
S
SCL
SDA
SCL
P
2309 F07
Figure 7. Timing Diagrams of START and STOP Conditions
Data Transferring
After the START condition, the I2C bus is busy and
data transfer can begin between the master and the
addressed slave. Data is transferred over the bus in
groups of nine bits, one byte followed by one acknowledge (ACK) bit. The master releases the SDA
line during the ninth SCL clock cycle. The slave device
can issue an ACK by pulling SDA LOW or issue a Not
Acknowledge (NACK) by leaving the SDA line high
impedance (the external pull-up resistor will hold the
line high). Change of data only occurs while the SCL
line is LOW.
Data Format
After a START condition, the master sends a 7-bit
address followed by a read/write (R/W) bit. The R/W
bit is 1 for a read request and 0 for a write request.
If the 7-bit address matches one of the LTC2309’s
9 pin-selectable addresses, the ADC is selected. When
2309fd
14
LTC2309
Applications Information
the ADC is addressed during a conversion, it will not
acknowledge R/W requests and will issue a NACK by
leaving the SDA line HIGH. If the conversion is complete, the LTC2309 issues an ACK by pulling the SDA
line LOW. The LTC2309 has two registers. The 12-bit
wide output register contains the last conversion result.
The 6-bit wide input register configures the input MUX
and the operating mode of the ADC.
Output Data Format
The output register contains the last conversion result.
After each conversion is completed, the device automatically enters either nap or sleep mode depending
on the setting of the SLP bit (see Nap Mode and Sleep
Mode sections). When the LTC2309 is addressed for
1
2
3
4
5
6
7
8
9
a read operation, it acknowledges by pulling SDA
LOW and acts as a transmitter. The master/receiver
can read up to two bytes from the LTC2309. After a
complete read operation of 2 bytes, a STOP condition
is needed to initiate a new conversion. The device will
NACK subsequent read operations while a conversion
is being performed.
The data output stream is 16 bits long and is shifted
out on the falling edges of SCL (see Figure 8a). The
first bit is the MSB and the 12th bit is the LSB of the
conversion result. The remaining four bits are zero.
Figures 14 and 15 are the transfer characteristics for
the bipolar and unipolar modes. Data is output on the
SDA line in 2’s complement format for bipolar readings
or in straight binary for unipolar readings.
1
2
3
4
5
6
7
8
9
•••
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
START BY
MASTER
B11
ACK BY
ADC
B10
B9
B8
B7
B6
B5
ACK BY
MASTER
MOST SIGNIFICANT DATA BYTE
ADDRESS FRAME
•••
B4
READ 1 BYTE
1
SCL
(CONTINUED)
2
3
4
5
6
7
8
9
•••
CONVERSION
INITIATED
SDA
(CONTINUED)
•••
B3
B2
B1
STOP
BY MASTER
B0
LEAST SIGNIFICANT DATA BYTE
READ 1 BYTE
NACK BY
MASTER
2309 F08a
Figure 8a. Timing Diagram for Reading from the LTC2309
2309fd
15
LTC2309
Applications Information
Input Data Format
When the LTC2309 is addressed for a write operation,
it acknowledges by pulling SDA LOW during the LOW
period before the 9th cycle and acts as a receiver. The
master/transmitter can then send 1 byte to program the
device. The input byte consists of the 6-bit DIN word
followed by two bits that are ignored by the ADC and
are considered don’t cares (X) (see Figure 8b). The
input bits are latched on the rising edge of SCL during
the write operation.
After power-up, the ADC initiates an internal reset
cycle which sets the DIN word to all 0s (S/D = O/S =
S0 = S1 = UNI = SLP = 0). A write operation may be
performed if the default state of the ADC’s configuration
is not desired. Otherwise, the ADC must be properly
addressed and followed by a STOP condition to initiate
a conversion.
read/write operation will also initiate new conversion,
but the output result may not be valid due to lack of
adequate acquisition time (see Acquisition section).
LTC2309 Address
The LTC2309 has two address pins (AD0 and AD1) that
may be tied HIGH, LOW, or left floating to enable one
of 9 possible addresses (see Table 2).
In addition to the configurable addresses listed in
Table 2, the LTC2309 also contains a global address
(1101011) which may be used for synchronizing multiple LTC2309s or other I2C LTC230X SAR ADCs (see
Synchronizing Multiple LTC2309s with Global Address
Call section).
Table 2. Address Assignment
Initiating a New Conversion
The LTC2309 awakens from either nap or sleep when
properly addressed for a read/write operation. A STOP
command may then be issued after performing the
read/write operation to trigger a new conversion.
Issuing a STOP command after the 8th SCL clock pulse
of the address frame and before the completion of a
1
2
3
4
5
6
7
8
9
1
2
AD1
AD0
ADDRESS
LOW
LOW
0001000
LOW
Float
0001001
LOW
HIGH
0001010
Float
HIGH
0001011
Float
Float
0011000
Float
LOW
0011001
HIGH
LOW
0011010
HIGH
Float
0011011
HIGH
HIGH
0101000
3
4
5
6
7
8
9
SCL
CONVERSION
INITIATED
SDA
A6
A5
A4
A3
A2
A1
START BY
MASTER
A0
R/W
S/D
ACK BY
ADC
ADDRESS FRAME
O/S
S1
S0
UNI
SLP
DIN WORD
WRITE 1 BYTE
X
X
ACK BY
ADC
STOP BY
MASTER
2309 F08b
Figure 8b. Timing Diagram for Writing to the LTC2309
2309fd
16
LTC2309
Applications Information
Continuous Read
In applications where the same input channel is sampled
each cycle, conversions can be continuously performed
and read without a write cycle (see Figure 9). The DIN
word remains unchanged from the last value written
into the device. If the device has not been written to
since power-up, the DIN word defaults to all 0s (S/D =
O/S = S0 = S1 = UNI = SLP = 0). At the end of a read
operation, a STOP condition may be given to start a new
conversion. At the conclusion of the conversion cycle,
the next result may be read using the method described
above. If the conversion cycle is not concluded and a
valid address selects the device, the LTC2309 gener-
S
7-BIT ADDRESS
CONVERSION
R ACK READ
NAP
P
ates a NACK signal indicating the conversion cycle is
in progress.
Continuous Read/Write
Once the conversion cycle is complete, the LTC2309
can be written to and then read from using the repeated
START (Sr) command. Figure 10 shows a cycle which
begins with a data write, a repeated START, followed
by a read and concluded with a STOP command. After
all 16 bits are read out, a conversion may be initiated
by issuing a STOP command. The following conversion will be performed using the newly programmed
data.
S
7-BIT ADDRESS
DATA OUTPUT CONVERSION
R ACK READ
NAP
DATA
OUTPUT
P
CONVERSION
2309 F09
Figure 9. Consecutive Reading with the Same Configuration
S
7-BIT ADDRESS
CONVERSION
NAP
W ACK
WRITE
DATA INPUT
Sr
7-BIT ADDRESS
ADDRESS
R ACK READ
DATA
OUTPUT
P
CONVERSION
2309 F10
Figure 10. Write, Read, START Conversion
2309fd
17
LTC2309
Applications Information
Synchronizing Multiple LTC2309s with a Global
Address Call
Nap Mode
In applications where several LTC2309s or other I2C SAR
ADCs from Linear Technology Corporation are used on
the same I2C bus, all converters can be synchronized
through the use of a global address call. Prior to issuing the global address call, all converters must have
completed a conversion cycle. The master then issues
a START, followed by the global address 1101011, and
a write request. All converters will be selected and acknowledge the request. The master then sends a write
byte (optional) followed by the STOP command. This will
update the channel selection (optional) and simultaneously initiate a conversion for all ADCs on the bus (see
Figure 11). In order to synchronize multiple converters
without changing the channel, a STOP command may
be issued after acknowledgement of the global write
command. Global read commands are not allowed and
the converters will NACK a global read request.
The ADC enters nap mode after a conversion is complete (tCONV) if the SLP bit is set to a logic 0. The supply current decreases to 210μA in nap mode between
conversions, thereby reducing the average power
dissipation as the sample rate decreases. For example,
the LTC2309 draws an average of 300µA at a 1ksps
sampling rate. The LTC2309 keeps only the reference
(VREF) and reference buffer (REFCOMP) circuitry active
when in nap mode.
Sleep Mode
The ADC enters sleep mode after a conversion is complete (tCONV) if the SLP bit is set to a logic 1. The ADC
draws only 7µA in sleep mode, provided that none of
the digital inputs are switching. When the LTC2309 is
properly addressed, the ADC is released from sleep mode
and requires 200ms (tREFWAKE) to wake up and charge
the respective 2.2μF and 10μF bypass capacitors on the
VREF and REFCOMP pins. A new conversion should not
be initiated before this time, as shown in Figure 12.
SCL
SDA
LTC2309
S
LTC2309
GLOBAL ADDRESS
CONVERSION
W ACK
NAP
LTC2309
WRITE (OPTIONAL)
DATA OUTPUT
P
CONVERSION OF ALL LTC2309s
2309 F11
Figure 11. Synchronous Multiple LTC2309s with a Global Address Call
S
7-BIT ADDRESS
CONVERSION
SLEEP
R/W ACK
tREFWAKE
P
CONVERSION
2309 F12
Figure 12. Exiting Sleep Mode and Starting a New Conversion
2309fd
18
LTC2309
Applications Information
If a write operation is being performed, acquisition of
the input signal begins on the falling edge of the sixth
clock cycle after the DIN word has been shifted in, as
shown in Figure 13b. The LTC2309 will acquire the
signal from the input channel that was most recently
programmed by the DIN word. A minimum of 240ns is
required to acquire the input signal before initiating a
new conversion.
Acquisition
The LTC2309 begins acquiring the input signal at different instances depending on whether a read or write
operation is being performed. If a read operation is
being performed, acquisition of the input signal begins
on the rising edge of the 9th clock pulse following the
address frame, as shown in Figure 13a.
1
2
3
4
5
6
7
8
9
1
2
SCL
ACQUISITION BEGINS
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
B11
B10
2309 F13a
tACQ
Figure 13a. Timing Diagram Showing Acquisition During a Read Operation
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
ACQUISITION BEGINS
SDA
A2
A1
A0
R/W
S/D
O/S
S1
S0
UNI SLP
X
X
tACQ
2309 F13b
111...111
011...111
111...110
BIPOLAR
ZERO
011...110
OUTPUT CODE
OUTPUT CODE (TWO’S COMPLEMENT)
Figure 13b. Timing Diagram Showing Acquisition During a Write Operation
000...001
000...000
111...111
111...110
FS = 4.096V
1LSB = FS/212
1LSB = 1mV
100...001
100...000
–FS/2
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
100...001
100...000
011...111 UNIPOLAR
ZERO
011...110
FS = 4.096V
1LSB = FS/212
1LSB = 1mV
000...001
000...000
0V
FS – 1LSB
INPUT VOLTAGE (V)
2309 F14
Figure 14. Bipolar Transfer Characteristics (2’s Complement)
2309 F15
Figure 15. Unipolar Transfer Characteristics (Straight Binary)
2309fd
19
LTC2309
Applications Information
Board Layout and Bypassing
To obtain the best performance, a printed circuit board with
a solid ground plane is required. Layout for the printed
board should ensure digital and analog signal lines are
separated as much as possible. Care should be taken not
to run any digital signals alongside an analog signal. All
analog inputs should be shielded by GND. VREF , REFCOMP
and VDD should be bypassed to the ground plane as close
to the pin as possible. Maintaining a low impedance path
for the common return of these bypass capacitors is
essential to the low noise operation of the ADC. These
traces should be as wide as possible. See Figures 16a-e
for a suggested layout.
2309 F16a
Figure 16a. Top Silkscreen
2309fd
20
LTC2309
Applications Information
2309 F16b
Figure 16b. Layer 1 Component Side
Figure 16c. Layer 2 Ground Plane
2309 F16c
2309fd
21
LTC2309
Applications Information
Figure 16d. Layer 3 Power Plane
2309 F16d
2309 F16e
Figure 16e. Layer Back Solder Side
22
2309fd
LTC2309
Package Description
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 ±0.05
4.50 ± 0.05
2.45 ± 0.05
3.10 ± 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ± 0.05
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 s 45° CHAMFER
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
2
2.45 ± 0.10
(4-SIDES)
(UF24) QFN 0105
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2309fd
23
LTC2309
Package Description
F Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1650)
6.40 – 6.60*
(.252 – .260)
1.05 ±0.10
6.60 ±0.10
20 19 18 17 16 15 14 13 12 11
4.50 ±0.10
0.45 ±0.05
6.40
(.252)
BSC
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50**
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
1.10
(.0433)
MAX
0° – 8°
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65
(.0256)
BSC
0.19 – 0.30
(.0075 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
F20 TSSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
2309fd
24
LTC2309
Revision History
REV
DATE
DESCRIPTION
D
7/10
Revised Block Diagram
(Revision history begins at Rev D)
PAGE NUMBER
Changed AVDD and DVDD pins to VDD only
Revised Note 2
1
2, 4-9, 20
5
Consolidated AVDD and DVDD into VDD and revised VREF and REFCOMP pin descriptions in Pin Functions section
Revised Figures 6b and 6c and Internal Reference paragraph, and added text to I2C Interface in Applications
Information section
7, 8
13, 14
Changed NAK to NACK in Figure 8a
15
Revised Typical Application
26
2309fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
25
LTC2309
Typical Application
Driving the LTC2309 with ±10V Input Signals Using a Precision Attenuator
5V
IN
OUT
LT1790-2.5
0.1µF
1µF
GND
10V
5V
7
8
450k
50k
9 150k
10
10µF
–
450k
+
1 450k
4pF
3
47pF
450k
2 150k
±10V
INPUT
SIGNAL
6 100Ω
LT1991
0.1µF
AD1 AD0
VDD
CH0
CH3
4pF
4
CH4
5
–10V
1.7k
LTC2309
CH1
CH2
50k
1.7k
ANALOG
INPUT
MUX
+
–
I2C
PORT
12-BIT
SAR ADC
SCL
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC)
SDA
CH5
CH6
INTERNAL
2.5V REF
CH7
COM
GND
VREF
2.2µF
REFCOMP
0.1µF
10µF
2309 TA02
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2309fd
26 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
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LT 0710 REV D • PRINTED IN USA
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