LTC2333-18
Buffered 8-Channel, 18-Bit, 800ksps
Differential ±10.24V ADC with
30VP-P Common Mode Range
DESCRIPTION
FEATURES
Eight Buffered Multiplexed Channels
nn 800ksps Throughput
nn 500pA/12nA Maximum Input Leakage at 85°C/125°C
nn ±3LSB INL (Maximum ±10.24V Range)
nn Guaranteed 18-Bit, No Missing Codes
nn Differential, Wide Common Mode Range Inputs
nn 8-Channel Multiplexer with SoftSpan Input Ranges:
±10.24V, 0V to 10.24V, ±5.12V, 0V to 5.12V
±12.5V, 0V to 12.5V, ±6.25V, 0V to 6.25V
nn 96.4dB Single-Conversion SNR (Typical)
nn −110dB THD (Typical) at f = 2kHz
IN
nn 128dB CMRR, –125dB Active Crosstalk (Typical)
nn 420ns Step Response (Full-Scale, 0.005% Settling)
nn Rail-to-Rail Input Overdrive Tolerance
nn Programmable Sequencer with No-Latency Control
nn Integrated Reference and Buffer (4.096V)
nn SPI CMOS (1.8V to 5V) and LVDS Serial I/O
nn 268mW Power Dissipation (Typical)
nn 48-Lead (7mm × 7mm) LQFP Package
The LTC®2333-18 is an 18-bit, low noise 8-channel multiplexed successive approximation register (SAR) ADC with
buffered differential, wide common mode range picoamp
inputs. Operating from a 5V low voltage supply, flexible
high voltage supplies, and using the internal reference
and buffer, this SoftSpan™ ADC can be configured on a
conversion-by-conversion basis to accept ±10.24V, 0V to
10.24V, ±5.12V, or 0V to 5.12V signals on any channel.
Alternately, the ADC may be programmed to cycle through
a sequence of channels and ranges without further user
intervention.
APPLICATIONS
The LTC2333-18 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces.
nn
The integrated picoamp-input analog buffers, wide input
common mode range and 128dB CMRR of the LTC233318 allow the ADC to directly digitize a variety of signals
using minimal board space and power. This input signal
flexibility, combined with ±3LSB INL, no missing codes
at 18 bits, and 96.4dB SNR, makes the LTC2333-18 an
ideal choice for many high voltage applications requiring
wide dynamic range.
Direct Sensor Measurement
nn Programmable Logic Controllers
nn Industrial Process Control
nn Test and Measurement
nn
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673, 9197235.
TYPICAL APPLICATION
15V
0.1µF
5V
0.1µF
2.2µF
Integral Nonlinearity vs
Output Code and Channel
1.8V TO 5V
0.1µF
CMOS OR LVDS
I/O INTERFACE
ARBITRARY
0V
0V
–10V
–5V
+10V
0V
0V
–10V
–10V
IN0+
IN0–
UNIPOLAR
VDDLBYP
1.5
OVDD LVDS/CMOS
PD
SDO
SCKO
SCKI
SDI
CS
BUSY
CNV
18-BIT
SAMPLING
ADC
MUX
IN7+
IN7–
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
ALL CHANNELS
1.0
SAMPLE
CLOCK
0.5
0
–0.5
–1.0
–1.5
DIFFERENTIAL INPUTS IN+/IN– WITH
WIDE INPUT COMMON MODE RANGE
VDD
LTC2333-18
• • •
TRUE BIPOLAR
+10V
VCC
BUFFERS
INL ERROR (LSB)
+10V
FULLY
DIFFERENTIAL
+5V
2.0
VEE REFBUF
EIGHT BUFFERED
CHANNELS
REFIN
–2.0
–131072
GND
233318 TA01a
0.1µF
47µF
0.1µF
–65536
0
65536
OUTPUT CODE
131072
233318 TA01b
–15V
233318f
For more information www.linear.com/LTC2333-18
1
LTC2333-18
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
ORDER INFORMATION
48
47
46
45
44
43
42
41
40
39
38
37
IN7+
IN7–
GND
VEE
GND
VDD
VDD
GND
VDDLBYP
CS
BUSY
SDI
TOP VIEW
IN6– 1
IN6+ 2
IN5– 3
IN5+ 4
IN4– 5
IN4+ 6
IN3– 7
IN3+ 8
IN2– 9
IN2+ 10
IN1– 11
IN1+ 12
36
35
34
33
32
31
30
29
28
27
26
25
GND
SDO–
SDO+
SCKO–/SDO
SCKO+/SCKO
OVDD
GND
SCKI–/SCKI
SCKI+
SDI–
SDI+
GND
IN0– 13
IN0+ 14
GND 15
VCC 16
VEE 17
GND 18
REFIN 19
GND 20
REFBUF 21
PD 22
LVDS/CMOS 23
CNV 24
Supply Voltage (VCC)......................–0.3V to (VEE + 40V)
Supply Voltage (VEE)................................. –17.4V to 0.3V
Supply Voltage Difference (VCC – VEE).......................40V
Supply Voltage (VDD)...................................................6V
Supply Voltage (OVDD).................................................6V
Internal Regulated Supply Bypass (VDDLBYP).... (Note 3)
Analog Input Voltage
IN0+ to IN7+,
IN0– to IN7– (Note 4).......... (VEE – 0.3V) to (VCC + 0.3V)
REFIN..................................................... –0.3V to 2.8V
REFBUF, CNV (Note 5).............. –0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 5)...... –0.3V to (OVDD + 0.3V)
Digital Output Voltage (Note 5)... –0.3V to (OVDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC2333C................................................. 0°C to 70°C
LTC2333I..............................................–40°C to 85°C
LTC2333H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
LX PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
TJMAX = 150°C, θJA = 53°C/W
http://www.linear.com/product/LTC2333-18#orderinfo
TRAY
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2333CLX-18#PBF
LTC2333LX-18
48-Lead (7mm × 7mm) Plastic LQFP
0°C to 70°C
LTC2333ILX-18#PBF
LTC2333LX-18
48-Lead (7mm × 7mm) Plastic LQFP
–40°C to 85°C
LTC2333HLX-18#PBF
LTC2333LX-18
48-Lead (7mm × 7mm) Plastic LQFP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
233318f
2
For more information www.linear.com/LTC2333-18
LTC2333-18
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 6)
SYMBOL
PARAMETER
CONDITIONS
VIN+
Absolute Input Range
(IN0+ to IN7+)
(Note 7)
l
VEE + 4
VCC – 4
V
VIN–
Absolute Input Range
(IN0– to IN7–)
(Note 7)
l
VEE + 4
VCC – 4
V
SoftSpan 7: ±2.5 • VREFBUF Range (Note 7)
SoftSpan 6: ±2.5 • VREFBUF/1.024 Range (Note 7)
SoftSpan 5: 0V to 2.5 • VREFBUF Range (Note 7)
SoftSpan 4: 0V to 2.5 • VREFBUF/1.024 Range (Note 7)
SoftSpan 3: ±1.25 • VREFBUF Range (Note 7)
SoftSpan 2: ±1.25 • VREFBUF/1.024 Range (Note 7)
SoftSpan 1: 0V to 1.25 • VREFBUF Range (Note 7)
SoftSpan 0: 0V to 1.25 • VREFBUF/1.024 Range (Note 7)
l
–2.5 • VREFBUF
l –2.5 • VREFBUF/1.024
l
0
l
0
l
–1.25 • VREFBUF
l –1.25 • VREFBUF/1.024
l
0
l
0
2.5 • VREFBUF
2.5 • VREFBUF/1.024
2.5 • VREFBUF
2.5 • VREFBUF/1.024
1.25 • VREFBUF
1.25 • VREFBUF/1.024
1.25 • VREFBUF
1.25 • VREFBUF/1.024
V
V
V
V
V
V
V
V
VIN+ – VIN– Input Differential Voltage
Range
VCM
Input Common Mode Voltage (Note 7)
Range
MIN
TYP
VEE + 4
VCC – 4
V
(VCC − VEE)
V
(Note 8)
l
−(VCC − VEE)
IOVERDRIVE Input Overdrive
Current Tolerance
VIN+ > VCC, VIN− > VCC (Note 8)
VIN+ < VEE, VIN− < VEE (Note 8)
l
l
0
C-Grade and I-Grade
H-Grade
l
l
Analog Input Leakage Current
RIN
Analog Input Resistance
CIN
Analog Input Capacitance
CMRR
Input Common Mode
Rejection Ratio
10
5
For Each Pin
VIN+ = VIN− = 18VP-P 200Hz Sine
l
105
1.3
VIHCNV
CNV High Level Input Voltage
l
VILCNV
CNV Low Level Input Voltage
l
IINCNV
CNV Input Current
VIN = 0V to VDD
UNITS
l
VIN+ – VIN– Input Differential Overdrive
Tolerance
IIN
MAX
500
12
pA
pA
nA
>1000
GΩ
3
pF
128
dB
V
–10
l
mA
mA
0.5
V
10
μA
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
l
18
Bits
No Missing Codes
l
18
Bits
Transition Noise
SoftSpans 7 and 6: ±10.24V and ±10V Ranges
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges
SoftSpans 3 and 2: ±5.12V and ±5V Ranges
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges
INL
Integral Linearity Error
SoftSpans 7 and 6: ±10.24V and ±10V Ranges (Note 10)
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges (Note 10)
SoftSpans 3 and 2: ±5.12V and ±5V Ranges (Note 10)
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges (Note 10)
DNL
Differential Linearity Error (Note 11)
ZSE
Zero-Scale Error
FSE
1.4
2.8
2.1
4.2
–3
–4
–3
–5
±1.25
±1.5
±0.75
±0.75
l
−0.9
(Note 12)
l
−700
Full-Scale Error
VREFBUF = 4.096V (REFBUF Overdriven) (Note 12)
l
−0.1
±0.025
Full-Scale Error Drift
VREFBUF = 4.096V (REFBUF Overdriven) (Note 12)
l
l
l
l
Zero-Scale Error Drift
LSBRMS
LSBRMS
LSBRMS
LSBRMS
3
4
3
5
LSB
LSB
LSB
LSB
±0.2
0.9
LSB
±80
700
μV
±4
±2.5
μV/°C
0.1
%FS
ppm/°C
233318f
For more information www.linear.com/LTC2333-18
3
LTC2333-18
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 9, 13)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz
l
l
l
l
SINAD
Signal-to-(Noise +
Distortion) Ratio
SNR
92.7
87.1
89.3
83.6
96.2
90.3
92.5
86.6
dB
dB
dB
dB
Signal-to-Noise Ratio
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz
l
l
l
l
93.2
87.2
89.5
83.6
96.4
90.4
92.5
86.6
dB
dB
dB
dB
THD
Total Harmonic Distortion
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz
l
l
l
l
SFDR
Spurious Free Dynamic
Range
SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz
SoftSpans 1 and 0: 0V to 5.12V and 0V to 5V Ranges, fIN = 2kHz
l
l
l
l
Channel-to-Channel
Active Crosstalk
Alternating Conversions with 18VP-P 200Hz Sine in ±10.24V
Range, Crosstalk to Any Other Channel
–110
–110
–114
–115
101
100
102
104
–3dB Input Bandwidth
–101
–99
–102
–101
Aperture Delay
Aperture Jitter
dB
dB
dB
dB
dB
dB
dB
dB
–125
dB
MHz
1
ns
150
ps
3
Full-Scale Step, 0.005% Settling
UNITS
111
111
115
115
6
Aperture Delay Matching
Transient Response
MAX
psRMS
420
ns
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
VREFIN
Internal Reference Output Voltage
CONDITIONS
Internal Reference Temperature Coefficient
(Note 14)
Internal Reference Line Regulation
VDD = 4.75V to 5.25V
MIN
TYP
MAX
2.043
2.048
2.053
5
20
l
0.1
Internal Reference Output Impedance
VREFIN
REFIN Voltage Range
1.25
V
ppm/°C
mV/V
20
REFIN Overdriven (Note 7)
UNITS
kΩ
2.2
V
233318f
4
For more information www.linear.com/LTC2333-18
LTC2333-18
REFERENCE BUFFER CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
VREFBUF
Reference Buffer Output Voltage
REFIN Overdriven, VREFIN = 2.048V
REFBUF Voltage Range
REFBUF Overdriven (Notes 7, 15)
REFBUF Input Impedance
VREFIN = 0V, Buffer Disabled
REFBUF Load Current
VREFBUF = 5V, (Notes 15, 16)
VREFBUF = 5V, Acquisition or Nap Mode (Note 15)
IREFBUF
MIN
TYP
MAX
UNITS
l
4.091
4.096
4.101
V
l
2.5
5
V
13
0.93
0.39
l
kΩ
1.2
mA
mA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS Digital Inputs and Outputs
VIH
High Level Input Voltage
l 0.8 • OVDD
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
VIN = 0V to OVDD
l
V
–10
0.2 • OVDD
V
10
μA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IOUT = –500μA
l OVDD – 0.2
5
pF
VOL
Low Level Output Voltage
IOUT = 500μA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
ISOURCE
Output Source Current
VOUT = 0V
–50
mA
ISINK
Output Sink Current
VOUT = OVDD
50
mA
V
0.2
–10
10
V
μA
LVDS Digital Inputs and Outputs
VID
Differential Input Voltage
l
200
350
600
mV
l
RID
On-Chip Input Termination
Resistance
90
106
10
125
Ω
MΩ
VICM
Common-Mode Input Voltage
l
IICM
Common-Mode Input Current
0.3
1.2
2.2
V
VIN+ = VIN– = 0V to OVDD
l
–10
10
μA
VOD
VOCM
Differential Output Voltage
RL = 100Ω Differential Termination
l
275
350
425
mV
Common-Mode Output Voltage
RL = 100Ω Differential Termination
l
1.1
1.2
1.3
V
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
–10
10
μA
CS = 0V, VICM = 1.2V
CS = OVDD
233318f
For more information www.linear.com/LTC2333-18
5
LTC2333-18
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN
VCC
Supply Voltage
l
VEE
Supply Voltage
l
TYP
MAX
UNITS
7.5
38
V
–16.5
0
V
VCC − VEE Supply Voltage Difference
l
10
VDD
Supply Voltage
l
4.75
IVCC
Supply Current
800ksps Sample Rate (Note 17)
Acquisition Mode (Note 17)
Nap Mode
Power Down Mode
l
l
l
l
IVEE
Supply Current
800ksps Sample Rate (Note 17)
Acquisition Mode (Note 17)
Nap Mode
Power Down Mode
l
l
l
l
–7.6
–9.2
–3.5
–15
l
1.71
38
V
5.00
5.25
V
7.2
8.4
2.9
6
7.7
9.1
3.3
15
mA
mA
mA
μA
–6.7
–8.1
–2.8
–4
mA
mA
mA
μA
CMOS I/O Mode
OVDD
Supply Voltage
5.25
V
IVDD
Supply Current
800ksps Sample Rate
800ksps Sample Rate, VREFBUF = 5V (Note 15)
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
l
10.6
9.4
2.1
1.7
106
106
11.9
10.7
2.7
2.4
275
550
mA
mA
mA
mA
μA
µA
IOVDD
Supply Current
800ksps Sample Rate (CL = 25pF)
Acquisition or Nap Mode
Power Down Mode
l
l
l
2.4
1
1
2.9
20
20
mA
μA
μA
PD
Power Dissipation
800ksps Sample Rate (Note 17)
Acquisition Mode (Note 17)
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
268
258
94
0.68
0.68
296
288
114
1.9
3.3
mW
mW
mW
mW
mW
5.25
V
LVDS I/O Mode
OVDD
Supply Voltage
IVDD
Supply Current
800ksps Sample Rate
800ksps Sample Rate, VREFBUF = 5V (Note 15)
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
l
13.4
12.2
3.7
3.4
106
106
14.5
13.7
4.5
4.1
275
550
mA
mA
mA
mA
μA
µA
IOVDD
Supply Current
800ksps Sample Rate, (RL = 100Ω)
Acquisition or Nap Mode (RL = 100Ω)
Power Down Mode
l
l
l
7
7
1
8.8
8.3
20
mA
mA
μA
PD
Power Dissipation
800ksps Sample Rate (Note 17)
Acquisition Mode (Note 17)
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
293
284
120
0.68
0.68
324
318
143
1.9
3.3
mW
mW
mW
mW
mW
l
2.375
233318f
6
For more information www.linear.com/LTC2333-18
LTC2333-18
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
fSMPL
Maximum Sampling Frequency
l
MIN
TYP
tCYC
Time Between Conversions
l
1.25
l
450
500
l
670
730
MAX
UNITS
800
ksps
μs
tCONV
Conversion Time
tACQ
Acquisition Time
tCNVH
CNV High Time
l
40
tCNVL
CNV Low Time
l
750
tBUSYLH
CNV↑ to BUSY Delay
tQUIET
Digital I/O Quiet Time from CNV↑
l
20
ns
tPDH
PD High Time
l
40
ns
tPDL
PD Low Time
l
40
ns
tWAKE
REFBUF Wake-Up Time
(tACQ = tCYC – tCONV – tBUSYLH)
CL = 25pF
550
ns
ns
ns
30
l
CREFBUF = 47μF, CREFIN = 0.1μF
ns
200
ns
ms
CMOS I/O Mode
tSCKI
SCKI Period
tSCKIH
tSCKIL
tSSDISCKI
SDI Setup Time from SCKI↑
tHSDISCKI
(Notes 18, 19)
l
10
ns
SCKI High Time
l
4
ns
SCKI Low Time
l
4
ns
(Note 18)
l
2
ns
SDI Hold Time from SCKI↑
(Note 18)
l
1
ns
tDSDOSCKI
SDO Data Valid Delay from SCKI↑
CL = 25pF (Note 18)
l
tHSDOSCKI
SDO Remains Valid Delay from SCKI↑
CL = 25pF (Note 18)
l
1.5
tSKEW
SDO to SCKO Skew
(Note 18)
l
–1
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
CL = 25pF (Note 18)
l
0
tEN
Bus Enable Time After CS↓
(Note 18)
tDIS
Bus Relinquish Time After CS↑
7.5
ns
ns
0
1
ns
l
15
ns
(Note 18)
l
15
ns
ns
LVDS I/O Mode
tSCKI
SCKI Period
(Note 20)
l
4
ns
tSCKIH
SCKI High Time
(Note 20)
l
1.5
ns
tSCKIL
SCKI Low Time
(Note 20)
l
1.5
ns
tSSDISCKI
SDI Setup Time from SCKI
(Notes 11, 20)
l
1.2
ns
tHSDISCKI
SDI Hold Time from SCKI
(Notes 11, 20)
l
–0.2
ns
tDSDOSCKI
SDO Data Valid Delay from SCKI
(Notes 11, 20)
l
tHSDOSCKI
SDO Remains Valid Delay from SCKI
(Notes 11, 20)
l
1
tSKEW
SDO to SCKO Skew
(Note 11)
l
–0.4
(Note 11)
l
0
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
6
ns
ns
0
0.4
ns
ns
tEN
Bus Enable Time After CS↓
l
50
ns
tDIS
Bus Relinquish Time After CS↑
l
15
ns
233318f
For more information www.linear.com/LTC2333-18
7
LTC2333-18
ADC TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VDDLBYP is the output of an internal voltage regulator, and should
only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND,
as described in the Pin Functions section. Do not connect this pin to any
external circuitry.
Note 4: When these pin voltages are taken below VEE or above VCC, they
will be clamped by internal diodes. This product can handle input currents
of up to 100mA below VEE or above VCC without latch-up.
Note 5: When these pin voltages are taken below GND or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle
currents of up to 100mA below GND or above VDD or OVDD without latch-up.
Note 6: –16.5V ≤ VEE ≤ 0V, 7.5V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V,
VDD = 5V, unless otherwise specified.
Note 7: Recommended operating conditions.
Note 8: Exceeding these limits on any channel may corrupt conversion
results on other channels. Driving an analog input above VCC on any
channel up to 10mA will not affect conversion results on other channels.
Driving an analog input below VEE may corrupt conversion results on other
channels. Refer to Applications Information section for further details.
Refer to Absolute Maximum Ratings section for pin voltage limits related
to device reliability.
Note 9: VCC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 800ksps,
internal reference and buffer, true bipolar input signal drive in bipolar
SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless
otherwise specified.
Note 10: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 11: Guaranteed by design, not subject to test.
Note 12: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
the offset voltage measured from –0.5LSB when the output code flickers
between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Fullscale error for these SoftSpan ranges is the worst-case deviation of the
first and last code transitions from ideal and includes the effect of offset
error. For unipolar SoftSpan ranges 5, 4, 1, and 0, zero-scale error is
the offset voltage measured from 0.5LSB when the output code flickers
between 00 0000 0000 0000 0000 and 00 0000 0000 0000 0001. Fullscale error for these SoftSpan ranges is the worst-case deviation of the
last code transition from ideal and includes the effect of offset error.
Note 13: All specifications in dB are referred to a full-scale input in the
relevant SoftSpan input range, except for crosstalk, which is referred to
the crosstalk injection signal amplitude.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: When REFBUF is overdriven, the internal reference buffer must
be disabled by setting REFIN = 0V.
Note 16: IREFBUF varies proportionally with sample rate.
Note 17: Analog input buffer supply currents from IVCC and IVEE are
reduced outside the acquisition period. Refer to nap mode in Applications
Information section.
Note 18: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,
and OVDD = 5.25V.
Note 19: A tSCKI period of 10ns minimum allows a shift clock frequency of
up to 100MHz for rising edge capture.
Note 20: VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
CMOS Timing
0.8 • OVDD
tWIDTH
0.2 • OVDD
tDELAY
tDELAY
0.8 • OVDD
0.8 • OVDD
0.2 • OVDD
0.2 • OVDD
50%
50%
233318 F01a
LVDS Timing (Differential)
+200mV
tWIDTH
–200mV
tDELAY
tDELAY
+200mV
+200mV
–200mV
–200mV
0V
0V
233318 F01b
Figure 1. Voltage Levels for Timing Specifications
233318f
8
For more information www.linear.com/LTC2333-18
LTC2333-18
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 800ksps, unless otherwise noted.
Integral Nonlinearity
vs Output Code and Channel
2.0
Integral Nonlinearity
vs Output Code and Channel
2.0
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
ALL CHANNELS
1.5
–0.5
0.5
0
–0.5
–1.0
–1.0
–1.5
–1.5
–2.0
–131072
–2.0
–131072
0
65536
OUTPUT CODE
131072
2.0
–65536
0
65536
OUTPUT CODE
0
±10.24V AND ±10V
RANGES
INL ERROR (LSB)
INL ERROR (LSB)
0.5
–0.5
±10.24V, ±10V
RANGES
–65536
0
65536
OUTPUT CODE
131072
90000
±10.24V RANGE
COUNTS
0
–0.5
–1.0
ARBITRARY DRIVE
IN+/IN– COMMON MODE
SWEPT –10.24V to 10.24V
0
65536
OUTPUT CODE
131072
233318 G07
0V TO 10.24V AND
0V TO 10V RANGES
0
16384
32768
49152
OUTPUT CODE
DC Histogram (Near Full-Scale)
90000
70000
60000
60000
50000
40000
50000
40000
30000
30000
20000
20000
10000
10000
–6
–4
–2
0
CODE
2
4
6
233318 G08
±10.24V RANGE
σ = 1.4
80000
70000
0
65536
233318 G06
±10.24V RANGE
σ = 1.3
80000
TRUE BIPOLAR DRIVE (IN– = 0V)
–65536
–1.00
DC Histogram (Zero-Scale)
0.5
–2.0
–131072
–0.25
233318 G05
1.0
–1.5
0
–0.50
COUNTS
1.5
0V TO 5V AND
0V TO 5.12V RANGES
0.25
–0.75
–2.0
–131072
131072
262144
UNIPOLAR DRIVE (IN– = 0V)
ONE CHANNEL
0.75
0
Integral Nonlinearity
vs Output Code
2.0
131072
196608
OUTPUT CODE
0.50
233318 G04
INL ERROR (LSB)
1.00
–1.5
0
65536
OUTPUT CODE
65536
Integral Nonlinearity
vs Output Code and Range
0.5
–1.0
–1.5
–65536
0
233318 G03
±5.12V, AND ±5V
RANGES
1.0
–2.0
–131072
–0.2
–0.5
131072
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ONE CHANNEL
1.5
1.0
±5.12V AND ±5V
RANGES
–0.1
Integral Nonlinearity
vs Output Code and Range
TRUE BIPOLAR DRIVE (IN– = 0V)
ONE CHANNEL
1.5
0.0
233318 G02
Integral Nonlinearity
vs Output Code and Range
2.0
0.1
–0.4
INL ERROR (LSB)
–65536
0.2
–0.3
233318 G01
–1.0
0.3
DNL ERROR (LSB)
INL ERROR (LSB)
INL ERROR (LSB)
0
ALL RANGES
ALL CHANNELS
0.4
1.0
0.5
–0.5
0.5
±10.24V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ALL CHANNELS
1.5
1.0
Differential Nonlinearity
vs Output Code and Range
0
131055
131058
131061
CODE
131064
131067
233318 G09
233318f
For more information www.linear.com/LTC2333-18
9
LTC2333-18
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 800ksps, unless otherwise noted.
32k Point Arbitrary Two-Tone FFT
32k Point FFT fSMPL = 800ksps,
fSMPL = 800ksps, IN+ = –7dBFS 2kHz
32k Point FFT fSMPL = 800ksps,
fIN = 2kHz
fIN = 2kHz
Sine, IN– = –7dBFS 3.1kHz Sine
SNR = 96.4dB
THD = –109dB
SINAD = 96.2dB
SFDR = 111dB
–60
–80
–100
–120
–40
–40
SNR = 96.4dB
THD = –117dB
SINAD = 96.4dB
SFDR = 120dB
–60
–80
–100
–120
–100
–120
–160
–160
–160
200
300
FREQUENCY (kHz)
–180
400
0
100
200
300
FREQUENCY (kHz)
32k Point FFT fSMPL = 800ksps,
fIN = 2kHz
100
±5.12V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–40
SNR = 92.7dB
THD = –114dB
SINAD = 92.7dB
SFDR = 117dB
–60
–80
–100
–120
SNR, SINAD vs VREFBUF,
fIN = 2kHz
–100
±2.5 • VREFBUF RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
SNR
96
SINAD
94
92
–160
100
200
300
FREQUENCY (kHz)
90
2.5
400
3
3.5
4
4.5
REFBUF VOLTAGE (V)
SNR, SINAD
vs Input Frequency
–60
SNR
94
90
86
10kΩ
SOURCE
–90
–110
1k
10k
FREQUENCY (Hz)
100k
233318 G16
2ND
–120
–125
3RD
–130
2.5
3
0
–20
1kΩ
SOURCE
–100
82
78
100
–115
3.5
4
4.5
REFBUF VOLTAGE (V)
–120
50Ω
SOURCE
10
100
1k
10k
FREQUENCY (Hz)
5
THD, Harmonics vs Input
Common Mode, fIN = 2kHz
–80
SINAD
THD
233318 G15
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–70
THD (dBFS)
98
–110
THD vs Input Frequency
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
400
±2.5 • VREFBUF RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
233318 G14
233318 G13
102
5
THD, HARMONICS (dBFS)
0
200
300
FREQUENCY (kHz)
THD, Harmonics vs VREFBUF,
fIN = 2kHz
–105
98
–140
–180
100
233318 G12
THD, HARMONICS (dBFS)
–20
0
233318 G11
SNR, SINAD (dBFS)
0
–180
400
233318 G10
SNR, SINAD (dBFS)
–80
–140
100
SFDR = 120dB
SNR = 96.5dB
–60
–140
0
±10.24V RANGE
ARBITRARY DRIVE
–20
–140
–180
AMPLITUDE (dBFS)
0
±10.24V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–20
AMPLITUDE (dBFS)
–40
AMPLITUDE (dBFS)
0
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
AMPLITUDE (dBFS)
0
–20
±10.24V SOFTSPAN
2VP–P FULLY DIFFERENTIAL DRIVE
–40
–60
–11V ≤ VCM ≤ 11V
–80
–100
THD
–120
–140
100k
233318 G17
–160
–15
3RD
–10
2ND
–5
0
5
10
INPUT COMMON MODE (V)
15
233318 G18
233318f
10
For more information www.linear.com/LTC2333-18
LTC2333-18
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 800ksps, unless otherwise noted.
CMRR vs Input Frequency
and Channel
SNR, SINAD vs Input Level,
fIN = 2kHz
97.0
96.8
140
SNR
130
96.4
SINAD
96.2
120
110
100
70
0
10
100
1k
10k
FREQUENCY (Hz)
100k
233318 G19
SNR
SINAD
95.0
94.0
93.0
–105
THD
–110
2ND
–115
3RD
1.5
1
5 25 45 65 85 105 125
TEMPERATURE (°C)
233318 G25
100k
1M
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
1.0
0.5 MAX DNL
0
–0.5 MIN DNL
–1.0
MIN INL
5 25 45 65 85 105 125
TEMPERATURE (°C)
233318 G24
0.050
Negative Full-Scale Error vs
Temperature and Channel
±10.24V RANGE
REFBUF OVERDRIVEN
VREFBUF = 4.096V
ALL CHANNELS
0.025
0.000
–0.025
–0.050
–0.100
–55 –35 –15
0.100
0.075
0.050
±10.24V RANGE
REFBUF OVERDRIVEN
VREFBUF = 4.096V
ALL CHANNELS
0.025
0.000
–0.025
–0.050
–0.075
–0.075
0.1
–55 –35 –15
MAX INL
–2.0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
FULL-SCALE ERROR (%)
0.075
FULL-SCALE ERROR (%)
ANALOG INPUT LEAKAGE CURRENT (pA)
0.100
10
1k
10k
FREQUENCY (Hz)
INL, DNL vs Temperature
Positive Full-Scale Error vs
Temperature and Channel
10k
100
100
233318 G23
Analog Input Leakage
Current vs Temperature
VIN = 0V
VIN = +10V
VIN = –10V
10
–1.5
233318 G22
1k
CH1, CH1, CH1, CH1...
2.0
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–125
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
16 ANALOG INPUT PIN TRACES
FOR EACH INPUT VOLTAGE
CH0, CH2, CH0, CH2...
233318 G21
–120
92.0
–55 –35 –15
–130
–160
1M
THD, Harmonics vs Temperature,
fIN = 2kHz
–100
THD, HARMONICS (dBFS)
SNR, SINAD (dBFS)
–95
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
96.0
–120
233318 G20
SNR, SINAD vs Temperature,
fIN = 2kHz
97.0
CH0, CH1, CH0, CH1...
–150
INL, DNL ERROR (LSB)
–30
–20
–10
INPUT LEVEL (dBFS)
–110
–140
80
95.8
–40
98.0
–100
90
96.0
±10.24V RANGE
IN0+ = 0V
IN0– = 18VP–P SINE
IN1+, IN1–, IN2+, IN2– = 0V
–90
CROSSTALK (dB)
96.6
–80
±10.24V RANGE
P–P SINE
ALL CHANNELS
IN+ = IN– = 18V
150
CMRR (dB)
SNR, SINAD (dBFS)
160
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
Crosstalk vs Input Frequency
and Conversion Sequence
5 25 45 65 85 105 125
TEMPERATURE (°C)
233318 G26
–0.100
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
233318 G27
233318f
For more information www.linear.com/LTC2333-18
11
LTC2333-18
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 800ksps, unless otherwise noted.
Zero-Scale Error vs
Temperature and Channel
1000
IVDD
12
1
0
–1
–2
–3
8
6
IVCC
4
2
0
IOVDD
–2
–4
–6
–4
–10
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
130
VEE
90
80
70
VDD
60
10
100
1.0
VCC = 38V, VEE = 0V
VCM = 4V to 34V
0.5
0
–0.5
VCC = 21.5V, VEE = –16.5V
VCM = –12.5V to 17.5V
–1.0
–2.0
–17
100k
0
17
INPUT COMMON MODE (V)
14
WITH NAP MODE
12 tCNVL = 750ns
10
OUTPUT CODE (LSB)
6
IVCC
4
2
0
IOVDD
–2
–4
–8
0
160
320
480
640
SAMPLING FREQUENCY (kHz)
800
233318 G34
2.048
2.047
2.046
2.045
–55 –35 –15
34
5 25 45 65 85 105 125
TEMPERATURE (°C)
233318 G33
Step Response
(Fine Settling)
131072
250
98304
200
65536
32768
0
–32768
±10.24V RANGE
IN+ = 199.91156kHz SQUARE WAVE
IN– = 0V
–65536
–98304
IVEE
–6
2.049
Step Response
(Large-Signal Settling)
Supply Current vs Sampling Rate
IVDD
15 UNITS
2.050
233318 G32
233318 G31
8
5 25 45 65 85 105 125
TEMPERATURE (°C)
2.051
±10.24V RANGE
–1.5
1k
10k
FREQUENCY (Hz)
IOVDD
0.1
Internal Reference Output
vs Temperature
1.5
OFFSET ERROR (LSB)
PSRR (dB)
2.0
IN+ = IN– = 0V
110
100
–IVEE
Offset Error
vs Input Common Mode
OVDD
120
1
233318 G30
INTERNAL REFERENCE OUTPUT (V)
140
IVCC
233318 G29
PSRR vs Frequency
VCC
10
0.01
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
233318 G28
150
100
IVEE
–8
–5
–55 –35 –15
SUPPLY CURRENT (mA)
POWER-DOWN CURRENT (µA)
2
50
IVDD
10
3
SUPPLY CURRENT (mA)
ZERO-SCALE ERROR (LSB)
14
±10.24V RANGE
ALL CHANNELS
4
–131072
–100 0 100 200 300 400 500 600 700 800 900
SETTLING TIME (ns)
233318 G35
DEVIATION FROM FINAL VALUE (LSB)
5
Power-Down Current
vs Temperature
Supply Current vs Temperature
150
±10.24V RANGE
IN+ = 199.91156kHz
SQUARE WAVE
IN– = 0V
100
50
0
–50
–100
–150
–200
–250
–100 0 100 200 300 400 500 600 700 800 900
SETTLING TIME (ns)
233318 G36
233318f
12
For more information www.linear.com/LTC2333-18
LTC2333-18
PIN FUNCTIONS
Pins that are the Same for All Digital I/O Modes
IN0+/IN0− to IN7+/IN7− (Pins 14/13, 12/11, 10/9, 8/7, 6/5,
4/3, 2/1, and 48/47): Positive and Negative Analog Inputs,
Channels 0 to 7. The converter samples (VIN+ – VIN–) and
digitizes the selected channel. Wide input common mode
range (VEE + 4V ≤ VCM ≤ VCC – 4V) and high common
mode rejection allow the inputs to accept a wide variety
of signal swings. Full-scale input range is determined by
the selected SoftSpan configuration.
GND (Pins 15, 18, 20, 25, 30, 36, 41, 44, 46): Ground.
Solder all GND pins to a solid ground plane.
VCC (Pin 16): Positive High Voltage Power Supply. The
range of VCC is 7.5V to 38V with respect to GND and 10V
to 38V with respect to VEE. Bypass VCC to GND close to
the pin with a 0.1μF ceramic capacitor.
VEE (Pins 17, 45): Negative High Voltage Power Supply.
The range of VEE is 0V to –16.5V with respect to GND and
–10V to –38V with respect to VCC. Connect Pins 17 and 45
together and bypass the VEE network to GND close to Pin
17 with a 0.1μF ceramic capacitor. In applications where
VEE is shorted to GND, this capacitor may be omitted.
REFIN (Pin 19): Bandgap Reference Output/Reference Buffer Input. An internal bandgap reference nominally outputs
2.048V on this pin. An internal reference buffer amplifies
VREFIN to create the converter master reference voltage
VREFBUF = 2 • VREFIN on the REFBUF pin. When using the
internal reference, bypass REFIN to GND (Pin 20) close to
the pin with a 0.1μF ceramic capacitor to filter the bandgap
output noise. If more accuracy is desired, overdrive REFIN
with an external reference in the range of 1.25V to 2.2V.
Do not load this pin when internal reference is used.
REFBUF (Pin 21): Internal Reference Buffer Output. An
internal reference buffer amplifies VREFIN to create the
converter master reference voltage VREFBUF = 2 • VREFIN
on this pin, nominally 4.096V when using the internal
bandgap reference. Bypass REFBUF to GND (Pin 20) close
to the pin with a 47μF ceramic capacitor. The internal
reference buffer may be disabled by grounding its input
at REFIN. With the buffer disabled, overdrive REFBUF with
an external reference voltage in the range of 2.5V to 5V.
When using the internal reference buffer, limit the loading
of any external circuitry connected to REFBUF to less than
200µA. Using a high input impedance amplifier to buffer
VREFBUF to any external circuits is recommended.
PD (Pin 22): Power Down Input. When this pin is brought
high, the LTC2333-18 is powered down and subsequent
conversion requests are ignored. If this occurs during a
conversion, the device powers down once the conversion
completes. If this pin is brought high twice without an
intervening conversion, an internal global reset is initiated, equivalent to a power-on-reset event. Logic levels
are determined by OVDD.
LVDS/CMOS (Pin 23): I/O Mode Select. Tie this pin to OVDD
to select LVDS I/O mode, or to ground to select CMOS I/O
mode. Logic levels are determined by OVDD.
CNV (Pin 24): Conversion Start Input. A rising edge on
this pin puts the internal sample-and-holds into the hold
mode and initiates a new conversion. CNV is not gated
by CS, allowing conversions to be initiated independent
of the state of the serial I/O bus.
BUSY (Pin 38): Busy Output. The BUSY signal indicates
that a conversion is in progress. This pin transitions lowto-high at the start of each conversion and stays high until
the conversion is complete. Logic levels are determined
by OVDD.
VDDLBYP (Pin 40): Internal 2.5V Regulator Bypass Pin. The
voltage on this pin is generated via an internal regulator
operating off of VDD. This pin must be bypassed to GND
close to the pin with a 2.2μF ceramic capacitor. Do not
connect this pin to any external circuitry.
VDD (Pins 42, 43): 5V Power Supply. The range of VDD
is 4.75V to 5.25V. Connect Pins 42 and 43 together and
bypass the VDD network to GND with a shared 0.1μF
ceramic capacitor close to the pins.
233318f
For more information www.linear.com/LTC2333-18
13
LTC2333-18
PIN FUNCTIONS
CMOS I/O Mode
LVDS I/O Mode
SDI+/SDI–, SCKI+, SDO+/SDO– (Pins 26/27, 28, and 34/35):
LVDS Inputs and Outputs. In CMOS I/O mode these pins
are Hi-Z.
SDI+/SDI– (Pins 26/27): LVDS Positive and Negative Serial
Data Input. Differentially drive SDI+/SDI– with the desired
MUX control words (see Table 1a), latched on both the
rising and falling edges of SCKI+/SCKI–. The SDI+/SDI–
input pair is internally terminated with a 100Ω differential
resistor when CS is low.
SCKI (Pin 29): CMOS Serial Clock Input. Drive SCKI with
the serial I/O clock. SCKI rising edges latch serial data in
on SDI and clock serial data out on SDO. For standard
SPI bus operation, capture output data at the receiver on
rising edges of SCKI. SCKI is allowed to idle either high
or low. Logic levels are determined by OVDD.
OVDD (Pin 31): I/O Interface Power Supply. In CMOS I/O
mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD
to GND (Pin 30) close to the pin with a 0.1μF ceramic
capacitor.
SCKO (Pin 32): CMOS Serial Clock Output. SCKI rising
edges trigger transitions on SCKO that are skew-matched to
the serial output data stream on SDO. The resulting SCKO
frequency is half that of SCKI. Rising and falling edges of
SCKO may be used to capture SDO data at the receiver
(FPGA) in double data rate (DDR) fashion. For standard
SPI bus operation, SCKO is not used and should be left
unconnected. SCKO is forced low at the falling edge of
BUSY. Logic levels are determined by OVDD.
SDO (Pin 33): CMOS Serial Data Output. The most recent
conversion result along with channel configuration information is clocked out onto the SDO pin on each rising edge
of SCKI. Output data formatting is described in the Digital
Interface section. Logic levels are determined by OVDD.
SDI (Pin 37): CMOS Serial Data Input. Drive this pin with
the desired MUX control words (see Table 1a), latched
on the rising edges of SCKI. Hold SDI low while clocking SCKI to configure the next conversion according to
the previously programmed sequence. Logic levels are
determined by OVDD.
CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI.
Logic levels are determined by OVDD.
SCKI+/SCKI– (Pins 28/29): LVDS Positive and Negative
Serial Clock Input. Differentially drive SCKI+/SCKI– with
the serial I/O clock. SCKI+/SCKI– rising and falling edges
latch serial data in on SDI+/SDI– and clock serial data out
on SDO+/SDO–. Idle SCKI+/SCKI– low, including when
transitioning CS. The SCKI+/SCKI– input pair is internally
terminated with a 100Ω differential resistor when CS is low.
OVDD (Pin 31): I/O Interface Power Supply. In LVDS I/O
mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD
to GND (Pin 30) close to the pin with a 0.1μF ceramic
capacitor.
SCKO+/SCKO– (Pins 32/33): LVDS Positive and Negative
Serial Clock Output. SCKO+/SCKO– outputs a copy of the
input serial I/O clock received on SCKI+/SCKI–, skewmatched with the serial output data stream on SDO+/SDO–.
Use the rising and falling edges of SCKO+/SCKO– to capture SDO+/SDO– data at the receiver (FPGA). The SCKO+/
SCKO– output pair must be differentially terminated with
a 100Ω resistor at the receiver (FPGA).
SDO+/SDO– (Pins 34/35): LVDS Positive and Negative Serial Data Output. The most recent conversion result along
with channel configuration information is clocked out onto
SDO+/SDO– on both rising and falling edges of SCKI+/
SCKI–. The SDO+/SDO– output pair must be differentially
terminated with a 100Ω resistor at the receiver (FPGA).
SDI (Pin 37): CMOS Serial Data Input. In LVDS I/O mode
this pin is Hi-Z.
CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low, and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI+/
SCKI–. The internal 100Ω differential termination resistors
on the SCKI+/SCKI– and SDI+/SDI– input pairs are disabled
when CS is high. Logic levels are determined by OVDD.
233318f
14
For more information www.linear.com/LTC2333-18
LTC2333-18
CONFIGURATION TABLES
Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Binary SoftSpan Codes SS[2:0] Based on Desired
Analog Input Range. Combine MUX Word Header (10) with Binary Channel Number and SoftSpan Code to Form MUX Control Word
C[7:0]. Use Serial Interface to Program LTC2333-18 Sequencer as Shown in Figures 16 to 19
BINARY SoftSpan CODE
SS[2:0]
ANALOG INPUT RANGE
FULL SCALE RANGE
BINARY FORMAT OF
CONVERSION RESULT
111
110
101
100
011
010
001
000
±2.5 • VREFBUF
±2.5 • VREFBUF/1.024
0V to 2.5 • VREFBUF
0V to 2.5 • VREFBUF/1.024
±1.25 • VREFBUF
±1.25 • VREFBUF/1.024
0V to 1.25 • VREFBUF
0V to 1.25 • VREFBUF/1.024
5 • VREFBUF
5 • VREFBUF/1.024
2.5 • VREFBUF
2.5 • VREFBUF/1.024
2.5 • VREFBUF
2.5 • VREFBUF/1.024
1.25 • VREFBUF
1.25 • VREFBUF/1.024
Two’s Complement
Two’s Complement
Straight Binary
Straight Binary
Two’s Complement
Two’s Complement
Straight Binary
Straight Binary
Table 1b. Reference Configuration Table. The LTC2333-18 Supports Three Reference Configurations. Analog Input Range Scales with
the Converter Master Reference Voltage, VREFBUF
REFERENCE CONFIGURATION
Internal Reference with
Internal Buffer
VREFIN
VREFBUF
2.048V
BINARY SoftSpan CODE
SS[2:0]
ANALOG INPUT RANGE
111
±10.24V
110
±10V
101
0V to 10.24V
100
0V to 10V
011
±5.12V
4.096V
1.25V
(Min Value)
2.5V
External Reference with
Internal Buffer
(REFIN Pin Externally
Overdriven)
2.2V
(Max Value)
4.4V
010
±5V
001
0V to 5.12V
000
0V to 5V
111
±6.25V
110
±6.104V
101
0V to 6.25V
100
0V to 6.104V
011
±3.125V
010
±3.052V
001
0V to 3.125V
000
0V to 3.052V
111
±11V
110
±10.742V
101
0V to 11V
100
0V to 10.742V
011
±5.5V
010
±5.371V
001
0V to 5.5V
000
0V to 5.371V
233318f
For more information www.linear.com/LTC2333-18
15
LTC2333-18
CONFIGURATION TABLES
Table 1b. Reference Configuration Table (Continued). The LTC2333-18 Supports Three Reference Configurations. Analog Input Range
Scales with the Converter Master Reference Voltage, VREFBUF
REFERENCE CONFIGURATION
VREFIN
0V
VREFBUF
BINARY SoftSpan CODE
SS[2:0]
2.5V
(Min Value)
External Reference
Unbuffered
(REFBUF Pin
Externally Overdriven,
REFIN Pin Grounded)
0V
5V
(Max Value)
ANALOG INPUT RANGE
111
±6.25V
110
±6.104V
101
0V to 6.25V
100
0V to 6.104V
011
±3.125V
010
±3.052V
001
0V to 3.125V
000
0V to 3.052V
111
±12.5V
110
±12.207V
101
0V to 12.5V
100
0V to 12.207V
011
±6.25V
010
±6.104V
001
0V to 6.25V
000
0V to 6.104V
233318f
16
For more information www.linear.com/LTC2333-18
LTC2333-18
FUNCTIONAL BLOCK DIAGRAM
CMOS I/O Mode
BUFFERS
VDD
VCC
VDDLBYP
OVDD
LTC2333-18
IN0+
IN0–
2.5V
REGULATOR
IN1+
SDO
IN1–
IN2+
SCKO
SEQUENCER
CMOS
SERIAL
I/O
INTERFACE
8-CHANNEL MULTIPLEXER
IN2–
IN3+
IN3–
IN4+
IN4–
IN5+
IN5–
18-BIT
SAMPLING
ADC
IN6+
IN6–
IN7–
VEE
SCKI
CS
18 BITS
REFERENCE
BUFFER
20k
2.048V
REFERENCE
IN7+
SDI
2×
GND
REFIN
REFBUF
CONTROL
LOGIC
BUSY
CNV PD
LVDS/CMOS
233318 BD01
LVDS I/O Mode
BUFFERS
IN0+
VDD
VCC
LTC2333-18
VDDLBYP
IN0–
OVDD
SDO+
2.5V
REGULATOR
IN1+
SDO–
IN1–
SCKO+
IN2+
IN3+
IN3–
IN4+
IN4–
IN5+
IN5–
SEQUENCER
8-CHANNEL MULTIPLEXER
IN2–
18-BIT
SAMPLING
ADC
IN6+
IN6–
2.048V
REFERENCE
IN7+
IN7–
VEE
GND
20k
LVDS
SERIAL
I/O
INTERFACE
SCKO–
SDI+
SDI–
SCKI+
SCKI–
18 BITS
CS
REFERENCE
BUFFER
2×
REFIN
REFBUF
CONTROL
LOGIC
BUSY
CNV PD
LVDS/CMOS
233318 BD02
233318f
For more information www.linear.com/LTC2333-18
17
LTC2333-18
TIMING DIAGRAM
CMOS I/O Mode
CS = PD = 0
SAMPLE N
SAMPLE N + 1
CNV
BUSY
CONVERT
ACQUIRE
1
2
3
4
C7
C6
C5 C4
5
6
7
8
9
C3
C2
C1
C0 C7
10
11
12
13
14
15
C6
C5
C4
C3
C2 C1
16
17
18
19
20
21
22
23
24
SCKI
DON’T CARE
SDI
CONTROL WORD FOR
CONVERSION N + 1
C0
CONTROL WORD FOR
CONVERSION N + 2
SCKO
DON’T CARE
SDO
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0 CH2 CH1 CH0 SS2 SS1 SS0 D17
CONVERSION RESULT
CHANNEL ID
CONVERSION RESULT
(REPETITION)
SoftSpan
233318 TD01
CONVERSION N
LVDS I/O Mode
CS = PD = 0
SAMPLE N
SAMPLE N + 1
CNV
(CMOS)
BUSY
(CMOS)
CONVERT
SCKI
(LVDS)
SDI
(LVDS)
ACQUIRE
1
DON’T CARE
C7
2
C6
3
4
C5 C4
5
6
7
C3
C2
C1
CONTROL WORD FOR
CONVERSION N + 1
8
9
10
11 12
13 14
C0 C7
C6
C5
C3
C4
15 16
C2 C1
17 18
19 20
21 22
23 24
C0
CONTROL WORD FOR
CONVERSION N + 2
SCKO
(LVDS)
SDO
(LVDS)
DON’T CARE
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
CONVERSION RESULT
CONVERSION N
D1 D0 CH2 CH1 CH0 SS2 SS1 SS0 D17
CHANNEL ID
SoftSpan
CONVERSION RESULT
(REPETITION)
233318 TD02
233318f
18
For more information www.linear.com/LTC2333-18
LTC2333-18
APPLICATIONS INFORMATION
The LTC2333-18 is an 18-bit, low noise 8-channel multiplexed successive approximation register (SAR) ADC
with buffered differential, wide common mode range
picoamp inputs. The ADC operates from a 5V low voltage supply and flexible high voltage supplies, nominally
±15V. Using the integrated low-drift reference and buffer
(VREFBUF = 4.096V nominal), this SoftSpan ADC can be
configured on a conversion-by-conversion basis to accept
±10.24V, 0V to 10.24V, ±5.12V, or 0V to 5.12V signals on
any channel. Alternately, the ADC may be programmed to
cycle through a sequence of channels and ranges without
further user intervention. The input signal range may be
expanded up to ±12.5V using an external 5V reference.
The integrated picoamp-input analog buffers, wide input
common mode range, and 128dB CMRR of the LTC2333- 18
allow the ADC to directly digitize a variety of signals using minimal board space and power. This input signal
flexibility, combined with ±3LSB INL, no missing codes
at 18-bits, and 96.4dB SNR, makes the LTC2333-18 an
ideal choice for many high voltage applications requiring
wide dynamic range.
The absolute common mode input range (VEE + 4V to
VCC – 4V) is determined by the choice of high voltage
supplies. These supplies may be biased asymmetrically
around ground and include the ability for VEE to be tied
directly to ground.
The LTC2333-18 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces, enabling it to communicate equally well with legacy microcontrollers and modern
FPGAs. The LTC2333-18 typically dissipates 268mW when
converting at 800ksps throughput. Optional nap and power
down modes may be employed to further reduce power
consumption during inactive periods.
CONVERTER OPERATION
The LTC2333-18 operates in two phases. During the acquisition phase, the sampling capacitors in each channel
connect to their respective analog input pins and track the
differential analog input voltage (VIN+ – VIN–). A rising edge
on the CNV pin transitions the S/H circuits from track mode
to hold mode, sampling the input signals and initiating a
conversion. During the conversion phase, the selected
channel's sampling capacitors are connected to an 18-bit
charge redistribution capacitor D/A converter (CDAC). The
CDAC is sequenced through a successive approximation
algorithm, effectively comparing the sampled input voltage
with binary-weighted fractions of the channel’s SoftSpan
full-scale range (e.g., VFSR/2, VFSR/4…VFSR/262144) using
a differential comparator. At the end of this process, the
CDAC output approximates the channel’s sampled analog
input. The ADC control logic then prepares the 18-bit digital
output code for serial transfer.
TRANSFER FUNCTION
The LTC2333-18 digitizes the full-scale voltage range into
218 levels. In conjunction with the ADC master reference
voltage, VREFBUF, the selected SoftSpan configuration
determines its input voltage range, full-scale range, LSB
size, and the binary format of its conversion result, as
shown in Tables 1a and 1b. For example, employing the
internal reference and buffer (VREFBUF = 4.096V nominal),
SoftSpan 7 configures a channel to accept a ±10.24V
bipolar analog input voltage range, which corresponds
to a 20.48V full-scale range with a 78.125μV LSB. Other
SoftSpan configurations and reference voltages may be
employed to convert both larger and smaller bipolar and
unipolar input ranges. Conversion results are output in
two’s complement binary format for all bipolar SoftSpan
ranges, and in straight binary format for all unipolar
SoftSpan ranges. The ideal two’s complement transfer
function is shown in Figure 2, while the ideal straight
binary transfer function is shown in Figure 3.
OUTPUT CODE (TWO’S COMPLEMENT)
OVERVIEW
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/262144
100...000
–FSR/2
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
233318 F02
Figure 2. LTC2333-18 Two’s Complement Transfer Function
For more information www.linear.com/LTC2333-18
233318f
19
LTC2333-18
OUTPUT CODE (STRAIGHT BINARY)
APPLICATIONS INFORMATION
connect to the integrated buffers Buffer+/Buffer– through
the sampling switches. The sampled voltage is reset during
the conversion process and is therefore re-acquired for
each new conversion.
111...111
111...110
100...001
100...000
011...111 UNIPOLAR
ZERO
011...110
VCC
BUFFER+
IN+
000...001
FSR = +FS
1LSB = FSR/262144
000...000
0V
BUFFER–
233318 F03
Figure 3. LTC2333-18 Straight Binary Transfer Function
CSAMP
30pF
VEE
VCC
FSR – 1LSB
INPUT VOLTAGE (V)
RSAMP
750Ω
IN–
RSAMP
750Ω
CSAMP
30pF
BIAS
VOLTAGE
233318 F04
VEE
BUFFERED ANALOG INPUTS
The LTC2333-18 samples the voltage difference (VIN+ –
VIN–) between its analog input pins over a wide common
mode input range while attenuating unwanted signals
common to both input pins by the common-mode rejection ratio (CMRR) of the ADC. Wide common mode
input range coupled with high CMRR allows the IN+/
IN– analog inputs to swing with an arbitrary relationship to each other, provided each pin remains between
(VCC – 4V) and (VEE + 4V). This feature of the LTC233318 enables it to accept a wide variety of signal swings,
including traditional classes of analog input signals such
as pseudo-differential unipolar, pseudo-differential true
bipolar, and fully differential, simplifying signal chain
design. For conversion of signals extending to VEE, the
unbuffered LTC2335-18 ADC is recommended.
The wide operating range of the high voltage supplies
offers further input common mode flexibility. As long as
the voltage difference limits of 10V ≤ (VCC – VEE) ≤ 38V
are observed, VCC and VEE may be independently biased
anywhere within their own individually allowed operating
ranges, including the ability for VEE to be tied directly to
ground. This feature enables the common mode input
range of the LTC2333-18 to be tailored to the specific
application’s requirements.
In all SoftSpan ranges, each channel’s analog inputs can
be modeled by the equivalent circuit shown in Figure 4. At
the start of acquisition, the sampling capacitors (CSAMP)
Figure 4. Equivalent Circuit for Differential Analog Inputs,
Single Channel Shown
The diodes between the inputs and the VCC and VEE supplies provide input ESD protection. While within the supply
voltages, the analog inputs of the LTC2333-18 draw only
5pA typical DC leakage current and the ESD protection
diodes do not turn on. This offers a significant advantage
over external op amp buffers, which often have diode
protection that turns on during transients and corrupts
the voltage on any filter capacitors at their inputs.
Bipolar SoftSpan Input Ranges
For conversions configured in SoftSpan ranges 7, 6, 3,
or 2, the LTC2333-18 digitizes the differential analog
input voltage (VIN+ – VIN–) over a bipolar span of
±2.5 • VREFBUF, ±2.5 • VREFBUF/1.024, ±1.25 • VREFBUF, or
±1.25 • VREFBUF/1.024, respectively, as shown in Table
1a. These SoftSpan ranges are useful for digitizing input
signals where IN+ and IN– swing above and below each
other. Traditional examples include fully differential input
signals, where IN+ and IN– are driven 180 degrees out-ofphase with respect to each other centered around a common
mode voltage (VIN+ + VIN–)/2, and pseudo-differential
true bipolar input signals, where IN+ swings above and
below a ground reference level, driven on IN–. Regardless
of the chosen SoftSpan range, the wide common mode
233318f
20
For more information www.linear.com/LTC2333-18
LTC2333-18
APPLICATIONS INFORMATION
input range and high CMRR of the IN+/IN– analog inputs
allow them to swing with an arbitrary relationship to each
other, provided each pin remains between (VCC – 4V) and
(VEE + 4V). The output data format for all bipolar SoftSpan
ranges is two’s complement.
Unipolar SoftSpan Input Ranges
For conversions configured in SoftSpan ranges 5, 4, 1,
or 0, the LTC2333-18 digitizes the differential analog
input voltage (VIN+ – VIN–) over a unipolar span of 0V
to 2.5 • VREFBUF, 0V to 2.5 • VREFBUF/1.024, 0V to 1.25 •
VREFBUF, or 0V to 1.25 • VREFBUF/1.024, respectively, as
shown in Table 1a. These SoftSpan ranges are useful for
digitizing input signals where IN+ remains above IN–. A
traditional example includes pseudo-differential unipolar
input signals, where IN+ swings above a ground reference
level, driven on IN–. Regardless of the chosen SoftSpan
range, the wide common mode input range and high CMRR
of the IN+/IN– analog inputs allow them to swing with an
arbitrary relationship to each other, provided each pin remains between (VCC – 4V) and (VEE + 4V). The output data
format for all unipolar SoftSpan ranges is straight binary.
INPUT DRIVE CIRCUITS
The CMOS buffer input stage offers a very high degree of
transient isolation from the sampling process. Most sensors, signal conditioning amplifiers and filter networks with
less than 10kΩ of impedance can drive the passive 3pF
analog input capacitance directly. For higher impedances
and slow-settling circuits, add a 680pF capacitor at the
pins to maintain the full DC accuracy of the LTC2333-18.
The very high input impedance of the unity gain buffers in the LTC2333-18 greatly reduces the input
drive requirements and make it possible to include
optional RC filters with kΩ impedance and arbitrarily
slow time constants for anti-aliasing or other purposes.
Micro-power op amps with limited drive capability are
also well suited to drive the high impedance analog inputs
directly.
The LTC2333-18 features proprietary circuitry to achieve
exceptional internal crosstalk isolation between channels
(–125dB typical). The PC board wiring to the analog inputs
should be short and shielded to prevent external capacitive
crosstalk between channels. The capacitance between adjacent package pins is 0.16pF. Low source resistance and/or
high source capacitance help reduce external capacitively
coupled crosstalk. Single ended input drive also enjoys
additional external crosstalk isolation because every other
input pin is grounded, or at a low impedance DC source,
and serves as a shield between channels.
Input Overdrive Tolerance
Driving an analog input above VCC on any channel up to
10mA will not affect conversion results on other channels.
Approximately 70% of this overdrive current will flow out
of the VCC pin and the remaining 30% will flow out of VEE.
This current flowing out of VEE will produce heat across
the VCC-VEE voltage drop and must be taken into account
for the total Absolute Maximum power dissipation of
500mW. Driving an analog input below VEE may corrupt
conversion results on other channels. This product can
handle input currents of up to 100mA below VEE or above
VCC without latch-up.
Keep in mind that driving the inputs above VCC or below
VEE may reverse the normal current flow from the external
power supplies driving these pins.
Input Filtering
The true high impedance analog inputs can accommodate
a very wide range of passive or active signal conditioning
filters. The buffered ADC inputs have an analog bandwidth
of 6MHz, and impose no particular bandwidth requirement
on external filters. The external input filters can therefore
be optimized independent of the ADC to reduce signal
chain noise and interference. A common filter configuration is the simple anti-aliasing and noise reducing RC filter
with its pole at half the sampling frequency. For example,
233318f
For more information www.linear.com/LTC2333-18
21
LTC2333-18
APPLICATIONS INFORMATION
TRUE BIPOLAR
+10V
IN+
0V
15V
OPTIONAL
LOWPASS FILTER
–10V
0.1µF
R = 590Ω
UNIPOLAR
LTC2333-18
+10V
0V
VCC
IN0+
IN0–
680pF
IN–
VEE REFBUF
–10V
0.1µF
REFIN
47µF
0.1µF
–15V
ONLY CHANNEL 0 SHOWN FOR CLARITY
233318 F05
Figure 5. Filtering Single-Ended Input Signals
sampling one channel at 800ksps yields R = 590Ω and
C = 680pF as shown in Figure 5.
High quality capacitors and resistors should be used in
the RC filters since these components can add distortion.
NPO/COG and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self-heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
Arbitrary and Fully Differential Analog Input Signals
The wide common mode input range and high CMRR of
the LTC2333-18 allow each channel’s IN+ and IN– pins to
swing with an arbitrary relationship to each other, provided
each pin remains between (VCC – 4V) and (VEE + 4V). This
feature of the LTC2333-18 enables it to accept a wide
variety of signal swings, simplifying signal chain design.
The two-tone test shown in Figure 6b demonstrates the
arbitrary input drive capability of the LTC2333-18. This test
simultaneously drives IN+ with a −7dBFS 2kHz single-ended
sine wave and IN− with a −7dBFS 3.1kHz single-ended sine
wave. Together, these signals sweep the analog inputs
across a wide range of common mode and differential
mode voltage combinations, similar to the more general
arbitrary input signal case. They also have a simple spectral representation. An ideal differential converter with no
common-mode sensitivity will digitize this signal as two
−7dBFS spectral tones, one at each sine wave frequency.
The FFT plot in Figure 6b demonstrates the LTC2333-18
response, which approaches this ideal with 120dB of
SFDR limited by the converter's second harmonic distortion response to the 3.1kHz sine wave on IN–.
233318f
22
For more information www.linear.com/LTC2333-18
LTC2333-18
APPLICATIONS INFORMATION
+10V
ARBITRARY
0V
0V
–10V
–5V
TRUE BIPOLAR
+10V
15V
FULLY
DIFFERENTIAL
+5V
+10V
0V
0V
–10V
–10V
0.1µF
IN+
UNIPOLAR
VCC
IN0+
IN0–
LTC2333-18
IN–
VEE REFBUF
REFIN
47µF
0.1µF
0.1µF
–15V
ONLY CHANNEL 0 SHOWN FOR CLARITY
233318 F06a
Figure 6a. Input Arbitrary, Fully Differential, True Bipolar, and Unipolar Signals
Arbitrary Drive
0
±10.24V RANGE
SFDR = 120dB
SNR = 96.5dB
–20
–60
–80
–100
–120
–40
–60
–80
–100
–120
–140
–140
–160
–160
–180
0
100
200
300
FREQUENCY (kHz)
–180
400
233318 F06b
Figure 6b. Two-Tone Test. IN+ = –7dBFS 2kHz Sine, IN– = –7dBFS
3.1kHz Sine, 32k Point FFT, fSMPL = 800ksps. Circuit Shown in
Figure 6a
–60
–80
–100
–120
0
–40
–60
–80
–100
–120
–140
–160
–160
0
100
400
200
300
FREQUENCY (kHz)
400
0V to 10.24V RANGE
SNR = 90.6dB
THD = –112dB
SINAD = 90.6dB
SFDR = 113dB
–20
–140
–180
200
300
FREQUENCY (kHz)
233318 F06c
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–40
100
Unipolar Drive
±10.24V RANGE
SNR = 96.4dB
THD = –109dB
SINAD = 96.2dB
SFDR = 111dB
–20
0
Figure 6c. IN+/IN– = –1dBFS 2kHz Fully Differential Sine, VCM = 0V,
32k Point FFT, fSMPL = 800ksps. Circuit Shown in Figure 6a
True Bipolar Drive
0
±10.24V RANGE
SNR = 96.4dB
THD = –115dB
SINAD = 96.3dB
SFDR = 119dB
–20
AMPLITUDE (dBFS)
–40
AMPLITUDE (dBFS)
Fully Differential Drive
0
–180
0
233318 F06d
Figure 6d. IN+ = –1dBFS 2kHz True Bipolar Sine, IN– = 0V, 32k Point
FFT, fSMPL = 800ksps. Circuit Shown in Figure 6a
100
200
300
FREQUENCY (kHz)
400
233318 F06e
Figure 6e. IN+ = –1dBFS 2kHz Unipolar Sine, IN– = 0V, 32k Point
FFT, fSMPL = 800ksps. Circuit Shown in Figure 6a
233318f
For more information www.linear.com/LTC2333-18
23
LTC2333-18
APPLICATIONS INFORMATION
The ability of the LTC2333-18 to accept arbitrary signal
swings over a wide input common mode range with high
CMRR can simplify application solutions. In practice,
many sensors produce a differential sensor voltage riding
on top of a large common mode signal. Figure 7a depicts
one way of using the LTC2333-18 to digitize signals of
this type. The amplifier stage provides a differential gain
of approximately 10V/V to the desired sensor signal while
the unwanted common mode signal is attenuated by the
ADC CMRR. The circuit employs the ±5V SoftSpan range of
the ADC. Figure 7b shows measured CMRR performance
of this solution, which is competitive with the best commercially available instrumentation amplifiers. Figure 7c
shows measured AC performance of this solution.
IN+
ARBITRARY
+
–
In Figure 8, another application circuit is shown which uses
two channels of the LTC2333-18 to sense the voltage on
and bidirectional current through a sense resistor over a
wide common mode range.
ADC REFERENCE
As shown previously in Table 1b, the LTC2333-18 supports
three reference configurations. The first uses both the internal bandgap reference and reference buffer. The second
externally overdrives the internal reference but retains the
internal buffer, which isolates the external reference from
ADC conversion transients. This configuration is ideal
for sharing a single precision external reference across
multiple ADCs. The third disables the internal buffer and
overdrives the REFBUF pin externally.
31V
LTC2057HV
INTERNAL HI-Z BUFFERS
ALLOW OPTIONAL
kΩ PASSIVE FILTERS
31V
3.65k
24V
2.49k
COMMON MODE
INPUT RANGE
549Ω
BUFFERED
ANALOG
INPUTS
GAIN = 10
2.2nF
2.49k
3.65k
IN–
–
+
VCC
IN0+
IN0–
LTC2333-18
DIFFERENTIAL MODE
INPUT RANGE: ±500mV
0V
0.1µF
LTC2057HV
BW = 10kHz
–7V
ONLY CHANNEL 0 SHOWN FOR CLARITY
VEE REFBUF
0.1µF
47µF
REFIN
0.1µF
–7V
233318 F07a
Figure 7a. Amplify Differential Signals with Gain of 10 Over a Wide Common Mode Range with Buffered Analog Inputs
233318f
24
For more information www.linear.com/LTC2333-18
LTC2333-18
APPLICATIONS INFORMATION
Internal Reference with Internal Buffer
160
±5V RANGE
150
140
CMRR (dB)
130
120
110
IN+ = IN– = 1VP–P SINE
100
90
80
70
60
10
100
1k
FREQUENCY (Hz)
10k
233318 F07b
Figure 7b. CMRR vs Input Frequency. Circuit Shown in Figure 7a
0
±5V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–20
SNR = 91.4dB
THD = –115dB
SINAD = 91.4dB
SFDR = 117dB
AMPLITUDE (dBFS)
–40
–60
–80
The LTC2333-18 has an on-chip, low noise, low drift
(20ppm/°C maximum), temperature compensated bandgap reference that is factory trimmed to 2.048V. The
reference output connects through a 20kΩ resistor to
the REFIN pin, which serves as the input to the on-chip
reference buffer, as shown in Figure 9a. When employing
the internal bandgap reference, the REFIN pin should be
bypassed to GND (Pin 20) close to the pin with a 0.1μF
ceramic capacitor to filter wideband noise. The reference
buffer amplifies VREFIN to create the converter master
reference voltage VREFBUF = 2 • VREFIN on the REFBUF pin,
nominally 4.096V when using the internal bandgap reference. Bypass REFBUF to GND (Pin 20) close to the pin with
at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or
X5R, 10V, 0805 size) to compensate the reference buffer,
absorb transient conversion currents, and minimize noise.
LTC2333-18
–100
–120
0.1µF
–140
REFBUF
–160
–180
20k
REFIN
0
80
160
240
FREQUENCY (kHz)
320
400
47µF
233318 F07c
BANDGAP
REFERENCE
REFERENCE
BUFFER
6.5k
6.5k
Figure 7c. IN+/IN– = 450mV 2kHz Fully Differential Sine,
0V ≤ VCM ≤ 24V, 32k Point FFT, fSMPL = 800ksps. Circuit
Shown in Figure 7a
GND
233318 F9a
15V
Figure 9a. Internal Reference with Internal Buffer Configuration
0.1µF
VS1
RSENSE
ISENSE
VS2
IN0+
IN0–
VCC
LTC2333-18
IN1+
–
IN1
VEE REFBUF
REFIN
0.1µF
0.1µF
47µF
233318 F08
–15V
ONLY CHANNELS 0 AND 1 SHOWN FOR CLARITY
V – VS2
ISENSE = S1
RSENSE
–10.24V ≤ VS1 ≤ 10.24V
–10.24V ≤ VS2 ≤ 10.24V
Figure 8. Sense Voltage (CH0) and Current (CH1) Over a
Wide Common Mode Range
233318f
For more information www.linear.com/LTC2333-18
25
LTC2333-18
APPLICATIONS INFORMATION
External Reference with Internal Buffer
External Reference with Disabled Internal Buffer
If more accuracy and/or lower drift is desired, REFIN can
be easily overdriven by an external reference since 20kΩ
of resistance separates the internal bandgap reference
output from the REFIN pin, as shown in Figure 9b. The
valid range of external reference voltage overdrive on the
REFIN pin is 1.25V to 2.2V, resulting in converter master reference voltages VREFBUF between 2.5V and 4.4V,
respectively. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power, and high
accuracy, the LTC6655-2.048 is well suited for use with the
LTC2333-18 when overdriving the internal reference. The
LTC6655-2.048 offers 0.025% (maximum) initial accuracy
and 2ppm/°C (maximum) temperature coefficient for high
precision applications. The LTC6655-2.048 is fully specified over the H-grade temperature range, complementing
the extended temperature range of the LTC2333-18 up to
125°C. Bypassing the LTC6655-2.048 with a 2.7µF to 100µF
ceramic capacitor close to the REFIN pin is recommended.
The internal reference buffer supports VREFBUF = 4.4V
maximum. By grounding REFIN, the internal buffer may
be disabled, allowing REFBUF to be overdriven with an
external reference voltage between 2.5V and 5V, as shown
in Figure 9c. Maximum input signal swing and SNR are
achieved by overdriving REFBUF using an external 5V
reference. The buffer feedback resistors load the REFBUF
pin with 13kΩ even when the reference buffer is disabled.
The LTC6655-5 offers the same small size, accuracy, drift,
and extended temperature range as the LTC6655-2.048,
and achieves a typical SNR of 97.9dB when paired with
the LTC2333-18. Bypass the LTC6655-5 to GND (Pin 20)
close to the REFBUF pin with at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or X5R, 10V, 0805 size) to
absorb transient conversion currents and minimize noise.
LTC2333-18
LTC2333-18
20k
REFIN
2.7µF
REFBUF
LTC6655-2.048
47µF
BANDGAP
REFERENCE
REFBUF
REFERENCE
BUFFER
6.5k
20k
REFIN
LTC6655-5
47µF
BANDGAP
REFERENCE
REFERENCE
BUFFER
6.5k
6.5k
6.5k
GND
GND
233318 F09b
Figure 9b. External Reference with Internal Buffer Configuration
233318 F09c
Figure 9c. External Reference with Disabled Internal
Buffer Configuration
233318f
26
For more information www.linear.com/LTC2333-18
LTC2333-18
APPLICATIONS INFORMATION
erence buffer and overdrives REFBUF with an external
LTC6655-4.096. In both cases REFBUF is bypassed to
GND with a 47µF ceramic capacitor.
15
DEVIATION FROM FINAL VALUE (LSB)
The LTC2333-18 converter draws a charge (QCONV) from
the REFBUF pin during each conversion cycle. On short
time scales most of this charge is supplied by the external
REFBUF bypass capacitor, but on longer time scales all of
the charge is supplied by either the reference buffer, or
when the internal reference buffer is disabled, the external
reference. This charge draw corresponds to a DC current
equivalent of IREFBUF = QCONV • fSMPL, which is proportional
to sample rate. In applications where a burst of samples
is taken after idling for long periods of time, as shown in
Figure 10, IREFBUF quickly transitions from approximately
0.4mA to 0.9mA (VREFBUF = 5V, fSMPL = 800ksps). This
current step triggers a transient response in the external
reference that must be considered, since any deviation in
VREFBUF affects converter accuracy. If an external reference
is used to overdrive REFBUF, the fast settling LTC6655
family of references is recommended.
±10.24V RANGE
IN+ = 10V
IN– = 0V
10
5
EXTERNAL REFERENCE ON REFBUF
0
INTERNAL REFERENCE BUFFER
–5
0
100
200
300
TIME (µs)
400
500
233318 F11
Figure 11. Burst Conversion Response of the
LTC2333-18, fSMPL = 800ksps
Internal Reference Buffer Transient Response
For optimum performance in applications employing burst
sampling, the external reference with internal reference
buffer configuration should be used. The internal reference
buffer incorporates a proprietary design that minimizes
movements in VREFBUF when responding to a burst of
conversions following an idle period. Figure 11 compares
the burst conversion response of the LTC2333-18 with an
input near full scale for two reference configurations. The
first configuration employs the internal reference buffer
with REFIN externally overdriven by an LTC6655-2.048,
while the second configuration disables the internal ref-
DYNAMIC PERFORMANCE
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion, and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2333-18 provides
guaranteed tested limits for both AC distortion and noise
measurements.
CNV
IDLE
PERIOD
IDLE
PERIOD
233318 F10
Figure 10. CNV Waveform Showing Burst Sampling
233318f
For more information www.linear.com/LTC2333-18
27
LTC2333-18
APPLICATIONS INFORMATION
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies below half the sampling frequency, excluding DC. Figure 12 shows that the LTC2333-18 achieves a
typical SINAD of 96.2dB in the ±10.24V range at a 800ksps
sampling rate with a true bipolar 2kHz input signal.
0
±10.24V RANGE
TRUE BIPOLAR DRIVE (IN– = 0V)
–20
AMPLITUDE (dBFS)
–40
SNR = 96.4dB
THD = –109dB
SINAD = 96.2dB
SFDR = 111dB
–60
–80
–100
–120
–140
–160
–180
0
100
200
300
FREQUENCY (kHz)
400
233318 F12
Figure 12. 32k Point FFT fSMPL = 800ksps, fIN = 2kHz
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 12 shows
that the LTC2333-18 achieves a typical SNR of 96.4dB in
the ±10.24V range at a 800ksps sampling rate with a true
bipolar 2kHz input signal.
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD = 20log
V22 + V32 + V42 ...VN2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through Nth harmonics, respectively. Figure 12 shows
that the LTC2333-18 achieves a typical THD of –109dB
(N = 6) in the ±10.24V range at a 800ksps sampling rate
with a true bipolar 2kHz input signal.
POWER CONSIDERATIONS
The LTC2333-18 requires four power supplies: the positive and negative high voltage power supplies (VCC and
VEE), the 5V core power supply (VDD) and the digital input/
output (I/O) interface power supply (OVDD). As long as
the voltage difference limits of 10V ≤ VCC – VEE ≤ 38V
are observed, VCC and VEE may be independently biased
anywhere within their own individual allowed operating
ranges, including the ability for VEE to be tied directly to
ground. This feature enables the common mode input
range of the LTC2333-18 to be tailored to the specific
application’s requirements. The flexible OVDD supply allows the LTC2333-18 to communicate with CMOS logic
operating between 1.8V and 5V, including 2.5V and 3.3V
systems. When using LVDS I/O mode, the range of OVDD
is 2.375V to 5.25V.
Power Supply Sequencing
The LTC2333-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2333-18 has
an internal power-on-reset (POR) circuit which resets the
converter on initial power-up and whenever VDD drops
below 2V. Once the supply voltage re-enters the nominal
233318f
28
For more information www.linear.com/LTC2333-18
LTC2333-18
APPLICATIONS INFORMATION
supply voltage range, the POR reinitializes the ADC. No
conversions should be initiated until at least 10ms after
a POR event to ensure the initialization period has ended.
When employing the internal reference buffer, allow 200ms
for the buffer to power up and recharge the REFBUF bypass
capacitor. Any conversion initiated before these times will
produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2333-18 sampling and conversion is controlled
by CNV. A rising edge on CNV transitions the S/H circuits
from track mode to hold mode, sampling the input signals
and initiating a conversion. Once a conversion has been
started, it cannot be terminated early except by resetting
the ADC, as discussed in the Reset Timing section. For
optimum performance, drive CNV with a clean, low jitter
signal and avoid transitions on data I/O lines leading up
to the rising edge of CNV. Additionally, for best crosstalk
performance, avoid high slew rates on the analog inputs for
100ns before and after the rising edge of CNV. Converter
status is indicated by the BUSY output, which transitions
low-to-high at the start of each conversion and stays high
until the conversion is complete. Once CNV is brought high
to begin a conversion, it should be returned low between
40ns and 60ns later or after the falling edge of BUSY to
minimize external disturbances during the internal conversion process. The CNV timing required to take advantage
of the reduced power nap mode of operation is described
in the Nap Mode section.
Internal Conversion Clock
The LTC2333-18 has an internal clock that is trimmed
to achieve a maximum conversion time of 550ns. With
a minimum acquisition time of 670ns, throughput performance of 800ksps is guaranteed without any external
adjustments. The LTC2333-18 is a multiplexed ADC and
converts one channel per CNV edge, taking a minimum of
1.25μs per conversion. Thus, while scanning N channels
(N = 1 to 8), a complete scan takes at least 1.25 • N μs and
the maximum per-channel throughput is 800/N ksps/ch.
Nap Mode
The LTC2333-18 can be placed into nap mode after a conversion has been completed to reduce power consumption
between conversions. In this mode a portion of the device
circuitry is turned off, including circuits associated with
sampling the analog input signals. Nap mode is enabled
by keeping CNV high between conversions, as shown in
Figure 13. To initiate a new conversion after entering nap
mode, bring CNV low and hold for at least 750ns before
bringing it high again. The converter acquisition time (tACQ)
is set by the CNV low time (tCNVL) when using nap mode.
Power Down Mode
When PD is brought high, the LTC2333-18 is powered
down and subsequent conversion requests are ignored. If
this occurs during a conversion, the device powers down
once the conversion completes. In this mode, the device
draws only a small regulator standby current resulting in a
typical power dissipation of 0.68mW. To exit power down
t CNVL
CNV
tCONV
BUSY
NAP
NAP MODE
tACQ
233318 F13
Figure 13. Nap Mode Timing for the LTC2333-18
233318f
For more information www.linear.com/LTC2333-18
29
LTC2333-18
APPLICATIONS INFORMATION
Reset Timing
A global reset of the LTC2333-18, equivalent to a poweron-reset event, may be executed without needing to cycle
the supplies. This feature is useful when recovering from
system-level events that require the state of the entire system to be reset to a known synchronized value. To initiate
a global reset, bring PD high twice without an intervening
conversion, as shown in Figure 14. The reset event is triggered on the second rising edge of PD, and asynchronously
ends based on an internal timer. Reset clears all serial data
output registers and restores the internal sequencer default
state of converting channels 0 through 7 sequentially, all
in SoftSpan 7. If reset is triggered during a conversion, the
conversion is immediately halted. The normal power down
behavior associated with PD going high is not affected by
reset. Once PD is brought low, wait at least 10ms before
initiating a conversion. When employing the internal reference buffer, allow 200ms for the buffer to power up and
recharge the REFBUF bypass capacitor. Any conversion
initiated before these times will produce invalid results.
Power Dissipation vs Sampling Frequency
When nap mode is employed, the power dissipation of
the LTC2333-18 decreases as the sampling frequency is
reduced, as shown in Figure 15. This decrease in average power dissipation occurs because a portion of the
LTC2333-18 circuitry is turned off during nap mode, and
the fraction of the conversion cycle (tCYC) spent napping
increases as the sampling frequency (fSMPL) is decreased.
14
WITH NAP MODE
12 tCNVL = 750ns
10
SUPPLY CURRENT (mA)
mode, bring the PD pin low and wait at least 10ms before
initiating a conversion. When employing the internal reference buffer, allow 200ms for the buffer to power up and
recharge the REFBUF bypass capacitor. Any conversion
initiated before these times will produce invalid results.
IVDD
8
6
IVCC
4
2
0
IOVDD
–2
–4
IVEE
–6
–8
0
160
320
480
640
SAMPLING FREQUENCY (kHz)
800
233318 F15
Figure 15. Power Dissipation of the LTC2333-18
Decreases with Decreasing Sampling Frequency
tPDH
t WAKE
PD
CNV
BUSY
RESET
tPDL
tCNVH
tCONV
SECOND RISING EDGE OF
PD TRIGGERS RESET
RESET TIME
SET INTERNALLY
233318 F14
Figure 14. Reset Timing for the LTC2333-18
233318f
30
For more information www.linear.com/LTC2333-18
LTC2333-18
APPLICATIONS INFORMATION
DIGITAL INTERFACE
Within a window, the device accepts control words on SDI
to configure the SoftSpan range and channel for the next
conversion and program the sequencer, and outputs 24-bit
packets containing the conversion result and configuration
information from the previous conversion on SDO.
The LTC2333-18 features CMOS and LVDS serial interfaces,
selectable using the LVDS/CMOS pin. The flexible OVDD
supply allows the LTC2333-18 to communicate with any
CMOS logic operating between 1.8V and 5V, including 2.5V
and 3.3V systems, while the LVDS interface supports low
noise digital designs. Together, these I/O interface options
enable the LTC2333-18 to communicate equally well with
legacy microcontrollers and modern FPGAs.
New data transaction windows open 10ms after powering up or resetting the LTC2333-18, and at the end of
each conversion on the falling edge of BUSY. The data
transaction should be completed with a minimum tQUIET
time of 20ns prior to the start of the next conversion, as
shown in Figure 16. New control words are only accepted
within this recommended data transaction window, but
configuration changes take effect immediately with no additional analog input settling time required before starting
the next conversion.
Serial CMOS I/O Mode
As shown in Figure 16, in CMOS I/O mode the serial data
bus consists of a serial clock input, SCKI, serial data input,
SDI, serial clock output, SCKO, and serial data output,
SDO. Communication with the LTC2333-18 across this
bus occurs during predefined data transaction windows.
CS = PD = 0
SAMPLE N
SAMPLE N + 1
t CYC
tCNVH
t CNVL
CNV
tCONV
BUSY
t ACQ
tBUSYLH
RECOMMENDED DATA TRANSACTION WINDOW
t SSDISCKI
SCKI
SDI
1
C7
DON’T CARE
2
3
4
5
6
7
C6
C5
C4
C3
C2
C1
t SCKI
8
9 10
t HSDISCKI
11
12
13
t QUIET
t SCKIH
14
15
16
17
18
19 20
t SCKIL
21
22
23
24
C0
DON’T CARE
CONTROL WORD FOR CONVERSION N + 1
t DSDOBUSYL
t SKEW
t HSDOSCKI
SCKO
t DSDOSCKI
SDO
DON’T CARE
D17
D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2 D1
CONVERSION RESULT
D0 CH2 CH1 CH0 SS2 SS1 SS0 D17
CHANNEL ID
24-BIT PACKET CONVERSION N
SoftSpan
CONVERSION RESULT
24-BIT PACKET CONVERSION N
(REPETITION) 233318 F16
Figure 16. Serial CMOS I/O Mode, Direct Per-Conversion Configuration
233318f
For more information www.linear.com/LTC2333-18
31
LTC2333-18
APPLICATIONS INFORMATION
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SCKO is forced low and
SDO is updated with the latest conversion result from the
just-completed conversion. Rising edges on SCKI serially
clock the conversion result and analog input channel configuration information out on SDO and trigger transitions
on SCKO that are skew-matched to the data on SDO. The
resulting SCKO frequency is half that of SCKI.
SCKI rising edges also latch control words provided on
SDI, which are used to set the SoftSpan range and channel for the next conversion, and program the sequencer.
See the section Configuring the Multiplexer and SoftSpan
Range for further details. SCKI is allowed to idle either
high or low in CMOS I/O mode. As shown in Figure 17,
the CMOS bus is enabled when CS is low and is disabled
and Hi-Z when CS is high, allowing the bus to be shared
across multiple devices.
The data on SDO are formatted as a 24-bit packet consisting
of an 18-bit conversion result, 3-bit analog channel ID, and
3-bit SoftSpan code, all presented MSB first. As suggested
in Figures 16 and 17, if more than 24 SCKI clocks are
applied, the 24-bit packet is repeated indefinitely on SDO.
When interfacing the LTC2333-18 with a standard SPI
bus, capture output data at the receiver on rising edges
of SCKI. SCKO is not used in this case. In other applications, such as interfacing the LTC2333-18 with an FPGA
or CPLD, rising and falling edges of SCKO may be used
to capture serial output data on SDO in double data rate
(DDR) fashion. Capturing data using SCKO adds robustness to delay variations over temperature and supply.
The LTC2333-18 guarantees a minimum data transfer window (tACQ – tQUIET) of 650ns while converting at 800ksps.
Thus, if an application needs to read the full 24-bit packet
of conversion result plus channel ID and SoftSpan, the
minimum usable SCKI frequency is 37MHz. Applications
needing to read only the conversion result may send only
18 SCKI pulses and thus have a minimum SCKI frequency
of 28MHz. The LTC2333-18 supports CMOS SCKI frequencies up to 100MHz.
Configuring the Multiplexer and SoftSpan Range in
CMOS I/O Mode
On power-up and after a reset, the LTC2333-18 defaults
to converting channels 0 through 7 sequentially, all in
SoftSpan 7. If this configuration does not need to be
changed, simply hold SDI low.
The LTC2333-18 multiplexer and SoftSpan range may
be controlled in two ways, depending on the needs of
the application. If the desired sequence of channels and
SoftSpan ranges are known ahead of time, the LTC233318’s internal sequencer may be programmed with a sequence of up to 16 configurations, and will cycle through
those configurations on subsequent conversions without
further user intervention. Alternately, if ultimate flexibility
is desired, the LTC2333-18 may be directly controlled by
overwriting the sequencer each conversion with the channel and SoftSpan range for the following conversion. This
reconfiguration has no latency and requires no additional
settling time or digital I/O overhead.
Using the Sequencer
To use the internal sequencer of the LTC2333-18, first
program it as described below with the desired sequence
of up to 16 configurations. Each of these configurations
specifies the desired channel number and SoftSpan range
for one conversion. The LTC2333-18 will then apply the
first configuration to the first conversion, the second
configuration to the second conversion, and so on until
the end of the programmed sequence is reached, at which
point the cycle will start again from the beginning.
Each data transaction window is an opportunity to program
the sequencer by clocking in a series of 8-bit control words
on SDI, each specifying a channel number and SoftSpan
range, as shown in Figures 16 and 17. To program the
sequencer with a series of up to 16 conversion configurations, write in the corresponding control words in the
desired conversion order during a single data transaction.
Words beyond the 16th valid word will be ignored.
233318f
32
For more information www.linear.com/LTC2333-18
SDO
tEN
24-BIT RESULT PACKET
PARTIAL WORD
(IGNORED)
RESULT PACKET
(PARTIAL)
Figure 17. Programming the Sequencer for a 10-Conversion Sequence, Serial CMOS Bus Response to CS
24-BIT RESULT PACKET
CONTROL WORD CONTROL WORD
FOR CONV N + 9 FOR CONV N + 10
t DIS
233318 F17
DON’T CARE
Hi-Z
24-BIT RESULT PACKET
CONTROL WORD
FOR CONV N + 8
Hi-Z
CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD
FOR CONV N + 2 FOR CONV N + 3 FOR CONV N + 4 FOR CONV N + 5 FOR CONV N + 6 FOR CONV N + 7
Hi-Z
CONTROL WORD
FOR CONV N + 1
DON’T CARE
Hi-Z
DON’T CARE
SDI
SCKO
DON’T CARE
SCKI
CS
BUSY
PD = 0
LTC2333-18
APPLICATIONS INFORMATION
233318f
For more information www.linear.com/LTC2333-18
33
LTC2333-18
APPLICATIONS INFORMATION
The control word format is as follows:
C[7]
C[6]
V
0
C[5]
C[4]
C[3]
C[2]
C[1]
C[0]
CH[2] CH[1] CH[0] SS[2] SS[1] SS[0]
The V bit (C[7]) controls whether the LTC2333-18 should
consider this a valid word. Any words which have V =
0 are considered invalid and are ignored (though valid
words will still be accepted after an invalid word). Words
which have V = 1 will be added to the sequencer in the
order provided. The C[6] bit is reserved for future use and
should be set to 0. The CH[2:0] (C[5:3]) bits are a binary
value 0 to 7 controlling the channel to be converted. The
SS[2:0] (C[2:0]) bits specify the desired SoftSpan range
for the conversion, as described in Table 1.
Sequencer programming is completed when the next
conversion is started. At this time, any incomplete words
are considered invalid and discarded. If one or more
valid words were provided, the sequencer is completely
overwritten with the new sequence, and the just-initiated
conversion employs the first provided configuration.
If no valid words were provided during the data transaction window, the sequencer program is unchanged, and
the pointer advances to the next entry in the previously
programmed cycle to configure the next conversion.
Thus, once the sequencer has been programmed, simply
hold SDI low during subsequent data transactions to
cycle continually through the programmed sequence of
configurations.
Direct Per-Conversion Configuration
As a special case of the sequencer, the LTC2333-18
multiplexer and SoftSpan range can be directly controlled
every conversion with no latency and no additional settling time or digital I/O overhead. To use the part in this
direct fashion, simply supply one control word on SDI
during a data transaction to specify the desired channel
number and SoftSpan range for the following conversion,
as shown in Figure 16.
If the desired channel and SoftSpan range for conversion
N+1 are known before seeing the result of conversion N,
specify the configuration by clocking in the corresponding
control word on SDI while clocking out the first 8 bits,
then hold SDI low. This particular use case is illustrated in
Figure 16. If the desired configuration is not known until
after the conversion data has been read, clock in 24 zeros
on SDI while the 24 bits of data are being read out; since
the V bits of those words are then 0, they are ignored.
Once the configuration has been determined, clock in 8
more bits on SDI which specify the desired configuration
for conversion N+1.
Serial LVDS I/O Mode
In LVDS I/O mode, information is transmitted using
positive and negative signal pairs (LVDS+/LVDS−) with bits
differentially encoded as (LVDS+ − LVDS−). These signals
are typically routed using differential transmission lines
with 100Ω characteristic impedance. Logical 1s and 0s
are nominally represented by differential +350mV and
−350mV, respectively. For clarity, all LVDS timing diagrams
and interface discussions adopt the logical rather than
physical convention.
As shown in Figure 18, in LVDS I/O mode the serial data
bus consists of a serial clock differential input, SCKI, serial
data differential input, SDI, serial clock differential output,
SCKO, and serial data differential output, SDO. Communication with the LTC2333-18 across this bus occurs during
predefined data transaction windows. Within a window,
the device accepts control words on SDI to configure the
SoftSpan range and channel for the next conversion and
program the sequencer, and outputs 24-bit packets containing the conversion result and configuration information
from the previous conversion on SDO.
New data transaction windows open 10ms after powering up or resetting the LTC2333-18, and at the end of
each conversion on the falling edge of BUSY. The data
transaction should be completed with a minimum tQUIET
233318f
34
For more information www.linear.com/LTC2333-18
LTC2333-18
APPLICATIONS INFORMATION
CS = PD = 0
SAMPLE N
CNV
(CMOS)
SAMPLE N + 1
t CYC
t CNVH
t CNVL
BUSY
(CMOS)
t CONV
t ACQ
t BUSYLH
RECOMMENDED DATA TRANSACTION WINDOW
t SSDISCKI
SCKI
(LVDS)
1
2
3
4
5
6
7
8
t SCKI
9
10
11
12
13
14
15
16
C7
DON’T CARE
C6
C5
C4
C3
C2
C1
17
18
19
20
21
22
23
24
t SCKIL
t HSDISCKI
SDI
(LVDS)
t QUIET
t SCKIH
C0
DON’T CARE
CONTROL WORD FOR CONVERSION N + 1
t DSDOBUSYL
t SKEW
t HSDOSCKI
SCKO
(LVDS)
t DSDOSCKI
SDO
(LVDS)
DON’T CARE
D17
D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
CONVERSION RESULT
D2
D1
D0 CH2 CH1 CH0 SS2 SS1 SS0
CHANNEL ID
24-BIT PACKET CONVERSION N
SoftSpan
D17
CONVERSION RESULT
24-BIT PACKET CONVERSION N
(REPETITION) 233318 F18
Figure 18. Serial LVDS I/O Mode, Direct Per-Conversion Configuration
time of 20ns prior to the start of the next conversion, as
shown in Figure 18. New control words are only accepted
within this recommended data transaction window, but
configuration changes take effect immediately with no additional analog input settling time required before starting
the next conversion.
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SDO is updated with the
latest conversion result from the just-completed conversion. Both rising and falling edges on SCKI serially clock the
conversion result and analog input channel configuration
information out on SDO. SCKI is also echoed on SCKO,
skew-matched to the data on SDO. Whenever possible,
it is recommend that rising and falling edges of SCKO be
used to capture DDR serial output data on SDO, as this will
yield the best robustness to delay variations over supply
and temperature.
SCKI rising and falling edges also latch control words
provided on SDI, which are used to set the SoftSpan range
and channel for the next conversion, and program the
sequencer. See the section Configuring the Multiplexer
and SoftSpan Range in LVDS I/O Mode for further details.
As shown in Figure 19, the LVDS bus is enabled when CS
is low and is disabled and Hi-Z when CS is high, allowing the bus to be shared across multiple devices. Due to
the high speeds often involved in LVDS signaling, LVDS
bus sharing must be carefully considered. Transmission
line limitations imposed by the shared bus may limit the
maximum achievable bus clock speed. LVDS inputs are
internally terminated with a 100Ω differential resistor when
CS is low, while outputs must be differentially terminated
with a 100Ω resistor at the receiver (FPGA). SCKI must
idle in the low state in LVDS I/O mode, including when
transitioning CS.
233318f
For more information www.linear.com/LTC2333-18
35
36
SDO
(LVDS)
tEN
24-BIT RESULT PACKET
RESULT PACKET
(PARTIAL)
Figure 19. Programming the Sequencer with a 10-Conversion Sequence, Serial LVDS Bus Response to CS
24-BIT RESULT PACKET
t DIS
233318 F19
DON’T CARE
Hi-Z
24-BIT RESULT PACKET
PARTIAL WORD
(IGNORED)
Hi-Z
CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD
FOR CONV N + 2 FOR CONV N + 3 FOR CONV N + 4 FOR CONV N + 5 FOR CONV N + 6 FOR CONV N + 7 FOR CONV N + 8 FOR CONV N + 9 FOR CONV N + 10
Hi-Z
CONTROL WORD
FOR CONV N + 1
DON’T CARE
Hi-Z
DON’T CARE
SDI
(LVDS)
SCKO
(LVDS)
DON’T CARE
SCKI
(LVDS)
CS
(CMOS)
BUSY
(CMOS)
PD = 0
LTC2333-18
APPLICATIONS INFORMATION
233318f
For more information www.linear.com/LTC2333-18
LTC2333-18
APPLICATIONS INFORMATION
The data on SDO are formatted as a 24-bit packet consisting
of an 18-bit conversion result, 3-bit analog channel ID, and
3-bit SoftSpan code, all presented MSB first. As suggested
in Figures 18 and 19, if more than 24 SCKI clocks are
applied, the 24-bit packet is repeated indefinitely on SDO.
for one conversion. The LTC2333-18 will then apply the
first configuration to the first conversion, the second
configuration to the second conversion, and so on until
the end of the programmed sequence is reached, at which
point the cycle will start again from the beginning.
The LTC2333-18 guarantees a minimum data transfer window (tACQ – tQUIET) of 650ns while converting at 800ksps.
Thus, if an application needs to read the full 24-bit packet
of conversion result plus channel ID and SoftSpan, the
minimum usable SCKI frequency is 19MHz (38Mbps). Applications needing to read only the conversion result may
send only 18 SCKI edges and thus have a minimum SCKI
frequency of 14MHz (28Mbps). The LTC2333-18 supports
LVDS SCKI frequencies up to 250MHz (500Mbps).
Each data transaction window is an opportunity to program
the sequencer by clocking in a series of 8-bit control words
on SDI, each specifying a channel number and SoftSpan
range, as shown in Figures 18 and 19. To program the
sequencer with a series of up to 16 conversion configurations, write in the corresponding control words in the
desired conversion order during a single data transaction.
Words beyond the 16th valid word will be ignored.
Configuring the Multiplexer and SoftSpan Range in
LVDS I/O Mode
On power-up and after a reset, the LTC2333-18 defaults
to converting channels 0 through 7 sequentially, all in
SoftSpan 7. If this configuration does not need to be
changed, simply hold SDI at an LVDS low level.
The LTC2333-18 multiplexer and SoftSpan range may be
controlled in two ways, depending on the needs of the application. If the desired sequence of channels and SoftSpan
ranges are known ahead of time, the LTC2333-18’s internal
sequencer may be programmed with a sequence of up to
16 configurations, and will cycle through those configurations on subsequent conversions without further user
intervention. Alternately if ultimate flexibility is desired, the
LTC2333-18 may be directly controlled by overwriting the
sequencer each conversion with the channel and SoftSpan
range for the following conversion. This reconfiguration
has no latency and requires no additional settling time or
digital I/O overhead.
Using the Sequencer
To use the internal sequencer of the LTC2333-18, first
program it as described below with the desired sequence
of up to 16 configurations. Each of these configurations
specifies the desired channel number and SoftSpan range
The control word format is as follows:
C[7]
C[6]
V
0
C[5]
C[4]
C[3]
C[2]
C[1]
C[0]
CH[2] CH[1] CH[0] SS[2] SS[1] SS[0]
The V bit (C[7]) controls whether the LTC2333-18 should
consider this a valid word. Any words which have V =
0 are considered invalid and are ignored (though valid
words will still be accepted after an invalid word). Words
which have V = 1 will be added to the sequencer in the
order provided. The C[6] bit is reserved for future use and
should be set to 0. The CH[2:0] (C[5:3]) bits are a binary
value 0 to 7 controlling the channel to be converted. The
SS[2:0] (C[2:0]) bits specify the desired SoftSpan range
for the conversion, as described in Table 1.
Sequencer programming is completed when the next
conversion is started. At this time, any incomplete words
are considered invalid and discarded. If one or more
valid words were provided, the sequencer is completely
overwritten with the new sequence, and the just-initiated
conversion employs the first provided configuration.
If no valid words were provided during the data transaction window, the sequencer program is unchanged, and
the pointer advances to the next entry in the previously
programmed cycle to configure the next conversion.
233318f
For more information www.linear.com/LTC2333-18
37
LTC2333-18
APPLICATIONS INFORMATION
Thus, once the sequencer has been programmed, simply
hold SDI at an LVDS low level during subsequent data
transactions to cycle continually through the programmed
sequence of configurations.
Direct Per-Conversion Configuration
As a special case of the sequencer, the LTC2333-18
multiplexer and SoftSpan range can be directly controlled
every conversion with no latency and no additional settling time or digital I/O overhead. To use the part in this
direct fashion, simply supply one control word on SDI
during a data transaction to specify the desired channel
number and SoftSpan range for the following conversion,
as shown in Figure 18.
If the desired channel and SoftSpan range for conversion
N+1 are known before seeing the result of conversion N,
specify the configuration by clocking in the corresponding
control word on SDI while clocking out the first 8 bits,
then hold SDI at an LVDS low level. This particular use
case is illustrated in Figure 18. If the desired configuration is not known until after the conversion data has been
read, clock in 24 zeros on SDI while the 24 bits of data
are being read out; since the V bits of those words are
then 0, they are ignored. Once the configuration has been
determined, clock in 8 more bits on SDI which specify the
desired configuration for conversion N+1.
BOARD LAYOUT
To obtain the best performance from the LTC2333-18, a
four-layer printed circuit board (PCB) is recommended.
Layout for the PCB should ensure the digital and analog
signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
Also minimize the length of the REFBUF to GND (Pin 20)
bypass capacitor return loop, and avoid routing CNV near
signals which could potentially disturb its rising edge.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Reference Design
For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer
to DC2365, the evaluation kit for the LTC2333-18.
233318f
38
For more information www.linear.com/LTC2333-18
LTC2333-18
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2333-18#packaging for the most recent package drawings.
LX Package
48-Lead Plastic LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1760 Rev A)
7.15 – 7.25
9.00 BSC
5.50 REF
7.00 BSC
48
0.50 BSC
1
2
48
SEE NOTE: 4
1
2
9.00 BSC
5.50 REF
7.00 BSC
7.15 – 7.25
0.20 – 0.30
A
A
PACKAGE OUTLINE
C0.30 – 0.50
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.60
1.35 – 1.45 MAX
11° – 13°
R0.08 – 0.20
GAUGE PLANE
0.25
0° – 7°
11° – 13°
0.09 – 0.20
1.00 REF
0.50
BSC
0.17 – 0.27
0.05 – 0.15
0.45 – 0.75
SECTION A – A
COMPONENT
PIN “A1”
TRAY PIN 1
BEVEL
XXYY
LTCXXXX
LX-ES
Q_ _ _ _ _ _
e3
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE
2. DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
5. DRAWING IS NOT TO SCALE
LX48 LQFP 0113 REV A
PACKAGE IN TRAY LOADING ORIENTATION
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
233318f
For more information www.linear.com/LTC2333-18
39
LTC2333-18
TYPICAL APPLICATION
Amplify Differential Signals with Gain of 10 Over a Wide Common Mode Range with Buffered Analog Inputs
+
–
IN+
ARBITRARY
31V
LTC2057HV
INTERNAL HI-Z BUFFERS
ALLOW OPTIONAL
kΩ PASSIVE FILTERS
31V
3.65k
24V
BUFFERED
ANALOG
INPUTS
2.49k
COMMON MODE
INPUT RANGE
549Ω
GAIN = 10
2.2nF
2.49k
3.65k
IN–
–
+
VCC
IN0+
IN0–
LTC2333-18
DIFFERENTIAL MODE
INPUT RANGE: ±500mV
0V
0.1µF
LTC2057HV
BW = 10kHz
–7V
ONLY CHANNEL 0 SHOWN FOR CLARITY
VEE REFBUF
0.1µF
47µF
REFIN
0.1µF
–7V
233318 TA02
RELATED PARTS
PART NUMBER
ADCs
LTC2358-18/LTC2358-16
DESCRIPTION
COMMENTS
Buffered 18-/16-bit, 200ksps/Ch, 8-Channel
Simultaneous Sampling, ±3.5LSB/±1LSB INL
LTC2335-18/LTC2335-16 18-/16-Bit, 1Msps, 8-Channel Multiplexed,
±3LSB/±1LSB INL, Serial ADC
LTC2348-18/LTC2348-16 18-/16-Bit, 200ksps/Ch, 8-Channel Simultaneous
Sampling, ±3/±1LSB INL, Serial ADC
LTC2345-18/LTC2345-16 18-/16-Bit, 200ksps/Ch, 8-Channel Simultaneous
Sampling, ±5/±1.25LSB INL, Serial ADC
LTC2338-18/LTC2337-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial,
Low Power ADC
LTC2336-18
LTC2328-18/LTC2327-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial,
LTC2326-18
Low Power ADC
LTC2373-18/LTC2372-18 18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC
LTC1859/LTC1858/
LTC1857
DACs
LTC2756/LTC2757
LTC2668
References
LTC6655
LT6657
Amplifiers
LTC2057/LTC2057HV
LT6020
LT1354/LT1355/LT1356
16-/14-/12-Bit, 8-Channel, 100ksps, Serial ADC
Buffered ±10.24V SoftSpan Inputs with Wide Common Mode Range,
96/94dB SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
±10.24V SoftSpan Inputs with Wide Common Mode Range, 97dB/94dB SNR,
Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
±10.24V SoftSpan Inputs with Wide Common Mode Range, 97/94dB SNR,
Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
±4.096V, SoftSpan Inputs with Wide Common Mode Range, 92/91dB SNR,
Serial CMOS and LVDS I/O, 7mm × 7mm QFN-48 Package
5V Supply, ±10.24V Fully Differential Input, 100dB SNR, MSOP-16 Package
5V Supply, ±10.24V Pseudo-Differential Input, 95dB SNR,
MSOP-16 Package
5V Supply, 8-Channel Multiplexed, Configurable Input Range, 100dB SNR,
DGC, 5mm × 5mm QFN-32 Package
±10V, SoftSpan, Single-Ended or Differential Inputs, Single 5V Supply,
SSOP-28 Package
18-Bit, Serial/Parallel IOUT SoftSpan DAC
±1LSB INL/DNL, Software-Selectable Ranges,
SSOP-28/7mm × 7mm LQFP-48 Package
16-Channel 16-/12-Bit ±10V VOUT SoftSpan DACs ±4LSB INL, Precision Reference 10ppm/°C Max, 6mm × 6mm QFN-40 Package
Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
Precision Low Drift Low Noise Buffered Reference 5V/3V/2.5V, 1.5ppm/°C, 0.5ppm Peak-to-Peak Noise, MSOP-8 Package
High Voltage, Low Noise Zero-Drift Op Amp
Dual, Micropower, 5Vµs, Rail-to-Rail Op Amp
Single/Dual/Quad 1mA, 12MHz, 400V/µs Op Amp
Maximum Input Offset: 4.5µV, Supply Voltage Range: 4.75V to 60V
Maximum Input Offset: 30µV, Maximum Supply Current: 100µA/Amplifier
Good DC Precision, Stable with All Capacitive Loads
233318f
40
LT 0517 • PRINTED IN USA
For more information www.linear.com/LTC2333-18
www.linear.com/LTC2333-18
LINEAR TECHNOLOGY CORPORATION 2017
