LTC2341-16
Dual, 16-Bit, 666ksps/ch
Differential SoftSpan ADC with
Wide Input Common Mode Range
DESCRIPTION
FEATURES
666ksps per Channel Throughput
nn Two Simultaneous Sampling Channels
nn ±1.25LSB INL (Maximum)
nn Guaranteed 16-Bit, No Missing Codes
nn Differential, Wide Common Mode Range Inputs
nn Per-Channel SoftSpan Input Ranges:
±4.096V, 0V to 4.096V, ±2.048V, 0V to 2.048V
±5V, 0V to 5V, ±2.5V, 0V to 2.5V
nn 93.4dB Single-Conversion SNR (Typical)
nn −114dB THD (Typical) at f = 2kHz
IN
nn 105dB CMRR (Typical) at f = 200Hz
IN
nn Rail-to-Rail Input Overdrive Tolerance
nn Guaranteed Operation to 125°C
nn Integrated Reference and Buffer (4.096V)
nn SPI CMOS (1.8V to 5V) and LVDS Serial I/O
nn Internal Conversion Clock, No Cycle Latency
nn 74mW Power Dissipation (Typical)
nn 32-Lead (5mm × 5mm) QFN Package
The LTC®2341-16 is a 16-bit, low noise 2-channel simultaneous sampling successive approximation register (SAR)
ADC with differential, wide common mode range inputs.
Operating from a 5V supply and using the internal reference
and buffer, both channels of this SoftSpanTM ADC can be
independently configured on a conversion-by-conversion
basis to accept ±4.096V, 0V to 4.096V, ±2.048V, or 0V
to 2.048V signals. One channel may also be disabled to
increase throughput on the other channel.
nn
The wide input common mode range and 105dB CMRR of
the LTC2341-16 analog inputs allow the ADC to directly
digitize a variety of signals, simplifying signal chain design.
This input signal flexibility, combined with ±1.25LSB INL,
no missing codes at 16 bits, and 93.4dB SNR, makes the
LTC2341-16 an ideal choice for many applications requiring wide dynamic range.
The LTC2341-16 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces. Either one or two lanes
of data output may be employed in CMOS mode, allowing
the user to optimize bus width and throughput.
APPLICATIONS
Programmable Logic Controllers
nn Industrial Process Control
nn Medical Imaging
nn High Speed Data Acquisition
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673,
9197235.
nn
TYPICAL APPLICATION
5V
0.1µF
VDD
5V
VDDLBYP
LTC2341-16
5V
16-BIT
SAR ADC
MUX
UNIPOLAR
IN1+ S/H
IN1–
0V
0V
DIFFERENTIAL INPUTS IN+/IN– WITH
WIDE INPUT COMMON MODE RANGE
REFBUF
TWO SIMULTANEOUS
SAMPLING CHANNELS
47µF
REFIN
GND
0.1µF
0.75
OVDD LVDS/CMOS
PD
0V
BIPOLAR
1.00
CMOS OR LVDS
I/O INTERFACE
FULLY
DIFFERENTIAL
5V
IN0+ S/H
IN0–
0V
Codeand
andChannel
Channel
vs Output
Output Code
SDO0
SDO1
SCKO
SCKI
SDI
CS
BUSY
CNV
234116 TA01a
0.50
INL ERROR (LSB)
5V
ARBITRARY
Integral Nonlinearity vs
1.8V TO 5V
0.1µF
2.2µF
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ALL CHANNELS
0.25
0
–0.25
–0.50
SAMPLE
CLOCK
–0.75
–1.00
–32768
–16384
0
16384
OUTPUT CODE
32768
234116 TA01b
234116f
For more information www.linear.com/LTC2341-16
1
LTC2341-16
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
ORDER INFORMATION
SDO–/SDI
BUSY
CS
VDDLBYP
GND
VDD
GND
GND
TOP VIEW
32 31 30 29 28 27 26 25
IN1– 1
24 SDO+
IN1+
2
23 SCKO–/SDO1
GND 3
22 SCKO+/SCKO
GND 4
21 OVDD
33
GND
GND 5
20 GND
GND 6
19 SCKI–/SCKI
–
7
18 SCKI+/SDO0
IN0+
8
17 SDI–
IN0
SDI+
CNV
LVDS/CMOS
PD
REFBUF
GND
GND
9 10 11 12 13 14 15 16
REFIN
Supply Voltage (VDD)...................................................6V
Supply Voltage (OVDD).................................................6V
Internal Regulated Supply Bypass (VDDLBYP).... (Note 3)
Analog Input Voltage
IN0+, IN1+,
IN0–, IN1– (Note 4)...................... –0.3V to (VDD + 0.3V)
REFIN..................................................... –0.3V to 2.8V
REFBUF, CNV (Note 4).............. –0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4)...... –0.3V to (OVDD + 0.3V)
Digital Output Voltage (Note 4)... –0.3V to (OVDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC2341C................................................. 0°C to 70°C
LTC2341I...............................................–40°C to 85°C
LTC2341H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 150°C, θJA = 44°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC2341-16#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2341CUH-16#PBF
LTC2341CUH-16#TRPBF
234116
32-Lead (5mm × 5mm) Plastic QFN
0°C to 70°C
LTC2341IUH-16#PBF
LTC2341IUH-16#TRPBF
234116
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
LTC2341HUH-16#PBF
LTC2341HUH-16#TRPBF
234116
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
234116f
For more information www.linear.com/LTC2341-16
LTC2341-16
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIN
+
Absolute Input Range
(IN0+, IN1+)
VIN–
Absolute Input Range
(IN0–, IN1–)
VIN+ – VIN– Input Differential Voltage
Range
VCM
MAX
UNITS
0
VDD
V
l
0
VDD
V
l
l
l
l
l
l
l
– VREFBUF
– VREFBUF/1.024
0
0
–0.5 • VREFBUF
–0.5 • VREFBUF/1.024
0
VREFBUF
VREFBUF/1.024
VREFBUF
VREFBUF/1.024
0.5 • VREFBUF
0.5 • VREFBUF/1.024
0.5 • VREFBUF
V
V
V
V
V
V
V
l
0
VDD
V
l
−VDD
VDD
V
l
–1
1
µA
(Note 6)
(Note 6)
SoftSpan 7: ±VREFBUF Range (Note 6)
SoftSpan 6: ±VREFBUF/1.024 Range (Note 6)
SoftSpan 5: 0V to VREFBUF Range (Note 6)
SoftSpan 4: 0V to VREFBUF/1.024 Range (Note 6)
SoftSpan 3: ±0.5 • VREFBUF Range (Note 6)
SoftSpan 2: ±0.5 • VREFBUF/1.024 Range (Note 6)
SoftSpan 1: 0V to 0.5 • VREFBUF Range (Note 6)
Input Common Mode Voltage (Note 6)
Range
VIN+ – VIN– Input Differential Overdrive
Tolerance
MIN
l
(Note 7)
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
Sample Mode
Hold Mode
CMRR
Input Common Mode
Rejection Ratio
VIN+ = VIN− = 3.6VP-P 200Hz Sine
VIHCNV
l
88
CNV High Level Input Voltage
l
1.3
VILCNV
CNV Low Level Input Voltage
l
IINCNV
CNV Input Current
VIN = 0V to VDD
TYP
90
10
pF
pF
105
dB
V
–10
l
0.5
V
10
μA
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN
Resolution
No Missing Codes
Transition Noise
SoftSpans 7 and 6: ±4.096V and ±4V Ranges
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges
SoftSpans 3 and 2: ±2.048V and ±2V Ranges
SoftSpan 1: 0V to 2.048V Range
INL
Integral Linearity Error
(Note 9)
DNL
ZSE
l
16
l
16
MAX
UNITS
Bits
Bits
0.39
0.76
0.76
1.6
LSBRMS
LSBRMS
LSBRMS
LSBRMS
l
–1.25
±0.30
1.25
LSB
Differential Linearity Error (Note 10)
l
−0.9
±0.20
0.9
LSB
Zero-Scale Error
l
−500
±65
500
(Note 11)
Zero-Scale Error Drift
FSE
TYP
Full-Scale Error
±2
VREFBUF = 4.096V (REFBUF Overdriven) (Note 11)
Full-Scale Error Drift
l
−0.13
±0.025
±2.5
μV
μV/°C
0.13
%FS
ppm/°C
234116f
For more information www.linear.com/LTC2341-16
3
LTC2341-16
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 8, 12)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
SINAD
Signal-to-(Noise +
Distortion) Ratio
SNR
90.4
85.0
85.0
79.4
93.4
88.7
88.7
83.3
dB
dB
dB
dB
Signal-to-Noise Ratio
SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
90.6
85.1
85.2
79.5
93.4
88.7
88.7
83.3
dB
dB
dB
dB
THD
Total Harmonic Distortion
SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
SFDR
Spurious Free Dynamic
Range
SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048 and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
Channel-to-Channel
Crosstalk
One Channel Converting 3.6VP-P 200Hz Sine in ±2.048V Range,
Crosstalk to Other Channel
–114
–111
–110
–109
99
95
96
97
–3dB Input Bandwidth
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Transient Response
MAX
–99
–95
–96
–97
dB
dB
dB
dB
115
112
111
110
dB
dB
dB
dB
−119
dB
22
MHz
1
ns
150
ps
3
Full-Scale Step, 0.005% Settling
UNITS
psRMS
210
ns
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
VREFIN
Internal Reference Output Voltage
CONDITIONS
Internal Reference Temperature Coefficient
(Note 13)
Internal Reference Line Regulation
VDD = 4.75V to 5.25V
MIN
TYP
MAX
2.043
2.048
2.053
5
20
l
Internal Reference Output Impedance
VREFIN
4
REFIN Voltage Range
REFIN Overdriven (Note 6)
1.25
UNITS
V
ppm/°C
0.1
mV/V
20
kΩ
2.2
V
234116f
For more information www.linear.com/LTC2341-16
LTC2341-16
REFERENCE BUFFER CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
VREFBUF
Reference Buffer Output Voltage
REFIN Overdriven, VREFIN = 2.048V
REFBUF Voltage Range
REFBUF Overdriven (Notes 6, 14)
REFBUF Input Impedance
VREFIN = 0V, Buffer Disabled
REFBUF Load Current
VREFBUF = 5V, 2 Channels Enabled (Notes 14, 15)
VREFBUF = 5V, Acquisition Mode (Note 14)
IREFBUF
MIN
TYP
MAX
UNITS
l
4.091
4.096
4.101
V
l
2.5
5
V
13
1.3
0.35
l
kΩ
1.6
mA
mA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS Digital Inputs and Outputs
VIH
High Level Input Voltage
l 0.8 • OVDD
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
VIN = 0V to OVDD
l
V
–10
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IOUT = –500μA
l OVDD – 0.2
0.2 • OVDD
V
10
μA
5
pF
V
VOL
Low Level Output Voltage
IOUT = 500μA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
ISOURCE
Output Source Current
VOUT = 0V
–50
mA
ISINK
Output Sink Current
VOUT = OVDD
50
mA
–10
0.2
V
10
μA
LVDS Digital Inputs and Outputs
VID
Differential Input Voltage
RID
On-Chip Input Termination
Resistance
VICM
Common-Mode Input Voltage
CS = 0V, VICM = 1.2V
CS = OVDD
IICM
Common-Mode Input Current
VIN+ = VIN– = 0V to OVDD
l
200
350
600
mV
l
80
106
10
130
Ω
MΩ
1.2
2.2
V
10
μA
l
0.3
l
–10
VOD
Differential Output Voltage
RL = 100Ω Differential Termination
l
275
350
425
mV
VOCM
Common-Mode Output Voltage
RL = 100Ω Differential Termination
l
1.1
1.2
1.3
V
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
–10
10
μA
234116f
For more information www.linear.com/LTC2341-16
5
LTC2341-16
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
4.75
5.00
5.25
V
l
1.71
CMOS I/O Mode
VDD
Supply Voltage
OVDD
Supply Voltage
5.25
V
IVDD
Supply Current
666ksps Sample Rate, 2 Channels Enabled
666ksps Sample Rate, 2 Channels Enabled, VREFBUF = 5V (Note 14)
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
13.7
12.3
1.2
65
65
16.0
14.8
2.0
225
500
mA
mA
mA
μA
µA
IOVDD
Supply Current
666ksps Sample Rate, 2 Channels Enabled (CL = 25pF)
Acquisition Mode
Power Down Mode
l
l
l
2.2
1
1
3.4
20
20
mA
μA
μA
PD
Power Dissipation
666ksps Sample Rate, 2 Channels Enabled
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
74
6.0
0.33
0.33
89
10
1.2
2.6
mW
mW
mW
mW
5.00
5.25
V
5.25
V
LVDS I/O Mode
VDD
Supply Voltage
l
4.75
OVDD
Supply Voltage
l
2.375
IVDD
Supply Current
IOVDD
PD
666ksps Sample Rate, 2 Channels Enabled
666ksps Sample Rate, 2 Channels Enabled, VREFBUF = 5V (Note 14)
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
15.7
14.4
2.7
65
65
18.0
16.8
3.8
225
500
mA
mA
mA
μA
µA
Supply Current
666ksps Sample Rate, 2 Channels Enabled (RL = 100Ω)
Acquisition Mode (RL = 100Ω)
Power Down Mode
l
l
l
7.4
7
1
9.5
8.2
20
mA
mA
μA
Power Dissipation
666ksps Sample Rate, 2 Channels Enabled
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
97
31
0.33
0.33
114
40
1.2
2.6
mW
mW
mW
mW
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
fSMPL
Maximum Sampling Frequency
2 Channels Enabled
1 Channel Enabled
l
l
tCYC
Time Between Conversions
2 Channels Enabled, fSMPL = 666ksps
1 Channel Enabled, fSMPL = 1000ksps
l
l
1500
1000
tCONV
Conversion Time
N Channels Enabled, 1 ≤ N ≤ 2
l
450 • N –40
6
MIN
TYP
MAX
UNITS
666
1000
ksps
ksps
ns
ns
500 • N –40
550 • N –40
ns
234116f
For more information www.linear.com/LTC2341-16
LTC2341-16
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
tACQ
Acquisition Time
(tACQ = tCYC – tCONV – tBUSYLH)
2 Channels Enabled, fSMPL = 666ksps
1 Channel Enabled, fSMPL = 1000ksps
MIN
TYP
l
l
410
460
520
520
tCNVH
CNV High Time
l
40
ns
tCNVL
CNV Low Time
l
410
ns
CL = 25pF
MAX
UNITS
ns
ns
tBUSYLH
CNV↑ to BUSY Delay
tQUIET
Digital I/O Quiet Time from CNV↑
l
20
30
ns
tPDH
PD High Time
l
40
ns
tPDL
PD Low Time
l
40
ns
tWAKE
REFBUF Wake-Up Time
l
CREFBUF = 47μF, CREFIN = 0.1μF
200
ns
ms
CMOS I/O Mode
tSCKI
SCKI Period
tSCKIH
l
10
ns
SCKI High Time
l
4
ns
tSCKIL
SCKI Low Time
l
4
ns
tSSDISCKI
SDI Setup Time from SCKI↑
(Note 16)
l
2
ns
tHSDISCKI
SDI Hold Time from SCKI↑
(Note 16)
l
1
tDSDOSCKI
SDO Data Valid Delay from SCKI↑
CL = 25pF (Note 16)
l
tHSDOSCKI
SDO Remains Valid Delay from SCKI↑
CL = 25pF (Note 16)
l
1.5
tSKEW
SDO to SCKO Skew
(Note 16)
l
–1
CL = 25pF (Note 16)
l
0
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
(Notes 16, 17)
ns
7.5
ns
ns
0
1
ns
ns
tEN
Bus Enable Time After CS↓
(Note 16)
l
15
ns
tDIS
Bus Relinquish Time After CS↑
(Note 16)
l
15
ns
LVDS I/O Mode
tSCKI
SCKI Period
(Note 18)
l
4
ns
tSCKIH
SCKI High Time
(Note 18)
l
1.5
ns
tSCKIL
SCKI Low Time
(Note 18)
l
1.5
ns
tSSDISCKI
SDI Setup Time from SCKI
(Notes 10, 18)
l
1.2
ns
tHSDISCKI
SDI Hold Time from SCKI
(Notes 10, 18)
l
–0.2
ns
tDSDOSCKI
SDO Data Valid Delay from SCKI
(Notes 10, 18)
l
tHSDOSCKI
SDO Remains Valid Delay from SCKI
(Notes 10, 18)
l
1
tSKEW
SDO to SCKO Skew
(Note 10)
l
–0.4
(Note 10)
l
0
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
6
ns
ns
0
0.4
ns
ns
tEN
Bus Enable Time After CS↓
l
50
ns
tDIS
Bus Relinquish Time After CS↑
l
15
ns
234116f
For more information www.linear.com/LTC2341-16
7
LTC2341-16
ADC TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: VDDLBYP is the output of an internal voltage regulator, and should
only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND,
as described in the Pin Functions section. Do not connect this pin to any
external circuitry.
Note 4: When these pin voltages are taken below ground or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle
currents of up to 100mA below ground or above VDD or OVDD without
latch-up.
Note 5: VDD = 5V unless otherwise specified.
Note 6: Recommended operating conditions.
Note 7: Exceeding these limits on one channel may corrupt conversion
results on the other channel. Refer to Absolute Maximum Ratings section
for pin voltage limits related to device reliability.
Note 8: VDD = 5V, OVDD = 2.5V, fSMPL = 666ksps, internal reference and
buffer, fully differential input signal drive in SoftSpan ranges 7 and 6,
bipolar input signal drive in SoftSpan ranges 3 and 2, unipolar input signal
drive in SoftSpan ranges 5, 4 and 1, unless otherwise specified.
Note 9: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 10: Guaranteed by design, not subject to test.
Note 11: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
the offset voltage measured from –0.5LSB when the output code flickers
between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
error for these SoftSpan ranges is the worst-case deviation of the first and
last code transitions from ideal and includes the effect of offset error. For
unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage
measured from 0.5LSB when the output code flickers between 0000 0000
0000 0000 and 0000 0000 0000 0001. Full-scale error for these SoftSpan
ranges is the worst-case deviation of the last code transition from ideal
and includes the effect of offset error.
Note 12: All specifications in dB are referred to a full-scale input in the
relevant SoftSpan input range, except for crosstalk, which is referred to
the crosstalk injection signal amplitude.
Note 13: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 14: When REFBUF is overdriven, the internal reference buffer must
be disabled by setting REFIN = 0V.
Note 15: IREFBUF varies proportionally with sample rate and the number of
active channels.
Note 16: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,
and OVDD = 5.25V.
Note 17: A tSCKI period of 10ns minimum allows a shift clock frequency of
up to 100MHz for rising edge capture.
Note 18: VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
CMOS Timings
0.8 • OVDD
tWIDTH
0.2 • OVDD
tDELAY
tDELAY
0.8 • OVDD
0.8 • OVDD
0.2 • OVDD
0.2 • OVDD
50%
50%
234116 F01
LVDS Timings (Differential)
+200mV
tWIDTH
–200mV
tDELAY
tDELAY
+200mV
+200mV
–200mV
–200mV
0V
0V
234116 F01b
Figure 1. Voltage Levels for Timing Specifications
8
234116f
For more information www.linear.com/LTC2341-16
LTC2341-16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 666ksps, unless otherwise noted.
Integral Nonlinearity
Differential Nonlinearity
vs Output
Output Code
Code and
and Channel
Channel
vs
vs
vs Output
Output Code
Code and
and Channel
Channel
0.75
0
–0.25
0.50
0.25
0
–0.25
–0.25
–0.50
–0.75
–0.75
–0.75
–1.00
32768
0
16384
32768
49152
OUTPUT CODE
234116 G01
1.00
1.00
1.00
–0.25
±4.096V AND ±4V
RANGES
–0.50
–0.75
–1.00
–32768
–16384
0
16384
OUTPUT CODE
32768
0V TO 2.048V RANGE
0
–0.25
0V TO 4.096V AND 0V TO 4V RANGES
0
–0.25
–0.50
–0.75
–0.75
–1.00
0
16384
32768
49152
OUTPUT CODE
–1.00
–32768
65536
250000
200000
150000
150000
COUNTS
200000
0
±4.096V RANGE
32768
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
SNR = 93.4dB
THD = –111dB
SINAD = 93.3dB
SFDR = 112dB
–40
100000
0
16384
OUTPUT CODE
32k Point FFT fSMPL = 666kHz,
ffIN
= 2kHz
IN = 2kHz
–20
AMPLITUDE (dBFS)
±4.096V RANGE
–16384
234116 G06
DC Histogram (Near Full-Scale)
–60
–80
–100
–120
–140
50000
50000
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
234116 G05
DC
DC Histogram
Histogram (Zero-Scale)
(Zero–Scale)
100000
ARBITRARY DRIVE
IN+/IN– COMMON MODE
SWEPT 0V TO 5V
0.25
–0.50
234116 G04
250000
INL ERROR (LSB)
INL ERROR (LSB)
0
±4.096V RANGE
0.50
0.25
32768
0.75
0.50
±2.048V AND ±2V
RANGES
0
16384
OUTPUT CODE
Integral Nonlinearity
vs Output Code
UNIPOLAR DRIVE (IN– = 0V)
ONE CHANNEL
0.75
0.50
0.25
–16384
234116 G03
Integral Nonlinearity
vs
vs Output
Output Code
Code and
and Range
Range
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ONE CHANNEL
0.75
–1.00
–32768
65536
234116 G02
Integral Nonlinearity
vs Output Code and Range
INL ERROR (LSB)
0
–0.50
0
16384
OUTPUT CODE
±2.048V AND ±2V
RANGES
0.25
–0.50
–16384
BIPOLAR DRIVE (IN– = 2.5V)
ONE CHANNEL
0.75
0.50
0.25
–1.00
–32768
COUNTS
1.00
ALL RANGES
ALL CHANNELS
0.75
DNL ERROR (LSB)
0.50
INL ERROR (LSB)
1.00
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ALL CHANNELS
INL ERROR (LSB)
1.00
Integral Nonlinearity
vs Output Code and Range
–160
0
–4
–3
–2
–1
0
1
CODE
2
3
4
234116 G07
0
32752
32754
32756
CODE
32758
32760
234116 G08
–180
0
111
222
FREQUENCY (kHz)
333
234116 G09
234116f
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9
LTC2341-16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 666ksps, unless otherwise noted.
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
0
111
222
FREQUENCY (kHz)
–180
333
0
111
222
FREQUENCY (kHz)
THD
3RD
–125
2ND
–130
–135
–140
2.5
3
3.5
4
4.5
REFBUF VOLTAGE (V)
5
92
SNR
88
SINAD
84
–90
–120
3RD
–130
2ND
0
1
2
3
4
INPUT COMMON MODE (V)
5
234116 G16
10
2ND
–110
–120
76
100
–130
100
10k
100k
FREQUENCY (Hz)
1M
3RD
1k
10k
100k
FREQUENCY (Hz)
1M
234116 G15
SNR, SINAD vs Input Level,
fIN
IN = 2kHz
CMRR vs Input Frequency and
Channel
130
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
±4.096V RANGE
IN+ = IN– = 3.6VP–P SINE
ALL CHANNELS
120
110
93.8
SNR
93.6
SINAD
93.2
–40
100
90
80
93.4
–140
THD
–100
94.0
SNR, SINAD (dBFS)
THD, HARMONICS (dBFS)
–80
80
1k
5
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–70
96
94.2
±4.096V RANGE
1VP–P FULLY DIFFERENTIAL DRIVE
–110
–150
–60
234116 G14
THD, Harmonics vs Input
Common Mode, fIN
IN = 2kHz
THD
3.5
4
4.5
REFBUF VOLTAGE (V)
THD, Harmonics
vs Input Frequency
234116 G13
–100
3
234116 G12
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
100
SNR, SINAD (dBFS)
THD, HARMONICS (dBFS)
104
–110
–120
92
SNR, SINAD
vs Input Frequency
±VREFBUF RANGE
FULLY DIFFERENIAL DRIVE (IN– = –IN+)
–115
SINAD
234116 G11
THD, Harmonics vs VREFBUF,
fIN
= 2kHz
IN
–105
SNR
94
88
2.5
333
234116 G10
–100
±VREFBUF RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
90
CMRR (dB)
–180
fIN = 2kHz
= 2kHz
96
SNR = 88.7dB
THD = –112dB
SINAD = 88.7dB
SFDR = 113dB
–40
–60
98
0V TO 4.096V RANGE
UNIPOLAR DRIVE (IN– = 0V)
–20
AMPLITUDE (dBFS)
–40
AMPLITUDE (dBFS)
0
±4.096V RANGE
ARBITRARY DRIVE
SFDR = 112dB
SNR = 93.5dB
SNR, SINAD vs VREFBUF,
THD, HARMONICS (dBFS)
0
–20
32k Point FFT fSMPL = 666kHz,
fIN
IN = 2kHz
SNR, SINAD (dBFS)
32k Point Arbitrary Two-Tone FFT
fSMPL = 666kHz, IN+ = –7dBFS 2kHz
Sine, IN– = –7dBFS
3.3kHzSine
Sine
= -7dBFS 3.2kHz
70
–30
–20
–10
INPUT LEVEL (dBFS)
0
234116 G17
60
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
234116 G18
234116f
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LTC2341-16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 666ksps, unless otherwise noted.
Crosstalk vs Input Frequency and
Channel
–90
–100
94.5
CH1
–115
–120
–125
–130
93.0
SINAD
92.5
92.0
–135
1k
10k
FREQUENCY (Hz)
100k
91.0
–55 –35 –15
1M
234116 G19
0.4
0.100
MAX DNL
0.1
0.0
MAX INL
–0.1
MIN DNL
–0.2
–0.3
–0.5
–55 –35 –15
0.050
0.025
0.000
–0.025
–0.050
5 25 45 65 85 105 125
TEMPERATURE (°C)
–0.100
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
234116 G22
0.100
2
1
0
–1
–2
–3
0.050
0.025
0.000
–0.025
–0.050
–0.100
–55 –35 –15
234116 G24
Power-Down Current
vs Temperature
1000
16
IVDD
14
12
10
8
6
4
2
IOVDD
100
234116 G25
–4
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
234116 G26
IVDD
10
1
0.1
–2
5 25 45 65 85 105 125
TEMPERATURE (°C)
5 25 45 65 85 105 125
TEMPERATURE (°C)
18
0
–4
±4.096V RANGE
REFBUF OVERDRIVEN
VREFBUF = 4.096V
ALL CHANNELS
0.075
20
±4.096V RANGE
ALL CHANNELS
3
–5
–55 –35 –15
234116 G21
Supply Current vs Temperature
SUPPLY CURRENT (mA)
ZERO-SCALE ERROR (LSB)
4
5 25 45 65 85 105 125
TEMPERATURE (°C)
234116 G23
Zero-Scale Error vs
Temperature and Channel
5
3RD
–0.075
–0.075
MIN INL
–0.4
2ND
–120
Negative Full-Scale Error vs
Temperature and Channel
±4.096V RANGE
REFBUF OVERDRIVEN
VREFBUF = 4.096V
ALL CHANNELS
0.075
FULL–SCALE ERROR (%)
INL, DNL ERROR (LSB)
0.3
THD
–115
Positive Full-Scale Error vs
Temperature and Channel
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
0.2
–110
234116 G20
INL, DNL vs Temperature
0.5
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–130
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
FULL–SCALE ERROR (%)
100
POWER-DOWN CURRENT (µA)
10
THD, Harmonics vs Temperature,
fIN
IN = 2kHz
–125
91.5
–140
–145
SNR
93.5
–105
THD, HARMONICS (dBFS)
SNR, SINAD (dBFS)
–110
–100
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
94.0
–105
CROSSTALK (dB)
95.0
±4.096V RANGE
IN0+ = –IN0– = 3.6VP–P SINE
ALL CHANNELS CONVERTING
–95
SNR, SINAD vs Temperature,
= 2kHz
fIN
IN = 2kHz
0.01
–55 –35 –15
IOVDD
5 25 45 65 85 105 125
TEMPERATURE (°C)
234116 G27
234116f
For more information www.linear.com/LTC2341-16
11
LTC2341-16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 666ksps, unless otherwise noted.
Offset Error vs Input Common
Mode
Mode and
and Channel
Channel
OFFSET ERROR (LSB)
INTERNAL REFERENCE OUTPUT (V)
±4.096V RANGE
ALL CHANNELS
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
0
1
2
3
4
INPUT COMMON MODE (V)
PSRR vs Frequency
2.052
5
150
15 UNITS
2.051
120
2.049
2.048
2.047
5 25 45 65 85 105 125
TEMPERATURE (°C)
70
POWER DISSIPATION (mW)
SUPPLY CURRENT (mA)
14
IVDD
10
8
6
4
111
222
333
444
555
SAMPLING FREQUENCY (kHz)
1M
234116 G30
50
N=1
40
30
20
0
666
0
200
400
600
800
SAMPLING FREQUENCY (kHz)
1000
234116 G32
Step
Step Response
Response (Fine
(Fine Settling)
Settling)
32768
100
24576
80
16384
±2.048V RANGE
IN+ = 666.6398kHz
SQUARE WAVE
IN– = 2.048V
DRIVEN BY 50Ω SOURCE
–16384
–24576
50 100 150 200 250 300 350 400
SETTLING TIME (ns)
DEVIATION FROM FINAL VALUE (LSB)
OUTPUT CODE (LSB)
100k
60
Step Response
(Large-Signal
(Large-SignalSettling)
Settling)
60
40
20
0
–20
–40
–60
–80
–100
–100 –50 0
234116 G33
12
1k
10k
FREQUENCY (Hz)
N=2
234116 G31
–32768
–100 –50 0
100
10
IOVDD
–8192
10
Power Dissipation vs Sampling
80
0
VDD
Rate, N
N Channels
Channels Enabled
Enabled
Rate,
16
8192
50
234116 G29
90
0
90
60
18
0
100
70
2.045
Supply Current
Current vs
vs Sampling
Sampling Rate
Rate
Supply
2
110
80
2.046
234116 G28
12
IN+ = IN– = 0V
130
2.050
2.044
–55 –35 –15
OVDD
140
PSRR (dB)
1.00
Internal Reference Output
vs Temperature
±2.048V RANGE
IN+ = 666.6398kHz
SQUARE WAVE
IN– = 2.048V
DRIVEN BY 50Ω SOURCE
50 100 150 200 250 300 350 400
SETTLING TIME (ns)
234116 G34
234116f
For more information www.linear.com/LTC2341-16
LTC2341-16
PIN FUNCTIONS
Pins that are the Same for All Digital I/O Modes
IN0+/IN0–, IN1+/IN1– (Pins 8/7, 2/1): Positive and Negative
Analog Inputs, Channels 0 and 1. The converter simultaneously samples and digitizes (VIN+ – VIN–) for both channels.
Wide input common mode range (0V ≤ VCM ≤ VDD) and
high common mode rejection allow the inputs to accept
a wide variety of signal swings. Full-scale input range is
determined by the channel’s SoftSpan configuration.
GND (Pins 3, 4, 5, 6, 9, 11, 20, 29, 31, 32, 33): Ground.
Solder all GND pins to a solid ground plane.
REFIN (Pin 10): Bandgap Reference Output/Reference
Buffer Input. An internal bandgap reference nominally
outputs 2.048V on this pin. An internal reference buffer
amplifies VREFIN to create the converter master reference
voltage VREFBUF = 2 • VREFIN on the REFBUF pin. When
using the internal reference, bypass REFIN to GND (Pin 11)
close to the pin with a 0.1μF ceramic capacitor to filter
the bandgap output noise. If more accuracy is desired,
overdrive REFIN with an external reference in the range
of 1.25V to 2.2V.
REFBUF (Pin 12): Internal Reference Buffer Output. An
internal reference buffer amplifies VREFIN to create the
converter master reference voltage VREFBUF = 2 • VREFIN on
this pin, nominally 4.096V when using the internal bandgap
reference. Bypass REFBUF to GND (Pin 11) close to the
pin with a 47μF ceramic capacitor. The internal reference
buffer may be disabled by grounding its input at REFIN.
With the buffer disabled, overdrive REFBUF with an external reference voltage in the range of 2.5V to 5V. When
using the internal reference buffer, limit the loading of any
external circuitry connected to REFBUF to less than 10µA.
Using a high input impedance amplifier to buffer VREFBUF
to any external circuits is recommended.
PD (Pin 13): Power Down Input. When this pin is brought
high, the LTC2341-16 is powered down and subsequent
conversion requests are ignored. If this occurs during a
conversion, the device powers down once the conversion
completes. If this pin is brought high twice without an
intervening conversion, an internal global reset is initiated, equivalent to a power-on-reset event. Logic levels
are determined by OVDD.
LVDS/CMOS (Pin 14): I/O Mode Select. Tie this pin to OVDD
to select LVDS I/O mode, or to ground to select CMOS I/O
mode. Logic levels are determined by OVDD.
CNV (Pin 15): Conversion Start Input. A rising edge on
this pin puts the internal sample-and-holds into the hold
mode and initiates a new conversion. CNV is not gated
by CS, allowing conversions to be initiated independent
of the state of the serial I/O bus.
BUSY (Pin 26): Busy Output. The BUSY signal indicates
that a conversion is in progress. This pin transitions lowto-high at the start of each conversion and stays high until
the conversion is complete. Logic levels are determined
by OVDD.
VDDLBYP (Pin 28): Internal 2.5V Regulator Bypass Pin. The
voltage on this pin is generated via an internal regulator
operating off of VDD. This pin must be bypassed to GND
close to the pin with a 2.2μF ceramic capacitor. Do not
connect this pin to any external circuitry.
VDD (Pin 30): 5V Power Supply. The range of VDD is 4.75V
to 5.25V. This pin must be bypassed to GND close to the
pin with a 0.1μF ceramic capacitor.
234116f
For more information www.linear.com/LTC2341-16
13
LTC2341-16
PIN FUNCTIONS
CMOS I/O Mode
LVDS I/O Mode
SDI+/SDI–, SDO+ (Pin 16/17, 24): LVDS Serial Data I/O.
In CMOS I/O mode, these pins are Hi-Z.
SDI+/SDI– (Pins 16/17): LVDS Positive and Negative Serial
Data Input. Differentially drive SDI+/SDI– with the desired
6-bit SoftSpan configuration word (see Table 1a), latched
on both the rising and falling edges of SCKI+/SCKI–. The
SDI+/SDI– input pair is internally terminated with a 100Ω
differential resistor when CS = 0.
SDO0, SDO1 (Pins 18, 23): CMOS Serial Data Outputs,
Channels 0 and 1. The most recent conversion result along
with channel configuration information is clocked out onto
the SDO pins on each rising edge of SCKI. Output data
formatting is described in the Digital Interface section.
Leave unused SDO outputs unconnected. Logic levels are
determined by OVDD.
SCKI (Pin 19): CMOS Serial Clock Input. Drive SCKI with
the serial I/O clock. SCKI rising edges latch serial data in
on SDI and clock serial data out on SDO0 and SDO1. For
standard SPI bus operation, capture output data at the
receiver on rising edges of SCKI. SCKI is allowed to idle
either high or low. Logic levels are determined by OVDD.
OVDD (Pin 21): I/O Interface Power Supply. In CMOS I/O
mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD
to GND (Pin 20) close to the pin with a 0.1μF ceramic
capacitor.
SCKO (Pin 22): CMOS Serial Clock Output. SCKI rising
edges trigger transitions on SCKO that are skew-matched
to the serial output data streams on SDO0 and SDO1. The
resulting SCKO frequency is half that of SCKI. Rising and
falling edges of SCKO may be used to capture SDO data
at the receiver (FPGA) in double data rate (DDR) fashion.
For standard SPI bus operation, SCKO is not used and
should be left unconnected. SCKO is forced low at the
falling edge of BUSY. Logic levels are determined by OVDD.
SDI (Pin 25): CMOS Serial Data Input. Drive this pin with the
desired 6-bit SoftSpan configuration word (see Table 1a),
latched on the rising edges of SCKI. If both channels will
be configured to operate only in SoftSpan 7, tie SDI to
OVDD. Logic levels are determined by OVDD.
CS (Pin 27): Chip Select Input. The serial data I/O bus is
enabled when CS is low and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI.
Logic levels are determined by OVDD.
14
SCKI+/SCKI– (Pins 18/19): LVDS Positive and Negative
Serial Clock Input. Differentially drive SCKI+/SCKI– with
the serial I/O clock. SCKI+/SCKI– rising and falling edges
latch serial data in on SDI+/SDI– and clock serial data out
on SDO+/SDO–. Idle SCKI+/SCKI– low, including when
transitioning CS. The SCKI+/SCKI– input pair is internally
terminated with a 100Ω differential resistor when CS = 0.
OVDD (Pin 21): I/O Interface Power Supply. In LVDS I/O
mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD
to GND (Pin 20) close to the pin with a 0.1μF ceramic
capacitor.
SCKO+/SCKO– (Pins 22/23): LVDS Positive and Negative
Serial Clock Output. SCKO+/SCKO– outputs a copy of the
input serial I/O clock received on SCKI+/SCKI–, skewmatched with the serial output data stream on SDO+/SDO–.
Use the rising and falling edges of SCKO+/SCKO– to capture SDO+/SDO– data at the receiver (FPGA). The SCKO+/
SCKO– output pair must be differentially terminated with
a 100Ω resistor at the receiver (FPGA).
SDO+/SDO– (Pins 24/25): LVDS Positive and Negative
Serial Data Output. The most recent conversion result
along with channel configuration information is clocked
out onto SDO+/SDO– on both rising and falling edges of
SCKI+/SCKI–, beginning with channel 0. The SDO+/SDO–
output pair must be differentially terminated with a 100Ω
resistor at the receiver (FPGA).
CS (Pin 27): Chip Select Input. The serial data I/O bus is
enabled when CS is low, and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI+/
SCKI–. The internal 100Ω differential termination resistors
on the SCKI+/SCKI– and SDI+/SDI– input pairs are disabled
when CS is high. Logic levels are determined by OVDD.
234116f
For more information www.linear.com/LTC2341-16
LTC2341-16
CONFIGURATION TABLES
Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Independent Binary SoftSpan Codes SS[2:0] for Each
Channel Based on Desired Analog Input Range. Combine SoftSpan Codes to Form 6-Bit SoftSpan Configuration Word S[5:0]. Use
Serial Interface to Write SoftSpan Configuration Word to LTC2341-16, as shown in Figure 19
BINARY SoftSpan CODE
SS[2:0]
111
110
101
100
011
010
001
000
ANALOG INPUT RANGE
±VREFBUF
±VREFBUF/1.024
0V to VREFBUF
0V to VREFBUF/1.024
±0.5 • VREFBUF
±0.5 • VREFBUF/1.024
0V to 0.5 • VREFBUF
Channel Disabled
FULL SCALE RANGE
2 • VREFBUF
2 • VREFBUF/1.024
VREFBUF
VREFBUF/1.024
VREFBUF
VREFBUF/1.024
0.5 • VREFBUF
Channel Disabled
BINARY FORMAT OF
CONVERSION RESULT
Two’s Complement
Two’s Complement
Straight Binary
Straight Binary
Two’s Complement
Two’s Complement
Straight Binary
All Zeros
Table 1b. Reference Configuration Table. The LTC2341-16 Supports Three Reference Configurations. Analog Input Range Scales with
the Converter Master Reference Voltage, VREFBUF
REFERENCE CONFIGURATION
Internal Reference with
Internal Buffer
VREFIN
VREFBUF
2.048V
BINARY SoftSpan CODE
SS[2:0]
ANALOG INPUT RANGE
111
±4.096V
110
±4V
101
0V to 4.096V
100
0V to 4V
011
±2.048V
010
±2V
001
0V to 2.048V
4.096V
1.25V
(Min Value)
2.5V
External Reference with
Internal Buffer
(REFIN Pin Externally
Overdriven)
2.2V
(Max Value)
4.4V
111
±2.5V
110
±2.441V
101
0V to 2.5V
100
0V to 2.441V
011
±1.25V
010
±1.221V
001
0V to 1.25V
111
±4.4V
110
±4.297V
101
0V to 4.4V
100
0V to 4.297V
011
±2.2V
010
±2.148V
001
0V to 2.2V
234116f
For more information www.linear.com/LTC2341-16
15
LTC2341-16
CONFIGURATION TABLES
Table 1b. Reference Configuration Table (Continued). The LTC2341-16 Supports Three Reference Configurations. Analog Input Range
Scales with the Converter Master Reference Voltage, VREFBUF
REFERENCE CONFIGURATION
VREFIN
0V
VREFBUF
BINARY SoftSpan CODE
SS[2:0]
2.5V
(Min Value)
External Reference
Unbuffered
(REFBUF Pin
Externally Overdriven,
REFIN Pin Grounded)
0V
16
5V
(Max Value)
ANALOG INPUT RANGE
111
±2.5V
110
±2.441V
101
0V to 2.5V
100
0V to 2.441V
011
±1.25V
010
±1.221V
001
0V to 1.25V
111
±5V
110
±4.883V
101
0V to 5V
100
0V to 4.883V
011
±2.5V
010
±2.441V
001
0V to 2.5V
234116f
For more information www.linear.com/LTC2341-16
LTC2341-16
FUNCTIONAL BLOCK DIAGRAM
CMOS I/O Mode
VDD
VDDLBYP
OVDD
LTC2341-16
2.5V
REGULATOR
IN0+
S/H
IN1+
IN1–
S/H
SDO0
2-CHANNEL MULTIPLEXER
IN0–
SDO1
16-BIT
SAR ADC
16 BITS
CMOS
SERIAL
I/O
INTERFACE
SCKO
SDI
SCKI
CS
2.048V
REFERENCE
20k
GND
REFERENCE
BUFFER
2×
REFIN
REFBUF
CONTROL
LOGIC
BUSY
CNV PD
LVDS/CMOS
234116 BD01
LVDS I/O Mode
VDD
VDDLBYP
OVDD
LTC2341-16
2.5V
REGULATOR
SDO+
SDO–
IN0+
S/H
IN1+
IN1–
S/H
SCKO+
2-CHANNEL MULTIPLEXER
IN0–
16-BIT
SAR ADC
16 BITS
LVDS
SERIAL
I/O
INTERFACE
SCKO–
SDI+
SDI–
SCKI+
SCKI–
CS
2.048V
REFERENCE
GND
20k
REFERENCE
BUFFER
2×
REFIN
REFBUF
CONTROL
LOGIC
BUSY
CNV PD
LVDS/CMOS
234116 BD02
234116f
For more information www.linear.com/LTC2341-16
17
LTC2341-16
TIMING DIAGRAM
CMOS I/O Mode
CS = PD = 0
SAMPLE N
SAMPLE N + 1
CNV
BUSY
CONVERT
ACQUIRE
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCKI
SDI
DON’T CARE
S5 S4 S3 S2 S1 S0
SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1
SCKO
DON’T CARE
SDO0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
0
0
0 C0 SS2 SS1 SS0 D15
SoftSpan
CONVERSION RESULT
CHANNEL ID
CHANNEL 0
CONVERSION N
SDO1
DON’T CARE
CONVERSION RESULT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
0
0
CHANNEL 1
CONVERSION N
0 C0 SS2 SS1 SS0 D15
CONVERSION RESULT
SoftSpan
CHANNEL 1
CONVERSION N
CHANNEL ID
CONVERSION RESULT
CHANNEL 0
CONVERSION N
234116 TD01
LVDS I/O Mode
CS = PD = 0
SAMPLE
N+1
SAMPLE N
CNV
(CMOS)
BUSY
(CMOS)
CONVERT
SCKI
(LVDS)
SDI
DON’T CARE
(LVDS)
ACQUIRE
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
42 43 44 45 46 47 48
S5 S4 S3 S2 S1 S0
SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1
SCKO
(LVDS)
SDO
(LVDS) DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
CONVERSION RESULT
CHANNEL 0
CONVERSION N
0
0
0 C0 SS2 SS1 SS0 D15 D14 D13
SoftSpan
CHANNEL ID
CHANNEL 1
CONVERSION N
0 0 0 C0 SS2 SS1 SS0 D15
SoftSpan
CHANNEL ID
CONVERSION
RESULT
CHANNEL 0
CONVERSION N
234116 TD02
18
234116f
For more information www.linear.com/LTC2341-16
LTC2341-16
APPLICATIONS INFORMATION
OVERVIEW
The LTC2341-16 is a 16-bit, low noise 2-channel simultaneous sampling successive approximation register (SAR)
ADC with differential, wide common mode range inputs.
Using the integrated low-drift reference and buffer (VREFBUF = 4.096V nominal), both channels of this SoftSpan
ADC can be independently configured on a conversionby-conversion basis to accept ±4.096V, 0V to 4.096V,
±2.048V, or 0V to 2.048V signals. The input signal range
may be expanded up to ±5V using an external 5V reference.
One channel may also be disabled to increase throughput
on the other channel.
The wide input common mode range and high CMRR
(105dB typical, VIN+ = VIN– = 3.6VP-P 200Hz Sine) of the
LTC2341-16 analog inputs allow the ADC to directly digitize
a variety of signals, simplifying signal chain design. This
input signal flexibility, combined with ±1.25LSB INL, no
missing codes at 16-bits, and 93.4dB SNR, makes the
LTC2341-16 an ideal choice for many applications requiring wide dynamic range.
The LTC2341-16 supports pin-selectable SPI CMOS
(1.8V to 5V) and LVDS serial interfaces, enabling it to
communicate equally well with legacy microcontrollers
and modern FPGAs. In CMOS mode, applications may
employ one or two lanes of serial output data, allowing
the user to optimize bus width and data throughput. The
LTC2341-16 typically dissipates 74mW when converting
two analog input channels simultaneously at 666ksps
per channel throughput. An optional power-down mode
may be employed to further reduce power consumption
during inactive periods.
CONVERTER OPERATION
The LTC2341-16 operates in two phases. During the acquisition phase, the sampling capacitors in both channels’
sample-and-hold (S/H) circuits connect to their respective analog input pins and track the differential analog
input voltage (VIN+ – VIN–). A rising edge on the CNV pin
transitions both channels’ S/H circuits from track mode
to hold mode, simultaneously sampling the input signals
on both channels and initiating a conversion. During the
conversion phase, each channel’s sampling capacitors
are connected, one channel at a time, to a 16-bit charge
redistribution capacitor D/A converter (CDAC). The CDAC
is sequenced through a successive approximation algorithm, effectively comparing the sampled input voltage
with binary-weighted fractions of the channel’s SoftSpan
full-scale range (e.g., VFSR/2, VFSR/4 … VFSR/65536) using a differential comparator. At the end of this process,
the CDAC output approximates the channel’s sampled
analog input. Once both channels have been converted
in this manner, the ADC control logic prepares the 16-bit
digital output codes from each channel for serial transfer.
TRANSFER FUNCTION
The LTC2341-16 digitizes each channel’s full-scale voltage
range into 216 levels. In conjunction with the ADC master
reference voltage, VREFBUF, a channel’s SoftSpan configuration determines its input voltage range, full-scale range,
LSB size, and the binary format of its conversion result, as
shown in Tables 1a and 1b. For example, employing the
internal reference and buffer (VREFBUF = 4.096V nominal),
SoftSpan 7 configures a channel to accept a ±4.096V bipolar analog input voltage range, which corresponds to a
8.192V full-scale range with a 125μV LSB. Other SoftSpan
configurations and reference voltages may be employed to
convert both larger and smaller bipolar and unipolar input
ranges. Conversion results are output in two’s complement binary format for all bipolar SoftSpan ranges, and
in straight binary format for all unipolar SoftSpan ranges.
The ideal two’s complement transfer function is shown in
Figure 2, while the ideal straight binary transfer function
is shown in Figure 3.
234116f
For more information www.linear.com/LTC2341-16
19
LTC2341-16
OUTPUT CODE (TWO’S COMPLEMENT)
APPLICATIONS INFORMATION
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/65536
100...000
–FSR/2
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
234116 F02
OUTPUT CODE (STRAIGHT BINARY)
Figure 2. LTC2341-16 Two’s Complement Transfer Function
111...111
111...110
100...001
100...000
011...111 UNIPOLAR
ZERO
011...110
000...001
FSR = +FS
1LSB = FSR/65536
000...000
0V
high CMRR allows the IN+/IN– analog inputs to swing
with an arbitrary relationship to each other, provided
both pins remain between ground and VDD. This feature
of the LTC2341-16 enables it to accept a wide variety
of signal swings, including traditional classes of analog
input signals such as pseudo-differential unipolar, pseudodifferential bipolar, and fully differential, simplifying signal
chain design.
In all SoftSpan ranges, each channel’s analog inputs can
be modeled by the equivalent circuit shown in Figure 4.
At the start of acquisition, the 80pF sampling capacitors
(CIN) connect to the analog input pins IN+/IN– through the
sampling switches, each of which has approximately 90Ω
(RIN) of on-resistance. The initial voltage on both sampling
capacitors at the start of acquisition is approximately equal
to the sampled common-mode voltage (VIN+ + VIN–)/2 from
the prior conversion. The external circuitry connected to
IN+ and IN– must source or sink the charge that flows
through RIN as the sampling capacitors settle from their
initial voltages to the new input pin voltages over the course
of the acquisition interval. During conversion and power
down modes, the analog inputs draw only a small leakage
current. The diodes at the inputs provide ESD protection.
FSR – 1LSB
INPUT VOLTAGE (V)
VDD
234116 F03
Figure 3. LTC2341-16 Straight Binary Transfer Function
IN+
ANALOG INPUTS
Each channel of the LTC2341-16 simultaneously samples
the voltage difference (VIN+ – VIN–) between its analog
input pins over a wide common mode input range while
attenuating unwanted signals common to both input
pins by the common-mode rejection ratio (CMRR) of
the ADC. Wide common mode input range coupled with
20
RIN
90Ω
VDD
IN–
RIN
90Ω
CIN
80pF
CIN
80pF
BIAS
VOLTAGE
234116 F04
Figure 4. Equivalent Circuit for Differential Analog Inputs,
Single Channel Shown
234116f
For more information www.linear.com/LTC2341-16
LTC2341-16
APPLICATIONS INFORMATION
Bipolar SoftSpan Input Ranges
For channels configured in SoftSpan ranges 7, 6, 3, or
2, the LTC2341-16 digitizes the differential analog input
voltage (VIN+ – VIN–) over a bipolar span of ±VREFBUF,
±VREFBUF/1.024, ±0.5 • VREFBUF, or ±0.5 • VREFBUF/1.024,
respectively, as shown in Table 1a. These SoftSpan ranges
are useful for digitizing input signals where IN+ and IN–
swing above and below each other. Traditional examples
include fully differential input signals, where IN+ and
IN– are driven 180 degrees out-of-phase with respect
to each other centered around a common mode voltage
(VIN+ + VIN–)/2, and pseudo-differential bipolar input
signals, where IN+ swings above and below a reference
level, driven on IN–. Regardless of the chosen SoftSpan
range, the wide common mode input range and high CMRR
of the IN+/IN– analog inputs allow them to swing with an
arbitrary relationship to each other, provided each pin
remains between ground and VDD. The output data format
for all bipolar SoftSpan ranges is two’s complement.
The LTC2341-16 sampling network RC time constant of
7.2ns implies a 16-bit settling time to a full-scale step of
approximately 11 • (RIN • CIN) = 79ns. The impedance and
self-settling of external circuitry connected to the analog
input pins will increase the overall settling time required.
Low impedance sources can directly drive the inputs of
the LTC2341-16 without gain error, but high impedance
sources should be buffered to ensure sufficient settling
during acquisition and to optimize the linearity and distortion performance of the ADC. Settling time is an important
consideration even for DC input signals, as the voltages on
the sampling capacitors will differ from the analog input
pin voltages at the start of acquisition.
Most applications should use a buffer amplifier to drive the
analog inputs of the LTC2341-16. The amplifier provides
low output impedance, enabling fast settling of the analog
signal during the acquisition phase. It also provides isolation between the signal source and the charge flow at the
analog inputs when entering acquisition.
Unipolar SoftSpan Input Ranges
Input Filtering
For channels configured in SoftSpan ranges 5, 4, or 1, the
LTC2341-16 digitizes the differential analog input voltage
(VIN+ – VIN–) over a unipolar span of 0V to VREFBUF, 0V
to VREFBUF/1.024, or 0V to 0.5 • VREFBUF, respectively, as
shown in Table 1a. These SoftSpan ranges are useful for
digitizing input signals where IN+ remains above IN–. A
traditional example includes pseudo-differential unipolar
input signals, where IN+ swings above a ground reference
level, driven on IN–. Regardless of the chosen SoftSpan
range, the wide common mode range and high CMRR of
the IN+/IN– analog inputs allow them to swing with an
arbitrary relationship to each other, provided each pin
remains between ground and VDD. The output data format
for all unipolar SoftSpan ranges is straight binary.
The noise and distortion of an input buffer amplifier and
other supporting circuitry must be considered since they
add to the ADC noise and distortion. Noisy input signals
should be filtered prior to the buffer amplifier with a lowbandwidth filter to minimize noise. The simple one-pole
RC lowpass filter shown in Figure 5 is sufficient for many
applications.
INPUT DRIVE CIRCUITS
The initial voltage on each channel’s sampling capacitors
at the start of acquisition must settle to the new input
pin voltages during the acquisition interval. The external
circuitry connected to IN+ and IN– must source or sink
the charge that flows through RIN as this settling occurs.
At the output of the buffer, a lowpass RC filter network
formed by the 90Ω sampling switch on-resistance (RIN)
and the 80pF sampling capacitance (CIN) limits the input
bandwidth on each channel to 22MHz, which is fast enough
to allow for sufficient transient settling during acquisition
while simultaneously filtering driver wideband noise. A
buffer amplifier with low noise density should be selected
to minimize SNR degradation over this bandwidth. An
additional filter network may be placed between the buffer output and ADC input to further minimize the noise
contribution of the buffer and reduce disturbances to the
buffer from ADC acquisition transients. A simple one-pole
lowpass RC filter is sufficient for many applications. It is
important that the RC time constant of this filter be small
234116f
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21
LTC2341-16
APPLICATIONS INFORMATION
LOWPASS
SIGNAL FILTER
UNIPOLAR
INPUT SIGNAL
5V
160Ω
+
BUFFER
AMPLIFIER
–
10nF
IN0+
IN0–
LTC2341-16
0V
BW = 100kHz
ONLY CHANNEL 0 SHOWN FOR CLARITY
234116 F05
Figure 5. Unipolar Signal Chain with Input Filtering
enough to allow the analog inputs to completely settle to
16-bit resolution within the ADC acquisition time (tACQ),
as insufficient settling can limit INL and THD performance.
Also note that the minimum acquisition time varies with
sampling frequency (fSMPL) and the number of enabled
channels.
High quality capacitors and resistors should be used in
the RC filters since these components can add distortion.
NPO/COG and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self-heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
Buffering Arbitrary and Fully Differential Analog Input
Signals
The wide common mode input range and high CMRR of
the LTC2341-16 allow each channel’s IN+ and IN– pins to
swing with an arbitrary relationship to each other, provided
both pins remain between ground and VDD. This unique
feature of the LTC2341-16 enables it to accept a wide
variety of signal swings, simplifying signal chain design.
In many applications, connecting a channel’s IN+ and IN–
pins directly to the existing signal chain circuitry will not
allow the channel’s sampling network to settle to 16-bit
resolution within the ADC acquisition time (tACQ). In these
cases, it is recommended that two unity-gain buffers be
inserted between the signal source and the ADC input
pins, as shown in Figure 6a. Table 2 lists several amplifier
and lowpass filter combinations recommended for use
in this circuit. The LT6237 combines fast settling, high
linearity, and low offset with 1.1nV/√Hz input-referred
noise density, enabling it to achieve the full ADC data sheet
SNR and THD specifications, as shown in the FFT plots in
Figures 6b to 6e. In applications where slightly degraded
SNR performance is acceptable, it is possible to drive the
LTC2341-16 using the lower-power LT6234. The LT6234
combines fast settling, good linearity, and low offset with
1.9nV/√Hz input-referred noise density, enabling it to drive
the LTC2341-16 with 1.5dB SNR loss compared with the
LT6237 when a 24.9Ω, 1nF filter is employed. As shown in
Table 2, the LT6237 may be used without a lowpass filter
at a loss of
