LTC2344-18
Quad, 18-Bit, 400ksps/ch
Differential SoftSpan ADC with
Wide Input Common Mode Range
DESCRIPTION
FEATURES
400ksps per Channel Throughput
nn Four Simultaneous Sampling Channels
nn ±4LSB INL (Maximum, ±4.096V Range)
nn Guaranteed 18-Bit, No Missing Codes
nn Differential, Wide Common Mode Range Inputs
nn Per-Channel SoftSpan Input Ranges:
±4.096V, 0V to 4.096V, ±2.048V, 0V to 2.048V
±5V, 0V to 5V, ±2.5V, 0V to 2.5V
nn 95dB Single-Conversion SNR (Typical)
nn −114dB THD (Typical) at f = 2kHz
IN
nn 102dB CMRR (Typical) at f = 200Hz
IN
nn Rail-to-Rail Input Overdrive Tolerance
nn Guaranteed Operation to 125°C
nn Integrated Reference and Buffer (4.096V)
nn SPI CMOS (1.8V to 5V) and LVDS Serial I/O
nn Internal Conversion Clock, No Cycle Latency
nn 81mW Power Dissipation (Typical)
nn 32-Lead (5mm × 5mm) QFN Package
The LTC®2344-18 is an 18-bit, low noise 4-channel simultaneous sampling successive approximation register (SAR)
ADC with differential, wide common mode range inputs.
Operating from a 5V supply and using the internal reference
and buffer, each channel of this SoftSpanTM ADC can be
independently configured on a conversion-by-conversion
basis to accept ±4.096V, 0V to 4.096V, ±2.048V, or 0V to
2.048V signals. Individual channels may also be disabled
to increase throughput on the remaining channels.
nn
The wide input common mode range and 102dB CMRR of
the LTC2344-18 analog inputs allow the ADC to directly
digitize a variety of signals, simplifying signal chain design. This input signal flexibility, combined with ±4LSB
INL, no missing codes at 18 bits, and 95dB SNR, makes
the LTC2344-18 an ideal choice for many applications
requiring wide dynamic range.
The LTC2344-18 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces. Between one and four
lanes of data output may be employed in CMOS mode,
allowing the user to optimize bus width and throughput.
APPLICATIONS
Programmable Logic Controllers
nn Industrial Process Control
nn Medical Imaging
nn High Speed Data Acquisition
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673,
9197235.
nn
TYPICAL APPLICATION
5V
0.1µF
2.2µF
Integral Nonlinearity vs
Output Code and Channel
1.8V TO 5V
0.1µF
CMOS OR LVDS
I/O INTERFACE
0V
0V
BIPOLAR
5V
UNIPOLAR
0V
DIFFERENTIAL INPUTS IN+/IN– WITH
1.0
SDO0
18-BIT
SAR ADC
SDO3
SCKO
SCKI
SDI
CS
BUSY
CNV
S/H
REFBUF
REFIN
GND
WIDE INPUT COMMON MODE RANGE
234418 TA01a
FOUR SIMULTANEOUS
SAMPLING CHANNELS
1.5
LTC2344-18
MUX
IN3+
S/H
IN3–
2.0
OVDD LVDS/CMOS
PD
S/H
• • •
5V
IN0+ S/H
IN0–
VDDLBYP
• • •
0V
VDD
INL ERROR (LSB)
5V
ARBITRARY
FULLY
DIFFERENTIAL
5V
47µF
0.1µF
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ALL CHANNELS
0.5
0
–0.5
–1.0
SAMPLE
CLOCK
–1.5
–2.0
–131072
–65536
0
65536
OUTPUT CODE
131072
234418 TA01b
234418f
For more information www.linear.com/LTC2344-18
1
LTC2344-18
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
ORDER INFORMATION
SDO–/SDI
BUSY
CS
VDDLBYP
GND
VDD
GND
GND
TOP VIEW
32 31 30 29 28 27 26 25
IN3– 1
24 SDO+/SDO3
IN3+
2
23 SCKO–/SDO2
IN2–
3
22 SCKO+/SCKO
IN2+
4
21 OVDD
33
GND
IN1– 5
20 GND
IN1+ 6
19 SCKI–/SCKI
IN0–
7
18 SCKI+/SDO1
IN0+
8
17 SDI–/SDO0
SDI+
CNV
LVDS/CMOS
PD
REFBUF
GND
GND
9 10 11 12 13 14 15 16
REFIN
Supply Voltage (VDD)...................................................6V
Supply Voltage (OVDD).................................................6V
Internal Regulated Supply Bypass (VDDLBYP).... (Note 3)
Analog Input Voltage
IN0+ to IN3+,
IN0– to IN3– (Note 4)................... –0.3V to (VDD + 0.3V)
REFIN..................................................... –0.3V to 2.8V
REFBUF, CNV (Note 4).............. –0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4)...... –0.3V to (OVDD + 0.3V)
Digital Output Voltage (Note 4)... –0.3V to (OVDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC2344C................................................. 0°C to 70°C
LTC2344I..............................................–40°C to 85°C
LTC2344H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 150°C, θJA = 44°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC2344-18#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2344CUH-18#PBF
LTC2344CUH-18#TRPBF
LTC2344IUH-18#PBF
LTC2344IUH-18#TRPBF
234418
32-Lead (5mm × 5mm) Plastic QFN
0°C to 70°C
234418
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
LTC2344HUH-18#PBF
LTC2344HUH-18#TRPBF
234418
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIN+
Absolute Input Range
(IN0+ to IN3+)
VIN–
Absolute Input Range
(IN0– to IN3–)
VIN+ – VIN– Input Differential Voltage
Range
VCM
MAX
UNITS
0
VDD
V
l
0
VDD
V
l
l
l
l
l
l
l
– VREFBUF
– VREFBUF/1.024
0
0
–0.5 • VREFBUF
–0.5 • VREFBUF/1.024
0
VREFBUF
VREFBUF/1.024
VREFBUF
VREFBUF/1.024
0.5 • VREFBUF
0.5 • VREFBUF/1.024
0.5 • VREFBUF
V
V
V
V
V
V
V
l
0
VDD
V
l
−VDD
VDD
V
l
–1
1
µA
(Note 6)
(Note 6)
SoftSpan 7: ±VREFBUF Range (Note 6)
SoftSpan 6: ±VREFBUF/1.024 Range (Note 6)
SoftSpan 5: 0V to VREFBUF Range (Note 6)
SoftSpan 4: 0V to VREFBUF/1.024 Range (Note 6)
SoftSpan 3: ±0.5 • VREFBUF Range (Note 6)
SoftSpan 2: ±0.5 • VREFBUF/1.024 Range (Note 6)
SoftSpan 1: 0V to 0.5 • VREFBUF Range (Note 6)
Input Common Mode Voltage (Note 6)
Range
VIN+ – VIN– Input Differential Overdrive
Tolerance
MIN
l
(Note 7)
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
Sample Mode
Hold Mode
CMRR
Input Common Mode
Rejection Ratio
VIN+ = VIN− = 3.6VP-P 200Hz Sine
VIHCNV
l
88
CNV High Level Input Voltage
l
1.3
VILCNV
CNV Low Level Input Voltage
l
IINCNV
CNV Input Current
VIN = 0V to VDD
TYP
90
10
pF
pF
102
dB
V
–10
l
0.5
V
10
μA
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN
Resolution
No Missing Codes
Transition Noise
SoftSpans 7 and 6: ±4.096V and ±4V Ranges
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges
SoftSpans 3 and 2: ±2.048V and ±2V Ranges
SoftSpan 1: 0V to 2.048V Range
INL
Integral Linearity Error
(Note 9)
DNL
ZSE
l
18
l
18
MAX
UNITS
Bits
Bits
1.6
3.2
3.2
6.3
LSBRMS
LSBRMS
LSBRMS
LSBRMS
l
–4
±1.5
4
LSB
Differential Linearity Error (Note 10)
l
−0.9
±0.5
0.9
LSB
Zero-Scale Error
l
−570
±50
570
(Note 11)
Zero-Scale Error Drift
FSE
TYP
Full-Scale Error
±2
VREFBUF = 4.096V (REFBUF Overdriven) (Note 11)
Full-Scale Error Drift
l
−0.13
±0.025
±2.5
μV
μV/°C
0.13
%FS
ppm/°C
234418f
For more information www.linear.com/LTC2344-18
3
LTC2344-18
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 8, 12)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
SINAD
Signal-to-(Noise +
Distortion) Ratio
SNR
91.0
85.0
85.1
79.3
95.0
89.1
89.1
83.3
dB
dB
dB
dB
Signal-to-Noise Ratio
SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
91.1
85.2
85.1
79.3
95.0
89.1
89.1
83.3
dB
dB
dB
dB
THD
Total Harmonic Distortion
SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
SFDR
Spurious Free Dynamic
Range
SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048 and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
Channel-to-Channel
Crosstalk
One Channel Converting 3.6VP-P 200Hz Sine in ±2.048V Range,
Crosstalk to All Other Channels
–114
–111
–110
–109
99
95
95
95
–3dB Input Bandwidth
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Transient Response
MAX
–99
–95
–95
–95
dB
dB
dB
dB
115
112
111
110
dB
dB
dB
dB
−109
dB
22
MHz
1
ns
150
ps
3
Full-Scale Step, 0.005% Settling
UNITS
psRMS
210
ns
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
VREFIN
Internal Reference Output Voltage
CONDITIONS
Internal Reference Temperature Coefficient
(Note 13)
Internal Reference Line Regulation
VDD = 4.75V to 5.25V
MIN
TYP
MAX
2.043
2.048
2.053
5
20
l
Internal Reference Output Impedance
VREFIN
4
REFIN Voltage Range
REFIN Overdriven (Note 6)
1.25
UNITS
V
ppm/°C
0.1
mV/V
20
kΩ
2.2
V
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
REFERENCE BUFFER CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
VREFBUF
Reference Buffer Output Voltage
REFIN Overdriven, VREFIN = 2.048V
IREFBUF
REFBUF Voltage Range
REFBUF Overdriven (Notes 6, 14)
REFBUF Input Impedance
VREFIN = 0V, Buffer Disabled
REFBUF Load Current
VREFBUF = 5V, 4 Channels Enabled (Notes 14, 15)
VREFBUF = 5V, Acquisition Mode (Note 14)
MIN
TYP
MAX
UNITS
l
4.091
4.096
4.101
V
l
2.5
5
V
13
1.5
0.39
l
kΩ
1.9
mA
mA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS Digital Inputs and Outputs
VIH
High Level Input Voltage
l 0.8 • OVDD
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
VIN = 0V to OVDD
l
V
–10
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IOUT = –500μA
l OVDD – 0.2
0.2 • OVDD
V
10
μA
5
pF
V
VOL
Low Level Output Voltage
IOUT = 500μA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
ISOURCE
Output Source Current
VOUT = 0V
–50
mA
ISINK
Output Sink Current
VOUT = OVDD
50
mA
–10
0.2
V
10
μA
LVDS Digital Inputs and Outputs
VID
Differential Input Voltage
RID
On-Chip Input Termination
Resistance
VICM
Common-Mode Input Voltage
IICM
Common-Mode Input Current
l
200
350
600
mV
l
80
106
10
130
Ω
MΩ
l
0.3
1.2
2.2
V
VIN+ = VIN– = 0V to OVDD
l
–10
10
μA
CS = 0V, VICM = 1.2V
CS = OVDD
VOD
Differential Output Voltage
RL = 100Ω Differential Termination
l
275
350
425
mV
VOCM
Common-Mode Output Voltage
RL = 100Ω Differential Termination
l
1.1
1.2
1.3
V
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
–10
10
μA
234418f
For more information www.linear.com/LTC2344-18
5
LTC2344-18
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
4.75
5.00
5.25
V
l
1.71
CMOS I/O Mode
VDD
Supply Voltage
OVDD
Supply Voltage
5.25
V
IVDD
Supply Current
400ksps Sample Rate, 4 Channels Enabled
400ksps Sample Rate, 4 Channels Enabled, VREFBUF = 5V (Note 14)
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
15.1
13.5
1.2
65
65
17.6
16.0
2.0
225
500
mA
mA
mA
μA
µA
IOVDD
Supply Current
400ksps Sample Rate, 4 Channels Enabled (CL = 25pF)
Acquisition Mode
Power Down Mode
l
l
l
2.0
1
1
3.0
20
20
mA
μA
μA
PD
Power Dissipation
400ksps Sample Rate, 4 Channels Enabled
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
81
6.0
0.33
0.33
96
10
1.2
2.6
mW
mW
mW
mW
5.00
5.25
V
5.25
V
LVDS I/O Mode
VDD
Supply Voltage
OVDD
Supply Voltage
IVDD
Supply Current
IOVDD
PD
l
4.75
l
2.375
400ksps Sample Rate, 4 Channels Enabled
400ksps Sample Rate, 4 Channels Enabled, VREFBUF = 5V (Note 14)
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
17.4
15.7
2.8
65
65
20.5
18.1
3.8
225
500
mA
mA
mA
μA
µA
Supply Current
400ksps Sample Rate, 4 Channels Enabled (RL = 100Ω)
Acquisition Mode (RL = 100Ω)
Power Down Mode
l
l
l
7.4
7
1
9.1
8.2
20
mA
mA
μA
Power Dissipation
400ksps Sample Rate, 4 Channels Enabled
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
106
32
0.33
0.33
126
40
1.2
2.6
mW
mW
mW
mW
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
fSMPL
Maximum Sampling Frequency
4 Channels Enabled
3 Channels Enabled
2 Channels Enabled
1 Channel Enabled
l
l
l
l
tCYC
Time Between Conversions
4 Channels Enabled, fSMPL = 400ksps
3 Channels Enabled, fSMPL = 500ksps
2 Channels Enabled, fSMPL = 666ksps
1 Channel Enabled, fSMPL = 1000ksps
l
l
l
l
6
MIN
2500
2000
1500
1000
TYP
MAX
UNITS
400
500
666
1000
ksps
ksps
ksps
ksps
ns
ns
ns
ns
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
tCONV
Conversion Time
N Channels Enabled, 1 ≤ N ≤ 4
l
425 • N –20
475 • N –20
525 • N –20
tACQ
Acquisition Time
(tACQ = tCYC – tCONV – tBUSYLH)
4 Channels Enabled, fSMPL = 400ksps
3 Channels Enabled, fSMPL = 500ksps
2 Channels Enabled, fSMPL = 666ksps
1 Channel Enabled, fSMPL = 1000ksps
l
l
l
l
390
415
440
465
600
575
550
525
tCNVH
CNV High Time
l
40
tCNVL
CNV Low Time
l
390
tBUSYLH
CNV↑ to BUSY Delay
tQUIET
Digital I/O Quiet Time from CNV↑
l
20
ns
tPDH
PD High Time
l
40
ns
tPDL
PD Low Time
l
40
ns
tWAKE
REFBUF Wake-Up Time
CL = 25pF
ns
ns
ns
ns
ns
ns
ns
30
l
CREFBUF = 47μF, CREFIN = 0.1μF
UNITS
200
ns
ms
CMOS I/O Mode
tSCKI
SCKI Period
tSCKIH
tSCKIL
tSSDISCKI
SDI Setup Time from SCKI↑
(Notes 16, 17)
l
10
ns
SCKI High Time
l
4
ns
SCKI Low Time
l
4
ns
(Note 16)
l
2
ns
1
tHSDISCKI
SDI Hold Time from SCKI↑
(Note 16)
l
tDSDOSCKI
SDO Data Valid Delay from SCKI↑
CL = 25pF (Note 16)
l
tHSDOSCKI
SDO Remains Valid Delay from SCKI↑
CL = 25pF (Note 16)
l
1.5
tSKEW
SDO to SCKO Skew
ns
7.5
ns
ns
(Note 16)
l
–1
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
CL = 25pF (Note 16)
l
0
0
1
ns
tEN
Bus Enable Time After CS↓
(Note 16)
l
15
ns
tDIS
Bus Relinquish Time After CS↑
(Note 16)
l
15
ns
ns
LVDS I/O Mode
tSCKI
SCKI Period
(Note 18)
l
4
ns
1.5
ns
1.5
ns
tSCKIH
SCKI High Time
(Note 18)
l
tSCKIL
SCKI Low Time
(Note 18)
l
tSSDISCKI
SDI Setup Time from SCKI
(Notes 10, 18)
l
1.2
ns
tHSDISCKI
SDI Hold Time from SCKI
(Notes 10, 18)
l
–0.2
ns
tDSDOSCKI
SDO Data Valid Delay from SCKI
(Notes 10, 18)
l
tHSDOSCKI
SDO Remains Valid Delay from SCKI
(Notes 10, 18)
l
1
tSKEW
SDO to SCKO Skew
(Note 10)
l
–0.4
(Note 10)
l
0
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
tEN
Bus Enable Time After CS↓
l
tDIS
Bus Relinquish Time After CS↑
l
6
ns
ns
0
0.4
ns
ns
50
ns
15
ns
234418f
For more information www.linear.com/LTC2344-18
7
LTC2344-18
ADC TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: VDDLBYP is the output of an internal voltage regulator, and should
only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND,
as described in the Pin Functions section. Do not connect this pin to any
external circuitry.
Note 4: When these pin voltages are taken below ground or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle
currents of up to 100mA below ground or above VDD or OVDD without
latch-up.
Note 5: VDD = 5V unless otherwise specified.
Note 6: Recommended operating conditions.
Note 7: Exceeding these limits on any channel may corrupt conversion
results on other channels. Refer to Absolute Maximum Ratings section for
pin voltage limits related to device reliability.
Note 8: VDD = 5V, OVDD = 2.5V, fSMPL = 400ksps, internal reference and
buffer, fully differential input signal drive in SoftSpan ranges 7 and 6,
bipolar input signal drive in SoftSpan ranges 3 and 2, unipolar input signal
drive in SoftSpan ranges 5, 4 and 1, unless otherwise specified.
Note 9: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 10: Guaranteed by design, not subject to test.
Note 11: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error
is the offset voltage measured from –0.5LSB when the output code
flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111.
Full-scale error for these SoftSpan ranges is the worst-case deviation of
the first and last code transitions from ideal and includes the effect of
offset error. For unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is
the offset voltage measured from 0.5LSB when the output code flickers
between 00 0000 0000 0000 0000 and 00 0000 0000 0000 0001. Fullscale error for these SoftSpan ranges is the worst-case deviation of the
last code transition from ideal and includes the effect of offset error.
Note 12: All specifications in dB are referred to a full-scale input in the
relevant SoftSpan input range, except for crosstalk, which is referred to
the crosstalk injection signal amplitude.
Note 13: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 14: When REFBUF is overdriven, the internal reference buffer must
be disabled by setting REFIN = 0V.
Note 15: IREFBUF varies proportionally with sample rate and the number of
active channels.
Note 16: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,
and OVDD = 5.25V.
Note 17: A tSCKI period of 10ns minimum allows a shift clock frequency of
up to 100MHz for rising edge capture.
Note 18: VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
CMOS Timings
0.8 • OVDD
tWIDTH
0.2 • OVDD
tDELAY
tDELAY
0.8 • OVDD
0.8 • OVDD
0.2 • OVDD
0.2 • OVDD
50%
50%
234418 F01
LVDS Timings (Differential)
+200mV
tWIDTH
–200mV
tDELAY
tDELAY
+200mV
+200mV
–200mV
–200mV
0V
0V
234418 F01b
Figure 1. Voltage Levels for Timing Specifications
8
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 400ksps, unless otherwise noted.
Integral Nonlinearity
vs Output Code and Channel
2.0
1.00
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ALL CHANNELS
1.5
1.0
0
–0.5
INL ERROR (LSB)
0.5
0.25
0
–0.25
0
–0.5
–0.50
–1.0
–1.5
–0.75
–1.5
0
65536
OUTPUT CODE
–1.00
131072
0
65536
4.0
2.0
0
–2.0
±4.096V AND ±4V
RANGES
–3.0
–4.0
–131072
–65536
0
65536
OUTPUT CODE
131072
1.0
0
0
–0.5
–1.0
–3.0
–1.5
234418 G04
65536
131072
196608
OUTPUT CODE
–2.0
–131072
262144
80000
±4.096V RANGE
σ = 1.5
60000
0
65536
OUTPUT CODE
0
±4.096V RANGE
1.6
σ = 2.2
COUNTS
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–20
SNR = 95.3dB
THD = –112dB
SINAD = 95.2dB
SFDR = 114dB
–40
40000
20000
131072
32k Point FFT fSMPL = 400kHz,
fIN = 2kHz
60000
20000
–65536
234418 G06
DC Histogram (Near Full-Scale)
40000
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
234418 G05
DC Histogram (Zero-Scale)
80000
0V TO 4.096V AND 0V TO 4V RANGES
0
ARBITRARY DRIVE
IN+/IN– COMMON MODE
SWEPT 0V TO 5V
0.5
–2.0
–4.0
±4.096V RANGE
1.0
0V TO 2.048V RANGE
–1.0
131072
1.5
AMPLITUDE (dBFS)
–1.0
2.0
INL ERROR (LSB)
INL ERROR (LSB)
±2.048V AND ±2V
RANGES
0
65536
OUTPUT CODE
Integral Nonlinearity
vs Output Code
UNIPOLAR DRIVE (IN– = 0V)
ONE CHANNEL
3.0
2.0
1.0
–65536
234418 G03
Integral Nonlinearity
vs Output Code and Range
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ONE CHANNEL
3.0
–2.0
–131072
262144
234418 G02
Integral Nonlinearity
vs Output Code and Range
4.0
131072
196608
OUTPUT CODE
±2.048V AND ±2V
RANGES
0.5
–1.0
–65536
BIPOLAR DRIVE (IN– = 2.5V)
ONE CHANNEL
1.5
1.0
234418 G01
INL ERROR (LSB)
2.0
0.50
–2.0
–131072
COUNTS
Integral Nonlinearity
vs Output Code and Range
ALL RANGES
ALL CHANNELS
0.75
DNL ERROR (LSB)
INL ERROR (LSB)
Differential Nonlinearity
vs Output Code and Channel
–60
–80
–100
–120
–140
–160
0
–10 –8 –6 –4 –2
0 2
CODE
4
6
8
10
234418 G07
0
131052 131056 131060 131064 131068 131072
CODE
234418 G08
–180
0
40
80
120
FREQUENCY (kHz)
160
200
234418 G09
234418f
For more information www.linear.com/LTC2344-18
9
LTC2344-18
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 400ksps, unless otherwise noted.
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
0
40
80
120
FREQUENCY (kHz)
160
–180
200
0
40
80
120
FREQUENCY (kHz)
160
THD, Harmonics vs VREFBUF,
fIN = 2kHz
106
–115
2ND
–120
–125
3RD
–130
–135
3.5
4
4.5
REFBUF VOLTAGE (V)
5
234418 G12
THD, Harmonics
vs Input Frequency
98
–70
94
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–80
SNR
SINAD
90
–90
–100
THD
–110
2ND
86
–120
82
100
–130
100
3
3.5
4
4.5
REFBUF VOLTAGE (V)
5
1k
10k
FREQUENCY (Hz)
100k
234418 G13
–100
96.0
–110
CMRR vs Input Frequency and
Channel
130
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
SNR, SINAD (dBFS)
–130
3RD
–140
0
1
2
3
4
INPUT COMMON MODE (V)
5
234418 G16
10
110
95.6
95.4
SNR
SINAD
95.0
–40
100
90
80
95.2
2ND
±4.096V RANGE
IN+ = IN– = 3.6VP–P SINE
ALL CHANNELS
120
95.8
THD
100k
234418 G15
SNR, SINAD vs Input Level,
fIN = 2kHz
±4.096V RANGE
1VP–P FULLY DIFFERENTIAL DRIVE
–120
1k
10k
FREQUENCY (Hz)
234418 G14
THD, Harmonics vs Input
Common Mode, fIN = 2kHz
THD, HARMONICS (dBFS)
3
3RD
–140
2.5
–150
94
90
2.5
200
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
102
THD
SNR, SINAD (dBFS)
THD, HARMONICS (dBFS)
–110
SINAD
SNR, SINAD
vs Input Frequency
±VREFBUF RANGE
FULLY DIFFERENIAL DRIVE (IN– = –IN+)
–105
SNR
96
234418 G11
234418 G10
–100
±VREFBUF RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
92
CMRR (dB)
–180
SNR, SINAD vs VREFBUF,
fIN = 2kHz
98
SNR = 89.4dB
THD = –109dB
SINAD = 89.4dB
SFDR = 111dB
–40
–60
100
0V TO 4.096V RANGE
UNIPOLAR DRIVE (IN– = 0V)
–20
AMPLITUDE (dBFS)
–40
AMPLITUDE (dBFS)
0
±4.096V RANGE
ARBITRARY DRIVE
SFDR = 119dB
SNR = 95.3dB
THD, HARMONICS (dBFS)
0
–20
32k Point FFT fSMPL = 400kHz,
fIN = 2kHz
SNR, SINAD (dBFS)
32k Point Arbitrary Two-Tone FFT
fSMPL = 400kHz, IN+ = –7dBFS 2kHz
Sine, IN– = –7dBFS 3.1kHz Sine
70
–30
–20
–10
INPUT LEVEL (dBFS)
0
234418 G17
60
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
234418 G18
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 400ksps, unless otherwise noted.
Crosstalk vs Input Frequency and
Channel
IN0+ = –IN0– = 3.6V
–100
CH1
–105
–110
–115
–120
95.5
94.5
93.5
–130
92.5
CH3
100
1k
10k
FREQUENCY (Hz)
100k
MAX DNL
MAX INL
–0.5
–1.0
–1.5
0.100
MIN DNL
MIN INL
–2.0
–55 –35 –15
0.050
0.025
0.000
–0.025
–0.050
–0.100
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
234418 G22
2
0
–2
–4
–6
0.050
0.025
0.000
–0.025
–0.050
–0.100
–55 –35 –15
234418 G25
5 25 45 65 85 105 125
TEMPERATURE (°C)
234418 G24
Power-Down Current
vs Temperature
IVDD
14
12
10
8
6
4
2
–2
5 25 45 65 85 105 125
TEMPERATURE (°C)
±4.096V RANGE
REFBUF OVERDRIVEN
VREFBUF = 4.096V
ALL CHANNELS
0.075
IVDD
16
0
–8
5 25 45 65 85 105 125
TEMPERATURE (°C)
1000
18
6
–10
–55 –35 –15
0.100
20
±4.096V RANGE
ALL CHANNELS
4
3RD
234418 G21
Supply Current vs Temperature
SUPPLY CURRENT (mA)
ZERO-SCALE ERROR (LSB)
8
2ND
234418 G23
Zero-Scale Error vs
Temperature and Channel
10
–115
–0.075
–0.075
5 25 45 65 85 105 125
TEMPERATURE (°C)
THD
Negative Full-Scale Error vs
Temperature and Channel
±4.096V RANGE
REFBUF OVERDRIVEN
VREFBUF = 4.096V
ALL CHANNELS
0.075
FULL-SCALE ERROR (%)
INL, DNL ERROR (LSB)
1.0
0
–110
Positive Full-Scale Error vs
Temperature and Channel
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
0.5
–105
234418 G20
INL, DNL vs Temperature
1.5
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–125
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
234418 G19
2.0
THD, Harmonics vs Temperature,
fIN = 2kHz
–120
92.0
–55 –35 –15
1M
–100
POWER-DOWN CURRENT (µA)
10
SINAD
94.0
93.0
–135
SNR
95.0
–125
–95
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
96.0
SNR, SINAD (dBFS)
–95
96.5
THD, HARMONICS (dBFS)
–90
CROSSTALK (dB)
97.0
±4.096V RANGE
P–P SINE
ALL CHANNELS CONVERTING
–85
FULL-SCALE ERROR (%)
–80
SNR, SINAD vs Temperature,
fIN = 2kHz
–4
–55 –35 –15
IOVDD
5 25 45 65 85 105 125
TEMPERATURE (°C)
234418 G26
100
10
1
0.1
0.01
–55 –35 –15
IOVDD
5 25 45 65 85 105 125
TEMPERATURE (°C)
234418 G27
234418f
For more information www.linear.com/LTC2344-18
11
LTC2344-18
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 400ksps, unless otherwise noted.
Offset Error vs Input Common
Mode and Channel
OFFSET ERROR (LSB)
INTERNAL REFERENCE OUTPUT (V)
±4.096V RANGE
ALL CHANNELS
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
1
2
3
4
INPUT COMMON MODE (V)
150
15 UNITS
2.051
120
2.049
2.048
2.047
12
10
8
6
4
IOVDD
100
200
300
SAMPLING FREQUENCY (kHz)
100k
1M
N=3
N=1
60
50
40
30
20
10
0
400
0
200
400
600
800
SAMPLING FREQUENCY (kHz)
1000
234418 G32
Step Response (Fine Settling)
131072
500
98304
400
65536
±2.048V RANGE
IN+ = 400.1767kHz SQUARE WAVE
IN– = 2.048V
DRIVEN BY 50Ω SOURCE
–65536
–98304
50 100 150 200 250 300 350 400 450
SETTLING TIME (ns)
DEVIATION FROM FINAL VALUE (LSB)
OUTPUT CODE (LSB)
1k
10k
FREQUENCY (Hz)
N=2
70
Step Response
(Large-Signal Settling)
300
200
100
0
–100
±2.048V RANGE
IN+ = 400.1767kHz
SQUARE WAVE
IN– = 2.048V
DRIVEN BY 50Ω SOURCE
–200
–300
–400
–500
–50 0
50 100 150 200 250 300 350 400 450
SETTLING TIME (ns)
234418 G33
12
100
234418 G30
N=4
234418 G31
–131072
–50 0
10
Power Dissipation vs Sampling
Rate, N Channels Enabled
POWER DISSIPATION (mW)
SUPPLY CURRENT (mA)
IVDD
–32768
VDD
234418 G29
80
0
50
5 25 45 65 85 105 125
TEMPERATURE (°C)
16
32768
90
60
90
0
100
70
2.045
18
2
110
80
2.046
Supply Current vs Sampling Rate
14
IN+ = IN– = 0V
130
2.044
–55 –35 –15
5
OVDD
140
2.050
234418 G28
0
PSRR vs Frequency
2.052
PSRR (dB)
2.0
Internal Reference Output
vs Temperature
234418 G34
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
PIN FUNCTIONS
Pins that are the Same for All Digital I/O Modes
IN0+/IN0– to IN3+/IN3– (Pins 8/7, 6/5, 4/3, and 2/1):
Positive and Negative Analog Inputs, Channels 0 to 3. The
converter simultaneously samples and digitizes (VIN+ –
VIN–) for all channels. Wide input common mode range
(0V ≤ VCM ≤ VDD) and high common mode rejection allow
the inputs to accept a wide variety of signal swings. Fullscale input range is determined by the channel’s SoftSpan
configuration.
PD (Pin 13): Power Down Input. When this pin is brought
high, the LTC2344-18 is powered down and subsequent
conversion requests are ignored. If this occurs during a
conversion, the device powers down once the conversion
completes. If this pin is brought high twice without an
intervening conversion, an internal global reset is initiated, equivalent to a power-on-reset event. Logic levels
are determined by OVDD.
GND (Pins 9, 11, 20, 29, 31, 32, 33): Ground. Solder all
GND pins to a solid ground plane.
LVDS/CMOS (Pin 14): I/O Mode Select. Tie this pin to OVDD
to select LVDS I/O mode, or to ground to select CMOS I/O
mode. Logic levels are determined by OVDD.
REFIN (Pin 10): Bandgap Reference Output/Reference
Buffer Input. An internal bandgap reference nominally
outputs 2.048V on this pin. An internal reference buffer
amplifies VREFIN to create the converter master reference
voltage VREFBUF = 2 • VREFIN on the REFBUF pin. When
using the internal reference, bypass REFIN to GND (Pin
11) close to the pin with a 0.1μF ceramic capacitor to filter
the bandgap output noise. If more accuracy is desired,
overdrive REFIN with an external reference in the range
of 1.25V to 2.2V.
BUSY (Pin 26): Busy Output. The BUSY signal indicates
that a conversion is in progress. This pin transitions lowto-high at the start of each conversion and stays high until
the conversion is complete. Logic levels are determined
by OVDD.
REFBUF (Pin 12): Internal Reference Buffer Output. An
internal reference buffer amplifies VREFIN to create the
converter master reference voltage VREFBUF = 2 • VREFIN on
this pin, nominally 4.096V when using the internal bandgap
reference. Bypass REFBUF to GND (Pin 11) close to the
pin with a 47μF ceramic capacitor. The internal reference
buffer may be disabled by grounding its input at REFIN.
With the buffer disabled, overdrive REFBUF with an external reference voltage in the range of 2.5V to 5V. When
using the internal reference buffer, limit the loading of any
external circuitry connected to REFBUF to less than 10µA.
Using a high input impedance amplifier to buffer VREFBUF
to any external circuits is recommended.
CNV (Pin 15): Conversion Start Input. A rising edge on
this pin puts the internal sample-and-holds into the hold
mode and initiates a new conversion. CNV is not gated
by CS, allowing conversions to be initiated independent
of the state of the serial I/O bus.
VDDLBYP (Pin 28): Internal 2.5V Regulator Bypass Pin. The
voltage on this pin is generated via an internal regulator
operating off of VDD. This pin must be bypassed to GND
close to the pin with a 2.2μF ceramic capacitor. Do not
connect this pin to any external circuitry.
VDD (Pin 30): 5V Power Supply. The range of VDD is 4.75V
to 5.25V. This pin must be bypassed to GND close to the
pin with a 0.1μF ceramic capacitor.
234418f
For more information www.linear.com/LTC2344-18
13
LTC2344-18
PIN FUNCTIONS
CMOS I/O Mode
LVDS I/O Mode
SDI+ (Pin 16): LVDS Positive Serial Data Input. In CMOS
I/O mode, this pin is Hi-Z.
SDI+/SDI– (Pins 16, 17): LVDS Positive and Negative Serial
Data Input. Differentially drive SDI+/SDI– with the desired
12-bit SoftSpan configuration word (see Table 1a), latched
on both the rising and falling edges of SCKI+/SCKI–. The
SDI+/SDI– input pair is internally terminated with a 100Ω
differential resistor when CS = 0.
SDO0 to SDO3 (Pins 17, 18, 23, 24): CMOS Serial Data
Outputs, Channels 0 to 3. The most recent conversion
result along with channel configuration information is
clocked out onto the SDO pins on each rising edge of SCKI.
Output data formatting is described in the Digital Interface
section. Leave unused SDO outputs unconnected. Logic
levels are determined by OVDD.
SCKI (Pin 19): CMOS Serial Clock Input. Drive SCKI with
the serial I/O clock. SCKI rising edges latch serial data in
on SDI and clock serial data out on SDO0 to SDO3. For
standard SPI bus operation, capture output data at the
receiver on rising edges of SCKI. SCKI is allowed to idle
either high or low. Logic levels are determined by OVDD.
OVDD (Pin 21): I/O Interface Power Supply. In CMOS I/O
mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD
to GND (Pin 20) close to the pin with a 0.1μF ceramic
capacitor.
SCKO (Pin 22): CMOS Serial Clock Output. SCKI rising
edges trigger transitions on SCKO that are skew-matched
to the serial output data streams on SDO0 to SDO3. The
resulting SCKO frequency is half that of SCKI. Rising and
falling edges of SCKO may be used to capture SDO data at
the receiver (FPGA) in double data rate (DDR) fashion. For
standard SPI bus operation, SCKO is not used and should
be left unconnected. SCKO is forced low at the falling edge
of BUSY. Logic levels are determined by OVDD.
SDI (Pin 25): CMOS Serial Data Input. Drive this pin with the
desired 12-bit SoftSpan configuration word (see Table 1a),
latched on the rising edges of SCKI. If all channels will be
configured to operate only in SoftSpan 7, tie SDI to OVDD.
Logic levels are determined by OVDD.
CS (Pin 27): Chip Select Input. The serial data I/O bus is
enabled when CS is low and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI.
Logic levels are determined by OVDD.
14
SCKI+/SCKI– (Pins 18, 19): LVDS Positive and Negative
Serial Clock Input. Differentially drive SCKI+/SCKI– with
the serial I/O clock. SCKI+/SCKI– rising and falling edges
latch serial data in on SDI+/SDI– and clock serial data out
on SDO+/SDO–. Idle SCKI+/SCKI– low, including when
transitioning CS. The SCKI+/SCKI– input pair is internally
terminated with a 100Ω differential resistor when CS = 0.
OVDD (Pin 21): I/O Interface Power Supply. In LVDS I/O
mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD
to GND (Pin 20) close to the pin with a 0.1μF ceramic
capacitor.
SCKO+/SCKO– (Pins 22, 23): LVDS Positive and Negative
Serial Clock Output. SCKO+/SCKO– outputs a copy of the
input serial I/O clock received on SCKI+/SCKI–, skewmatched with the serial output data stream on SDO+/SDO–.
Use the rising and falling edges of SCKO+/SCKO– to capture SDO+/SDO– data at the receiver (FPGA). The SCKO+/
SCKO– output pair must be differentially terminated with
a 100Ω resistor at the receiver (FPGA).
SDO+/SDO– (Pins 24, 25): LVDS Positive and Negative
Serial Data Output. The most recent conversion result
along with channel configuration information is clocked
out onto SDO+/SDO– on both rising and falling edges of
SCKI+/SCKI–, beginning with channel 0. The SDO+/SDO–
output pair must be differentially terminated with a 100Ω
resistor at the receiver (FPGA).
CS (Pin 27): Chip Select Input. The serial data I/O bus is
enabled when CS is low, and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI+/
SCKI–. The internal 100Ω differential termination resistors
on the SCKI+/SCKI– and SDI+/SDI– input pairs are disabled
when CS is high. Logic levels are determined by OVDD.
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
CONFIGURATION TABLES
Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Independent Binary SoftSpan Codes SS[2:0] for Each
Channel Based on Desired Analog Input Range. Combine SoftSpan Codes to Form 12-Bit SoftSpan Configuration Word S[11:0]. Use
Serial Interface to Write SoftSpan Configuration Word to LTC2344-18, as shown in Figure 19
BINARY SoftSpan CODE
SS[2:0]
111
110
101
100
011
010
001
000
ANALOG INPUT RANGE
FULL SCALE RANGE
±VREFBUF
±VREFBUF/1.024
0V to VREFBUF
0V to VREFBUF/1.024
±0.5 • VREFBUF
±0.5 • VREFBUF/1.024
0V to 0.5 • VREFBUF
Channel Disabled
2 • VREFBUF
2 • VREFBUF/1.024
VREFBUF
VREFBUF/1.024
VREFBUF
VREFBUF/1.024
0.5 • VREFBUF
Channel Disabled
BINARY FORMAT OF
CONVERSION RESULT
Two’s Complement
Two’s Complement
Straight Binary
Straight Binary
Two’s Complement
Two’s Complement
Straight Binary
All Zeros
Table 1b. Reference Configuration Table. The LTC2344-18 Supports Three Reference Configurations. Analog Input Range Scales with
the Converter Master Reference Voltage, VREFBUF
REFERENCE CONFIGURATION
Internal Reference with
Internal Buffer
VREFIN
VREFBUF
2.048V
BINARY SoftSpan CODE
SS[2:0]
ANALOG INPUT RANGE
111
±4.096V
110
±4V
101
0V to 4.096V
100
0V to 4V
011
±2.048V
010
±2V
001
0V to 2.048V
4.096V
1.25V
(Min Value)
2.5V
External Reference with
Internal Buffer
(REFIN Pin Externally
Overdriven)
2.2V
(Max Value)
4.4V
111
±2.5V
110
±2.441V
101
0V to 2.5V
100
0V to 2.441V
011
±1.25V
010
±1.221V
001
0V to 1.25V
111
±4.4V
110
±4.297V
101
0V to 4.4V
100
0V to 4.297V
011
±2.2V
010
±2.148V
001
0V to 2.2V
234418f
For more information www.linear.com/LTC2344-18
15
LTC2344-18
CONFIGURATION TABLES
Table 1b. Reference Configuration Table (Continued). The LTC2344-18 Supports Three Reference Configurations. Analog Input Range
Scales with the Converter Master Reference Voltage, VREFBUF
REFERENCE CONFIGURATION
VREFIN
0V
VREFBUF
BINARY SoftSpan CODE
SS[2:0]
2.5V
(Min Value)
External Reference
Unbuffered
(REFBUF Pin
Externally Overdriven,
REFIN Pin Grounded)
0V
16
5V
(Max Value)
ANALOG INPUT RANGE
111
±2.5V
110
±2.441V
101
0V to 2.5V
100
0V to 2.441V
011
±1.25V
010
±1.221V
001
0V to 1.25V
111
±5V
110
±4.883V
101
0V to 5V
100
0V to 4.883V
011
±2.5V
010
±2.441V
001
0V to 2.5V
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
FUNCTIONAL BLOCK DIAGRAM
CMOS I/O Mode
VDD
VDDLBYP
IN0+
IN0–
S/H
OVDD
LTC2344-18
2.5V
REGULATOR
SDO0
• • •
IN1+
S/H
IN2+
IN2–
S/H
IN3+
IN3–
S/H
18-BIT
SAR ADC
4-CHANNEL MULTIPLEXER
IN1–
18 BITS
CMOS
SERIAL
I/O
INTERFACE
SDO3
SCKO
SDI
SCKI
CS
2.048V
REFERENCE
GND
20k
REFERENCE
BUFFER
2×
REFIN
REFBUF
CONTROL
LOGIC
BUSY
CNV PD
LVDS/CMOS
234418 BD01
234418f
For more information www.linear.com/LTC2344-18
17
LTC2344-18
FUNCTIONAL BLOCK DIAGRAM
LVDS I/O Mode
VDD
IN0
VDDLBYP
IN0–
S/H
OVDD
LTC2344-18
+
SDO+
2.5V
REGULATOR
SDO–
SCKO+
IN1+
S/H
IN2+
IN2–
S/H
IN3+
IN3–
S/H
18-BIT
SAR ADC
4-CHANNEL MULTIPLEXER
IN1–
18 BITS
LVDS
SERIAL
I/O
INTERFACE
SCKO–
SDI+
SDI–
SCKI+
SCKI–
CS
2.048V
REFERENCE
GND
20k
REFERENCE
BUFFER
2×
REFIN
REFBUF
CONTROL
LOGIC
BUSY
CNV PD
LVDS/CMOS
234418 BD02
18
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
TIMING DIAGRAM
CMOS I/O Mode
CS = PD = 0
SAMPLE N
SAMPLE N + 1
CNV
BUSY
CONVERT
ACQUIRE
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCKI
SDI
DON’T CARE
S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1
SCKO
DON’T CARE
SDO0
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
• • •
CONVERSION RESULT
0 C1 C0 SS2 SS1 SS0 D17
CHAN ID SoftSpan
CONVERSION RESULT
CHANNEL 0
CONVERSION N
SDO3
CHANNEL 1
CONVERSION N
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 C1 C0 SS2 SS1 SS0 D17
DON’T CARE
CONVERSION RESULT
CHAN ID SoftSpan
CHANNEL 3
CONVERSION N
CONVERSION RESULT
CHANNEL 0
CONVERSION N
234418 TD01
LVDS I/O Mode
CS = PD = 0
SAMPLE
N+1
SAMPLE N
CNV
(CMOS)
BUSY
(CMOS)
CONVERT
SCKI
(LVDS)
SDI
DON’T CARE
(LVDS)
ACQUIRE
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
90 91 92 93 94 95 96
S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1
SCKO
(LVDS)
SDO
(LVDS) DON’T CARE D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONVERSION RESULT
0 C1 C0 SS2 SS1 SS0 D17 D16 D15 D0 0 C1 C0 SS2 SS1 SS0 D17
CHAN ID SoftSpan
CHANNEL 0
CONVERSION N
CHANNEL 1
CONVERSION N
CHAN ID SoftSpan
CHANNEL 3
CONVERSION N
CONVERSION
RESULT
CHANNEL 0
CONVERSION N
234418 TD02
234418f
For more information www.linear.com/LTC2344-18
19
LTC2344-18
APPLICATIONS INFORMATION
OVERVIEW
The LTC2344-18 is an 18-bit, low noise 4-channel simultaneous sampling successive approximation register
(SAR) ADC with differential, wide common mode range
inputs. Using the integrated low-drift reference and buffer
(VREFBUF = 4.096V nominal), each channel of this SoftSpan
ADC can be independently configured on a conversionby-conversion basis to accept ±4.096V, 0V to 4.096V,
±2.048V, or 0V to 2.048V signals. The input signal range
may be expanded up to ±5V using an external 5V reference. Individual channels may also be disabled to increase
throughput on the remaining channels.
The wide input common mode range and high CMRR
(102dB typical, VIN+ = VIN– = 3.6VP-P 200Hz Sine) of the
LTC2344-18 analog inputs allow the ADC to directly digitize a variety of signals, simplifying signal chain design.
This input signal flexibility, combined with ±4LSB INL,
no missing codes at 18-bits, and 95dB SNR, makes the
LTC2344-18 an ideal choice for many applications requiring wide dynamic range.
The LTC2344-18 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces, enabling it to communicate equally well with legacy microcontrollers and
modern FPGAs. In CMOS mode, applications may employ
between one and four lanes of serial output data, allowing
the user to optimize bus width and data throughput. The
LTC2344-18 typically dissipates 81mW when converting
four analog input channels simultaneously at 400ksps
per channel throughput. An optional power-down mode
may be employed to further reduce power consumption
during inactive periods.
CONVERTER OPERATION
The LTC2344-18 operates in two phases. During the acquisition phase, the sampling capacitors in each channel’s
sample-and-hold (S/H) circuit connect to their respective
analog input pins and track the differential analog input
voltage (VIN+ – VIN–). A rising edge on the CNV pin transi-
20
tions all channels’ S/H circuits from track mode to hold
mode, simultaneously sampling the input signals on all
channels and initiating a conversion. During the conversion
phase, each channel’s sampling capacitors are connected,
one channel at a time, to an 18-bit charge redistribution
capacitor D/A converter (CDAC). The CDAC is sequenced
through a successive approximation algorithm, effectively
comparing the sampled input voltage with binary-weighted
fractions of the channel’s SoftSpan full-scale range (e.g.,
VFSR/2, VFSR/4 … VFSR/262144) using a differential
comparator. At the end of this process, the CDAC output
approximates the channel’s sampled analog input. Once
all channels have been converted in this manner, the ADC
control logic prepares the 18-bit digital output codes from
each channel for serial transfer.
TRANSFER FUNCTION
The LTC2344-18 digitizes each channel’s full-scale voltage
range into 218 levels. In conjunction with the ADC master
reference voltage, VREFBUF, a channel’s SoftSpan configuration determines its input voltage range, full-scale range,
LSB size, and the binary format of its conversion result, as
shown in Tables 1a and 1b. For example, employing the
internal reference and buffer (VREFBUF = 4.096V nominal),
SoftSpan 7 configures a channel to accept a ±4.096V bipolar analog input voltage range, which corresponds to a
8.192V full-scale range with a 31.25μV LSB. Other SoftSpan
configurations and reference voltages may be employed to
convert both larger and smaller bipolar and unipolar input
ranges. Conversion results are output in two’s complement binary format for all bipolar SoftSpan ranges, and
in straight binary format for all unipolar SoftSpan ranges.
The ideal two’s complement transfer function is shown in
Figure 2, while the ideal straight binary transfer function
is shown in Figure 3.
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
OUTPUT CODE (TWO’S COMPLEMENT)
APPLICATIONS INFORMATION
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/262144
100...000
–FSR/2
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
234418 F02
OUTPUT CODE (STRAIGHT BINARY)
Figure 2. LTC2344-18 Two’s Complement Transfer Function
111...111
111...110
100...001
100...000
011...111 UNIPOLAR
ZERO
011...110
000...001
FSR = +FS
1LSB = FSR/262144
000...000
0V
high CMRR allows the IN+/IN– analog inputs to swing
with an arbitrary relationship to each other, provided
each pin remains between ground and VDD. This feature
of the LTC2344-18 enables it to accept a wide variety of
signal swings, including traditional classes of analog input
signals such as pseudo-differential unipolar, pseudodifferential bipolar, and fully differential, simplifying
signal chain design.
In all SoftSpan ranges, each channel’s analog inputs can
be modeled by the equivalent circuit shown in Figure 4.
At the start of acquisition, the 80pF sampling capacitors
(CIN) connect to the analog input pins IN+/IN– through the
sampling switches, each of which has approximately 90Ω
(RIN) of on-resistance. The initial voltage on both sampling
capacitors at the start of acquisition is approximately equal
to the sampled common-mode voltage (VIN+ + VIN–)/2
from the prior conversion. The external circuitry connected
to IN+ and IN– must source or sink the charge that flows
through RIN as the sampling capacitors settle from their
initial voltages to the new input pin voltages over the course
of the acquisition interval. During conversion and power
down modes, the analog inputs draw only a small leakage
current. The diodes at the inputs provide ESD protection.
FSR – 1LSB
INPUT VOLTAGE (V)
234418 F03
VDD
Figure 3. LTC2344-18 Straight Binary Transfer Function
RIN
90Ω
IN+
CIN
80pF
ANALOG INPUTS
Each channel of the LTC2344-18 simultaneously samples
the voltage difference (VIN+ – VIN–) between its analog
input pins over a wide common mode input range while
attenuating unwanted signals common to both input
pins by the common-mode rejection ratio (CMRR) of
the ADC. Wide common mode input range coupled with
VDD
IN–
RIN
90Ω
CIN
80pF
BIAS
VOLTAGE
234418 F04
Figure 4. Equivalent Circuit for Differential Analog Inputs,
Single Channel Shown
234418f
For more information www.linear.com/LTC2344-18
21
LTC2344-18
APPLICATIONS INFORMATION
Bipolar SoftSpan Input Ranges
For channels configured in SoftSpan ranges 7, 6, 3, or
2, the LTC2344-18 digitizes the differential analog input
voltage (VIN+ – VIN–) over a bipolar span of ±VREFBUF,
±VREFBUF/1.024, ±0.5 • VREFBUF, or ±0.5 • VREFBUF/1.024,
respectively, as shown in Table 1a. These SoftSpan ranges
are useful for digitizing input signals where IN+ and IN–
swing above and below each other. Traditional examples
include fully differential input signals, where IN+ and
IN– are driven 180 degrees out-of-phase with respect
to each other centered around a common mode voltage
(VIN+ + VIN–)/2, and pseudo-differential bipolar input
signals, where IN+ swings above and below a reference
level, driven on IN–. Regardless of the chosen SoftSpan
range, the wide common mode input range and high CMRR
of the IN+/IN– analog inputs allow them to swing with an
arbitrary relationship to each other, provided each pin
remains between ground and VDD. The output data format
for all bipolar SoftSpan ranges is two’s complement.
The LTC2344-18 sampling network RC time constant of
7.2ns implies an 18-bit settling time to a full-scale step of
approximately 13 • (RIN • CIN) = 94ns. The impedance and
self-settling of external circuitry connected to the analog
input pins will increase the overall settling time required.
Low impedance sources can directly drive the inputs of
the LTC2344-18 without gain error, but high impedance
sources should be buffered to ensure sufficient settling
during acquisition and to optimize the linearity and distortion performance of the ADC. Settling time is an important
consideration even for DC input signals, as the voltages on
the sampling capacitors will differ from the analog input
pin voltages at the start of acquisition.
Most applications should use a buffer amplifier to drive the
analog inputs of the LTC2344-18. The amplifier provides
low output impedance, enabling fast settling of the analog
signal during the acquisition phase. It also provides isolation between the signal source and the charge flow at the
analog inputs when entering acquisition.
Unipolar SoftSpan Input Ranges
Input Filtering
For channels configured in SoftSpan ranges 5, 4, or 1, the
LTC2344-18 digitizes the differential analog input voltage
(VIN+ – VIN–) over a unipolar span of 0V to VREFBUF, 0V
to VREFBUF/1.024, or 0V to 0.5 • VREFBUF, respectively, as
shown in Table 1a. These SoftSpan ranges are useful for
digitizing input signals where IN+ remains above IN–. A
traditional example includes pseudo-differential unipolar
input signals, where IN+ swings above a ground reference
level, driven on IN–. Regardless of the chosen SoftSpan
range, the wide common mode range and high CMRR of
the IN+/IN– analog inputs allow them to swing with an
arbitrary relationship to each other, provided each pin
remains between ground and VDD. The output data format
for all unipolar SoftSpan ranges is straight binary.
The noise and distortion of an input buffer amplifier and
other supporting circuitry must be considered since they
add to the ADC noise and distortion. Noisy input signals
should be filtered prior to the buffer amplifier with a lowbandwidth filter to minimize noise. The simple one-pole
RC lowpass filter shown in Figure 5 is sufficient for many
applications.
INPUT DRIVE CIRCUITS
The initial voltage on each channel’s sampling capacitors
at the start of acquisition must settle to the new input
pin voltages during the acquisition interval. The external
circuitry connected to IN+ and IN– must source or sink
the charge that flows through RIN as this settling occurs.
22
At the output of the buffer, a lowpass RC filter network
formed by the 90Ω sampling switch on-resistance (RIN)
and the 80pF sampling capacitance (CIN) limits the input
bandwidth on each channel to 22MHz, which is fast enough
to allow for sufficient transient settling during acquisition
while simultaneously filtering driver wideband noise. A
buffer amplifier with low noise density should be selected
to minimize SNR degradation over this bandwidth. An
additional filter network may be placed between the buffer output and ADC input to further minimize the noise
contribution of the buffer and reduce disturbances to the
buffer from ADC acquisition transients. A simple one-pole
lowpass RC filter is sufficient for many applications. It is
important that the RC time constant of this filter be small
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
APPLICATIONS INFORMATION
LOWPASS
SIGNAL FILTER
UNIPOLAR
INPUT SIGNAL
5V
160Ω
+
BUFFER
AMPLIFIER
–
10nF
IN0+
IN0–
LTC2344-18
0V
BW = 100kHz
ONLY CHANNEL 0 SHOWN FOR CLARITY
234418 F05
Figure 5. Unipolar Signal Chain with Input Filtering
enough to allow the analog inputs to completely settle to
18-bit resolution within the ADC acquisition time (tACQ),
as insufficient settling can limit INL and THD performance.
Also note that the minimum acquisition time varies with
sampling frequency (fSMPL) and the number of enabled
channels.
High quality capacitors and resistors should be used in
the RC filters since these components can add distortion.
NPO/COG and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self-heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
Buffering Arbitrary and Fully Differential Analog Input
Signals
The wide common mode input range and high CMRR of
the LTC2344-18 allow each channel’s IN+ and IN– pins
to swing with an arbitrary relationship to each other,
provided each pin remains between ground and VDD. This
unique feature of the LTC2344-18 enables it to accept a
wide variety of signal swings, simplifying signal chain
design. In many applications, connecting a channel’s IN+
and IN– pins directly to the existing signal chain circuitry
will not allow the channel’s sampling network to settle to
18-bit resolution within the ADC acquisition time (tACQ). In
these cases, it is recommended that two unity-gain buffers
be inserted between the signal source and the ADC input
pins, as shown in Figure 6a. Table 2 lists several amplifier
and lowpass filter combinations recommended for use
in this circuit. The LT6237 combines fast settling, high
linearity, and low offset with 1.1nV/√Hz input-referred
noise density, enabling it to achieve the full ADC data sheet
SNR and THD specifications, as shown in the FFT plots in
Figures 6b to 6e. In applications where slightly degraded
SNR performance is acceptable, it is possible to drive the
LTC2344-18 using the lower-power LT6234. The LT6234
combines fast settling, good linearity, and low offset with
1.9nV/√Hz input-referred noise density, enabling it to drive
the LTC2344-18 with 1.9dB SNR loss compared with the
LT6237 when a 24.9Ω, 1nF filter is employed. As shown in
Table 2, the LT6237 may be used without a lowpass filter
at a loss of ≤1dB SNR due to increased wideband noise.
Table 2. Recommended Amplifier and Filter Combinations for the Buffer Circuits in Figures 6a and 9. AC Performance Measured
Using Circuit in Figure 6a, ±4.096V Range for Fully Differential Input Drive, ±2.048V Range for Bipolar Input Drive
AMPLIFIER
RFILT
(Ω)
CFILT
(nF)
INPUT SIGNAL DRIVE
SNR
(dB)
THD
(dB)
SINAD
(dB)
SFDR
(dB)
½ LT6237
24.9
1
FULLY DIFFERENTIAL
95.2
−114
95.2
115
½ LT6234
24.9
1
FULLY DIFFERENTIAL
93.3
−114
93.3
115
½ LT6237
24.9
1
BIPOLAR
89.3
–110
89.3
111
½ LT6234
24.9
1
BIPOLAR
87.6
−110
87.6
111
½ LT6237
0
0
BIPOLAR
88.6
−110
88.6
111
½ LT6234
0
0
BIPOLAR
83.3
−109
83.3
111
234418f
For more information www.linear.com/LTC2344-18
23
LTC2344-18
APPLICATIONS INFORMATION
5V
ARBITRARY
FULLY
DIFFERENTIAL
5V
–
6V
AMPLIFIER
0V
5V
IN+
0V
BIPOLAR
5V
UNIPOLAR
IN–
CFILT
IN0+
IN0–
LTC2344-18
+
CFILT
–
0V
RFILT
+
AMPLIFIER
0V
OPTIONAL
LOWPASS FILTERS
REFBUF
RFILT
REFIN
0.1µF
47µF
–2V
DIFFERENTIAL INPUTS IN+/IN– WITH
WIDE INPUT COMMON MODE RANGE
ONLY CHANNEL 0 SHOWN FOR CLARITY
234418 F06a
Figure 6a. Buffering Arbitrary, Fully Differential, Bipolar, and Unipolar Signals.
See Table 2 For Recommended Amplifier and Filter Combinations
Arbitrary Drive
0
0
±4.096V RANGE
ARBITRARY DRIVE
SFDR = 118dB
SNR = 95.3dB
–40
–60
–80
–100
–120
–60
–80
–100
–120
–140
–160
–160
0
40
80
120
FREQUENCY (kHz)
160
SNR = 95.3dB
THD = –111dB
SINAD = 95.2dB
SFDR = 113dB
–40
–140
–180
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
Fully Differential Drive
–180
200
0
40
80
120
FREQUENCY (kHz)
160
234418 F06b
200
234418 F06c
Figure 6b. Two-Tone Test. IN+ = –7dBFS 2kHz Sine, IN – = –7dBFS
3.1kHz Sine, 32k Point FFT, fSMPL = 400ksps. Circuit Shown in
Figure 6a with LT6237 Amplifiers, RFILT = 24.9Ω, CFILT = 1nF
Figure 6c. IN+/IN– = –1dBFS 2kHz Fully Differential Sine, Common
Mode = 2.5V, 32k Point FFT, fSMPL = 400ksps. Circuit Shown in
Figure 6a with LT6237 Amplifiers, RFILT = 24.9Ω, CFILT = 1nF
Bipolar Drive
Unipolar Drive
0
SNR = 89.4dB
THD = –112dB
SINAD = 89.4dB
SFDR = 114dB
–40
–60
–80
–100
–120
–60
–80
–100
–120
–140
–160
–160
0
40
80
120
FREQUENCY (kHz)
160
200
SNR = 89.4dB
THD = –109dB
SINAD = 89.3dB
SFDR = 111dB
–40
–140
–180
0V TO 4.096V RANGE
UNIPOLAR DRIVE (IN– = 0V)
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
0
±2.048V RANGE
BIPOLAR DRIVE (IN– = 2.5V)
–180
0
234418 F06d
Figure 6d. IN+ = –1dBFS 2kHz Bipolar Sine, IN – = 2.5V, 32k
Point FFT, fSMPL = 400ksps. Circuit Shown in Figure 6a with
LT6237 Amplifiers, RFILT = 24.9Ω, CFILT = 1nF
24
40
80
120
FREQUENCY (kHz)
160
200
234418 F06e
Figure 6e. IN+ = –1dBFS 2kHz Unipolar Sine, IN – = 0V, 32k Point
FFT, fSMPL = 400ksps. Circuit Shown in Figure 6a with LT6237
Amplifiers, RFILT = 24.9Ω, CFILT = 1nF
For more information www.linear.com/LTC2344-18
234418f
LTC2344-18
APPLICATIONS INFORMATION
The ability of the LTC2344-18 to accept arbitrary signal
swings over a wide input common mode range with high
CMRR can simplify application solutions. Figure 7 depicts
one way of using the LTC2344-18 to digitize signals of
this type. Two channels of the LTC2344-18 simultaneously
sense the voltage on and bidirectional current through a
sense resistor over a wide common mode range. In many
applications of this type, the impedance of the external
circuitry is low enough that the ADC sampling network
can fully settle without buffering.
The common mode input range of the LTC2344-18 includes
VDD, allowing the circuit shown in Figure 8a to amplify and
measure a load current (ILOAD) from a single 5V supply.
Figure 8b shows a measured transient supply current
step of an LTC3207 LED driver load. Note the LTC6252
supplies limit the usable current sense range of this circuit
to 50mA to 450mA.
Figure 9a illustrates a more general method of amplifying
an input signal. The amplifier stage provides a differential
gain of approximately 10V/V to the desired sensor signal
while the unwanted common mode signal is attenuated
by the ADC CMRR. Figure 9b shows measured CMRR
performance of this solution, which is competitive with
the best commercially available instrumentation amplifiers.
IN0+
IN0–
VS1
IN1+
IN1–
ISENSE
RSENSE
LTC2344-18
REFBUF
VS2
REFIN
47µF
0.1µF
234418 F07
ONLY CHANNELS 0 AND 1 SHOWN FOR CLARITY
V – VS2
ISENSE = S1
RSENSE
0V ≤ VS1 ≤ 5V
0V ≤ VS2 ≤ 5V
Figure 7. Simultaneously Sense Voltage (CH0) and Current
(CH1) Over a Wide Common Mode Range
5V
2.49k
1Ω
274Ω
–
ILOAD
VDD
IN0+
IN0–
5V
+
LTC2344-18
LTC6252
REFBUF
LOAD
47µF
REFIN
0.1µF
ONLY CHANNEL 0 SHOWN FOR CLARITY
234418 F08a
Figure 8a. Sense 50mA to 450mA Current from Single 5V
Supply with Amplification
200
0V TO 4.096V RANGE
180
160
ILOAD (mA)
The two-tone test shown in Figure 6b demonstrates the
arbitrary input drive capability of the LTC2344-18. This test
simultaneously drives IN+ with a −7dBFS 2kHz single-ended
sine wave and IN− with a −7dBFS 3.1kHz single-ended sine
wave. Together, these signals sweep the analog inputs
across a wide range of common mode and differential
mode voltage combinations, similar to the more general
arbitrary input signal case. They also have a simple spectral representation. An ideal differential converter with no
common-mode sensitivity will digitize this signal as two
−7dBFS spectral tones, one at each sine wave frequency.
The FFT plot in Figure 6b demonstrates the LTC2344-18
response approaches this ideal, with 118dB of SFDR
limited by the converter's second harmonic distortion
response to the 2kHz sine wave on IN+.
140
120
100
80
0
10
20
30
40
TIME (µs)
50
60
234418 F08b
Figure 8b. Transient Supply Current Step Measured Using
Circuit in Figure 8a Loaded with LTC3207 LED Driver
234418f
For more information www.linear.com/LTC2344-18
25
LTC2344-18
APPLICATIONS INFORMATION
IN+
Buffering Single-Ended Analog Input Signals
6V
+
–
½ LT6237
LOWPASS FILTERS
2.49k
1nF
IN0+
IN0–
549Ω
2.49k
IN–
While the circuit shown in Figure 6a is capable of buffering
single-ended input signals, the circuit shown in Figure 10
is preferable when the single-ended signal reference level
is inherently low impedance and doesn't require buffering.
This circuit eliminates one driver and lowpass filter, reducing part count, power dissipation, and SNR degradation
due to driver noise. Using the recommended driver and
filter combinations in Table 2, the performance of this
circuit with single-ended input signals is on par with the
performance of the circuit in Figure 6a.
24.9Ω
LTC2344-18
1nF
24.9Ω
–
+
½ LT6237
–2V
REFBUF
REFIN
47µF
BW ~ 6.4MHz
ONLY CHANNEL 0 SHOWN FOR CLARITY
0.1µF
234418 F09a
Figure 9a. Digitize Differential Signals with High CMRR
150
ADC REFERENCE
As shown previously in Table 1b, the LTC2344-18 supports
three reference configurations. The first uses both the internal bandgap reference and reference buffer. The second
externally overdrives the internal reference but retains the
internal buffer, which isolates the external reference from
ADC conversion transients. This configuration is ideal
for sharing a single precision external reference across
multiple ADCs. The third disables the internal buffer and
overdrives the REFBUF pin externally.
±4.096V RANGE
IN+ = IN– = 5Vpp SINE
140
CMRR (dB)
130
120
110
100
90
80
10
100
1k
10k
FREQUENCY (Hz)
Internal Reference with Internal Buffer
100k
The LTC2344-18 has an on-chip, low noise, low drift
(20ppm/°C maximum), temperature compensated bandgap reference that is factory trimmed to 2.048V. The
reference output connects through a 20kΩ resistor to
234418 F09b
Figure 9b. CMRR vs Input Frequency. Circuit Shown in Figure 9a
6V
5V
UNIPOLAR
IN+
+
AMPLIFIER
–
–2V
0V
OPTIONAL
LOWPASS FILTER
RFILT
CFILT
IN0+
IN0–
LTC2344-18
IN–
REFBUF
47µF
REFIN
0.1µF
ONLY CHANNEL 0 SHOWN FOR CLARITY
234418 F10
Figure 10. Buffering Single-Ended Input Signals. See Table 2 For Recommended
Amplifier and Filter Combinations
26
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
APPLICATIONS INFORMATION
the REFIN pin, which serves as the input to the on-chip
reference buffer, as shown in Figure 11a. When employing
the internal bandgap reference, the REFIN pin should be
bypassed to GND (Pin 11) close to the pin with a 0.1μF
ceramic capacitor to filter wideband noise. The reference
buffer amplifies VREFIN to create the converter master
reference voltage VREFBUF = 2 • VREFIN on the REFBUF pin,
nominally 4.096V when using the internal bandgap reference. Bypass REFBUF to GND (Pin 11) close to the pin with
at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or
X5R, 10V, 0805 size) to compensate the reference buffer,
absorb transient conversion currents, and minimize noise.
LTC2344-18
20k
REFIN
0.1µF
REFBUF
47µF
BANDGAP
REFERENCE
REFERENCE
BUFFER
6.5k
External Reference with Internal Buffer
If more accuracy and/or lower drift is desired, REFIN can
be easily overdriven by an external reference since 20kΩ
of resistance separates the internal bandgap reference
output from the REFIN pin, as shown in Figure 11b. The
valid range of external reference voltage overdrive on the
REFIN pin is 1.25V to 2.2V, resulting in converter master reference voltages VREFBUF between 2.5V and 4.4V,
respectively. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power, and high
accuracy, the LTC6655-2.048 is well suited for use with the
LTC2344-18 when overdriving the internal reference. The
LTC6655-2.048 offers 0.025% (maximum) initial accuracy
and 2ppm/°C (maximum) temperature coefficient for high
precision applications. The LTC6655-2.048 is fully specified over the H-grade temperature range, complementing
the extended temperature range of the LTC2344-18 up to
125°C. Bypassing the LTC6655-2.048 with a 2.7µF to 100µF
ceramic capacitor close to the REFIN pin is recommended.
6.5k
External Reference with Disabled Internal Buffer
GND
234418 F11a
Figure 11a. Internal Reference with Internal Buffer Configuration
The internal reference buffer supports VREFBUF = 4.4V
maximum. By grounding REFIN, the internal buffer may
be disabled allowing REFBUF to be overdriven with an
external reference voltage between 2.5V and 5V, as shown
LTC2344-18
20k
REFIN
2.7µF
REFBUF
LTC6655-2.048
47µF
BANDGAP
REFERENCE
REFERENCE
BUFFER
6.5k
6.5k
GND
234418 F11b
Figure 11b. External Reference with Internal Buffer Configuration
234418f
For more information www.linear.com/LTC2344-18
27
LTC2344-18
APPLICATIONS INFORMATION
LTC2344-18
20k
REFIN
REFBUF
LTC6655-5
BANDGAP
REFERENCE
REFERENCE
BUFFER
6.5k
47µF
6.5k
GND
234418 F11c
Figure 11c. External Reference with Disabled Internal
Buffer Configuration
in Figure 11c. Maximum input signal swing and SNR are
achieved by overdriving REFBUF using an external 5V
reference. The buffer feedback resistors load the REFBUF
pin with 13kΩ even when the reference buffer is disabled.
The LTC6655-5 offers the same small size, accuracy, drift,
and extended temperature range as the LTC6655-2.048,
and achieves a typical SNR of 96.5dB when paired with
the LTC2344-18. Bypass the LTC6655-5 to GND (Pin 11)
close to the REFBUF pin with at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or X5R, 10V, 0805 size) to
absorb transient conversion currents and minimize noise.
The LTC2344-18 converter draws a charge (QCONV) from
the REFBUF pin during each conversion cycle. On short
time scales most of this charge is supplied by the external
REFBUF bypass capacitor, but on longer time scales all of
the charge is supplied by either the reference buffer, or
when the internal reference buffer is disabled, the external
reference. This charge draw corresponds to a DC current
equivalent of IREFBUF = QCONV • fSMPL, which is proportional
to sample rate. In applications where a burst of samples
is taken after idling for long periods of time, as shown in
Figure 12, IREFBUF quickly transitions from approximately
0.4mA to 1.5mA (VREFBUF = 5V, fSMPL = 400kHz). This
current step triggers a transient response in the external
reference that must be considered, since any deviation
in VREFBUF affects converter accuracy. If an external
reference is used to overdrive REFBUF, the fast settling
LTC6655 family of references is recommended.
Internal Reference Buffer Transient Response
For optimum performance in applications employing burst
sampling, the external reference with internal reference
buffer configuration should be used. The internal reference
buffer incorporates a proprietary design that minimizes
movements in VREFBUF when responding to a burst of
CNV
IDLE
PERIOD
IDLE
PERIOD
234418 F12
Figure 12. CNV Waveform Showing Burst Sampling
28
234418f
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LTC2344-18
APPLICATIONS INFORMATION
DEVIATION FROM FINAL VALUE (LSB)
20
±4.096V SOFTSPAN
IN+ = 4V
IN– = 0V
15
to frequencies below half the sampling frequency, excluding DC. Figure 14 shows that the LTC2344-18 achieves a
typical SINAD of 95.2dB in the ±4.096V range at a 400kHz
sampling rate with a fully differential 2kHz input signal.
0
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–20
SNR = 95.3dB
THD = –112dB
SINAD = 95.2dB
SFDR = 114dB
–40
AMPLITUDE (dBFS)
conversions following an idle period. Figure 13 compares
the burst conversion response of the LTC2344-18 with an
input near full scale for two reference configurations. The
first configuration employs the internal reference buffer
with REFIN externally overdriven by an LTC6655-2.048,
while the second configuration disables the internal reference buffer and overdrives REFBUF with an external
LTC6655-4.096. In both cases REFBUF is bypassed to
GND with a 47µF ceramic capacitor.
–60
–80
–100
–120
–140
–160
10
EXTERNAL REFERENCE ON REFBUF
–180
0
5
40
80
120
FREQUENCY (kHz)
160
200
234418 F14
Figure 14. 32k Point FFT fSMPL = 400ksps, fIN = 2kHz
0
INTERNAL REFERENCE BUFFER
–5
0
100
200
300
TIME (µs)
400
500
234418 F13
Figure 13. Burst Conversion Response of the LTC2344-18,
fSMPL = 400ksps
DYNAMIC PERFORMANCE
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion, and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2344-18 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 14 shows
that the LTC2344-18 achieves a typical SNR of 95.3dB in
the ±4.096V range at a 400kHz sampling rate with a fully
differential 2kHz input signal.
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
THD = 20log
V22 + V32 + V42 ...VN2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through Nth harmonics, respectively. Figure 14 shows
234418f
For more information www.linear.com/LTC2344-18
29
LTC2344-18
APPLICATIONS INFORMATION
that the LTC2344-18 achieves a typical THD of –112dB
(N = 6) in the ±4.096V range at a 400kHz sampling rate
with a fully differential 2kHz input signal.
POWER CONSIDERATIONS
The LTC2344-18 provides two power supply pins: the 5V
core power supply (VDD) and the digital input/output (I/O)
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2344-18 to communicate with CMOS logic
operating between 1.8V and 5V, including 2.5V and 3.3V
systems. When using LVDS I/O mode, the range of OVDD
is 2.375V to 5.25V.
Power Supply Sequencing
The LTC2344-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2344-18 has
an internal power-on-reset (POR) circuit which resets the
converter on initial power-up and whenever VDD drops
below 2V. Once the supply voltage re-enters the nominal
supply voltage range, the POR reinitializes the ADC. No
conversions should be initiated until at least 10ms after
a POR event to ensure the initialization period has ended.
When employing the internal reference buffer, allow 200ms
for the buffer to power up and recharge the REFBUF bypass
capacitor. Any conversion initiated before these times will
produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2344-18 sampling and conversion is controlled by
CNV. A rising edge on CNV transitions all channels’ S/H
circuits from track mode to hold mode, simultaneously
sampling the input signals on all channels and initiating
a conversion. Once a conversion has been started, it
cannot be terminated early except by resetting the ADC,
as discussed in the Reset Timing section. For optimum
performance, drive CNV with a clean, low jitter signal and
30
avoid transitions on data I/O lines leading up to the rising
edge of CNV. Additionally, to minimize channel-to-channel
crosstalk, avoid high slew rates on the analog inputs for
100ns before and after the rising edge of CNV. Converter
status is indicated by the BUSY output, which transitions
low-to-high at the start of each conversion and stays high
until the conversion is complete. Once CNV is brought high
to begin a conversion, it should be returned low between
40ns and 60ns later or after the falling edge of BUSY to
minimize external disturbances during the internal conversion process. If CNV is returned low after the falling edge
of BUSY, it should be held low for at least 390ns before
bringing it high again, since the converter acquisition
time (tACQ) is set by the CNV low time (tCNVL) in this case.
Internal Conversion Clock
The LTC2344-18 has an internal clock that is trimmed to
achieve a maximum conversion time of 525 • N – 20ns
with N channels enabled. With a minimum acquisition time
of 390ns when converting four channels simultaneously,
throughput performance of 400ksps is guaranteed without
any external adjustments.
Power Down Mode
When PD is brought high, the LTC2344-18 is powered
down and subsequent conversion requests are ignored. If
this occurs during a conversion, the device powers down
once the conversion completes. In this mode, the device
draws only a small regulator standby current resulting in a
typical power dissipation of 0.33mW. To exit power down
mode, bring the PD pin low and wait at least 10ms before
initiating a conversion. When employing the internal reference buffer, allow 200ms for the buffer to power up and
recharge the REFBUF bypass capacitor. Any conversion
initiated before these times will produce invalid results.
Reset Timing
A global reset of the LTC2344-18, equivalent to a poweron-reset event, may be executed without needing to cycle
the supplies. This feature is useful when recovering from
system-level events that require the state of the entire sys-
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
APPLICATIONS INFORMATION
tem to be reset to a known synchronized value. To initiate
a global reset, bring PD high twice without an intervening
conversion, as shown in Figure 15. The reset event is triggered on the second rising edge of PD, and asynchronously
ends based on an internal timer. Reset clears all serial data
output registers and restores the internal SoftSpan configuration register default state of all channels in SoftSpan 7.
If reset is triggered during a conversion, the conversion
is immediately halted. The normal power down behavior
associated with PD going high is not affected by reset. Once
PD is brought low, wait at least 10ms before initiating a
conversion. When employing the internal reference buffer,
allow 200ms for the buffer to power up and recharge the
REFBUF bypass capacitor. Any conversion initiated before
these times will produce invalid results.
18
SUPPLY CURRENT (mA)
16
14
IVDD
12
10
8
6
4
IOVDD
2
0
0
100
200
300
SAMPLING FREQUENCY (kHz)
400
234418 F16
Figure 16. Power Dissipation of the LTC2344-18
Decreases with Decreasing Sampling Frequency
Auto Nap Mode
DIGITAL INTERFACE
The LTC2344-18 automatically enters nap mode after a
conversion has finished and completely powers up once a
new conversion is initiated on the rising edge of CNV. Auto
nap mode causes the power dissipation of the LTC234418 to decrease as the sampling frequency is reduced,
as shown in Figure 16. This decrease in average power
dissipation occurs because a portion of the LTC2344-18
circuitry is turned off during nap mode, and the fraction
of the conversion cycle (tCYC) spent napping increases as
the sampling frequency (fSMPL) is decreased.
The LTC2344-18 features CMOS and LVDS serial interfaces,
selectable using the LVDS/CMOS pin. The flexible OVDD
supply allows the LTC2344-18 to communicate with any
CMOS logic operating between 1.8V and 5V, including
2.5V and 3.3V systems, while the LVDS interface supports
low noise digital designs. In CMOS mode, applications
may employ between one and four lanes of serial data
output, allowing the user to optimize bus width and data
tPDH
t WAKE
PD
CNV
BUSY
RESET
tPDL
tCNVH
tCONV
SECOND RISING EDGE OF
PD TRIGGERS RESET
RESET TIME
SET INTERNALLY
234418 F15
Figure 15. Reset Timing for the LTC2344-18
234418f
For more information www.linear.com/LTC2344-18
31
LTC2344-18
APPLICATIONS INFORMATION
CS = PD = 0
SAMPLE N
tCNVL
CNV
tCONV
BUSY
tACQ
tBUSYLH
RECOMMENDED DATA TRANSACTION WINDOW
tSCKI
tSCKIH
SCKI
SDI
SAMPLE N + 1
tCYC
tCNVH
1
S11
DON’T CARE
2
3
4 5
tSCKIL
6
7
tQUIET
tSSDISCKI
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tHSDISCKI
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
SOFTSPAN CONFIGURATION WORD FOR CONVERSION N + 1
tHSDOSCKI
tDSDOBUSYL
tSKEW
SCKO
tDSDOSCKI
SDO0
DON’T CARE
D17
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONVERSION RESULT
CHAN ID SOFTSPAN
CONVERSION RESULT
CHANNEL 0
24-BIT PACKET
CONVERSION N
• • •
SDO3
0 C1 C0 SS2 SS1 SS0 D17
DON’T CARE
D17
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONVERSION RESULT
CHANNEL 3
24-BIT PACKET
CONVERSION N
CHANNEL 1
24-BIT PACKET
CONVERSION N
0 C1 C0 SS2 SS1 SS0 D17
CHAN ID SOFTSPAN
CONVERSION RESULT
CHANNEL 0
24-BIT PACKET
CONVERSION N
234418 TD01
Figure 17. Serial CMOS I/O Mode
throughput. Together, these I/O interface options enable
the LTC2344-18 to communicate equally well with legacy
microcontrollers and modern FPGAs.
Serial CMOS I/O Mode
As shown in Figure 17, in CMOS I/O mode the serial data
bus consists of a serial clock input, SCKI, serial data
input, SDI, serial clock output, SCKO, and four lanes of
serial data output, SDO0 to SDO3. Communication with
the LTC2344-18 across this bus occurs during predefined
data transaction windows. Within a window, the device
accepts 12-bit SoftSpan configuration words for the next
conversion on SDI and outputs 24-bit packets containing
conversion results and channel configuration information
from the previous conversion on SDO0 to SDO3. New
data transaction windows open 10ms after powering up
or resetting the LTC2344-18, and at the end of each conversion on the falling edge of BUSY. In the recommended
32
use case, the data transaction should be completed with
a minimum tQUIET time of 20ns prior to the start of the
next conversion, as shown in Figure 17. New SoftSpan
configuration words are only accepted within this recommended data transaction window, but SoftSpan changes
take effect immediately with no additional analog input
settling time required before starting the next conversion.
It is still possible to read conversion data after starting the
next conversion, but this will degrade conversion accuracy
and therefore is not recommended.
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SCKO is forced low and
SDO0 to SDO3 are updated with the latest conversion
results from analog input channels 0 to 3, respectively.
Rising edges on SCKI serially clock conversion results
and analog input channel configuration information out
on SDO0 to SDO3 and trigger transitions on SCKO that are
skew-matched to the data on SDO0 to SDO3. The resulting
234418f
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LTC2344-18
APPLICATIONS INFORMATION
SCKO frequency is half that of SCKI. SCKI rising edges
also latch SoftSpan configuration words provided on SDI,
which are used to program the internal 12-bit SoftSpan
configuration register. See the section Programming the
SoftSpan Configuration Register in CMOS I/O Mode for
further details. SCKI is allowed to idle either high or low
in CMOS I/O mode. As shown in Figure 18, the CMOS
bus is enabled when CS is low and is disabled and Hi-Z
when CS is high, allowing the bus to be shared across
multiple devices.
The data on SDO0 to SDO3 are grouped into 24-bit packets
consisting of an 18-bit conversion result, followed by a zero,
2-bit analog channel ID, and 3-bit SoftSpan code, all presented MSB first. As suggested in Figures 17 and 18, each
SDO lane outputs these packets for all analog input channels in a sequential, circular manner. For example, the first
24-bit packet output on SDO0 corresponds to analog input
channel 0, followed by the packets for channels 1, 2 and 3.
The data output on SDO0 then wraps back to channel
0, and this pattern repeats indefinitely. Other SDO lanes
follow a similar circular pattern, except the first packet
presented on each lane corresponds to its associated
analog input channel.
When interfacing the LTC2344-18 with a standard SPI
bus, capture output data at the receiver on rising edges of
SCKI. SCKO is not used in this case. Multiple SDO lanes
are also usually not useful in this case. In other applications, such as interfacing the LTC2344-18 with an FPGA
or CPLD, rising and falling edges of SCKO may be used
to capture serial output data on SDO0 to SDO3 in double
data rate (DDR) fashion. Capturing data using SCKO adds
robustness to delay variations over temperature and supply.
Full Four Lane Serial CMOS Output Data Capture
As shown in Table 3, full 400ksps per channel throughput
can be achieved with a 65MHz SCKI frequency by capturing
the first packet (24 SCKI cycles total) from all four serial
data output lanes SDO0 to SDO3. This configuration also
allows conversion results from all channels to be captured
using as few as 18 SCKI cycles if the 2-bit analog channel
ID and 3-bit SoftSpan code are not needed. Multi-lane data
capture is usually best suited for use with FPGA or CPLD
capture hardware, but may be useful in other applicationspecific cases.
Fewer Than Four Lane Serial CMOS Output Data Capture
Applications that cannot accommodate the full four
lanes of serial data capture may employ fewer lanes
without reconfiguring the LTC2344-18. For example,
capturing the first two packets (48 SCKI cycles total)
from SDO0 and SDO2 provides data for analog input
channels 0 and 1, and 2 and 3, respectively, using two
PD = 0
BUSY
CS
SCKI DON’T CARE
DON’T CARE
NEW SoftSpan CONFIGURATION WORD
(OVERWRITES INTERNAL CONFIG REGISTER)
SDI DON’T CARE
SCKO
SDO3
DON’T CARE
Hi-Z
Hi-Z
Hi-Z
CHANNEL 0 PACKET
CHANNEL 1 PACKET
CHANNEL 2 PACKET
CHANNEL 3 PACKET
(PARTIAL)
tEN
• • •
SDO0
FIVE ALL-ZERO WORDS AND ONE PARTIAL WORD
(INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)
Hi-Z
Hi-Z
t DIS
CHANNEL 3 PACKET
CHANNEL 0 PACKET
CHANNEL 1 PACKET
CHANNEL 2 PACKET
(PARTIAL)
Hi-Z
234418 F18
Figure 18. Internal SoftSpan Configuration Register Behavior. Serial CMOS Bus Response to CS
234418f
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33
LTC2344-18
APPLICATIONS INFORMATION
output lanes. If only one lane can be accommodated,
capturing the first four packets (96 SCKI cycles total)
from SDO0 provides data for all analog input channels.
As shown in Table 3, full 400ksps per channel throughput
can be achieved with a 65MHz SCKI frequency in the four
lane case, but the maximum CMOS SCKI frequency of
100MHz limits the throughput to less than 400ksps per
channel in the two lane and one lane cases. Finally, note
that in choosing the number of lanes and which lanes
to use for data capture, the user is not restricted to the
specific cases mentioned above. Other choices may be
more optimal in particular applications.
Programming the SoftSpan Configuration Register in
CMOS I/O Mode
The internal 12-bit SoftSpan configuration register controls the SoftSpan range for all analog input channels of
the LTC2344-18. The default state of this register after
power-up or resetting the device is all ones, configuring
each channel to convert in SoftSpan 7, the ± VREFBUF range
(see Table 1a). The state of this register may be modified
by providing a new 12-bit SoftSpan configuration word on
SDI during the data transaction window shown in Figure
17. New SoftSpan configuration words are only accepted
within this recommended data transaction window, but
SoftSpan changes take effect immediately with no additional analog input settling time required before starting
the next conversion. Setting a channel’s SoftSpan code to
SS[2:0] = 000 immediately disables the channel, resulting
in a corresponding reduction in tCONV on the next conver-
sion. Similarly, enabling a previously disabled channel
requires no additional analog input settling time before
starting the next conversion. The mapping between the
serial SoftSpan configuration word, the internal SoftSpan
configuration register, and each channel’s 3-bit SoftSpan
code is illustrated in Figure 19.
If fewer than 12 SCKI rising edges are provided during a
data transaction window, the partial word received on SDI
will be ignored and the SoftSpan configuration register will
not be updated. If exactly 12 SCKI rising edges are provided,
the SoftSpan configuration register will be updated to
match the received SoftSpan configuration word, S[11:0].
The one exception to this behavior occurs when S[11:0] is
all zeros. In this case, the SoftSpan configuration register
will not be updated, allowing applications to retain the
current SoftSpan configuration state by idling SDI low. If
more than 12 SCKI rising edges are provided during a data
transaction window, each complete 12-bit word received
on SDI will be interpreted as a new SoftSpan configuration
word and applied to the SoftSpan configuration register
as described above. Any partial words are ignored.
Typically, applications will update the SoftSpan configuration register in the manner shown in Figures 17 and 18.
After the opening of a new data transaction window at the
falling edge of BUSY, the user supplies a 12-bit SoftSpan
configuration word on SDI during the first 12 SCKI cycles.
This new word overwrites the internal configuration
register contents following the 12th SCKI rising edge.
The user then holds SDI low for the remainder of the
Table 3. Required SCKI Frequency to Achieve Various Throughputs in Common Output Bus Configurations with Four Channels
Enabled. Shaded Entries Denote Throughputs That Are Not Achievable In a Given Configuration. Calculated Using fSCKI = (Number of
SCKI Cycles)/(tACQ,MIN – tQUIET)
I/O MODE
CMOS
LVDS
34
REQUIRED fSCKI (MHz) TO ACHIEVE THROUGHPUT OF
200ksps/CHANNEL
100ksps/CHANNEL
400ksps/CHANNEL
(tACQ = 2890ns)
(tACQ = 7890ns)
(tACQ = 390ns)
NUMBER OF SDO
LANES
NUMBER OF SCKI
CYCLES
4
18
50
7
3
4
24
65
9
4
2
48
Not Achievable
17
7
1
96
Not Achievable
34
13
1
48
130 (260Mbps)
17 (34Mbps)
7 (14Mbps)
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
APPLICATIONS INFORMATION
CMOS I/O MODE
tSCKIH
tSCKI
SCKI
1
SDI
DON’T CARE
2
S11
3
S10
4
S9
5
S8
6
S7
S6
tSSDISCKI
tSCKIL
7
8
S5
9
S4
S3
10
S2
11
12
tHSDISCKI
S1
S0
SoftSpan CONFIGURATION WORD
LVDS I/O MODE
tSCKI
SCKI
(LVDS)
1
2
tSCKIH
tSCKIL
3
4
tSSDISCKI
5
6
7
8
9
10
tSSDISCKI
SDI
(LVDS)
DON’T CARE
S11
S10
S9
S8
S7
11
12
tHSDISCKI
S6
S5
S4
S3
S2
S1
S0
SoftSpan CONFIGURATION WORD
INTERNAL 12-BIT SoftSpan CONFIGURATION REGISTER
(SAME FOR CMOS AND LVDS)
11
10
9
CHANNEL 3 SoftSpan
CODE SS[2:0]
8
7
6
CHANNEL 2 SoftSpan
CODE SS[2:0]
5
4
3
2
CHANNEL 1 SoftSpan
CODE SS[2:0]
1
0
CHANNEL 0 SoftSpan
CODE SS[2:0]
234418 F19
Figure 19. Mapping Between Serial SoftSpan Configuration Word, Internal SoftSpan
Configuration Register, and SoftSpan Code for Each Analog Input Channel
data transaction window causing the register to retain
its contents regardless of the number of additional SCKI
cycles applied. SoftSpan settings may be retained across
multiple conversions by holding SDI low for the entire
data transaction window, regardless of the number of
SCKI cycles applied.
Serial LVDS I/O Mode
In LVDS I/O mode, information is transmitted using positive and negative signal pairs (LVDS+/LVDS−) with bits
differentially encoded as (LVDS+ − LVDS−). These signals
are typically routed using differential transmission lines
with 100Ω characteristic impedance. Logical 1s and 0s
are nominally represented by differential +350mV and
−350mV, respectively. For clarity, all LVDS timing diagrams
and interface discussions adopt the logical rather than
physical convention.
As shown in Figure 20, in LVDS I/O mode the serial data
bus consists of a serial clock differential input, SCKI, serial
data differential input, SDI, serial clock differential output,
SCKO, and serial data differential output, SDO. Communication with the LTC2344-18 across this bus occurs during
predefined data transaction windows. Within a window,
the device accepts 12-bit SoftSpan configuration words
for the next conversion on SDI and outputs 24-bit packets
containing conversion results and channel configuration
information from the previous conversion on SDO. New
data transaction windows open 10ms after powering up
or resetting the LTC2344-18, and at the end of each conversion on the falling edge of BUSY. In the recommended
use case, the data transaction should be completed with
a minimum tQUIET time of 20ns prior to the start of the
next conversion, as shown in Figure 20. New SoftSpan
configuration words are only accepted within this recommended data transaction window, but SoftSpan changes
take effect immediately with no additional analog input
234418f
For more information www.linear.com/LTC2344-18
35
LTC2344-18
APPLICATIONS INFORMATION
CS = PD = 0
SAMPLE N + 1
SAMPLE N
t CYC
tCNVH
CNV
(CMOS)
BUSY
(CMOS)
t CNVL
tCONV
t ACQ
tBUSYLH
RECOMMENDED DATA TRANSACTION WINDOW
t SCKI
SCKI
(LVDS)
SDI
(LVDS)
1
DON’T CARE
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 89 90 91 92 93 94 95 96
t SSDISCKI
t SSDISCKI
t HSDISCKI
t SCKIL
S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
t DSDOBUSYL
SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1
t HSDOSCKI
SCKO
(LVDS)
SDO
(LVDS)
2
t HSDISCKI
tQUIET
t SCKIH
t SKEW
t DSDOSCKI
DON’T CARE
D17
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONVERSION RESULT
0 C1 C0 SS2 SS1 SS0 D17 D16 D15 D0 0 C1 C0 SS2 SS1 SS0 D17
CHAN ID SoftSpan
CHANNEL 0
24-BIT PACKET
CONVERSION N
CHANNEL 1
24-BIT PACKET
CONVERSION N
CHAN ID SoftSpan
CHANNEL 3
24-BIT PACKET
CONVERSION N
CONVERSION
RESULT
CHANNEL 0
24-BIT PACKET
CONVERSION N
234418 F20
Figure 20. Serial LVDS I/O Mode
settling time required before starting the next conversion.
It is still possible to read conversion data after starting the
next conversion, but this will degrade conversion accuracy
and therefore is not recommended.
Just prior to the falling edge of BUSY and the opening
of a new data transaction window, SDO is updated with
the latest conversion results from analog input channel
0. Both rising and falling edges on SCKI serially clock
conversion results and analog input channel configuration
information out on SDO. SCKI is also echoed on SCKO,
skew-matched to the data on SDO. Whenever possible, it
is recommended that rising and falling edges of SCKO be
used to capture DDR serial output data on SDO, as this will
yield the best robustness to delay variations over supply
and temperature. SCKI rising and falling edges also latch
SoftSpan configuration words provided on SDI, which are
used to program the internal 12-bit SoftSpan configuration register. See the section Programming the SoftSpan
Configuration Register in LVDS I/O Mode for further
details. As shown in Figure 21, the LVDS bus is enabled
36
when CS is low and is disabled and Hi-Z when CS is high,
allowing the bus to be shared across multiple devices.
Due to the high speeds involved in LVDS signaling, LVDS
bus sharing must be carefully considered. Transmission
line limitations imposed by the shared bus may limit the
maximum achievable bus clock speed. LVDS inputs are
internally terminated with a 100Ω differential resistor when
CS is low, while outputs must be differentially terminated
with a 100Ω resistor at the receiver (FPGA). SCKI must
idle in the low state in LVDS I/O mode, including when
transitioning CS.
The data on SDO are grouped into 24-bit packets consisting
of an 18-bit conversion result, followed by a zero, 2-bit
analog channel ID and 3-bit SoftSpan code, all presented
MSB first. As suggested in Figures 20 and 21, SDO outputs
these packets for all analog input channels in a sequential,
circular manner. For example, the first 24-bit packet output
on SDO corresponds to analog input channel 0, followed
by the packets for channels 1, 2 and 3. The data output
on SDO then wraps back to channel 0, and this pattern
repeats indefinitely.
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
APPLICATIONS INFORMATION
Serial LVDS Output Data Capture
As shown in Table 3, full 400ksps per channel throughput
can be achieved with a 130MHz SCKI frequency by capturing four packets (48 SCKI cycles total) of DDR data from
SDO. The LTC2344-18 supports LVDS SCKI frequencies
up to 250MHz.
Programming the SoftSpan Configuration Register in
LVDS I/O Mode
The internal 12-bit SoftSpan configuration register controls the SoftSpan range for all analog input channels of
the LTC2344-18. The default state of this register after
power-up or resetting the device is all ones, configuring
each channel to convert in SoftSpan 7, the ± VREFBUF range
(see Table 1a). The state of this register may be modified
by providing a new 12-bit SoftSpan configuration word on
SDI during the data transaction window shown in Figure
20. New SoftSpan configuration words are only accepted
within this recommended data transaction window, but
SoftSpan changes take effect immediately with no additional analog input settling time required before starting
the next conversion. Setting a channel’s SoftSpan code to
SS[2:0] = 000 immediately disables the channel, resulting
in a corresponding reduction in tCONV on the next conversion. Similarly, enabling a previously disabled channel
requires no additional analog input settling time before
starting the next conversion. The mapping between the
serial SoftSpan configuration word, the internal SoftSpan
configuration register, and each channel’s 3-bit SoftSpan
code is illustrated in Figure 19.
If fewer than 12 SCKI edges (rising plus falling) are
provided during a data transaction window, the partial
word received on SDI will be ignored and the SoftSpan
configuration register will not be updated. If exactly 12
SCKI edges are provided, the SoftSpan configuration
register will be updated to match the received SoftSpan
configuration word, S[11:0]. The one exception to this
behavior occurs when S[11:0] is all zeros. In this case,
the SoftSpan configuration register will not be updated,
allowing applications to retain the current SoftSpan configuration state by idling SDI low. If more than 12 SCKI
edges are provided during a data transaction window, each
complete 12-bit word received on SDI will be interpreted
as a new SoftSpan configuration word and applied to the
SoftSpan configuration register as described above. Any
partial words are ignored.
Typically, applications will update the SoftSpan configuration register in the manner shown in Figures 20 and 21.
After the opening of a new data transaction window at
the falling edge of BUSY, the user supplies a 12-bit DDR
SoftSpan configuration word on SDI during the first 12
SCKI cycles. This new word overwrites the internal configuration register contents following the 6th SCKI falling
edge. The user then holds SDI low for the remainder of
the data transaction window causing the register to retain
its contents regardless of the number of additional SCKI
cycles applied. SoftSpan settings may be retained across
multiple conversions by holding SDI low for the entire
data transaction window, regardless of the number of
SCKI cycles applied.
PD = 0
BUSY
(CMOS)
CS
(CMOS)
tEN
tDIS
SCKI
DON’T CARE
(LVDS)
SDI
DON’T CARE
(LVDS)
SCKO
(LVDS)
SDO
(LVDS)
DON’T CARE
NEW SoftSpan CONFIGURATION WORD
(OVERWRITES INTERNAL CONFIG REGISTER)
FIVE ALL-ZERO WORDS AND ONE PARTIAL WORD
(INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)
DON’T CARE
Hi-Z
Hi-Z
Hi-Z
CHANNEL 0 PACKET
CHANNEL 1 PACKET
CHANNEL 2 PACKET
CHANNEL 3 PACKET
(PARTIAL)
Hi-Z
234418 F21
Figure 21. Internal SoftSpan Configuration Register Behavior. Serial LVDS Bus Response to CS
234418f
For more information www.linear.com/LTC2344-18
37
LTC2344-18
BOARD LAYOUT
To obtain the best performance from the LTC2344-18, a
four-layer printed circuit board (PCB) is recommended.
Layout for the PCB should ensure the digital and analog
signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
Also minimize the length of the REFBUF to GND (Pin 11)
bypass capacitor return loop, and avoid routing CNV near
signals which could potentially disturb its rising edge.
38
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Reference Design
For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer
to DC2520, the evaluation kit for the LTC2344-18.
234418f
For more information www.linear.com/LTC2344-18
LTC2344-18
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2344-18#packaging for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ±0.05
3.45 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
31 32
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ±0.10
3.45 ±0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
234418f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
www.linear.com/LTC2344-18
39
LTC2344-18
TYPICAL APPLICATION
Sense Current from Rail with Amplification
5V
2.49k
1Ω
274Ω
–
+
ILOAD
VDD
IN0+
IN0–
5V
LTC2344-18
LTC6252
REFBUF
LOAD
REFIN
47µF
0.1µF
ONLY CHANNEL 0 SHOWN FOR CLARITY
234418 TA02
RELATED PARTS
PART NUMBER
ADCs
LTC2345-18/LTC2345-16
DESCRIPTION
COMMENTS
18-Bit/16-Bit, 200ksps, 8-Channel Simultaneous
Sampling, ±5/±1.25LSB INL, Serial ADC
LTC2348-18/LTC2348-16 18-/16-Bit, 200ksps, 8-Channel Simultaneous
Sampling, ±3/±1LSB INL, Serial ADC
LTC2335-18/LTC2335-16 18-Bit/16-Bit, 1Msps, 8-Channel Multiplexed,
±3/±1LSB INL, Serial ADC
LTC2378-20/LTC2377-20/ 20-Bit, 1Msps/500ksps/250ksps,
LTC2376-20
±0.5ppm INL Serial, Low Power ADC
LTC2338-18/LTC2337-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial,
LTC2336-18
Low Power ADC
LTC2328-18/LTC2327-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial,
LTC2326-18
Low Power ADC
LTC2373-18/LTC2372-18 18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC
5V Supply, SoftSpan Inputs with Wide Common Mode Range, 92/91dB
SNR, Serial CMOS and LVDS I/O, 7mm × 7mm QFN-48 Package
±10.24V SoftSpan Inputs with Wide Common Mode Range, 97/94dB SNR,
Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
±10.24V SoftSpan Inputs with Wide Common Mode Range, 97/94dB SNR,
Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
2.5V Supply, ±5V Fully Differential Input, 104dB SNR, MSOP-16 and
4mm × 3mm DFN-16 Packages
5V Supply, ±10.24V Fully Differential Input, 100dB SNR, MSOP-16 Package
5V Supply, ±10.24V Pseudo-Differential Input, 95dB SNR,
MSOP-16 Package
5V Supply, 8 Channel Multiplexed, Configurable Input Range, 100dB SNR,
DGC, 5mm × 5mm QFN-32 Package
LTC2379-18/LTC2378-18/ 18-Bit,1.6Msps/1Msps/500ksps/250ksps, Serial, 2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC, Pin
LTC2377-18/LTC2376-18 Low Power ADC
Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps, Serial, 2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC, Pin
Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2377-16/LTC2376-16 Low Power ADC
LTC2389-18/LTC2389-16 18-Bit/16-Bit, 2.5Msps, Parallel/Serial ADC
5V Supply, Pin-Configurable Input Range, 99.8dB/96dB SNR, Parallel or
Serial I/O 7mm × 7mm LQFP-48 and QFN-48 Packages
LTC2173-14/LTC2174-14/ 14-Bit, 80Msps/105Msps/125Msps 1.8V Quad
376mW/450mW/558mW, 73.1dB SNR, 88dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
LTC2175-14
ADC, Ultralow Power
LTC1859/LTC1858/
16-/14-/12-Bit, 8-Channel, 100ksps, Serial ADC ±10V, SoftSpan, Single-Ended or Differential Inputs, Single 5V Supply,
LTC1857
SSOP-28 Package
LTC1609
16-Bit, 200ksps Serial ADC
±10V, Configurable Unipolar/Bipolar Input, SSOP-28 and SO-20 Packages
LTC1606/LTC1605
16-Bit, 250ksps/100ksps, Parallel ADC
±10V Input, 5V Supply, 75mW/55mW, SSOP-28 and SO-28 Packages
DACs
±1LSB INL/DNL, Software-Selectable Ranges, SSOP-28/7mm × 7mm
LTC2756/LTC2757
18-Bit, Serial/Parallel IOUT SoftSpan DAC
LQFP-48 Package
LTC2668
16-Channel 16-/12-Bit ±10V VOUT SoftSpan DACs ±4LSB INL, Precision Reference 10ppm/°C Max, 6mm × 6mm QFN-40 Package
References
LTC6657
Low Drift Low Noise Buffered Reference
5V/3V/2.5V, 1.5ppm/°C, 0.5ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6655
Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6652
Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
Amplifiers
LT6236/LT6237/LT6238 Single/Dual/Quad Operational Amplifier with
215MHz, 3.5mA/Amplifier, 1.1nV/√Hz
Low Wideband Noise
LT6233/LT6234/LT6235 Single/Dual/Quad Low Noise Rail-to-Rail Output 60MHz,1.2mA,1.2nV/√Hz,15V/μs,0.5mV
Op Amps
720MHz, 3.5mA Power Efficient Rail-to-Rail I/O 720MHz GBW, Unity Gain Stable, Low Noise
LTC6252/LTC6253/
LTC6254
Op Amp
40 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2344-18
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2344-18
234418f
LT 0816 • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2016