LTC2355IMSE-14#PBF

LTC2355-12/LTC2355-14 Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown FEATURES n n n n n n n n n n n DESCRIPTION 3.5Msps Conversion Rate 74.2dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits Low Power Dissipation: 18mW 3.3V Single Supply Operation 2.5V Internal Bandgap Reference can be Overdriven 3-Wire SPI-Compatible Serial Interface Sleep (13µW) Shutdown Mode Nap (4mW) Shutdown Mode 80dB Common Mode Rejection 0V to 2.5V Unipolar Input Range Tiny 10-Lead MSOP Package The LTC®2355-12/LTC2355-14 are 12-bit/14-bit, 3.5Msps serial ADCs with differential inputs. The devices draw only 5.5mA from a single 3.3V supply and come in a tiny 10-lead MSOP package. A Sleep shutdown feature further reduces power consumption to 13µW. The combination of speed, low power and tiny package makes the LTC2355-12/LTC2355-14 suitable for high speed, portable applications. The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The devices convert 0V to 2.5V unipolar inputs differentially. The absolute voltage swing for AIN+ and AIN– extends from ground to the supply voltage. APPLICATIONS Communications Data Acquisition Systems n Uninterrupted Power Supplies n Multiphase Motor Control n Multiplexed Data Acquisition n RFID n n L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. The serial interface sends out the conversion results during the 16 clock cycles following a CONV rising edge for compatibility with standard serial interfaces. If two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 3.5Msps can be achieved with a 63MHz clock. BLOCK DIAGRAM THD, 2nd, 3rd and SFDR vs Input Frequency 10µF 3.3V 1 + 14-BIT ADC S&H AIN– 2 – –56 THREESTATE SERIAL OUTPUT PORT –62 SDO 8 14 3 VREF 10 2.5V REFERENCE 10µF 4 GND 5 9 6 CONV TIMING LOGIC 11 EXPOSED PAD SCK 2355 TA01 THD, 2nd, 3rd (dB) AIN+ –50 VDD 14-BIT LATCH 7 LTC2355-14 –68 THD 2nd –74 3rd –80 –86 –92 –98 –104 –110 0.1 1 10 FREQUENCY (MHz) 100 2355 G02 2355fb For more information www.linear.com/LTC2355-12 1 LTC2355-12/LTC2355-14 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) TOP VIEW Supply Voltage (VDD)...................................................4V Analog and VREF Input Voltages (Note 3).....................................–0.3V to (VDD + 0.3V) Digital Input Voltages.................... – 0.3V to (VDD + 0.3V) Digital Output Voltage....................– 0.3V to (VDD + 0.3V) Power Dissipation................................................100mW Operation Temperature Range LTC2355C-12/LTC2355C-14...................... 0°C to 70°C LTC2355I-12/LTC2355I-14....................– 40°C to 85°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec).................... 300°C ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL LTC2355CMSE-12#PBF AIN+ AIN– VREF GND GND 1 2 3 4 5 10 9 8 7 6 11 GND CONV SCK SDO VDD GND MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 40°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB http://www.linear.com/product/LTC2355-12#orderinfo PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2355CMSE-12#TRPBF LTCVX 10-Lead Plastic MSOP 0°C to 70°C LTC2355IMSE-12#PBF LTC2355IMSE-12#TRPBF LTCVX 10-Lead Plastic MSOP –40°C to 85°C LTC2355CMSE-14#PBF LTC2355CMSE-14#TRPBF LTCVY 10-Lead Plastic MSOP 0°C to 70°C LTC2355IMSE-14#PBF LTC2355IMSE-14#TRPBF LTCVY 10-Lead Plastic MSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. CONVERTER CHARACTERISTICS l denotes the specifications which apply over the full operating The temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3.3V. LTC2355-12 PARAMETER CONDITIONS Resolution (No Missing Codes) MIN l 12 TYP LTC2355-14 MAX MIN TYP MAX 14 UNITS Bits Integral Linearity Error (Notes 4, 5, 18) l –2 ±0.25 2 –4 ±0.5 4 LSB Offset Error (Notes 4, 18) l –10 ±1 10 –20 ±2 20 LSB Gain Error (Note 4, 18) l –30 ±5 30 –80 ±10 80 Gain Tempco Internal Reference (Note 4) External Reference ±15 ±1 ±15 ±1 LSB ppm/°C ppm/°C 2355fb 2 For more information www.linear.com/LTC2355-12 LTC2355-12/LTC2355-14 ANALOG INPUT l denotes the specifications which apply over the full operating temperature range, otherwise The specifications are at TA = 25°C. With internal reference. VDD = 3.3V. SYMBOL PARAMETER CONDITIONS VIN Analog Differential Input Range (Notes 3, 8, 9) 3.1V ≤ VDD ≤ 3.6V VCM Analog Common Mode + Differential Input Range (Note 10) IIN Analog Input Leakage Current CIN Analog Input Capacitance (Note 19) tACQ Sample-and-Hold Acquisition Time (Note 6) MIN l TYP MAX V 0 to VDD V 1 l tAP Sample-and-Hold Aperture Delay Time tJITTER Sample-and-Hold Aperture Delay Time Jitter CMRR Analog Input Common Mode Rejection Ratio UNITS 0 to 2.5 µA 13 pF 39 l fIN = 1MHz, VIN = 0V to 3V fIN = 100MHz, VIN = 0V to 3V ns 1 ns 0.3 ps –60 –15 dB dB DYNAMIC ACCURACY l denotes the specifications which apply over the full operating temperature range, The otherwise specifications are at TA = 25°C with external reference = 2.55V. VDD = 3.3V. LTC2355-12 PARAMETER CONDITIONS SINAD Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal 1.4MHz Input Signal l Total Harmonic Distortion 100kHz First 5 Harmonics 1.4MHz First 5 Harmonics l SFDR Spurious Free Dynamic Range 100kHz Input Signal 1.4MHz Input Signal 86 82 86 82 dB dB IMD Intermodulation Distortion 1.25V to 2.5V 1.25MHz into AIN+, 0V to 1.25V, 1.2MHz into AIN– –82 –82 dB dB Code-to-Code Transition Noise VREF = 2.5V (Note 18) 0.25 1 LSBRMS Full Power Bandwidth VIN = 2.5VP-P, SDO = 11585LSBP-P (Note 15) 50 50 MHz Full Linear Bandwidth S/(N + D) ≥ 68dB 5 5 MHz THD MIN TYP 69 71.1 71.1 LTC2355-14 SYMBOL –86 –82 MAX MIN TYP 71 74.2 73.8 –86 –82 –76 MAX UNITS dB dB dB dB –78 INTERNAL REFERENCE CHARACTERISTICS l denotes the specifications which apply over the The full operating temperature range, otherwise specifications are at TA = 25°C, VDD = 3.3V. PARAMETER CONDITIONS VREF Output Voltage IOUT = 0 MIN VREF Output Tempco TYP MAX UNITS 2.5 V 15 ppm/°C µV/V VREF Line Regulation VDD = 3.1V to 3.6V, VREF = 2.5V 600 VREF Output Resistance Load Current = 0.5mA 0.2 Ω VREF Settling Time CREF = 10µF 2 ms External VREF Input Range 2.55 VDD V 2355fb For more information www.linear.com/LTC2355-12 3 LTC2355-12/LTC2355-14 DIGITAL INPUTS AND DIGITAL OUTPUTS l denotes the specifications which apply over the The full operating temperature range, otherwise specifications are at TA = 25°C, VDD = 3.3V. SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VDD = 3.6V l VIL Low Level Input Voltage VDD = 3.1V l 0.6 V IIN Digital Input Current VIN = 0V to VDD l ±10 µA CIN Digital Input Capacitance VOH High Level Output Voltage VDD = 3.3V, IOUT = –200µA l VOL Low Level Output Voltage VDD = 3.1V, IOUT= 160µA VDD = 3.1V, IOUT = 1.6mA l VOUT = 0V to VDD l IOZ Hi-Z Output Leakage DOUT COZ Hi-Z Output Capacitance DOUT ISOURCE Output Short-Circuit Source Current ISINK Output Short-Circuit Sink Current MIN TYP MAX UNITS 2.4 2.5 V 5 pF 2.9 V 0.05 0.10 0.4 V V ±10 µA 1 pF VOUT = 0V, VDD = 3.3V 20 mA VOUT = VDD = 3.3V 15 mA POWER REQUIREMENTS l denotes the specifications which apply over the full operating temperature The range, otherwise specifications are at TA = 25°C. (Note 17) SYMBOL PARAMETER VDD Supply Voltage IDD Supply Current PD Power Dissipation CONDITIONS Active Mode Nap Mode Sleep Mode (LTC2355-12) Sleep Mode (LTC2355-14) l l MIN TYP MAX 3.1 3.3 3.6 V 5.5 1.1 4 4 8 1.5 15 12 mA mA µA µA 18 UNITS mW 2355fb 4 For more information www.linear.com/LTC2355-12 LTC2355-12/LTC2355-14 TIMING CHARACTERISTICS l denotes the specifications which apply over the full operating temperature The range, otherwise specifications are at TA = 25°C. VDD = 3.3V. SYMBOL PARAMETER CONDITIONS fSAMPLE(MAX) Maximum Sampling Rate per Channel (Conversion Rate) MIN l tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) TYP 3.5 Clock Period (Note 16) l UNITS MHz l tSCK MAX 15.872 286 ns 10000 ns tCONV Conversion Time (Note 6) 17 t1 Minimum High or Low SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 ns t3 Nearest SCK Edge Before CONV (Note 6) 0 ns t4 Minimum High or Low CONV Pulse Width (Note 6) 4 ns t5 SCK↑ to Sample Mode (Note 6) 4 ns t6 CONV↑ to Hold Mode (Notes 6, 11) 1.2 ns t7 16th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 t8 Delay from SCK to Valid Bits 0 Through 13 (Notes 6, 12) t9 SCK↑ to Hi-Z at SDO (Notes 6, 12) t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) t12 VREF Settling Time After Sleep-to-Wake Transition (Note 14) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: When these pins are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than VDD without latchup. Note 4: Offset and full-gain specifications are measured for a single-ended AIN+ input with AIN– grounded and using the internal 2.5V reference. Note 5: Integral linearity is tested with an external 2.55V reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The analog input range is defined for the voltage difference between AIN+ and AIN–. Note 9: The absolute voltage at AIN+ and AIN– must be within this range. Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. 18 SCLK cycles ns 8 6 2 ns ns ns 2 ms Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns) because the 2.2ns delay through the sample-and-hold is subtracted from the CONV to Hold mode delay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 13: The time period for acquiring the input signal is started by the 16th rising clock and it is ended by the rising edge of convert. Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10µF capacitive load. Note 15: The full power bandwidth is the frequency where the output code swing drops to 3dB with a 2.5VP-P input sine wave. Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read with an arbitrarily long clock. Note 17: VDD = 3.3V, fSAMPLE = 3.5Msps. Note 18: The LTC2355-14 is measured and specified with 14-bit resolution (1LSB = 152µV) and the LTC2355-12 is measured and specified with 12-bit resolution (1LSB = 610µV). Note 19: The sampling capacitor at each input accounts for 4.1pF of the input capacitance. 2355fb For more information www.linear.com/LTC2355-12 5 LTC2355-12/LTC2355-14 TYPICAL PERFORMANCE CHARACTERISTICS THD, 2nd and 3rd vs Input Frequency SINAD vs Input Frequency –56 71 –62 THD, 2nd, 3rd (dB) 74 68 SINAD (dB) SFDR vs Input Frequency –50 65 62 59 –68 –74 3rd –86 –92 53 –104 100 80 –80 –98 1 10 FREQUENCY (MHz) 86 THD 2nd 56 50 0.1 92 SFDR (dB) 77 TA = 25°C, VDD = 3.3V (LTC2355-14) 68 62 56 –110 0.1 1 10 FREQUENCY (MHz) 50 0.1 100 2355 G02 2355 G01 0 74 –20 –10 –20 –30 –30 –40 –40 MAGNITUDE (dB) 65 62 59 56 53 50 0.1 1 10 FREQUENCY (MHz) 100 MAGNITUDE (dB) 0 –10 68 –50 –60 –70 –80 –60 –70 –80 –90 –100 –100 –110 –120 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 FREQUENCY (MHz) –110 –120 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 FREQUENCY (MHz) 2355 G05 Differential Linearity vs Output Code 2355 G06 Integral Linearity vs Output Code 1.0 4 0.8 3 0.6 INTEGRAL LINEARITY (LSB) DIFFERENTIAL LINEARITY (LSB) –50 –90 2355 G04 0.4 0.2 0 –0.2 –0.4 –0.6 2 1 0 –1 –2 –3 –0.8 –1.0 100 1.4MHz Sine Wave 8192 Point FFT Plot 77 71 1 10 FREQUENCY (MHz) 2355 G03 100kHz Sine Wave 8192 Point FFT Plot SNR vs Input Frequency SNR (dB) 74 0 4096 12288 8192 OUTPUT CODE 16384 –4 0 4096 8192 12288 16384 OUTPUT CODE 2355 G07 2355 G08 2355fb 6 For more information www.linear.com/LTC2355-12 LTC2355-12/LTC2355-14 TYPICAL PERFORMANCE CHARACTERISTICS Differential and Integral Linearity vs Conversion Rate TA = 25°C, VDD = 3.3V (LTC2355-14) SINAD vs Conversion Rate, Input Frequency = 1.4MHz 4 75 3 MAX DNL 1 SINAD (dB) LINEARITY (LSB) 74 MAX INL 2 0 MIN INL –1 MIN DNL –2 73 72 71 –3 –4 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 70 2 2.2 2.4 2.6 2.8 CONVERSION RATE (Msps) 3.2 3.4 3.6 3.8 3 4 CONVERSION RATE (Msps) 2355 G09 2355 G10 TA = 25°C, VDD = 3.3V (LTC2355-12 and LTC2355-14) 12 2.5VP-P Power Bandwidth CMRR vs Frequency PSRR vs Frequency –25 0 6 –30 –20 –35 –40 –12 –18 PSRR (dB) –40 –6 CMRR (dB) AMPLITUDE (dB) 0 –60 –55 –80 –24 –60 –100 –30 –36 1M 10M 100M FREQUENCY (Hz) –65 –120 100 1G 1k 10k 100k 1M FREQUENCY (Hz) 2355 G11 10M 2.4902 2.4900 2.4900 Internal Reference Voltage vs VDD 100 1k 10k FREQUENCY (Hz) 10 100k 6 5.5 VREF (V) 2.4896 2.4894 2.4894 2.4892 2.4892 1M VDD Supply Current vs Conversion Rate 2.4898 VREF (V) 1 2355 G13 VDD SUPPLY CURRENT (mA) 2.4902 2.4896 –70 100M 2355 G12 Internal Reference Voltage vs Load Current 2.4898 –45 –50 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 2.4890 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) 2355 G14 2.4890 2.6 2.8 3.0 3.2 VDD (V) 3.4 3.6 0 0 0.5 1 1.5 2 2.5 3 3.5 4 CONVERSION RATE (Mps) 2355 G15 2355 G16 2355fb For more information www.linear.com/LTC2355-12 7 LTC2355-12/LTC2355-14 PIN FUNCTIONS AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates fully differentially with respect to AIN– with a 0V to 2.5V differential swing and a 0V to VDD common mode swing. (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in mind that internal analog currents and digital output signal currents flow through this pin. Care should be taken to place the 0.1µF bypass capacitor as close to Pins 6 and 7 as possible. AIN– (Pin 2): Inverting Analog Input. AIN– operates fully differentially with respect to AIN+ with a – 2.5V to 0V differential swing and a 0V to VDD common mode swing. SDO (Pin 8): Three-State Serial Data Output. Each set of output data words represents the difference between AIN+ and AIN– analog inputs at the start of the previous conversion. VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and to a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Can be overdriven by an external reference between 2.55V and VDD. SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising edge. Responds to TTL (≤3.3V) and 3.3V CMOS levels. One or more SCK pulses wakes the ADC from sleep mode. GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These ground pins and the exposed pad must be tied directly to the solid ground plane under the part. Keep in mind that analog signal currents and digital output signal currents flow through these pins. CONV (Pin 10): Convert Start. Holds the analog input signal and starts the conversion on the rising edge. Responds to TTL (≤3.3V) and 3.3V CMOS levels. Two CONV pulses with SCK in fixed high or fixed low state start Nap mode. Four or more CONV pulses with SCK in fixed high or fixed low state start Sleep mode. VDD (Pin 7): 3.3V Positive Supply. This single power pin supplies 3.3V to the entire device. Bypass to GND and to a solid analog ground plane with a 10µF ceramic capacitor BLOCK DIAGRAM 10µF 3.3V AIN+ 1 + 14-BIT ADC S&H AIN– 2 VDD – THREESTATE SERIAL OUTPUT PORT 14-BIT LATCH 7 LTC2355-14 8 SDO 10 CONV 9 SCK 14 3 VREF 2.5V REFERENCE 10µF 4 GND 5 6 TIMING LOGIC 11 EXPOSED PAD 2355 BD 2355fb 8 For more information www.linear.com/LTC2355-12 LTC2355-12/LTC2355-14 TIMING DIAGRAM LTC2355-12 Timing Diagram t2 t3 16 17 t7 t1 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 16 17 18 1 SCK t4 t5 CONV t6 INTERNAL S/H STATUS tACQ SAMPLE HOLD t8 t8 t10 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION Hi-Z SDO SAMPLE D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X HOLD t9 Hi-Z X 2355 TD01 14-BIT DATA WORD tCONV tTHROUGHPUT *BITS MARKED "X" AFTER D0 SHOULD BE IGNORED. LTC2355-14 Timing Diagram t2 t3 16 17 t7 t1 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 16 17 18 1 SCK t4 t5 CONV t6 INTERNAL S/H STATUS tACQ SAMPLE HOLD t8 SDO Hi-Z SAMPLE t8 t10 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 HOLD t9 D0 Hi-Z 2355 TD01b 14-BIT DATA WORD tCONV tTHROUGHPUT Nap Mode and Sleep Mode Waveforms SLK t1 t1 CONV NAP SLEEP t12 VREF 2355 TD02 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS SCK to SDO Delay SCK VIH SCK t8 t10 SDO VIH t9 VOH VOL 90% SDO 10% 2355 TD03 2355fb For more information www.linear.com/LTC2355-12 9 LTC2355-12/LTC2355-14 APPLICATIONS INFORMATION DRIVING THE ANALOG INPUT The differential analog inputs of the LTC2355-12/LTC2355‑14 may be driven differentially or as a single-ended input (i.e., the AIN– input is grounded). Both differential analog inputs, AIN+ and AIN–, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC2355-12/LTC2355-14 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier must be used. The main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). Also keep in mind while choosing an input amplifier the amount of noise and harmonic distortion added by the amplifier. CHOOSING AN INPUT AMPLIFIER Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (