LTC2356-12/LTC2356-14
Serial 12-Bit/14-Bit, 3.5Msps
Sampling ADCs with Shutdown
Description
Features
n
n
n
n
n
n
n
n
n
n
n
3.5Msps Conversion Rate
74.1dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits
Low Power Dissipation: 18mW
3.3V Single Supply Operation
2.5V Internal Bandgap Reference can be Overdriven
3-Wire SPI-Compatible Serial Interface
Sleep (13µW) Shutdown Mode
Nap (4mW) Shutdown Mode
80dB Common Mode Rejection
±1.25V Bipolar Input Range
Tiny 10-Lead MSOP Package
The LTC®2356-12/LTC2356-14 are 12-bit/14-bit, 3.5Msps
serial ADCs with differential inputs. The devices draw
only 5.5mA from a single 3.3V supply and come in a
tiny 10-lead MSOP package. A Sleep shutdown feature
further reduces power consumption to 13µW. The combination of speed, low power and tiny package makes the
LTC2356-12/LTC2356-14 suitable for high speed, portable
applications.
The 80dB common mode rejection allows users to eliminate
ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert –1.25V to 1.25V bipolar inputs
differentially. The absolute voltage swing for AIN+ and
AIN– extends from ground to the supply voltage.
Applications
Communications
Data Acquisition Systems
n Uninterrupted Power Supplies
n Multiphase Motor Control
n Multiplexed Data Acquisition
n RFID
n
n
The serial interface sends out the conversion results during
the 16 clock cycles following a CONV rising edge for compatibility with standard serial interfaces. If two additional
clock cycles for acquisition time are allowed after the data
stream in between conversions, the full sampling rate of
3.5Msps can be achieved with a 63MHz clock.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
Block Diagram
THD, 2nd and 3rd vs Input Frequency
for Differential Input Signals
10µF 3.3V
1
+
14-BIT ADC
S&H
AIN–
2
–
–56
THREESTATE
SERIAL
OUTPUT
PORT
–62
SDO
8
14
3
VREF
10
2.5V
REFERENCE
10µF
4
GND
5
11
EXPOSED PAD
–68
–74
THD
2nd
3rd
–80
–86
–92
SCK
9
6
CONV
TIMING
LOGIC
THD, 2nd, 3rd (dB)
AIN+
–50
VDD
14-BIT LATCH
7
LTC2356-14
2356 BD
–98
–104
0.1
1
10
FREQUENCY (MHz)
100
2356 G02
2356fd
For more information www.linear.com/LTC2356-12
1
LTC2356-12/LTC2356-14
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
TOP VIEW
Supply Voltage (VDD)...................................................4V
Analog and VREF Input Voltages
(Note 3).....................................–0.3V to (VDD + 0.3V)
Digital Input Voltages.................... – 0.3V to (VDD + 0.3V)
Digital Output Voltage....................– 0.3V to (VDD + 0.3V)
Power Dissipation................................................100mW
Operation Temperature Range
LTC2356C-12/LTC2356C-14...................... 0°C to 70°C
LTC2356I-12/LTC2356I-14....................– 40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
Order Information
LEAD FREE FINISH
TAPE AND REEL
LTC2356CMSE-12#PBF
AIN+
AIN–
VREF
GND
GND
1
2
3
4
5
10
9
8
7
6
11
CONV
SCK
SDO
VDD
GND
MSE PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 40°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC2356-12#orderinfo
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2356CMSE-12#TRPBF LTCWN
10-Lead Plastic MSOP
0°C to 70°C
LTC2356IMSE-12#PBF
LTC2356IMSE-12#TRPBF LTCWN
10-Lead Plastic MSOP
–40°C to 85°C
LTC2356CMSE-14#PBF
LTC2356CMSE-14#TRPBF LTCVF
10-Lead Plastic MSOP
0°C to 70°C
LTC2356IMSE-14#PBF
LTC2356IMSE-14#TRPBF LTCVF
10-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Converter
Characteristics l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3.3V.
LTC2356-12
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
MIN
l
12
TYP
LTC2356-14
MAX
MIN
(Notes 4, 5, 18)
l
–2
±0.25
2
–4
–10
±1
10
–40
±5
40
Offset Error
(Notes 4, 18)
Gain Error
(Note 4, 18)
l
Gain Tempco
Internal Reference (Note 4)
External Reference
2
MAX
14
Integral Linearity Error
l
TYP
±15
±1
UNITS
Bits
±0.5
4
LSB
–30
±2
30
LSB
–80
±10
80
LSB
±15
±1
ppm/°C
ppm/°C
2356fd
For more information www.linear.com/LTC2356-12
LTC2356-12/LTC2356-14
Analog
Input l denotes the specifications which apply over the full operating temperature range,
The
otherwise specifications are at TA = 25°C. With internal reference. VDD = 3.3V.
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Differential Input Range (Notes 3, 8, 9)
3.1V ≤ VDD ≤ 3.6V
VCM
Analog Common Mode + Differential
Input Range (Note 10)
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
(Note 19)
tACQ
Sample-and-Hold Acquisition Time
(Note 6)
tAP
Sample-and-Hold Aperture Delay Time
tJITTER
Sample-and-Hold Aperture Delay Time Jitter
CMRR
Analog Input Common Mode Rejection Ratio
MIN
l
TYP
MAX
UNITS
–1.25 to 1.25
V
0 to VDD
V
1
l
µA
13
pF
39
l
fIN = 1MHz, VIN = 0V to 3V
fIN = 100MHz, VIN = 0V to 3V
ns
1
ns
0.3
ps
–60
–15
dB
dB
Dynamic
Accuracy l denotes the specifications which apply over the full operating
The
temperature range,
+
–
otherwise specifications are at TA = 25°C with external reference = 2.55V. VDD = 3.3V. Single-ended AIN signal drive with AIN = 1.5V
DC. Differential signal drive with VCM = 1.5V at AIN+ and AIN–
LTC2356-12
PARAMETER
CONDITIONS
SINAD
Signal-to-Noise Plus
Distortion Ratio
100kHz Input Signal (Note 19)
1.4MHz Input Signal (Note 19)
l
Total Harmonic
Distortion
100kHz First 5 Harmonics (Note 19)
1.4MHz First 5 Harmonics (Note 19)
l
SFDR
Spurious Free
Dynamic Range
100kHz Input Signal (Note 19)
1.4MHz Input Signal (Note 19)
86
82
86
82
dB
dB
IMD
Intermodulation
Distortion
0.625VP-P to 1.4MHz Summed with 0.625VP-P
1.56MHz into AIN+ and Inverted into AIN–
–82
–82
dB
Code-to-Code
Transition Noise
VREF = 2.5V (Note 18)
0.25
1
LSBRMS
Full Power Bandwidth VIN = 2.5VP-P, SDO = 11585LSBP-P (Note 15)
50
50
MHz
Full Linear Bandwidth S/(N + D) ≥ 68dB
5
5
MHz
THD
MIN
TYP
68
71.1
71.1
LTC2356-14
SYMBOL
–86
–82
MAX
MIN
TYP
70
74.1
72.3
–86
–82
–76
MAX
UNITS
dB
dB
dB
dB
–78
Internal
Reference Characteristics l denotes the specifications which apply over the
The
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V.
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
MIN
VREF Output Tempco
TYP
MAX
UNITS
2.5
V
15
ppm/°C
VREF Line Regulation
VDD = 3.1V to 3.6V, VREF = 2.5V
600
µV/V
VREF Output Resistance
Load Current = 0.5mA
0.2
Ω
VREF Settling Time
CREF = 10µF
2
ms
External VREF Input Range
2.55
VDD
V
2356fd
For more information www.linear.com/LTC2356-12
3
LTC2356-12/LTC2356-14
Digital
Inputs and Digital Outputs l denotes the specifications which apply over the
The
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V.
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 3.6V
l
VIL
Low Level Input Voltage
VDD = 3.1V
l
0.6
V
IIN
Digital Input Current
VIN = 0V to VDD
l
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VDD = 3.3V, IOUT = –200µA
l
VOL
Low Level Output Voltage
VDD = 3.1V, IOUT= 160µA
VDD = 3.1V, IOUT = 1.6mA
l
VOUT = 0V to VDD
l
IOZ
Hi-Z Output Leakage DOUT
COZ
Hi-Z Output Capacitance DOUT
ISOURCE
Output Short-Circuit Source Current
ISINK
Output Short-Circuit Sink Current
MIN
TYP
MAX
UNITS
2.4
2.5
V
5
pF
2.9
V
0.05
0.10
0.4
V
V
±10
µA
1
pF
VOUT = 0V, VDD = 3.3V
20
mA
VOUT = VDD = 3.3V
15
mA
Power
Requirements l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 17)
SYMBOL
PARAMETER
CONDITIONS
VDD
Supply Voltage
IDD
Supply Current
Active Mode
Nap Mode
Sleep Mode (LTC2356-12)
Sleep Mode (LTC2356-14)
PD
Power Dissipation
Active Mode with SCK in Fixed State (Hi or Lo)
4
MIN
3.1
l
l
TYP
MAX
3.3
3.6
V
5.5
1.1
4
4
8
1.5
15
12
mA
mA
µA
µA
18
UNITS
mW
2356fd
For more information www.linear.com/LTC2356-12
LTC2356-12/LTC2356-14
Timing Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3.3V.
SYMBOL
PARAMETER
CONDITIONS
fSAMPLE(MAX) Maximum Sampling Rate per Channel
(Conversion Rate)
MIN
l
tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period)
TYP
3.5
Clock Period
(Note 16)
l
UNITS
MHz
l
tSCK
MAX
15.872
286
ns
10000
ns
tCONV
Conversion Time
(Note 6)
17
t1
Minimum High or Low SCLK Pulse Width
(Note 6)
2
ns
t2
CONV to SCK Setup Time
(Notes 6, 10)
3
ns
t3
Nearest SCK Edge Before CONV
(Note 6)
0
ns
t4
Minimum High or Low CONV Pulse Width
(Note 6)
4
ns
t5
SCK↑ to Sample Mode
(Note 6)
4
ns
t6
CONV↑ to Hold Mode
(Notes 6, 11)
1.2
ns
t7
16th SCK↑ to CONV≠ Interval (Affects Acquisition Period)
(Notes 6, 7, 13)
45
ns
t8
Delay from SCK to Valid Data
(Notes 6, 12)
8
ns
t9
SCK↑ to Hi-Z at SDO
(Notes 6, 12)
6
ns
t10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
t12
VREF Settling Time After Sleep-to-Wake Transition
(Note 14)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and full-gain specifications are measured for a single-ended
AIN+ input with AIN– grounded and using the internal 2.5V reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between AIN+ and AIN–. Performance is specified with AIN– = 1.5V DC while
driving AIN+.
Note 9: The absolute voltage at AIN+ and AIN– must be within this range.
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
18
2
SCLK cycles
ns
2
ms
Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)
because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
16th rising clock and it is ended by the rising edge of convert.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops to 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock.
Note 17: VDD = 3.3V, fSAMPLE = 3.5Msps.
Note 18: The LTC2356-14 is measured and specified with 14-bit resolution
(1LSB = 152µV) and the LTC2356-12 is measured and specified with
12-bit resolution (1LSB = 610µV).
Note 19: The sampling capacitor at each input accounts for 4.1pF of the
input capacitance.
2356fd
For more information www.linear.com/LTC2356-12
5
LTC2356-12/LTC2356-14
Typical Performance Characteristics
TA = 25°C, VDD = 3.3V (LTC2356-14)
SINAD vs Input Frequency
THD, 2nd and 3rd vs Input Frequency
–50
74
–56
71
–62
THD, 2nd, 3rd (dB)
77
SINAD (dB)
68
65
62
59
–74
–80
–86
56
–92
53
–98
50
0.1
1
10
FREQUENCY (MHz)
THD
2nd
3rd
–68
–104
0.1
100
1
10
FREQUENCY (MHz)
2356 G01
2356 G02
SNR vs Input Frequency
SFDR vs Input Frequency
92
77
86
74
71
80
68
74
SNR (dB)
SFDR (dB)
100
68
65
62
59
62
56
56
53
50
0.1
1
10
FREQUENCY (MHz)
50
0.1
100
1
10
FREQUENCY (MHz)
2356 G03
2356 G04
1.4MHz Sine Wave 8192 Point
FFT Plot
0
0
–10
–10
–20
–20
–30
–30
–40
–40
MAGNITUDE (dB)
MAGNITUDE (dB)
100kHz Sine Wave 8192 Point
FFT Plot
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–110
–120
–110
–120
0
250k 500k 750k 1M 1.25M 1.5M 1.75M
FREQUENCY (Hz)
0
250k 500k 750k 1M 1.25M 1.5M 1.75M
FREQUENCY (Hz)
2356 G05
6
100
2356 G06
2356fd
For more information www.linear.com/LTC2356-12
LTC2356-12/LTC2356-14
Typical Performance Characteristics
TA = 25°C, VDD = 3.3V (LTC2356-14)
Differential Linearity vs Output Code
Integral Linearity vs Output Code
1.0
4
3
0.6
INTEGRAL LINEARITY (LSB)
DIFFERENTIAL LINEARITY (LSB)
0.8
0.4
0.2
0
–0.2
–0.4
–0.6
2
1
0
–1
–2
–3
–0.8
–1.0
0
4096
12288
8192
OUTPUT CODE
–4
16384
0
8192
4096
16384
12288
OUTPUT CODE
2356 G07
2356 G08
Differential and Integral Linearity
vs Conversion Rate
SINAD vs Conversion Rate, Input
Frequency = 1.4MHz
4
75
3
74
MAX INL
1
SINAD (dB)
LINEARITY (LSB)
2
MAX DNL
MIN DNL
0
–1
MIN INL
–2
73
72
71
–3
–4
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
70
2.0 2.2 2.4 2.6 2.8
CONVERSION RATE (Msps)
3
3.2 3.4 3.6 3.8 4.0
CONVERSION RATE (Msps)
2356 G09
12
2356 G10
CMRR vs Frequency
2.5VP-P Power Bandwidth
0
6
–20
–40
–6
CMRR (dB)
AMPLITUDE (dB)
0
–12
–18
–60
–80
–24
–100
–30
–36
1M
10M
100M
FREQUENCY (Hz)
1G
–120
100
1k
2356 G11
10k
100k 1M
FREQUENCY (Hz)
10M
100M
2356 G12
2356fd
For more information www.linear.com/LTC2356-12
7
LTC2356-12/LTC2356-14
Typical Performance Characteristics
TA = 25°C, VDD = 3.3V (LTC2356-12 and LTC2356-14)
Internal Reference Voltage vs
Load Current
PSRR vs Frequency
–25
2.4902
–30
2.4900
–35
2.4898
–45
VREF (V)
PSRR (dB)
–40
–50
–55
2.4894
–60
2.4892
–65
–70
2.4896
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
2.4890
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (mA)
2356 G13
2356 G14
VDD Supply Current vs
Conversion Rate
Internal Reference Voltage vs VDD
6
5.5
2.4902
VDD SUPPLY CURRENT (mA)
2.4900
VREF (V)
2.4898
2.4896
2.4894
2.4892
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
2.4890
2.6
2.8
3.0
3.2
VDD (V)
3.4
3.6
0
0
1
1.5
2
2.5
3
3.5
4
CONVERSION RATE (Mps)
2356 G15
8
0.5
2356 G16
2356fd
For more information www.linear.com/LTC2356-12
LTC2356-12/LTC2356-14
Pin Functions
AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates
fully differentially with respect to AIN– with a –1.25V to
1.25V differential swing with respect to AIN– and a 0V to
VDD common mode swing.
AIN– (Pin 2): Inverting Analog Input. AIN– operates fully
differentially with respect to AIN+ with a 1.25V to –1.25V
differential swing with respect to AIN+ and a 0V to VDD
common mode swing.
VREF (Pin 3): 2.5V Internal Reference. Bypass to GND
and to a solid analog ground plane with a 10µF ceramic
capacitor (or 10µF tantalum in parallel with 0.1µF ceramic).
Can be overdriven by an external reference between 2.55V
and VDD.
GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these pins.
VDD (Pin 7): 3.3V Positive Supply. This single power pin
supplies 3.3V to the entire device. Bypass to GND and to
a solid analog ground plane with a 10µF ceramic capacitor
(or 10µF tantalum in parallel with 0.1µF ceramic). Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1µF bypass capacitor as close to Pins 6 and
7 as possible.
SDO (Pin 8): Three-State Serial Data Output. Each set
of output data words represents the difference between
AIN+ and AIN– analog inputs at the start of the previous
conversion. The output format is 2’s complement.
SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising
edge. Responds to TTL (≤3.3V) and 3.3V CMOS levels.
One or more pulses wake from sleep.
CONV (Pin 10): Convert Start. Holds the analog input signal
and starts the conversion on the rising edge. Responds
to TTL (≤3.3V) and 3.3V CMOS levels. Two CONV pulses
with SCK in fixed high or fixed low state start Nap mode.
Four or more CONV pulses with SCK in fixed high or fixed
low state start Sleep mode.
2356fd
For more information www.linear.com/LTC2356-12
9
LTC2356-12/LTC2356-14
Block Diagram
10µF 3.3V
AIN+
1
+
AIN–
2
–
VDD
14-BIT ADC
S&H
THREESTATE
SERIAL
OUTPUT
PORT
14-BIT LATCH
7
LTC2356-14
8
SDO
10
CONV
9
SCK
14
VREF
3
2.5V
REFERENCE
10µF
GND
4
5
6
TIMING
LOGIC
11
2356 BD
EXPOSED PAD
Timing DiagramS
LTC2356-12 Timing Diagram
t2
t3
17
18
1
t7
t1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
16
17
18
1
SCK
t4
t5
CONV
t6
INTERNAL
S/H STATUS
tACQ
SAMPLE
HOLD
SAMPLE
t8
t8
SDO
Hi-Z
t9
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X*
HOLD
X*
Hi-Z
2356 TD01
14-BIT DATA WORD
tCONV
tTHROUGHPUT
*BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.
10
2356fd
For more information www.linear.com/LTC2356-12
LTC2356-12/LTC2356-14
Timing DiagramS
LTC2356-14 Timing Diagram
t2
t3
17
18
t7
t1
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
16
17
18
1
SCK
t4
t5
CONV
t6
INTERNAL
S/H STATUS
tACQ
SAMPLE
HOLD
SAMPLE
t8
t8
SDO
Hi-Z
t9
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
HOLD
D0
Hi-Z
2356 TD01b
14-BIT DATA WORD
tCONV
tTHROUGHPUT
Nap Mode and Sleep Mode Waveforms
SCK
t1
t1
CONV
NAP
SLEEP
t12
VREF
2356 TD02
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
SCK to SDO Delay
SCK
VIH
SCK
t8
t10
SDO
VIH
t9
VOH
VOL
90%
SDO
10%
2356 TD03
2356fd
For more information www.linear.com/LTC2356-12
11
LTC2356-12/LTC2356-14
Applications Information
Driving the Analog Input
The differential analog inputs of the LTC2356-12/LTC2356-14
may be driven differentially or as a single-ended input (i.e.,
the AIN– input is set to VCM). Both differential analog inputs,
AIN+ and AIN–, are sampled at the same instant. Any
unwanted signal that is common to both inputs of each
input pair will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw
only one small current spike while charging the sampleand-hold capacitors at the end of conversion. During
conversion, the analog inputs draw only a small leakage
current. If the source impedance of the driving circuit
is low, then the LTC2356-12/LTC2356-14 inputs can be
driven directly. As source impedance increases, so will
acquisition time. For minimum acquisition time with
high source impedance, a buffer amplifier must be used.
The main requirement is that the amplifier driving the
analog input(s) must settle after the small current spike
before the next conversion starts (settling time must be
39ns for full throughput rate). Also keep in mind while
choosing an input amplifier the amount of noise and
harmonic distortion added by the amplifier.
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude of
the voltage spike seen by the amplifier from charging the
sampling capacitor, choose an amplifier that has a low output
impedance (
