ADC12DL066
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SNAS188G – FEBRUARY 2004 – REVISED FEBRUARY 2013
ADC12DL066 Dual 12-Bit, 66 Msps, 450 MHz Input Bandwidth A/D Converter w/Internal
Reference
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FEATURES
DESCRIPTION
•
The ADC12DL066 is a dual, low power monolithic
CMOS analog-to-digital converter capable of
converting analog input signals into 12-bit digital
words at 66 Megasamples per second (Msps),
minimum. This converter uses a differential, pipeline
architecture with digital error correction and an onchip sample-and-hold circuit to minimize die size and
power consumption while providing excellent dynamic
performance and a 450 MHz Full Power Bandwidth.
Operating on a single 3.3V power supply, the
ADC12DL066 achieves 10.7 effective bits and
consumes just 686 mW at 66 Msps, including the
reference current. The Power Down feature reduces
power consumption to 75 mW.
1
2
•
•
•
•
•
Choice of Binary or 2’s Complement Output
Format
Single +3.3V Supply Operation
Outputs 2.4V to 3.3V Compatible
Pin Compatible with ADC12D040
Power Down Mode
Internal/External Reference
KEY SPECIFICATIONS
•
•
•
•
•
Resolution: 12 Bits
DNL: ±0.5 LSB (typ)
SNR (fIN = 10 MHz): 66 dB (typ)
SFDR (fIN = 10 MHz): 81 dB (typ)
Power Consumption
– Operating: 686 mW (typ)
– Power Down Mode: 75 mW (typ)
APPLICATIONS
•
•
•
•
•
•
•
Ultrasound and Imaging
Instrumentation
Communications Receivers
Sonar/Radar
xDSL
Cable Modems
DSP Front Ends
The differential inputs provide a full scale differential
input swing equal to 2 times VREF with the possibility
of a single-ended input. Full use of the differential
input is recommended for optimum performance. The
digital outputs from the two ADCs are available on
separate 12-bit buses with an output data format
choice of offset binary or two’s complement.
To ease interfacing to lower voltage systems, the
digital output driver power pins of the ADC12DL066
can be connected to a separate supply voltage in the
range of 2.4V to the digital supply voltage.
This device is available in the 64-lead TQFP package
and will operate over the industrial temperature range
of −40°C to +85°C. An evaluation board is available
to ease the evaluation process.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
ADC12DL066
SNAS188G – FEBRUARY 2004 – REVISED FEBRUARY 2013
www.ti.com
Stage
1
Stage
2
Stage
3
Stage
n
| |
S/H
VIN A-
Stage
9
Stage
10
2
||
2
VA
Stage
11
AGND
2
||
VIN A+
| |
Block Diagram
22
Timing
Control
11-Stage Pipeline Converter
3
CLK
VD
Digital Correction
DGND
12
12
VRP A
Output
Buffers
VRM A
DA0-DA11
OEA
VRN A
VDR
INT/EXT REF
DR GND
Bandgap
Reference
VREF
VRP B
OF
12
Output
Buffers
VRM B
VRN B
DB0-DB11
OEB
12
DGND
PD
Digital Correction
VD
3
11-Stage Pipeline Converter
Timing
Control
22
Stage
2
Stage
3
Stage
n
2
| |
2
Stage
1
2
| |
S/H
VIN B+
||
||
2
VIN B-
Stage
9
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Stage
10
Stage
11
VA
AGND
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ADC12DL066
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Connection Diagram
Figure 1. 64-Lead TQFP Package
Package Number PAG
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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
15
2
VINA+
VINB+
16
1
VINA−
VINB−
7
VREF
11
Differential analog input pins. With a 1.0V reference voltage the
differential full-scale input signal level is 2.0 VP-P with each input pin
voltage centered on a common mode voltage, VCM. The negative
input pins may be connected to VCM for single-ended operation, but
a differential input signal is required for best performance.
VA
Reference input. This pin should be bypassed to AGND with a 0.1
µF capacitor when an external reference is used. VREF is 1.0V
nominal and should be between 0.8V to 1.5V.
Reference source select pin. With a logic low at this pin the internal
1.0V reference is selected and the VREF pin need not be driven.
With a logic high on this pin an external reference voltage should
be applied to VREF input pin 7.
INT/EXT REF
DGND
4
13
5
VRPA
VRPB
14
4
VRMA
VRMB
12
6
VRNA
VRNB
These pins are high impedance reference bypass pins only; they
are not reference output pins. Bypass per Reference Pins. DO
NOT LOAD these pins.
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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin No.
Symbol
Equivalent Circuit
Description
DIGITAL I/O
60
CLK
22
41
OEA
OEB
59
PD
21
OF
24–29
34–39
DA0–DA11
42–47
52–57
DB0–DB11
VA
Digital clock input. The range of frequencies for this input is as
specified in the electrical tables with guaranteed performance at 66
MHz. The input is sampled on the rising edge of this input.
OEA and OEB are the output enable pins that, when low, holds
their respective data output pins in the active state. When either of
these pins is high, the corresponding outputs are in a high
impedance state.
PD is the Power Down input pin. When high, this input puts the
converter into the power down mode. When this pin is low, the
converter is in the active mode.
DGND
Output Format pin. A logic low on this pin causes output data to be
in offset binary format. A logic high on this pin causes the output
data to be in 2’s complement format.
Digital data output pins that make up the 12-bit conversion results
of their respective converters. DA0 and DB0 are the LSBs, while
DA11 and DB11 are the MSBs of the output words. Output levels
are TTL/CMOS compatible.
ANALOG POWER
9, 18, 19, 62,
63
VA
3, 8, 10, 17,
20, 61, 64
AGND
Positive analog supply pins. These pins should be connected to a
quiet +3.3V source and bypassed to AGND with 0.1 µF capacitors
located within 1 cm of these power pins, and with a 10 µF
capacitor.
The ground return for the analog supply.
DIGITAL POWER
33, 48
VD
32, 49
DGND
30, 51
23, 31, 40,
50, 58
VDR
DR GND
Positive digital supply pin. This pin should be connected to the
same quiet +3.3V source as is VA and be bypassed to DGND with
a 0.1 µF capacitor located within 1 cm of the power pin and with a
10 µF capacitor.
The ground return for the digital supply.
Positive digital supply pin for the ADC12DL066's output drivers.
This pin should be connected to a voltage source of +2.4V to VD
and be bypassed to DR GND with a 0.1 µF capacitor. If the supply
for this pin is different from the supply used for VA and VD, it should
also be bypassed with a 10 µF capacitor. VDR should never exceed
the voltage on VD. All bypass capacitors should be located within 1
cm of the supply pin.
The ground return for the digital supply for the ADC12DL066's
output drivers. These pins should be connected to the system
digital ground, but not be connected in close proximity to the
ADC12DL066's DGND or AGND pins. See LAYOUT AND
GROUNDING (Layout and Grounding) for more details.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2) (3)
VA, VD, VDR
4.2V
≤ 100 mV
|VA–VD|
−0.3V to (VA or VD +0.3V)
Voltage on Any Input or Output Pin
Input Current at Any Pin (4)
Package Input Current
±25 mA
(4)
±50 mA
See (5)
Package Dissipation at TA = 25°C
ESD Susceptibility (6)
Human Body Model
2500V
Machine Model
250V
Soldering Temperature, Infrared, 10 sec. (7)
235°C
−65°C to +150°C
Storage Temperature
(1)
(2)
(3)
(4)
(5)
(6)
(7)
All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 25 mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula
PDMAX = (TJmax - TA ) / θJA. The values for maximum power dissipation will only be reached when the device is operated in a severe
fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the
temperature at the top of the package body above 183°C for a minimum 60 seconds. The temperature measured on the package body
must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle.
Operating Ratings (1) (2)
Operating Temperature
−40°C ≤ TA ≤ +85°C
Supply Voltage (VA, VD)
+3.0V to +3.6V
Output Driver Supply (VDR)
+2.4V to VD
VREF Input
0.8V to 1.5V
−0.05V to (VD + 0.05V)
CLK, PD, OE
0V to (VA − 0.5V)
Analog Input Pins
Common Mode Input Voltage
(VCM)
0.5V to 1.5V
≤100mV
|AGND–DGND|
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Package Thermal Resistance
6
Package
θJ-A
64-Lead TQFP
50°C / W
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Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, VREF = +1.0V, fCLK = 66 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin.
Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1) (2) (3)
Symbol
Parameter
Conditions
Typical
Limits
(4)
(4)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
12
Bits (min)
INL
Resolution with No Missing Codes
Integral Non Linearity (5)
±1.2
±3.0
LSB (max)
DNL
Differential Non Linearity
±0.5
±1.0
LSB (max)
PGE
Positive Gain Error
±0.2
±3.6
%FS (max)
NGE
Negative gain Error
±0.2
±3.6
%FS (max)
TC GE
Gain Error Tempco
+1.3
-0.9
%FS (max)
%FS (min)
VOFF
Offset Error (VIN+ = VIN−)
TC VOFF
Offset Error Tempco
−40°C ≤ TA ≤ +85°C
−60
0.18
−40°C ≤ TA ≤ +85°C
ppm/°C
−2.4
ppm/°C
Under Range Output Code
0
0
Over Range Output Code
4095
4095
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCM
Common Mode Input Voltage
1.0
CIN
VIN Input Capacitance (each pin to GND)
VIN = 2.5 Vdc + 0.7 Vrms
(CLK LOW)
8
(CLK HIGH)
7
VREF
External Reference Voltage (6)
1.00
RREF
Reference Input Resistance
100
(1)
(2)
(3)
(4)
(5)
(6)
0.5
V (min)
1.5
V (max)
pF
pF
0.8
1.5
V (min)
V (max)
MΩ (min)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited see Note 4 in the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes
above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure
accurate conversions (see Figure 2).
To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to AOQL (Average Outgoing
Quality Level).
Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through
positive and negative full-scale.
Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ (SOT-23
package) is recommended for external reference applications.
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Converter Electrical Characteristics (continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, VREF = +1.0V, fCLK = 66 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin.
Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C(1)(2)(3)
Symbol
Parameter
Typical
Conditions
(4)
Limits
(4)
Units
(Limits)
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
SNR
SINAD
ENOB
THD
H2
H3
SFDR
IMD
0 dBFS Input, Output at −3 dB
450
fIN = 1 MHz, VIN = −0.5 dBFS
66
fIN = 10 MHz, VIN = −0.5 dBFS
66
fIN = 33 MHz, VIN = −0.5 dBFS
64
dB
fIN = 146 MHz, VIN = −0.5 dBFS
55
dB
fIN = 1 MHz, VIN = −0.5 dBFS
66
fIN = 10 MHz, VIN = −0.5 dBFS
66
fIN = 33 MHz, VIN = −0.5 dBFS
63
fIN = 146MHz, VIN = −0.5 dBFS
53
dB
fIN = 1 MHz, VIN = −0.5 dBFS
10.7
Bits
fIN = 10 MHz, VIN = −0,5 dBFS
10.7
fIN = 33 MHz, VIN = −0,5 dBFS
10.3
Bits
fIN = 146MHz, VIN = −0,5 dBFS
8.7
Bits
fIN = 1 MHz, VIN = −0.5 dBFS
−78
dB
fIN = 10 MHz, VIN = −0.5 dBFS
−78
fIN = 33 MHz, VIN = −0.5 dBFS
−70
dB
fIN = 146MHz, VIN = −0.5 dBFS
−59
dB
fIN = 1 MHz, VIN = −0.5 dBFS
−90
fIN = 10 MHz, VIN = −0.5 dBFS
−85
fIN = 33 MHz, VIN = −0.5 dBFS
−72
dB
fIN = 146MHz, VIN = −0.5 dBFS
−67
dB
fIN = 1 MHz, VIN = −0.5 dBFS
−83
fIN = 10 MHz, VIN = −0.5 dBFS
−85
fIN = 33 MHz, VIN = −0.5 dBFS
−76
dB
fIN = 146MHz, VIN = −0.5 dBFS
−66
dB
fIN = 1 MHz, VIN = −0.5 dBFS
79
fIN = 10 MHz, VIN = −0.5 dBFS
81
fIN = 33 MHz, VIN = −0.5 dBFS
72
dB
fIN = 146MHz, VIN = −0.5 dBFS
63
dB
fIN = 9.6 MHz and 10.2 MHz, each = −6.0
dBFS
−64
dBFS
Channel—Channel Offset Match
±0.03
%FS
Channel—Channel Gain Match
±0.1
%FS
10 MHz Tested, Channel;
20 MHz Other Channel
80
dB
10 MHz Tested, Channel;
195 MHz Other Channel
63
dB
Full Power Bandwidth
Signal-to-Noise Ratio
Signal-to-Noise and Distortion
Effective Number of Bits
Total Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
Spurious Free Dynamic Range
Intermodulation Distortion
MHz
dB
64
dB (min)
dB
63.3
dB (min)
dB
10.2
−67.8
Bits (min)
dB (min)
dB
−70.4
dB (min)
dB
−71.0
dB (min)
dB
68.5
dB (min)
INTER-CHANNEL CHARACTERISTICS
Crosstalk
8
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DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, VREF = +1.0V, fCLK = 66 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin.
Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1) (2) (3)
Symbol
Parameter
Conditions
Typical
(4)
Limits
(4)
Units
(Limits)
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VD = 3.6V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
1.0
V (max)
IIN(1)
Logical “1” Input Current
VIN = 3.3V
10
µA
IIN(0)
Logical “0” Input Current
VIN = 0V
−10
µA
CIN
Digital Input Capacitance
5
pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
VOUT(1)
Logical “1” Output Voltage
IOUT = −0.5 mA
VOUT(0)
Logical “0” Output Voltage
IOUT = 1.6 mA, VDR = 3V
IOZ
TRI-STATE Output Current
+ISC
Output Short Circuit Source Current
−ISC
Output Short Circuit Sink Current
COUT
Digital Output Capacitance
VDR = 2.5V
2.3
V (min)
VDR = 3V
2.7
V (min)
0.4
V (max)
VOUT = 2.5V or 3.3V
100
nA
VOUT = 0V
−100
nA
VOUT = 0V
−20
mA
VOUT = VDR
20
mA
5
pF
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
PD Pin = DGND, VREF = 1.0V
PD Pin = VD
177
14
237
mA (max)
mA
ID
Digital Supply Current
PD Pin = DGND
PD Pin = VD , fCLK = 0
31
8.7
34
mA (max)
mA
IDR
Digital Output Supply Current
PD Pin = DGND, CL = 0 pF (5)
PD Pin = VD, fCLK = 0