LTC2415/LTC2415-1
24-Bit No Latency ∆Σ™
ADCs with Differential Input and
Differential Reference
DESCRIPTION
FEATURES
2× Speed Up Version of the LTC2410/LTC2413:
15Hz Output Rate, 50Hz or 60Hz Notch—LTC2415;
13.75Hz Output Rate, Simultaneous 50Hz/60Hz
Notch—LTC2415-1
nn Differential Input and Differential Reference with
GND to VCC Common Mode Range
nn 2ppm INL, No Missing Codes
nn 2.5ppm Gain Error
nn 0.23ppm Noise
nn Single Conversion Settling Time for Multiplexed
Applications
nn Internal Oscillator—No External Components
Required
nn 24-Bit ADC in Narrow SSOP-16 Package
(SO-8 Footprint)
nn Single Supply 2.7V to 5.5V Operation
nn Low Supply Current (200µA) and Auto Shutdown
nn
APPLICATIONS
Direct Sensor Digitizer
Weight Scales
nn Direct Temperature Measurement
nn Gas Analyzers
nn Strain Gage Transducers
nn Instrumentation
nn Data Acquisition
nn Industrial Process Control
nn 6-Digit DVMs
nn
nn
The LTC®2415/2415-1 are micropower 24‑bit differential
∆Σ analog to digital converters with integrated oscillator,
2ppm INL, 0.23ppm RMS noise and a 2.7V to 5.5V supply
range. They use delta-sigma technology and provide single
cycle settling time for multiplexed applications. Through a
single pin, the LTC2415 can be configured for better than
110dB input differential mode rejection at 50Hz or 60Hz
±2%, or it can be driven by an external oscillator for a
user defined rejection frequency. The LTC2415-1 can be
configured for better than 87dB input differential mode
rejection over the range of 49Hz to 61.2Hz (50Hz and 60Hz
±2% simultaneously). The internal oscillator requires no
external frequency setting components.
The converters accept any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and remote sensing measurement configurations. The full-scale
differential input range is from –0.5VREF to 0.5VREF. The
reference common mode voltage, VREFCM, and the input
common mode voltage, VINCM, may be independently set
anywhere within the GND to VCC range of the LTC2415/
LTC2415-1. The DC common mode input rejection is
better than 140dB.
The LTC2415/LTC2415-1 communicate through a flexible
3-wire digital interface which is compatible with SPI and
MICROWIRE protocols.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and C-Load
and No Latency ∆Σ are trademarks of Linear Technology Corporation. All other trademarks are
the property of their respective owners.
TYPICAL APPLICATION
VCC
2.7V TO 5.5V
1µF
VCC
1µF
2
VCC
FO
14
LTC2415/
LTC2415-1
REFERENCE
VOLTAGE
0.1V TO VCC
3
REF +
4
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
5
IN +
SDO
IN –
CS
6
1, 7, 8, 9, 10, 15, 16
GND
SCK
= INTERNAL OSC/50Hz REJECTION (LTC2415)
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION (LTC2415)
= INTERNAL 50Hz/60Hz REJECTION (LTC2415-1)
BRIDGE
IMPEDANCE
100Ω TO 10k
13
12
3
3-WIRE
SPI INTERFACE
5
6
2
REF + VCC
IN +
IN –
4
REF – GND
1, 7, 8
9, 10,
15, 16
11
2415 TA01
12 SDO
13 SCK
LTC2415/
LTC2415-1
11 CS
3-WIRE
SPI INTERFACE
FO
14
2415 TA02
2415fa
For more information www.linear.com/LTC2415
1
LTC2415/LTC2415-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
Supply Voltage (VCC) to GND........................ –0.3V to 7V
Analog Input Pins Voltage
to GND.......................................–0.3V to (VCC + 0.3V)
Reference Input Pins Voltage
to GND.......................................–0.3V to (VCC + 0.3V)
Digital Input Voltage to GND..........–0.3V to (VCC + 0.3V)
Digital Output Voltage to GND........–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2415C/LTC2415-1C ............................. 0°C to 70°C
LTC2415I/LTC2415-1I ...........................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
TOP VIEW
GND
1
16 GND
VCC
2
15 GND
REF +
3
14 FO
REF –
4
13 SCK
IN +
5
12 SDO
IN –
6
11 CS
GND
7
10 GND
GND
8
9
GND
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2415CGN#PBF
LTC2415CGN#TRPBF
2415
16-Lead Plastic SSOP
0°C to 70°C
LTC2415IGN#PBF
LTC2415IGN#TRPBF
2415I
16-Lead Plastic SSOP
–40°C to 85°C
LTC2415-1CGN#PBF
LTC2415-1CGN#TRPBF
24151
16-Lead Plastic SSOP
0°C to 70°C
LTC2415-1IGN#PBF
LTC2415-1IGN#TRPBF
24151I
16-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5)
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6)
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC, (Note 14)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+
Offset Error
Offset Error Drift
Positive Gain Error
MIN
Positive Gain Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+
Negative Gain Error
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
●
TYP
MAX
24
UNITS
Bits
●
1
2
5
14
ppm of VREF
ppm of VREF
ppm of VREF
●
0.5
2
mV
20
●
2.5
nV/°C
12
0.03
●
2.5
ppm of VREF
ppm of VREF/°C
12
ppm of VREF
2415fa
2
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)
PARAMETER
CONDITIONS
Negative Gain Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
MIN
TYP
MAX
UNITS
0.03
ppm of VREF/°C
Output Noise
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF – = GND,
GND ≤ IN– = IN+ ≤ VCC, (Note 13)
1.1
µVRMS
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC, (Note 7)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC, (Note 8)
Input Common Mode Rejection
60Hz ±2% (LTC2415)
Input Common Mode Rejection
50Hz ±2% (LTC2415)
MIN
TYP
MAX
UNITS
l
130
140
l
140
dB
l
140
dB
dB
Input Normal Mode Rejection
60Hz ±2% (LTC2415)
(Note 7)
l
110
140
dB
Input Normal Mode Rejection
50Hz ±2% (LTC2415)
(Note 8)
l
110
140
dB
Input Common Mode Rejection
49Hz to 61.2Hz (LTC2415-1)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
l
140
dB
Input Normal Mode Rejection
49Hz to 61.2Hz (LTC2415-1)
FO = GND
l
87
dB
Input Normal Mode Rejection
External Clock fEOSC/2560 ±14%
(LTC2415-1)
External Oscillator
l
87
dB
Input Normal Mode Rejection
External Clock fEOSC/2560 ±4%
(LTC2415-1)
External Oscillator
l
110
140
dB
Reference Common Mode
Rejection DC
2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V,
VREF = 2.5V, IN– = IN+ = GND
l
130
140
dB
Power Supply Rejection, DC
REF+ = VCC, REF– = GND, IN– = IN+ = GND
100
dB
Power Supply Rejection, 60Hz ±2%
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7)
120
dB
Power Supply Rejection, 50Hz ±2% REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 8)
120
dB
ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
● GND – 0.3V
VCC + 0.3V
V
IN–
Absolute/Common Mode IN– Voltage
● GND – 0.3V
VCC + 0.3V
V
VIN
Input Differential Voltage Range
(IN+ – IN–)
●
–VREF/2
VREF/2
V
REF+
Absolute/Common Mode REF+ Voltage
●
0.1
VCC
V
REF–
Absolute/Common Mode REF– Voltage
●
GND
VCC – 0.1V
V
VREF
Reference Differential Voltage Range
(REF+ – REF–)
●
0.1
VCC
V
2415fa
For more information www.linear.com/LTC2415
3
LTC2415/LTC2415-1
ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3,4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CS
(IN+)
IN+ Sampling Capacitance
CS
(IN–)
IN– Sampling Capacitance
18
pF
CS (REF+)
REF+ Sampling Capacitance
18
pF
CS (REF–)
REF– Sampling Capacitance
18
pF
(IN+)
IN+ DC Leakage Current
IDC_LEAK (IN–)
IN– DC Leakage Current
IDC_LEAK
IDC_LEAK
(REF+)
REF+ DC Leakage Current
IDC_LEAK (REF–) REF– DC Leakage Current
18
CS = VCC, IN+ = GND
CS = VCC, IN– = GND
CS = VCC, REF+ = 5V
CS = VCC, REF– = GND
pF
●
–10
1
10
nA
●
–10
1
10
nA
●
–10
1
10
nA
●
–10
1
10
nA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3)
SYMBOL PARAMETER
VIH
VIL
VIH
VIL
IIN
IIN
CIN
CIN
VOH
VOL
VOH
VOL
IOZ
CONDITIONS
MIN
High Level Input Voltage
CS, FO
Low Level Input Voltage
CS, FO
High Level Input Voltage
SCK
Low Level Input Voltage
SCK
Digital Input Current
CS, FO
Digital Input Current
SCK
Digital Input Capacitance
CS, FO
Digital Input Capacitance
SCK
High Level Output Voltage
SDO
Low Level Output Voltage
SDO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
0V ≤ VIN ≤ VCC
●
●
0V ≤ VIN ≤ VCC (Note 9)
●
High Level Output Voltage
SCK
Low Level Output Voltage
SCK
Hi-Z Output Leakage
SDO
TYP
2.5
2.0
–10
0.8
0.6
10
–10
10
µA
0.8
0.6
2.5
2.0
●
(Note 9)
IO = –800µA
●
IO = 1.6mA
●
IO = –800µA (Note 10)
●
IO = 1.6mA (Note 10)
●
●
UNITS
V
V
V
V
V
V
V
V
µA
●
●
MAX
10
pF
10
pF
VCC – 0.5
V
0.4
VCC – 0.5
V
V
–10
0.4
V
10
µA
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
CONDITIONS
MIN
l
CS = 0V (Note 12)
CS = VCC (Note 12)
l
l
TYP
2.7
200
20
MAX
UNITS
5.5
V
300
30
µA
µA
2415fa
4
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 3,4)
SYMBOL
PARAMETER
CONDITIONS
MIN
fEOSC
External Oscillator Frequency Range
l
tHEO
External Oscillator High Period
tLEO
External Oscillator Low Period
tCONV
Conversion Time (LTC2415)
TYP
MAX
UNITS
2.56
500
kHz
l
0.25
390
µs
l
0.25
390
µs
FO = 0V
FO = VCC
External Oscillator (Note 11)
l
l
l
65.43
78.52
66.77
68.1
80.12
81.72
10278/fEOSC (in kHz)
ms
ms
ms
Conversion Time (LTC2415-1)
FO = 0V
External Oscillator (Note 11)
l
l
71.3
72.8
74.3
10278/fEOSC (in kHz)
ms
ms
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10), LTC2415
Internal Oscillator (Note 10), LTC2415-1
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
l
fESCK
External SCK Frequency Range
(Note 9)
l
tLESCK
External SCK Low Period
(Note 9)
l
250
ns
tHESCK
External SCK High Period
(Note 9)
l
250
ns
tDOUT_ISCK Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12), LTC2415
Internal Oscillator (Notes 10, 12), LTC2415-1
External Oscillator (Notes 10, 11)
l
l
l
1.64
1.80
tDOUT_ESCK External SCK 32-Bit Data Output Time
(Note 9)
l
19.2
17.5
fEOSC/8
45
kHz
kHz
kHz
55
%
2000
kHz
1.67
1.70
1.83
1.86
256/fEOSC (in kHz)
ms
ms
ms
32/fESCK (in kHz)
ms
t1
CS ↓ to SDO Low Z
l
0
200
ns
t2
CS ↑ to SDO High Z
l
0
200
ns
t3
CS ↓ to SCK ↓
(Note 10)
l
0
200
ns
t4
CS ↓ to SCK ↑
(Note 9)
l
50
tKQMAX
SCK ↓ to SDO Valid
tKQMIN
SDO Hold After SCK ↓
l
15
ns
t5
SCK Set-Up Before CS ↓
l
50
ns
t6
SCK Hold After CS ↓
l
220
l
(Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7 to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: FO pin tied to GND or to VCC or to external conversion clock source
with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2% (external
oscillator).
ns
50
ns
ns
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2% (external
oscillator).
Note 9: The converter is in external SCK mode of operation such that the
SCK pin is used as digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that the
SCK pin is used as digital output. In this mode of operation the SCK pin
has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Refer to Offset Accuracy and Drift in the Applications Information
section.
2415fa
For more information www.linear.com/LTC2415
5
LTC2415/LTC2415-1
TYPICAL PERFORMANCE CHARACTERISTICS
105.5
TA = 25°C
105.0
104.5
213
121
TA = 90°C
211
209
VCC = 5V
VREF = 2.5V
VINCM = 1.25V
REF + = 2.5V
REF – = GND
FO = GND
207
TA = –45°C
104.0
125
205
–1.25
103.5
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
VIN (V)
–0.75
TA = –45°C
–0.25
0.25
VIN (V)
0.75
0.5
2.5
TA = –45°C
2.0
TA = 25°C
1.5
INL ERROR (ppm OF VREF)
INL ERROR (ppm OF VREF)
1.0
0
TA = 90°C
TA = 25°C
1.0
0.5
0
–1.0
TA = 90°C
–1.5
–1.0
1
1.5
2
–2.5
–1.25
2.5
8
6
4
2
0
–105.5
–104.8
–104
–103.3
OUTPUT CODE (ppm OF VREF)
–102.5
2415 G07
10
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
10
GAUSSIAN
DISTRIBUTION
m = –103.5ppm
σ = 0.27ppm
TA = –45°C
–0.75
–0.25
0.25
VIN (V)
0.75
–0.75
–0.25
0.25
VIN (V)
0.75
TA = 90°C
6
4
2
0
TA = 25°C
–2
TA = –45°C
–4
–6
REF + = 2.5V
VCC = 2.7V
VREF = 2.5V
REF – = GND
VINCM = 1.25V FO = GND
–10
–1.25
1.25
–0.75
–0.25
0.25
VIN (V)
0.75
12
GAUSSIAN
DISTRIBUTION
m = –104.0ppm
σ = 0.25ppm
2
0
–105
1.25
2415 G06
Noise Histogram
(Output Rate = 45Hz,
VCC = 5V, VREF = 5V)
10,000 CONSECUTIVE
READINGS
V = 5V
8 VCC = 5V
REF
VIN = 0V
REF + = 5V
6 REF – = GND
IN + = 2.5V
IN – = 2.5V
4 FO = 460800Hz
TA = 25°C
1.25
Integral Nonlinearity Over
Temperature (VCC = 2.7V,
VREF = 2.5V)
2415 G05
Noise Histogram
(Output Rate = 15Hz,
VCC = 5V, VREF = 5V)
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
FO = GND
TA = 25°C
TA = 25°C
8
–8
2415 G04
12
10
TA = –45°C
–2.0
–1.5
–2.5 –2 –1.5 –1 –0.5 0 0.5
VIN (V)
REF + = 2.5V
VCC = 5V
VREF = 2.5V
REF – = GND
VINCM = 1.25V FO = GND
–0.5
–0.5
113
2415 G03
Integral Nonlinearity Over
Temperature (VCC = 5V,
VREF = 2.5V)
Integral Nonlinearity Over
Temperature (VCC = 5V,
VREF = 5V)
VCC = 5V
VREF = 5V
VINCM = 2.5V
REF + = 5V
REF – = GND
FO = GND
117
105
–1.25
1.25
TA = 90°C
2415 G02
2415 G01
1.5
REF + = 2.5V
VCC = 2.7V
VREF = 2.5V
REF – = GND
VINCM = 1.25V FO = GND
109
TA = 25°C
INL ERROR (ppm OF VREF)
TUE (ppm OF VREF)
106.0
215
TUE (ppm OF VREF)
VCC = 5V
VREF = 5V
VINCM = 2.5V
REF + = 5V
REF – = GND
FO = GND
TA = 90°C
Total Unadjusted Error Over
Temperature (VCC = 2.7V,
VREF = 2.5V)
NUMBER OF READINGS (%)
106.5
Total Unadjusted Error Over
Temperature (VCC = 5V,
VREF = 2.5V)
TUE (ppm OF VREF)
Total Unadjusted Error Over
Temperature (VCC = 5V,
VREF = 5V)
10
8
6
4
Noise Histogram
(Output Rate = 15Hz,
VCC = 5V, VREF = 2.5V)
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = GND
TA = 25C
GAUSSIAN
DISTRIBUTION
m = –209.2ppm
σ = 0.56ppm
2
–104.5
–104
–103.5
OUTPUT CODE (ppm OF VREF)
–103
2415 G08
0
–212
–210.5
–209
–207.5
OUTPUT CODE (ppm OF VREF)
–206
2415 G10
2415fa
6
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
TYPICAL PERFORMANCE CHARACTERISTICS
6
4
10
8
6
4
10,000 CONSECUTIVE
READINGS
VCC = 2.7V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = GND
TA = 25°C
2
2
0
–211.5
–210.5
–209.5
–208.5
OUTPUT CODE (ppm OF VREF)
0
–116
–207.5
–114.5
–113
–111.5
OUTPUT CODE (ppm OF VREF)
Long-Term Histogram
(60Hrs)
VCC = 5V
VREF = 5V
10 VIN = 0V
REF + = 5V
REF – = GND
8 IN + = 2.5V
IN – = 2.5V
F = GND
6 O
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = –103.9ppm
σ = 0.27ppm
4
2
–103.5
–104
–104.5
OUTPUT CODE (ppm OF VREF)
0.5
VCC = 5V
VREF = 5V
VIN = 0V
REF + = 5V
REF – = GND
–101.5
–102.0
–102.5
IN + = 2.5V
IN – = 2.5V
FO = GND
TA = 25°C
–103.0
–103.5
–104.0
–104.5
–105.5
–105
0.4
0.3
VCC = 5V
VREF = 5V
VINCM = 2.5V
REF + = 5V
REF – = GND
FO = GND
TA = 25°C
0.2
0.1
0
0
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2
INPUT DIFFERENTIAL VOLTAGE (V)
5 10 15 20 25 30 35 40 45 50 55 60
TIME (HRS)
RMS Noise vs Temperature (TA)
RMS Noise vs VCC
1400
IN + = VINCM
IN – = VINCM
FO = GND
TA = 25°C
2.5
2415 G18
2415 G17
1560
1520
1250
RMS NOISE (nV)
RMS NOISE (nV)
VCC = 5V
VREF = 5V
VIN = 0V
REF + = 5V
REF – = GND
–107.5
2415 G14
–101.0
RMS Noise vs VINCM
1800
–110.9
–109.8
–108.6
OUTPUT CODE (ppm OF VREF)
RMS Noise vs Input Differential
Voltage
2415 G16
1600
0
–112
–110
–105.0
0
–103
GAUSSIAN
DISTRIBUTION
m = –109.8ppm
σ = 0.50ppm
2
Consecutive ADC Readings vs
Time
ADC READINGS (ppm OF VREF)
12
10,000 CONSECUTIVE
READINGS
V = 2.7V
8 VCC = 2.5V
REF
VIN = 0V
REF + = 2.5V
6 REF – = GND
IN + = 1.25V
IN – = 1.25V
4 FO = 460800Hz
TA = 25°C
2415 G13
2415 G11
NUMBER OF READINGS (%)
10
GAUSSIAN
DISTRIBUTION
m = –113.1ppm
σ = 0.59ppm
RMS NOISE (ppm OF VREF)
8
12
GAUSSIAN
DISTRIBUTION
m = –209.3ppm
σ = 0.49ppm
Noise Histogram
(Output Rate = 45Hz,
VCC = 2.7V, VREF = 2.5V)
1400
1200
1480
1100
VCC = 5V
VIN = 0V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
FO = GND
950
1000
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VINCM (V)
2415 G19
800
–50
RMS NOISE (nV)
10
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = 460800Hz
TA = 25°C
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
12
Noise Histogram
(Output Rate = 15Hz,
VCC = 2.7V, VREF = 2.5V)
NUMBER OF READINGS (%)
Noise Histogram
(Output Rate = 45Hz,
VCC = 5V, VREF = 2.5V)
–25
0
25
50
TEMPERATURE (°C)
75
1440
1400
1360
1320
100
2415 G20
1280
2.7
VREF = 2.5V
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
2415 G21
2415fa
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7
LTC2415/LTC2415-1
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Noise vs VREF
Offset Error vs VINCM
–103.0
RMS NOISE (nV)
1400
1200
VCC = 5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
1000
800
0
0.5
1
1.5
2 2.5 3
VREF (V)
3.5
4
4.5
Offset Error vs Temperature (TA)
VCC = 5V
VREF = 5V
VIN = 0V
REF + = 5V
REF – = GND
IN + = VINCM
IN – = VINCM
FO = GND
TA = 25°C
–103.4
–103.8
–104.2
–104.4
–190
–210
–230
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
–103.6
–104.4
–104.8
–105.2
2.7
3.1
3.5 3.9 4.3 4.7
VCC AND VREF (V)
3.5
3.9 4.3
VCC (V)
0
–1
–2
4.7
5.1
5.5
2415 G28
VCC = 5V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = GND
FO = GND
–3
–45 –30 –15
5.5
0 15 30 45 60
TEMPERATURE (°C)
–4
–8
0.5
90
–Full-Scale Error vs
Temperature (TA)
0
4
0
75
2415 G27
– FULL-SCALE ERROR (ppm OF VREF)
+ FULL-SCALE ERROR (ppm OF VREF)
+ FULL-SCALE ERROR (ppm OF VREF)
1
3.1
1
+Full-Scale Error vs VREF
2
0
2.7
5.1
8
3
100
2
2415 G26
5
75
3
–104.0
+Full-Scale Error vs VCC
4
0
25
50
TEMPERATURE (°C)
+Full-Scale Error vs
Temperature (TA)
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
2415 G25
VREF = 2.5V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = GND
FO = GND
TA = 25°C
–25
2415 G24
+ FULL-SCALE ERROR (ppm OF VREF)
–170
–104.6
–50
Offset Error vs VCC and VREF
–103.2
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
–150
VCC = 5V
VIN = 0V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
FO = GND
2415 G23
Offset Error vs VCC
–130
–104.2
–105.0
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VINCM (V)
5
VREF = 2.5V
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
–104.0
–104.6
2415 G22
–110
–103.8
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
1600
VCC = 5V
REF + = VREF
REF – = GND
IN + = 0.5 • REF +
IN – = GND
FO = GND
TA = 25°C
1
1.5
2
2.5 3 3.5
VREF (V)
4
4.5
5
2415 G29
–1
–2
–3
–4
–5
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = 2.5V
FO = GND
–6
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2415 G30
2415fa
8
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LTC2415/LTC2415-1
TYPICAL PERFORMANCE CHARACTERISTICS
–Full-Scale Error vs VCC
–Full-Scale Error vs VREF
PSRR vs Frequency at VCC
8
–1
–2
VREF = 2.5V
REF + = 2.5V
REF – = GND
IN + = GND
IN – = 1.25V
FO = GND
TA = 25°C
–3
–4
–5
2.7
3.5
3.1
3.9 4.3
VCC (V)
4.7
5.1
0
4
0
VCC = 5V
REF + = VREF
REF – = GND
IN + = GND
IN – = 0.5 • REF +
FO = GND
TA = 25°C
–4
–8
–12
0.5
5.5
1
1.5
2
2.5 3 3.5
VREF (V)
4
PSRR vs Frequency at VCC
–100
5
–80
–100
100
10000
FREQUENCY AT VCC (Hz)
–40
–60
–80
1000000
–120
15200
15300
15400
FREQUENCY AT VCC (Hz)
15500
400
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
500
300
190 FO = GND
CS = GND
180 SCK = SDO = N/C
VCC = 5.5V
VCC = 4.1V
170
VCC = 2.7V
160
140
–45 –30 –15
20
0 15 30 45 60
TEMPERATURE (°C)
75
90
2415 G36
18
100
16
30
40
10
20
OUTPUT DATA RATE (READINGS/SEC)
50
VCC = 5.5V
19
17
0
VREF+ = VCC
210 V – = GND
REF
VIN+ = VIN– = GND
200
+
24 VREF– = VCC
VREF = GND
23 VIN+ = VIN– = GND
FO = GND
22 CS = V
CC
21 SCK = SDO = N/C
200
0
Conversion Current vs
Temperature (TA)
25
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = GND
FO = EXT OSC
CS = GND
SCK =N/C
SDO = N/C
600
250
Sleep Current vs
Temperature (TA)
1000
700
100
150
200
FREQUENCY AT VCC (Hz)
2415 G35
Conversion Current vs Output
Data Rate
800
50
150
2415 G34
900
0
2415 G33
220
VCC = 4.1V DC + 0.7V AC
REF + = 2.5V
REF – = GND
IN + = IN – = GND
FO = GND
TA = 25°C
–100
1
–120
SUPPLY CURRENT (µA)
–20
–60
–120
–80
0
REJECTION (dB)
REJECTION (dB)
–40
–60
PSRR vs Frequency at VCC
0
–20
4.5
–40
2415 G32
2415 G31
REF + = 2.5V
REF – = GND
IN + = IN – = GND
FO = GND
TA = 25°C
VCC = 4.1V DC + 1.4V AC
REF + = 2.5V
REF – = GND
IN + = IN – = GND
FO = GND
TA = 25°C
–20
REJECTION (dB)
– FULL-SCALE ERROR (ppm OF VREF)
– FULL-SCALE ERROR (ppm OF VREF)
0
15
–45 –30 –15
2415 G37
VCC = 4.1V
VCC = 2.7V
0 15 30 45 60
TEMPERATURE (°C)
75
90
2415 G38
2415fa
For more information www.linear.com/LTC2415
9
LTC2415/LTC2415-1
PIN FUNCTIONS
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground
pins internally connected for optimum ground current
flow and VCC decoupling. Connect each one of these pins
to a ground plane through a low impedance connection.
All seven pins must be connected to ground for proper
operation.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data Output
period. In External Serial Clock Operation mode, SCK is
used as digital input for the external serial interface clock
during the Data Output period. A weak internal pull-up is
automatically activated in Internal Serial Clock Operation
mode. The Serial Clock Operation mode is determined by
the logic level applied to the SCK pin at power up or during
the most recent falling edge of CS.
REF + (Pin 3), REF– (Pin 4): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
is maintained more positive than the reference negative
input, REF –, by at least 0.1V.
IN + (Pin 5), IN– (Pin 6): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from
– 0.5 • (VREF) to 0.5 • (VREF). Outside this input range the
converter produces unique overrange and underrange
output codes.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
FO (Pin 14): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion time.
When the FO pin is connected to VCC (LTC2415 only), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the FO pin is connected
to GND (FO = OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz (LTC2415)
or simultaneous 50Hz/60Hz (LTC2415-1). When FO is
driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency fEOSC/2560.
2415fa
10
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
FUNCTIONAL BLOCK DIAGRAM
INTERNAL
OSCILLATOR
VCC
GND
IN +
IN –
AUTOCALIBRATION
AND CONTROL
+
–∫
∫
FO
(INT/EXT)
∫
∑
SDO
SERIAL
INTERFACE
ADC
SCK
CS
REF +
REF –
DECIMATING FIR
– +
DAC
2415 FD
Figure 1. Functional Block Diagram
TEST CIRCUITS
SDO
VCC
1.69k
CLOAD = 20pF
1.69k
SDO
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
2415 TA03
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
2415 TA04
2415fa
For more information www.linear.com/LTC2415
11
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2415/LTC2415-1 are low power, delta-sigma
analog-to-digital converters with an easy to use 3-wire
serial interface (see Figure 1). Their operation is made
up of three states. The converter operating cycle begins
with the conversion, followed by the sleep state and ends
with the data output (see Figure 2). The 3-wire interface
consists of serial data output (SDO), serial clock (SCK)
and chip select (CS).
CONVERT
Through timing control of the CS and SCK pins, the
LTC2415/LTC2415-1 offer several flexible modes of
operation (internal or external SCK and free-running
conversion modes). These various modes do not require
programming configuration registers; moreover, they do
not disturb the cyclic operation described above. These
modes of operation are described in detail in the Serial
Interface Timing Modes section.
Conversion Clock
SLEEP
FALSE
Data is updated on the falling edge of SCK allowing the
user to reliably latch data on the rising edge of SCK (see
Figure 3). The data output state is concluded once 32 bits
are read out of the ADC or when CS is brought HIGH. The
device automatically initiates a new conversion and the
cycle repeats.
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
2415 F02
Figure 2. LTC2415 State Transition Diagram
Initially, the LTC2415/LTC2415-1 perform a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, power consumption
is reduced by an order of magnitude if CS is HIGH. The
part remains in the sleep state as long as CS is HIGH.
The conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion
just performed. This result is shifted out on the serial data
out pin (SDO) under the control of the serial clock (SCK).
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or 60Hz
plus their harmonics. The filter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2415/LTC2415-1 incorporate a highly
accurate on-chip oscillator. This eliminates the need for
external frequency setting components such as crystals
or oscillators. Clocked by the on-chip oscillator, the
LTC2415 achieves a minimum of 110dB rejection at the
line frequency (50Hz or 60Hz ±2%), while the LTC2415‑1
achieves a minimum of 87db rejection at 50Hz ±2% and
60Hz ±2% simultaneously.
Ease of Use
The LTC2415/LTC2415-1 data output has no latency,
filter settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog voltages is easy.
2415fa
12
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
The LTC2415/LTC2415-1 perform a full-scale calibration
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of full-scale readings with respect to time, supply
voltage change and temperature drift.
Unlike the LTC2410 and LTC2413, the LTC2415 and
LTC2415-1 do not perform an offset calibration every
conversion cycle. This enables the LTC2415/LTC2415-1 to
double their output rate while maintaining line frequency
rejection. The initial offset of the LTC2415/LTC2415-1 is
within 2mV independent of VREF. Based on the LTC2415/
LTC2415-1 new modulator architecture, the temperature
drift of the offset is less then 0.01ppm/°C. More information on the LTC2415/LTC2415-1 offset is described in the
Offset Accuracy and Drift section of this data sheet.
Power-Up Sequence
The LTC2415/LTC2415-1 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 2.2V. This feature guarantees the
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)
When the VCC voltage rises above this critical threshold, the
converter creates an internal power-on-reset (POR) signal
with a duration of approximately 0.5ms. The POR signal
clears all internal registers. Following the POR signal, the
LTC2415/LTC2415-1 start a normal conversion cycle and
follow the succession of states described above. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
These converters accept a truly differential external
reference voltage. The absolute/common mode voltage
specification for the REF+ and REF– pins covers the entire
range from GND to VCC. For correct converter operation, the
REF+ pin must always be more positive than the REF– pin.
The LTC2415/LTC2415-1 can accept a differential reference
voltage from 0.1V to VCC. The converter output noise is
determined by the thermal noise of the front-end circuits,
and as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter’s effective resolution.
On the other hand, a reduced reference voltage will improve
the converter’s overall INL performance.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn
on and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2415/LTC2415-1 convert the bipolar differential input signal, VIN = IN+ – IN–,
from –FS = –0.5 • VREF to +FS = 0.5 • VREF where
VREF = REF+ – REF–. Outside this range, the converters
indicate the overrange or the underrange condition using
distinct output codes.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the performance of the device. In the physical layout, it is important
to maintain the parasitic capacitance of the connection
between these series resistors and the corresponding
pins as low as possible; therefore, the resistors should
be located as close as practical to the pins. The effect of
the series resistance on the converter accuracy can be
evaluated from the curves presented in the Input Current/
Reference Current sections. In addition, series resistors
will introduce a temperature dependent offset error due to
the input leakage current. A 1nA input leakage current will
develop a 1ppm offset error on a 5k resistor if VREF = 5V.
This error has a very strong temperature dependency.
Output Data Format
The LTC2415/LTC2415-1 serial output data stream is 32
bits long. The first 3 bits represent status information
indicating the sign and conversion state. The next 24 bits
2415fa
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13
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
are the conversion result, MSB first. The remaining 5 bits
are sub LSBs beyond the 24-bit level that may be included
in averaging or discarded without loss of resolution. The
third and fourth bit together are also used to indicate an
underrange condition (the differential input voltage is
below –FS) or an overrange condition (the differential
input voltage is above +FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is 0.01µF) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi constant
reference differential impedance. For the LTC2415, when
FO = LOW (internal oscillator and 60Hz notch), the typical
differential reference resistance is 1.3MΩ which will generate a gain error of approximately 0.38ppm for each ohm of
source resistance driving REF+ or REF–. When FO = HIGH
(internal oscillator and 50Hz notch), the typical differential
reference resistance is 1.56MΩ which will generate a gain
error of approximately 0.32ppm for each ohm of source
resistance driving REF+ or REF–. For the LTC2415‑1, the
typical differential reference resistance is 1.43MΩ. When
FO is driven by an external oscillator with a frequency fEOSC
(external conversion clock operation), the typical differen50
VCC = 5V
REF + = 5V
REF – = GND
IN + = 5V
IN – = 2.5V
FO = GND
TA = 25°C
–10
–20
–30
CREF = 0.01µF
CREF = 0.001µF
–40
–50
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
0
CREF = 100pF
CREF = 0pF
1
10
100
1k
RSOURCE (Ω)
10k
40
CREF = 100pF
CREF = 0pF
30
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = 2.5V
FO = GND
TA = 25°C
20
10
0
100k
CREF = 0.01µF
CREF = 0.001µF
1
10
100
1k
RSOURCE (Ω)
2415 F25
Figure 25. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
–180
–360
–450
Figure 26. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
450
CREF = 0.01µF
–90
–270
2415 F26
CREF = 0.1µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CREF = 1µF, 10µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
0
360
270
180
90
0
2415 F27
Figure 27. +FS Error vs RSOURCE at REF+ and REF– (Large CREF)
30
100k
10k
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CREF = 1µF, 10µF
CREF = 0.1µF
CREF = 0.01µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2415 F28
Figure 28. –FS Error vs RSOURCE at REF+ and REF– (Large CREF)
For more information www.linear.com/LTC2415
2415fa
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
tial reference resistance is 0.20 • 1012/fEOSCΩ and each
ohm of source resistance driving REF+ or REF– will result in
2.47 • 10–6 • fEOSCppm gain error. The effect of the source
resistance on the two reference pins is additive with respect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by
the REF+ and REF– pins and external capacitance CREF
connected to these pins are shown in Figures 25, 26, 27
and 28.
In addition to this gain error, the converter INL performance
is degraded by the reference source impedance. When FO
= LOW (internal oscillator and 60Hz notch), every 100Ω of
source resistance driving REF+ or REF– translates into about
1.34ppm additional INL error. For the LTC2415, when FO
= HIGH (internal oscillator and 50Hz notch), every 100Ω
of source resistance driving REF+ or REF– translates into
about 1.1ppm additional INL error; and for the LTC2415‑1
operating with simultaneous 50Hz/60Hz rejection, every
100Ω of source resistance leads to an additional 1.22ppm
of additional INL error. When FO is driven by an external
oscillator with a frequency fEOSC, every 100Ω of source
resistance driving REF+ or REF– translates into about 8.73 •
10–6 • fEOSCppm additional INL error. Figure 26 shows the
typical INL error due to the source resistance driving the
REF+ or REF– pins when large CREF values are used. The
effect of the source resistance on the two reference pins is
additive with respect to this INL error. In general, matching
of source impedance for the REF+ and REF– pins does not
help the gain or the INL error. The user is thus advised
to minimize the combined source impedance driving the
REF+ and REF– pins rather than to try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by REF+
and REF–, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05µV typical and 0.5µV
maximum full-scale error.
15
12
9
INL (ppm OF VREF)
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 0.5 • (IN + + IN –) = 2.5V
FO = GND
CREF = 10µF
TA = 25°C
RSOURCE = 1000Ω
RSOURCE = 500Ω
6
3
0
–3
RSOURCE = 100Ω
–6
–9
–12
–15
–0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5
VINDIF/VREFDIF
2415 F29
Figure 29. INL vs Differential Input Voltage (VIN = IN+ – IN–) and Reference
Source Resistance (RSOURCE at REF+ and REF– for Large CREF Values (CREF ≥ 1µF)
2415fa
For more information www.linear.com/LTC2415
31
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
Normal Mode Rejection, Output Rate and Running
Averages
a running average can be performed. By averaging two
consecutive ADC readings, a Sinc1 notch is combined with
the Sinc4 digital filter yielding the frequency response
shown in Figures 33 and 34. In order to preserve the 2×
output rate, adjacent results are averaged with the following algorithm:
The LTC2415/LTC2415-1 both contain an identical Sinc4
digital filter (see Figures 30 and 31) which offers excellent
line frequency noise rejection. For the LTC2415, a notch
frequency of either 50Hz or 60Hz (see Figure 32) is user
selectable by tying pin FO high or low, respectively. On the
other hand, the LTC2415-1 offers simultaneous rejection
of 50Hz and 60Hz by tying FO low. This sets the notch
frequency to approximately 55Hz (see Figure 32).
Result 1 = average (sample 0, sample 1)
Result 2 = average (sample 1, sample 2)
Result 3 = average (sample 2, sample 3)
…
At a notch frequency of 55Hz, the LTC2415-1 rejects 50Hz
±2% and 60Hz ±2% better than 72dB. In order to achieve
better than 87dB rejection of both 50Hz and 60Hz ±2%,
VCC = 5V
VREF = 5V
VIN = 2.5V
FO = 0
–40
–60
–80
–20
–70
–80
–60
–80
–100
–100
–120
–60
–40
REJECTION (dB)
REJECTION (dB)
–20
0
REJECTION (dB)
0
Result N = average (sample n-1, sample n)
50
100
150
200
FREQUENCY AT VIN (Hz)
–140
250
fS/2
0
fS
INPUT FREQUENCY
Figure 31. Rejection vs Frequency at VIN
0
–90
–20
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION RATIO (dB)
–140
–12
–8
–4
0
4
8
12
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
2415 F32
2415 F31
–80
–100
–100
–120
–130
–140
–110
–130
2415 F30
Figure 30. Rejection vs Frequency at VIN
–100
–120
–120
1
–90
48
50
52
54
56
58
60
62
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
Figure 32. Rejection vs Frequency at VIN
MEASURED DATA
CALCULATED DATA
–40
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN(P-P) = 5V
TA = 25°C
– 60
–80
–100
–120
0
20
40
60
80
100
120
140
INPUT FREQUENCY (Hz)
160
180
200
220
2415 F34
2415 F33
Figure 33. Normal Mode Rejection
when Using an Internal Oscillator
Figure 34. Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 100% of Full Scale
2415fa
32
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
Sample Driver for LTC2415/LTC2415-1 SPI Interface
The code begins by declaring variables and allocating four
memory locations to store the 32-bit conversion result.
This is followed by initializing PORT D’s SPI configuration.
The program then enters the main sequence. It activates
the LTC2415/LTC2415‑1 serial interface by setting the
SS output low, sending a logic low to CS. It next waits in
a loop for a logic low on the data line, signifying end-ofconversion. After the loop is satisfied, four SPI transfers
are completed, retrieving the conversion. The main sequence ends by setting SS high. This places the LTC2415/
LTC2415‑1 serial interface in a high impedance state and
initiates another conversion.
Figure 35 shows the use of an LTC2415/LTC2415‑1 with a
differential multiplexer. This is an inexpensive multiplexer
that will contribute some error due to leakage if used directly
with the output from the bridge, or if resistors are inserted
as a protection mechanism from overvoltage. Although the
bridge output may be within the input range of the A/D and
multiplexer in normal operation, some thought should be
given to fault conditions that could result in full excitation
voltage at the inputs to the multiplexer or ADC. The use of
amplification prior to the multiplexer will largely eliminate
errors associated with channel leakage developing error
voltages in the source impedance.
The performance of the LTC2415/LTC2415‑1 can be verified
using the demonstration board DC291A, see Figure 40 for
the schematic. This circuit uses the computer’s serial port
to generate power and the SPI digital signals necessary
for starting a conversion and reading the result. It includes
a Labview application software program (see Figure 39)
which graphically captures the conversion results. It can
be used to determine noise performance, stability and
with an external source, linearity. As exemplified in the
schematic, the LTC2415/LTC2415‑1 are extremely easy
to use. This demonstration board and associated software
is available by contacting Linear Technology.
The LTC2415/LTC2415‑1 have a very simple serial interface that makes interfacing to microprocessors and
microcontrollers very easy.
The listing in Figure 38 is a simple assembler routine for
the 68HC11 microcontroller. It uses PORT D, configuring it for SPI data transfer between the controller and the
LTC2415/LTC2415‑1. Figure 36 shows the simple 3-wire
SPI connection.
5V
5V
+
16
12
14
15
11
3
REF +
4
REF –
5
2
13
5
3
IN +
6
IN –
6
4
8
9
2
VCC
LTC2415/
LTC2415-1
74HC4052
1
TO OTHER
DEVICES
47µF
10
GND
1, 7, 8, 9,
10, 15, 16
2415 F35
A0
A1
Figure 35. Use a Differential Multiplexer to Expand Channel Capability
SCK
LTC2415/ SDO
LTC2415-1
CS
13
12
11
68HC11
SCK (PD4)
MISO (PD2)
SS (PD5)
2415 F36
Figure 36. Connecting the LTC2415/LTC2415-1 to a 68HC11 MCU Using the SPI Serial Interface
For more information www.linear.com/LTC2415
2415fa
33
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
Correlated Double Sampling with the
LTC2415/LTC2415-1
Figure 37 shows the LTC2415/LTC2415-1 in a correlated
double sampling circuit that achieves a noise floor of
under 100nV. In this scheme, the polarity of the bridge is
alternated every other sample and the result is the average
of a pair of samples of opposite sign. This technique has
the benefit of canceling any fixed DC error components
in the bridge, amplifiers and the converter, as these will
alternate in polarity relative to the signal. Offset voltages
and currents, thermocouple voltages at junctions of dissimilar metals and the lower frequency components of 1/f
noise are virtually eliminated.
The LTC2415/LTC2415-1 have the virtue of being able to
digitize an input voltage that is outside the range defined
by the reference, thereby providing a simple means to
implement a ratiometric example of correlated double
sampling.
This circuit uses a bipolar amplifier (LT1219—U1 and
U2) that has neither the lowest noise nor the highest gain.
It does, however, have an output stage that can effectively suppress the conversion spikes from the LTC2415/
LTC2415-1. The LT1219 is a C-LoadTM stable amplifier
that, by design, needs at least 0.1µF output capacitance to
remain stable. The 0.1µF ceramic capacitors at the outputs
(C1 and C2) should be placed and routed to minimize lead
inductance or their effectiveness in preventing envelope
detection in the input stage will be reduced. Alternatively,
several smaller capacitors could be placed so that lead
inductance is further reduced. This is a consideration
because the frequency content of the conversion spikes
extends to 50MHz or more. The output impedance of most
op amps increases dramatically with frequency but the
effective output impedance of the LT1219 remains low,
determined by the ESR and inductance of the capacitors
above 10MHz. The conversion spikes that remain at the
output of other bipolar amplifiers pass through the feedback
network and often overdrive the input of the amplifier,
producing envelope detection. RFI may also be present
on the signal lines from the bridge; C3 and C4 provide RFI
suppression at the signal input, as well as suppressing
transient voltages during bridge commutation.
The wideband noise density of the LT1219 is 33nV√Hz,
seemingly much noisier than the lowest noise amplifiers.
However, in the region just below the 1/f corner that is
not well suppressed by the correlated double sampling,
the average noise density is similar to the noise density
of many low noise amplifiers. If the amplifier is rolled off
below about 1500Hz, the total noise bandwidth is determined by the converter’s Sinc4 filter at about 12Hz. The
use of correlated double sampling involves averaging even
numbers of samples; hence, in this situation, two samples
would be averaged to give an input-referred noise level of
about 100nVRMS.
Level shift transistors Q4 and Q5 are included to allow
excitation voltages up to the maximum recommended
for the bridge. In the case shown, if a 10V supply is
used, the excitation voltage to the bridge is 8.5V and
the outputs of the bridge are above the supply rail of the
ADC. U1 and U2 are also used to produce a level shift to
bring the outputs within the input range of the converter.
This instrumentation amplifier topology does not require
well-matched resistors in order to produce good CMRR.
However, the use of R2 requires that R3 and R6 match
well, as the common mode gain is approximately –12dB.
If the bridge is composed of four equal 350Ω resistors,
the differential component associated with mismatch of R3
and R6 is nearly constant with either polarity of excitation
and, as with offset, its contribution is canceled.
2415fa
34
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
APPLICATIONS INFORMATION
10V
ELIMINATE FOR 5V
OPERATION (CONNECT 2.7k
RESISTORS TO 100Ω
RESISTORS)
1.5k
1.5k
Q2
100Ω
DIFFERENCE
AMP
10V
0.1µf
Q3
3
100Ω
R2
27k
22Ω
5V
Q4
5V
22Ω
Q5
–
1k
1000pF
2.7k
2
+
7
U1
LT1219
4
5k
6
5
C1
0.1µF
SHDN
5V
R4
499Ω
R3 10k
2.7k
5
C3 2.2nF
C4 2.2nF
350Ω
×4
R5
499Ω
6
IN–
LTC2415/
LTC2415-1
3
REF+
R6 10k
1000pF
10V
POL
0.1µf
1k
74HC04
2
Q1
3
–
+
22Ω
R1
61.9Ω
0.1%
5k
6
REF–
GND
5
C2
0.1µF
SHDN
33Ω
100Ω
22Ω
4
7
U2
LT1219
4
IN+
Q1: SILICONIX Si9802DY
Q2, Q3: MMBD2907
Q4, Q5: MMBD3904
(800) 554-5565
30pF
30pF
2415 F37
Figure 37. Correlated Double Sampling Resolves 100nV
2415fa
For more information www.linear.com/LTC2415
35
LTC2415/LTC2415-1
TYPICAL APPLICATIONS
************************************************************
* This example program transfers the LTC2415/LTC2415-1 32-bit output
*
* conversion result into four consecutive 8-bit memory locations.
************************************************************
*68HC11 register definition
PORTD EQU $1008 Port D data register
*
“ – , – , SS* ,CSK ;MOSI,MISO,TxD ,RxD”
DDRD EQU $1009 Port D data direction register
SPSR EQU $1028 SPI control register
*
“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
SPSR EQU $1029 SPI status register
*
“SPIF,WCOL, – ,MODF; – , – , – , – “
SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter
*
* RAM variables to hold the LTC2415/LTC2415-1’s 32 conversion result
*
DIN1 EQU $00 This memory location holds the LTC2415/LTC2415-1’s bits
DIN2 EQU $01 This memory location holds the LTC2415/LTC2415-1’s bits
DIN3 EQU $02 This memory location holds the LTC2415/LTC2415-1’s bits
DIN4 EQU $03 This memory location holds the LTC2415/LTC2415-1’s bits
*
**********************
* Start GETDATA Routine *
**********************
*
ORG $C000 Program start location
INIT1 LDS #$CFFF Top of C page RAM, beginning location of stack
LDAA #$2F –,–,1,0;1,1,1,1
–, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
*
STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set
LDAA #$38 –,–,1,1;1,0,0,0
STAA DDRD SS*, SCK, MOSI are configured as Outputs
*
MISO, TxD, RxD are configured as Inputs
*DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
LDAA #$50
STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0
and the clock rate is E/2
*
*
(This assumes an E-Clock frequency of 4MHz. For higher EClock frequencies, change the above value of $50 to a value
*
that ensures the SCK frequency is 2MHz or less.)
*
PSHX
GETDATA
PSHY
PSHA
LDX #$0 The X register is used as a pointer to the memory locations
*
that hold the conversion data
LDY #$1000
BCLR PORTD, Y %00100000 This sets the SS* output bit to a logic
* low, selecting the LTC2415/LTC2415-1
*
*
31
23
15
07
-
24
16
08
00
2415fa
36
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
TYPICAL APPLICATIONS
********************************************
* The next short loop waits for the
*
* LTC2415/LTC2415-1’s conversion to finish before
*
* starting the SPI data transfer
*
********************************************
*
CONVEND
LDAA PORTD
Retrieve the contents of port D
ANDA #%00000100 Look at bit 2
*
Bit 2 = Hi; the LTC2415/LTC2415-1’s conversion is not
*
complete
*
Bit 2 = Lo; the LTC2415/LTC2415-1’s conversion is complete
BNE CONVEND Branch to the loop’s beginning while bit 2 remains
high
*
*
********************
* The SPI data transfer *
********************
*
TRFLP1 LDAA #$0 Load accumulator A with a null byte for SPI transfer
STAA SPDR This writes the byte in the SPI data register and starts
*
the transfer
WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial
transfer/exchange by reading the SPI Status Register
BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR’s MSB
and is set to one at the end of an SPI transfer. The branch
*
*
will occur while SPIF is a zero.
LDAA SPDR Load accumulator A with the current byte of LTC2415/LTC2415-1 data
that was just received
STAA 0,X Transfer the LTC2415/LTC2415-1’s data to memory
INX
Increment the pointer
CPX #DIN4+1
Has the last byte been transferred/exchanged?
BNE TRFLP1 If the last byte has not been reached, then proceed to the
*
next byte for transfer/exchange
BSET PORTD,Y %00100000 This sets the SS* output bit to a logic high,
de-selecting the LTC2415/LTC2415-1
*
PULA
Restore the A register
PULY
Restore the Y register
PULX
Restore the X register
RTS
Figure 38. This is an Example of 68HC11 Code That Captures the LTC2415/LTC2415-1
Conversion Results Over the SPI Serial Interface Shown in Figure 40
2415fa
For more information www.linear.com/LTC2415
37
LTC2415/LTC2415-1
TYPICAL APPLICATIONS
Figure 39. Display Graphic
PCB LAYOUT AND FILM
LTC2415CGN
Differential Input 24-Bit ADC
with 2¥ Output Rate
Demo Circuit DC382
www.linear-tech.com
LTC Confidential For Customer Use Only
Silkscreen Top
Top Layer
2415fa
38
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
PCB LAYOUT AND FILM
Bottom Layer
2415fa
For more information www.linear.com/LTC2415
39
LTC2415/LTC2415-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ±.004
× 45°
(0.38 ±0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.0250
(0.635)
BSC
GN16 REV B 0212
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2415fa
40
For more information www.linear.com/LTC2415
LTC2415/LTC2415-1
REVISION HISTORY
REV
DATE
DESCRIPTION
A
08/15
Reduced external oscillator maximum frequency to 500kHz.
PAGE NUMBER
Removed noise histogram plots for 105Hz output rate.
Adjusted output data rate on G27 to maximum of 50 readings/second.
5
6, 7
9
2415fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC2415
41
LTC2415/LTC2415-1
TYPICAL APPLICATION
VCC
U1
LT1460ACN8-2.5
JP1
JUMPER
1
3
6 VOUT
+
2
VIN
VCC
2
GND
C1
10µF
35V
R2
3Ω
+
4
U2
LT1236ACN8-5
JP2
JUMPER
1
2
6 VOUT
+
C2
22µF
25V
C3
10µF
35V
+
4
10
VCC
J5
GND
1
C6
0.1µF
1
BANANA JACK
J6 1
REF +
+
3
4
5
BANANA JACK
J7 1
REF –
6
BANANA JACK
J8 1
VIN+
C5
10µF
35V
1
J2
GND
2
11
CS
FO
REF –
SCK
VIN+
SDO
VIN –
6
13
R3
51k
2
7
3
8
2
VCC
REF +
12
11
U4
LTC2415/
LTC2415-1
GND
GND
GND
U3B
74HC14
4
4
9
U3A
74HC14
3
2
5
R4
51k
1
14
13
U3C
74HC14
12
16
15
5
U3D
74HC14
6
10
9
R5
49.9Ω
R6
3k
8
1
R7
22k
3
2
R8
51k
JP5
JUMPER
2
J1
VEXT
P1
DB9
U3F
74HC14
GND GND GND GND
1
7
8
9
1
1
3
C4
100µF
16V
1
JP4
JUMPER
1
3
VCC
J3
BANANA JACK
J10 1
GND
2
GND
U3E
74HC14
2
BANANA JACK
J9 1
VIN –
R1
10Ω
1
JP3
JUMPER
1
3
BANANA JACK
J4 1
VEXT
VIN
D1
BAV74LT1
2
Q1
MMBT3904LT1
VCC
NOTES:
INSTALL JUMBER JP1 AT PIN 1 AND PIN 2
INSTALL JUMBER JP2 AT PIN 1 AND PIN 2
INSTALL JUMBER JP3 AT PIN 1 AND PIN 2
BYPASS CAP
FOR U3
C7
0.1µF
2415 F40
Figure 40. 24-Bit A/D Demo Board Schematic
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/°C Drift, 0.05% Max Initial Accuracy
LT1025
Micropower Thermocouple Cold Junction Compensator
80µA Supply Current, 0.5°C Initial Accuracy
LTC1043
Dual Precision Instrumentation Switched Capacitor Building Block Precise Charge, Balanced Switching, Low Power
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5µV Offset, 1.6µVP-P Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/°C Max Drift,
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402
1-/2-Channel, 24-Bit, No Latency ∆Σ ADCs in MSOP
LTC2414/LTC2418
4-/8-Channel, 24-Bit, No Latency ∆Σ ADCs with Differential Inputs 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410
24-Bit, No Latency ∆Σ ADC with Differential Inputs
800nVRMS Noise, Pin Compatible with LTC2415
LTC2411
24-Bit, No Latency ∆Σ ADC with Differential Inputs in MSOP
1.45µVRMS Noise, 4ppm INL
LTC2413
24-Bit, No Latency ∆Σ ADC with Differential Inputs
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2420
20-Bit, No Latency ∆Σ ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
2415fa
42 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2415
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2415
LT 0815 REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2001
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湘ICP备2023018690号
