LTC2439-1
8-/16-Channel
16-Bit No Latency ∆Σ™ ADC
FEATURES
DESCRIPTION
16-Channel Single-Ended or 8-Channel Differential
Inputs
nn Low Supply Current (200µA, 4µA in Autosleep)
nn Rail-to-Rail Differential Input/Reference
nn 16-Bit No Missing Codes
nn 1µV RMS Noise, 16-ENOBS Independent of V
REF
nn Very Low Transition Noise: Less Than 0.02LSB
nn Operates with a Reference as Low as 100mV with
1.5µV LSB Step Size
nn Guaranteed Modulator Stability and Lock-Up
Immunity for Any Input and Reference Conditions
nn Single Supply 2.7V to 5.5V Operation
nn Internal Oscillator—No External Components
Required
nn 87dB Min, 50Hz and 60Hz Simultaneous Notch Filter
nn Pin Compatible with the 24-Bit LTC2418
nn 28-Lead SSOP Packag
The LTC®2439-1 is a 16-channel (8-differential) micropower
16-bit ∆Σ analog-to-digital converter. It operates from 2.7V
to 5.5V and includes an integrated oscillator, 0.12LSB
INL and 1µV RMS noise. It uses delta-sigma technology
and provides single cycle settling time for multiplexed
applications. Through a single pin, the LTC2439-1 can be
configured for better than 87dB differential mode rejection
at 50Hz and 60Hz ±2%, or it can be driven by an external
oscillator for a user-defined rejection frequency. The
internal oscillator requires no external frequency setting
components.
nn
The LTC2439-1 accepts any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and remote
sensing measurement applications. It can be configured
to take 8 differential channels or 16 single-ended channels. The full-scale bipolar input range is from –0.5VREF
to 0.5VREF. The reference common mode voltage, VREFCM,
and the input common mode voltage, VINCM, may be independently set between GND and VCC. The DC common
mode input rejection is better than 140dB.
APPLICATIONS
Direct Sensor Digitizer
Weight Scales
nn Direct Temperature Measurement
nn Gas Analyzers
nn Strain Gauge Transducers
nn Instrumentation
nn Data Acquisition
nn Industrial Process Control
nn
nn
The LTC2439-1 communicates through a flexible
4-wire digital interface that is compatible with SPI and
MICROWIRE protocols.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No
Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
Minimum Resolvable
Signal vs VREF
2.7V TO 5.5V
THERMOCOUPLE
21 CH0
22 CH1
•
•
•
28 CH7
1 CH8
•
•
•
8 CH15
REF +
1µF
9
VCC
FO
16-CHANNEL
MUX
+
–
DIFFERENTIAL
16-BIT ∆Σ ADC
SDI
SCK
SDO
CS
19
20
18
17
16
= EXTERNAL OSCILLATOR
= 50Hz and 60Hz REJECTION
4-WIRE
SPI INTERFACE
10 COM
12 REF –
15
GND
MINIMUM RESOLVABLE SIGNAL (µV)
90
11
80
70
60
50
40
30
20
10
0
LTC2439-1
241418 TA01a
0
5
4
3
VREF (V)
24361 TA02
*FOR VREF = 0.4V RESOLUTION IS LIMITED BY STEP SIZE
1
2
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1
LTC2439-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Supply Voltage (VCC) to GND........................ –0.3V to 7V
Analog Input Voltage to GND.........–0.3V to (VCC + 0.3V)
Reference Input Voltage to GND....–0.3V to (VCC + 0.3V)
Digital Input Voltage to GND..........–0.3V to (VCC + 0.3V)
Digital Output Voltage to GND........–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2439-1C.............................................. 0°C to 70°C
LTC2439-1I...........................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
CH8
1
28 CH7
CH9
2
27 CH6
CH10
3
26 CH5
CH11
4
25 CH4
CH12
5
24 CH3
CH13
6
23 CH2
CH14
7
22 CH1
CH15
8
21 CH0
VCC
9
20 SDI
COM 10
19 FO
REF+ 11
18 SCK
–
17 SDO
12
REF
NC 13
16 CS
NC 14
15 GND
GN PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2439-1CGN#PBF
LTC2439-1CGN#TRPBF
LTC2439-1CGN
28-Lead Plastic SSOP
0°C to 70°C
LTC2439-1IGN#PBF
LTC2439-1IGN#TRPBF
LTC2439-1IGN
28-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5)
Integral Nonlinearity
4.5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6)
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Notes 6, 15)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC, (Notes 12,15)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+ (Note 15)
Offset Error
Offset Error Drift
Positive Full-Scale Error
Positive Full-Scale Error Drift
MIN
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+
l
TYP
MAX
16
UNITS
Bits
l
0.06
0.12
0.30
1.25
LSB
LSB
LSB
l
5
20
µV
10
l
0.16
0.03
nV/°C
1.25
LSB
ppm of VREF/°C
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LTC2439-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Negative Full-Scale Error
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+ (Note 15)
MIN
Negative Full-Scale Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
l
TYP
MAX
UNITS
0.16
1.25
LSB
0.03
ppm of VREF/°C
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
5V ≤ VCC ≤ 5.5V, REF+ = 5V, VREF– = GND,
GND ≤ IN– = IN+ ≤ 5V (Note 12)
Output Noise
MIN
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC, (Note 5)
Input Normal Mode Rejection
49Hz to 61.2Hz
(Note 5)
Reference Common Mode
Rejection DC
2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V,
VREF = 2.5V, IN– = IN+ = GND (Note 5)
Power Supply Rejection, DC
Power Supply Rejection,
Simultaneous 50Hz/60Hz ±2%
MAX
UNITS
LSB
LSB
0.20
0.20
1
Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC (Note 5)
Input Common Mode Rejection
49Hz to 61.2Hz
TYP
µVRMS
l
130
140
dB
l
140
dB
l
87
dB
l
130
140
dB
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND
120
dB
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND
120
dB
ANALOG INPUT AND REFERENCE
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
CONDITIONS
MIN
TYP
MAX
l
GND – 0.3
VCC + 0.3
V
IN–
Absolute/Common Mode IN– Voltage
l
GND – 0.3
VCC + 0.3
V
VIN
Input Differential Voltage Range (IN+ – IN–)
l
–VREF/2
VREF/2
V
REF+
Absolute/Common Mode REF+ Voltage
l
0.1
VCC
V
REF–
Absolute/Common Mode REF– Voltage
l
GND
VCC – 0.1
V
VREF
Reference Differential Voltage Range
(REF+ – REF–)
l
0.1
VCC
V
CS (IN+)
IN+ Sampling Capacitance
18
pF
CS (IN–)
IN– Sampling Capacitance
18
pF
CS
(REF+)
REF+ Sampling Capacitance
18
pF
CS
(REF–)
REF– Sampling Capacitance
18
UNITS
pF
IDC_LEAK (IN+)
IN+ DC Leakage Current
CS = VCC = 5.5V, IN+ = GND
l
–100
1
100
nA
IDC_LEAK (IN–)
IN– DC Leakage Current
CS = VCC = 5.5V, IN– = 5V
l
–100
1
100
nA
l
–100
1
100
nA
l
–100
1
100
nA
(REF+)
REF+ DC Leakage Current
CS = VCC
IDC_LEAK (REF–)
REF– DC Leakage Current
CS = VCC = 5.5V, REF– = GND
IDC_LEAK
= 5.5V, REF+ = 5V
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LTC2439-1
ANALOG INPUT AND REFERENCE
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
Off Channel to On Channel Isolation
(RIN = 100Ω)
DC
1Hz
fS = 15,3600Hz
MIN
TYP
140
140
140
dB
dB
dB
tOPEN
MUX Break-Before-Make Interval
2.7V ≤ VCC ≤ 5.5V
100
ns
IS(OFF)
Channel Off Leakage Current
Channel at VCC and GND
–100
l
1
MAX
UNITS
100
nA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
CS, FO, SDI
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
l
VIL
Low Level Input Voltage
CS, FO, SDI
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
l
VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 8)
2.7V ≤ VCC ≤ 3.3V (Note 8)
l
VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 8)
2.7V ≤ VCC ≤ 5.5V (Note 8)
l
IIN
Digital Input Current
CS, FO, SDI
0V ≤ VIN ≤ VCC
l
IIN
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 8)
l
CIN
Digital Input Capacitance
CS, FO, SDI
CIN
Digital Input Capacitance
SCK
(Note 8)
VOH
High Level Output Voltage
SDO
IO = –800µA
l
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
l
VOH
High Level Output Voltage
SCK
IO = –800µA (Note 9)
l
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 9)
l
IOZ
Hi-Z Output Leakage
SDO
l
TYP
MAX
UNITS
2.5
2.0
V
V
0.8
0.6
V
V
2.5
2.0
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
10
pF
10
pF
VCC – 0.5
V
0.4
V
VCC – 0.5
V
–10
0.4
V
10
µA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
Sleep Mode
CONDITIONS
MIN
l
CS = 0V (Note 11)
CS = VCC (Note 11)
CS = VCC, 2.7V ≤ VCC ≤ 3.3V (Note 11, 14)
l
l
TYP
2.7
200
4
2
MAX
UNITS
5.5
V
300
15
µA
µA
µA
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LTC2439-1
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
MAX
UNITS
fEOSC
External Oscillator Frequency Range
CONDITIONS
l
2.56
MIN
TYP
2000
kHz
tHEO
External Oscillator High Period
l
0.25
390
µs
tLEO
External Oscillator Low Period
l
0.25
390
tCONV
Conversion Time
FO = 0V
External Oscillator (Note 10)
l
l
143.8
146.7
149.6
20510/fEOSC (in kHz)
ms
ms
fISCK
Internal SCK Frequency
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
17.5
fEOSC/8
kHz
kHz
DISCK
Internal SCK Duty Cycle
(Note 9)
l
fESCK
External SCK Frequency Range
(Note 8)
l
tLESCK
External SCK Low Period
(Note 8)
l
250
ns
tHESCK
External SCK High Period
(Note 8)
l
250
ns
tDOUT_ISCK
Internal SCK 19-Bit Data Output Time
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
l
l
1.06
tDOUT_ESCK
External SCK 19-Bit Data Output Time
(Note 7)
l
t1
CS ↓ to SDO Low
l
0
200
ns
t2
CS ↑ to SDO High Z
l
0
200
ns
t3
CS ↓ to SCK ↓
(Note 9)
l
0
200
ns
t4
CS ↓ to SCK ↑
(Note 8)
l
50
tKQMAX
SCK ↓ to SDO Valid
tKQMIN
SDO Hold After SCK ↓
t5
45
55
%
2000
kHz
1.09
1.11
152/fEOSC (in kHz)
ms
ms
19/fESCK (in kHz)
ms
ns
220
l
µs
ns
l
15
ns
SCK Set-Up Before CS ↓
l
50
ns
t6
SCK Hold After CS ↓
l
t7
SDI Setup Before SCK↑
(Note 5)
l
100
ns
t8
SDI Hold After SCK↑
(Note 5)
l
100
ns
(Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN–,
VINCM = (IN+ + IN–)/2, IN+ and IN– are defined as the selected positive and
negative input respectively.
Note 4: FO pin tied to GND or to VCC or to external conversion clock source
with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a precise analog input voltage. Maximum specifications are limited by
the LSB step size (VREF/216) and the single shot measurement. Typical
specifications are measured from the center of the quantization band.
Note 7: FO = GND (internal oscillator) or fEOSC = 139800Hz ±2% (external
oscillator).
50
ns
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in kHz.
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used as digital output. In this mode of operation the SCK pin
has a total equivalent load capacitance CLOAD = 20pF.
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 12: 1µV RMS noise is independent of VREF. Since the noise
performance is limited by the quantization, lowering VREF improves the
effective resolution.
Note 13: Guaranteed by design and test correlation.
Note 14: The low sleep mode current is valid only when CS is high.
Note 15: These parameters are guaranteed by design over the full supply
and temperature range. Automated testing procedures are limited by the
LSB Step Size (VREF/216).
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5
LTC2439-1
PIN FUNCTIONS
CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8):
Analog Inputs. May be programmed for single-ended or
differential mode.
VCC (Pin 9): Positive Supply Voltage. Bypass to GND
(Pin 15) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
COM (Pin 10): The common negative input (IN–) for all
single-ended multiplexer configurations. The voltage on
Channel 0 to 15 and COM input pins can have any value
between GND – 0.3V and VCC + 0.3V. Within these limits,
the two selected inputs (IN+ and IN–) provide a bipolar
input range (VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF.
Outside this input range, the converter produces unique
overrange and underrange output codes.
REF+ (Pin 11), REF– (Pin 12): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the positive reference input, REF+,
is maintained more positive than the negative reference
input, REF–, by at least 0.1V.
GND (Pin 15): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 16): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 17): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = VCC), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
SCK (Pin 18): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the
Data Output period. In External Serial Clock Operation
mode, SCK is used as the digital input for the external serial interface clock during the Data Output period. A weak
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode
is determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
FO (Pin 19): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to GND (FO = 0V), the
converter uses its internal oscillator and rejects 50Hz and
60Hz simultaneously. When FO is driven by an external
clock signal with a frequency fEOSC, the converter uses
this signal as its system clock and the digital filter has
87dB minimum rejection in the range fEOSC/2560 ±14%
and 110dB minimum rejection at fEOSC/2560 ±4%.
SDI (Pin 20): Serial Digital Data Input. During the Data
Output period, this pin is used to shift in the multiplexer
address started from the first rising SCK edge. During the
Conversion and Sleep periods, this pin is in the DON’T
CARE state. However, a HIGH or LOW logic level should
be maintained on SDI in the DON’T CARE mode to avoid
an excessive current in the SDI input buffers.
NC (Pins 13, 14): Not Internally Connected. Do not connect or connect to ground.
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LTC2439-1
FUNCTIONAL BLOCK DIAGRAM
VCC
AUTOCALIBRATION
AND CONTROL
REF +
REF –
GND
CH0
CH1
•
•
•
CH15
COM
IN +
MUX
IN –
–
FO
(INT/EXT)
INTERNAL
OSCILLATOR
+
DIFFERENTIAL
3RD ORDER
∆Σ MODULATOR
SDI
SCK
SDO
CS
SERIAL
INTERFACE
ADDRESS
DECIMATING FIR
24391 F01
Figure 1
TEST CIRCUITS
VCC
SDO
1.69k
1.69k
CLOAD = 20pF
SDO
CLOAD = 20pF
241418 TC01
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
241418 TC02
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
APPLICATIONS INFORMATION
CONVERTER OPERATION
POWER UP
IN + = CH0, IN – = CH1
Converter Operation Cycle
CONVERT
The LTC2439-1 is a multichannel, low power, delta-sigma
analog-to-digital converter with an easy-to-use 4‑wire
serial interface (see Figure 1). Its operation is made up
of three states. The converter operating cycle begins with
the conversion, followed by the low power sleep state and
ends with the data input/output (see Figure 2). The 4-wire
interface consists of serial data input (SDI), serial data
output (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2439-1 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
While in the sleep state, power consumption is reduced by
nearly two orders of magnitude. The conversion result is
held indefinitely in a static shift register while the converter
is in the sleep state.
SLEEP
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
ADDRESS INPUT
24391 F02
Figure 2. LTC2439-1 State Transition Diagram
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LTC2439-1
APPLICATIONS INFORMATION
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to
the low power sleep mode and the conversion result is
still held in the internal static shift register. If CS remains
LOW after the first rising edge of SCK, the device begins
outputting the conversion result and inputting channel
selection bits. Taking CS high at this point will terminate
the data output state and start a new conversion. The
channel selection control bits are shifted in through SDI
from the first rising edge of SCK and depending on the
control bits, the converter updates its channel selection
immediately and is valid for the next conversion. The details
of channel selection control bits are described in the Input
Data Mode section. The output data is shifted out the SDO
pin under the control of the serial clock (SCK). The output
data is updated on the falling edge of SCK allowing the
user to reliably latch data on the rising edge of SCK (see
Figure 3). The data output state is concluded once 19
bits are read out of the ADC or when CS is brought HIGH.
The device automatically initiates a new conversion and
the cycle repeats. In order to maintain compatibility with
24-/32-bit data transfers, it is possible to clock the
LTC2439‑1 with additional serial clock pulses. This results
in additional data bits which are always logic HIGH.
Through timing control of the CS and SCK pins, the
LTC2439-1 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require programming
configuration registers; moreover, they do not disturb the
cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing
Modes section.
CS
SDO
Hi-Z
BIT18
BIT17
BIT16
BIT15
BIT14
EOC
(0)
SIG
MSB
B22
BIT13
BIT12
BIT11
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
LSB
CONVERSON RESULT
SCK
SDI
(1)
(0)
EN
SGL
ODD/
SIGN
A2
A1
SLEEP
A0
DON’T CARE
DATA INPUT/OUTPUT
CONVERSION
Figure 3a. Input/Output Data Timing
CONVERSION RESULT
N–1
SDO
24391 F03a
CONVERSION RESULT
N
CONVERSION RESULT
N+1
Hi-Z
Hi-Z
Hi-Z
SCK
SDI
ADDRESS
N
OPERATION
DON’T CARE
DON’T CARE
OUTPUT
N–1
ADDRESS
N+1
CONVERSION N
OUTPUT
N
ADDRESS
N+2
CONVERSION N + 1
Figure 3b. Typical Operation Sequence
OUTPUT
N+1
24391 F03b
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LTC2439-1
APPLICATIONS INFORMATION
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz and
60Hz plus their harmonics. The filter rejection performance
is directly related to the accuracy of the converter system
clock. The LTC2439-1 incorporates a highly accurate
on-chip oscillator. This eliminates the need for external
frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2436‑1
achieves a minimum of 87dB rejection over the range
49Hz to 61.2Hz.
Ease of Use
The LTC2439-1 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2439-1 performs offset and full-scale calibrations
in every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2439-1 automatically enters an internal reset
state when the power supply voltage VCC drops below
approximately 2V. This feature guarantees the integrity
of the conversion result and of the serial interface mode
selection. (See the 3-wire I/O sections in the Serial Interface
Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a typical duration of 1ms. The POR signal
clears all internal registers. Following the POR signal,
the LTC2439-1 starts a normal conversion cycle and
follows the succession of states described above. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
The LTC2439-1 accepts a truly differential external reference voltage. The absolute/common mode voltage specification for the REF+ and REF– pins covers the entire range
from GND to VCC. For correct converter operation, the
REF+ pin must always be more positive than the REF– pin.
The LTC2439-1 can accept a differential reference voltage
from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and
as such, its value in microvolts is nearly constant with
reference voltage. A decrease in reference voltage will
significantly improve the converter’s effective resolution,
since the thermal noise (1µV) is well below the quantization level of the device (75.6µV for a 5V reference).
At the minimum reference (100mV) the thermal noise
remains constant at 1µV RMS (or 6µVP-P), while the
quantization is reduced to 1.5µV per LSB. As a result,
lowering the reference improves the effective resolution
for low level input voltages.
Input Voltage Range
The two selected pins are labeled IN+ and IN– (see Table
1). Once selected (either differential or single-ended
multiplexing mode), the analog input is differential with
a common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside these
limits, the ESD protection devices begin to turn on and
the errors due to input leakage current increase rapidly.
Within these limits, the LTC2439-1 converts the bipolar
differential input signal, VIN = IN+ – IN–, from –FS = –0.5
• VREF to +FS = 0.5 • VREF where VREF = REF+ – REF–.
Outside this range the converter indicates the overrange
or the underrange condition using distinct output codes.
Input signals applied to IN+ and IN– pins may extend
300mV below ground or above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ or IN– pins without affecting the performance
of the device. In the physical layout, it is important to main24391fb
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9
LTC2439-1
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tain the parasitic capacitance of the connection between
these series resistors and the corresponding pins as low
as possible; therefore, the resistors should be located as
close as practical to the pins. In addition, series resistors
will introduce a temperature dependent offset error due
to the input leakage current. A 10nA input leakage current
will develop a 1LBS offset error on an 8k resistor if VREF =
5V. This error has a very strong temperature dependency.
Table 1. Channel Selection
MUX ADDRESS
ODD/
SGL SIGN
CHANNEL SELECTION
A2
A1
A0
0
1
* 0
0
0
0
0
IN+
IN–
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
IN–
2
3
IN+
IN–
4
5
IN+
IN–
6
7
IN+
IN–
8
9
IN+
IN–
10
11
IN+
IN–
12
13
IN+
IN–
14
15
IN+
IN–
IN–
IN+
COM
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
*Default at power up
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Input Data Format
When the LTC2439-1 is powered up, the default selection
used for the first conversion is IN+ = CH0 and IN– = CH1
(Address = 00000). In the data input/output mode following
the first conversion, a channel selection can be updated
using an 8-bit word. The LTC2439-1 serial input data is
clocked into the SDI pin on the rising edge of SCK (see
Figure 3a). The input is composed of an 8-bit word with
the first 3 bits acting as control bits and the remaining 5
bits as the channel address bits.
The first 2 bits are always 10 for proper updating operation. The third bit is EN. For EN = 1, the following 5 bits
are used to update the input channel selection. For EN =
0, previous channel selection is kept and the following bits
are ignored. Therefore, the address is updated when the 3
control bits are 101 and kept for 100. Alternatively, the 3
control bits can be all zero to keep the previous address.
This alternation is intended to simplify the SDI interface
allowing the user to simply connect SDI to ground if no
update is needed. Combinations other than 101, 100 and
000 of the 3 control bits should be avoided.
When update operation is set (101), the following 5 bits
are the channel address. The first bit, SGL, decides if the
differential selection mode (SGL = 0) or the single-ended
selection mode is used (SGL = 1). For SGL = 0, two adjacent
channels can be selected to form a differential input; for
SGL = 1, one of the 16 channels (CH0-CH15) is selected
as the positive input and the COM pin is used as the negative input. For a given channel selection, the converter will
measure the voltage between the two channels indicated
by IN+ and IN– in the selected row of Table 1.
Output Data Format
The LTC2439-1 serial output data stream is 19 bits long.
The first 3 bits represent status information indicating the
conversion state and sign. The next 16 bits are the conversion result, MSB first. The third and fourth bit together are
also used to indicate an underrange condition (both bits
low means the differential input voltage is below –FS) or an
overrange condition (both bits high means the differential
input voltage is above +FS).
Bit 18 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 17 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 16 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is 0.01µF) may be
required in certain configurations for anti-aliasing or general input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 50Hz/60Hz notch),
the typical differential input resistance is 2MΩ which will
generate a gain error of approximately 1LSB at full scale
for each 60Ω of source resistance driving IN+ or IN–. When
FO is driven by an external oscillator with a frequency
fEOSC (external conversion clock operation), the typical
differential input resistance is 0.28 • 1012/fEOSCΩ and each
ohm of source resistance driving IN+ or IN– will result in
VINCM + 0.5VIN
IN +
CIN
CPAR
≅ 20pF
RSOURCE
VINCM – 0.5VIN
LTC2439-1
IN –
CIN
CPAR
≅ 20pF
24361 F13
Figure 13. An RC Network at IN+ and IN–
3
CIN = 0.01µF
CIN = 0.001µF
+FS ERROR (LSB)
For relatively small values of input capacitance (CIN <
0.01µF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the source
impedance result in only small errors. Such values for CIN
will deteriorate the converter offset and gain performance
without significant benefits of signal filtering and the user
is advised to avoid them. Nevertheless, when small values
of CIN are unavoidably present as parasitics of input multiplexers, wires, connectors or sensors, the LTC2439-1 can
maintain its accuracy while operating with relative large
values of source resistance as shown in Figures 14 and 15.
These measured results may be slightly different from the
first order approximation suggested earlier because they
include the effect of the actual second order input network
together with the nonlinear settling process of the input
amplifiers. For small CIN values, the settling on IN+ and
IN– occurs almost independently and there is little benefit
in trying to match the source impedance for the two pins.
RSOURCE
CIN = 100pF
2
CIN = 0pF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 5V
IN – = 2.5V
FO = GND
TA = 25°C
1
0
1
10
100
1k
RSOURCE (Ω)
10k
100k
24361 F14
Figure 14. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
0
–FS ERROR (LSB)
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 13. The CPAR capacitor
includes the LTC2439-1 pin capacitance (5pF typical)
plus the capacitance of the test fixture used to obtain the
results shown in Figures 14 and 15. A careful implementation can bring the total input capacitance (CIN + CPAR)
closer to 5pF thus achieving better performance than the
one predicted by Figures 14 and 15. For simplicity, two
distinct situations can be considered.
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = 2.5V
FO = GND
TA = 25°C
–1
CIN = 0.01µF
–2
CIN = 0.001µF
CIN = 100pF
–3
CIN = 0pF
1
10
100
1k
RSOURCE (Ω)
10k
100k
24361 F15
Figure 15. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
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If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are used
for the external source impedance seen by IN+ and IN–,
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
+FS ERROR (LSB)
16
12
CIN = 1µF, 10µF
CIN = 0.1µF
8
CIN = 0.01µF
4
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
24361 F16
Figure 16. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
0
CIN = 0.01µF
–4
–FS ERROR (LSB)
In addition to this gain error, an offset error term may
also appear. The offset error is proportional with the
mismatch between the source impedance driving the two
input pins IN+ and IN– and with the difference between the
input and reference common mode voltages. While the
input drive circuit nonzero source impedance combined
with the converter average input current will not degrade
the INL performance, indirect distortion may result from
the modulation of the offset error by the common mode
component of the input signal. Thus, when using large
CIN capacitor values, it is advisable to carefully match the
source impedance seen by the IN+ and IN– pins. When FO
= LOW (internal oscillator and 50Hz/60Hz notch), every
60Ω mismatch in source impedance transforms a fullscale common mode input signal into a differential mode
input signal of 1LSB. When FO is driven by an external
oscillator with a frequency fEOSC, every 1Ω mismatch in
source impedance transforms a full-scale common mode
input signal into a differential mode input signal of 1.11 •
10–7 • fEOSCLSB. Figure 18 shows the typical offset error
due to input common mode voltage for various values of
source resistance imbalance between the IN+ and IN– pins
when large CIN values are used.
20
–8
CIN = 0.1µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
–12
–16
–20
CIN = 1µF, 10µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
24361 F17
Figure 17. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
8
VCC = 5V
REF + = 5V
REF – = GND
IN + = IN – = VINCM
A
OFFSET ERROR (LSB)
1.11 • 10–7 • fEOSCLSB gain error at full scale. The effect
of the source resistance on the two input pins is additive
with respect to this gain error. The typical +FS and –FS
errors as a function of the sum of the source resistance
seen by IN+ and IN– for large values of CIN are shown in
Figures 16 and 17.
4
B
C
D
0
E
F
–4
–8
FO = GND
TA = 25°C
RSOURCEIN – = 500Ω
CIN = 10µF
G
0
0.5
1
1.5
A: ∆RIN = +400Ω
B: ∆RIN = +200Ω
C: ∆RIN = +100Ω
D: ∆RIN = 0Ω
2 2.5 3
VINCM (V)
3.5
4
4.5
5
E: ∆RIN = –100Ω
F: ∆RIN = –200Ω
G: ∆RIN = –400Ω
24361 F18
Figure 18. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance
Imbalance (∆RIN = RSOURCEIN+ – RSOURCEIN–) for
Large CIN Values (CIN ≥ 1µF)
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LTC2439-1
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the expected drift of the dynamic current, offset and gain
errors will be insignificant (about 1% of their respective
values over the entire temperature and voltage range). Even
for the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 15k source resistance will create
a 0LSB typical and 1LSB maximum offset voltage.
Reference Current
In a similar fashion, the LTC2439-1 samples the differential
reference pins REF+ and REF– transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in the same two distinct situations.
For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01µF)
may be required as reference filters in certain configurations. Such capacitors will average the reference sampling
3
VCC = 5V
REF + = 5V
REF – = GND
IN + = 5V
IN – = 2.5V
FO = GND
TA = 25°C
–1
In addition to this gain error, the converter INL performance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 50Hz/60Hz notch),
every 1000Ω of source resistance driving REF+ or REF–
translates into about 1LSB additional INL error. When FO
is driven by an external oscillator with a frequency fEOSC,
every 100Ω of source resistance driving REF+ or REF–
translates into about 5.5 • 10–7 • fEOSCLSB additional INL
error. Figure 23 shows the typical INL error due to the
source resistance driving the REF+ or REF– pins when large
CREF values are used. The effect of the source resistance
on the two reference pins is additive with respect to this
INL error. In general, matching of source impedance for
CREF = 0.01µF
CREF = 0.001µF
–FS ERROR (LSB)
+FS ERROR (LSB)
0
charge and the external source resistance will see a quasi
constant reference differential impedance. When FO =
LOW (internal oscillator and 50Hz/60Hz notch), the typical differential reference resistance is 1.4MΩ which will
generate a gain error of approximately 1LSB full scale
for each 40Ω of source resistance driving REF+ or REF–.
When FO is driven by an external oscillator with a frequency
fEOSC (external conversion clock operation), the typical
differential reference resistance is 0.20 • 1012/fEOSCΩ and
each ohm of source resistance driving REF+ or REF– will
result in 1.54 • 10–7 • fEOSCLSB gain error at full scale.
The effect of the source resistance on the two reference
pins is additive with respect to this gain error. The typical
+FS and –FS errors for various combinations of source
resistance seen by the REF+ and REF– pins and external
capacitance CREF connected to these pins are shown in
Figures 19, 20, 21 and 22.
CREF = 0.01µF
–2
CREF = 100pF
2
CREF = 0pF
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = 2.5V
FO = GND
TA = 25°C
1
CREF = 0.001µF
CREF = 100pF
–3
CREF = 0pF
1
10
100
1k
RSOURCE (Ω)
10k
100k
0
1
24361 F19
Figure 19. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
24
10
100
1k
RSOURCE (Ω)
10k
100k
2412 F19
Figure 20. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
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0
30
CREF = 0.01µF
22
11
17
22
30
–FS ERROR (LSB)
+FS ERROR (LSB)
6
CREF = 0.1µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
17
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CREF = 0.1µF
11
CREF = 0.01µF
6
CREF = 1µF, 10µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
24361 F21
Figure 21. +FS Error vs RSOURCE at REF+ and REF– (Large CREF)
INL (LSB)
1
RSOURCE = 1000Ω
0
–1
–0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5
VINDIF/VREFDIF
VCC = 5V
FO = GND
REF+ = 5V
CREF = 10µF
– = GND
REF
TA = 25°C
24361 F23
VINCM = 0.5 • (IN + + IN –) = 2.5V
Figure 23. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF–
for Large CREF Values (CREF ≥ 1µF)
the REF+ and REF– pins does not help the gain or the INL
error. The user is thus advised to minimize the combined
source impedance driving the REF+ and REF– pins rather
than to try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by REF+
and REF–, the expected drift of the dynamic current gain
CREF = 1µF, 10µF
24361 F22
Figure 22. –FS Error vs RSOURCE at REF+ and REF– (Large CREF)
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05µV typical and 0.5µV
maximum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2439-1 can
produce up to 6.8 readings per second. The actual output
data rate will depend upon the length of the sleep and data
output phases which are controlled by the user and which
can be made insignificantly short. When operated with an
external conversion clock (FO connected to an external oscillator), the LTC2439-1 output data rate can be increased
as desired. The duration of the conversion phase is 20510/
fEOSC. If fEOSC = 139,800Hz, the converter behaves as if the
internal oscillator is used with simultaneous 50Hz/60Hz.
There is no significant difference in the LTC2439‑1 performance between these two operation modes.
An increase in fEOSC over the nominal 139,800Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must
be carefully considered.
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LTC2439-1
APPLICATIONS INFORMATION
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent performance degradation can be substantially reduced by
relying upon the LTC2439-1’s exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and should
maintain a very high degree of matching and symmetry
in the circuits driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used,
the previous section provides formulae for evaluating the
effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2439-1 typical
performance can be inferred from Figures 14, 15, 19 and
20 in which the horizontal axis is scaled by 139,800/fEOSC.
Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the
output data rate) will start to decrease the effectiveness
of the internal auto-calibration circuits. This will result in
a progressive degradation in the converter accuracy and
linearity. Typical measured performance curves for output
data rates up to 100 readings per second are shown in
Figures 24, 25, 26, 27, 28 and 29. In order to obtain the
highest possible level of accuracy from this converter at
output data rates above 20 readings per second, the user
is advised to maximize the power supply voltage used
and to limit the maximum ambient operating temperature.
In certain circumstances, a reduction of the differential
reference voltage may be beneficial.
Increasing Input Resolution by Reducing Reference
Voltage
The resolution of the LTC2439-1 can be increased by
reducing the reference voltage. It is often necessary to
amplify low level signals to increase the voltage resolution
of ADCs that cannot operate with a low reference voltage.
The LTC2439-1 can be used with reference voltages as
low as 100mV, corresponding to a ±50mV input range
with full 16-bit resolution. Reducing the reference voltage
is functionally equivalent to amplifying the input signal,
however no amplifier is required.
The LTC2439-1 has a 76µV LSB when used with a 5V reference, however the thermal noise of the inputs is 1µVRMS
and is independent of reference voltage. Thus reducing
the reference voltage will increase the resolution at the
inputs as long as the LSB voltage is significantly larger
than 1µVRMS. A 325mV reference corresponds to a 5µV
LSB, which is approximately the peak-to-peak value of the
1µVRMS input thermal noise. At this point, the output code
will be stable to ±1LSB for a fixed input. As the reference
is decreased further, the measured noise will approach
1µVRMS.
Figure 30 shows two methods of dividing down the reference voltage to the LTC2439-1. Where absolute accuracy
is required, a precision divider such as the Vishay MPM
series dividers in a SOT-23 package may be used. A 51:1
divider provides a 98mV reference to the LTC2439‑1 from
a 5V source. The resulting ±49mV input range and 1.5µV
LSB is suitable for thermocouple and 10mV full-scale
strain gauge measurements.
If high initial accuracy is not critical, a standard 2% resistor array such as the Panasonic EXB series may be used.
Single package resistor arrays provide better temperature
stability than discrete resistors. An array of eight resistors
can be configured as shown to provide a 294mV reference
to the LTC2439-1 from a 5V source. The fully differential
property of the LTC2439-1 reference terminals allow the
reference voltage to be taken from four central resistors in
the network connected in parallel, minimizing drift in the
presence of thermal gradients. This is an ideal reference for
medium accuracy sensors such as silicon micromachined
pressure and force sensors. These devices typically have
accuracies on the order of 2% and full-scale outputs of
50mV to 200mV.
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26
For more information www.linear.com/LTC2439-1
LTC2439-1
APPLICATIONS INFORMATION
420
15
360
TA = 85°C
TA = 25°C
0
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = EXTERNAL OSCILLATOR
300
60
–FS ERROR (LSB)
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
+FS ERROR (LSB)
OFFSET ERROR (LSB)
30
240
180
TA = 85°C
120
TA = 25°C
0
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
13
0
TA = 85°C
14
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
–2.5V < VIN < 2.5V
FO = EXTERNAL OSCILLATOR
RESOLUTION = LOG2(VREF/INLMAX)
12
10
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
24361 F27
Figure 27. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
TA = 25°C
OFFSET ERROR (LSB)
RESOLUTION (BITS)
RESOLUTION (BITS)
14
12
24361 F26
16
16
16
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
RESOLUTION = LOG2(VREF/NOISERMS)
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
Figure 26. –FS Error vs Output
Data Rate and Temperature
18
TA = 85°C
0
Figure 25. +FS Error vs Output
Data Rate and Temperature
17
15
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = EXTERNAL OSCILLATOR
300
24361 F25
Figure 24. Offset Error vs Output
Data Rate and Temperature
TA = 25°C
240
420
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
24361 F24
TA = 25°C
180
360
60
0
TA = 85°C
120
8
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
24361 F28
Figure 28. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
VCC = 5V
REF + = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
TA = 25°C
8
VREF = 5V
VREF = 2.5V
0
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
24361 F29
Figure 29. Offset Error vs Output
Data Rate and Reference Voltage
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For more information www.linear.com/LTC2439-1
27
LTC2439-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.386 – .393*
(9.804 – 9.982)
.045 ±.005
28 27 26 25 24 23 22 21 20 19 18 17 1615
.033
(0.838)
REF
.150 – .165
.254 MIN
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
.0250 BSC
.0165 ±.0015
1
RECOMMENDED SOLDER PAD LAYOUT
.015 ±.004
× 45°
(0.38 ±0.10)
.0075 – .0098
(0.19 – 0.25)
2 3
4
5 6
7
8
.0532 – .0688
(1.35 – 1.75)
9 10 11 12 13 14
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN28 REV B 0212
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
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28
For more information www.linear.com/LTC2439-1
LTC2439-1
REVISION HISTORY
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
B
09/15
Reformatted Order Information.
PAGE NUMBER
2
24391fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
www.linear.com/LTC2439-1
29
LTC2439-1
TYPICAL APPLICATION
PANASONIC EXB-2HV202G
REF +
5V
5V
8 × 2k
ARRAY
0.1µF
9
REF –
VREF = 294mV
±147mV INPUT RANGE
4.5µV LSB
11
5V
VISHAY MPM1001/5002B
5V
50k
REF +
1k
HONEYWELL
FSL05N2C
500 GRAM
FORCE SENSOR
12
21
22
4.7µF
VCC
FO
REF +
REF –
SD1
8
10
15
REF –
20
CH0
LTC2439-1
CH1
SCK
SDO
THERMOCOUPLE
19
CH15
CS
18
17
16
CH10
GND
24391 F30
VREF = 95.04mV
±49mV INPUT RANGE
1.5µV LSB
Figure 30. Increased Resolution Bridge/Temperature Measurement
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1043
Dual Precision Instrumentation Switched Capacitor Building Block Precise, Charge Balanced Switching, Low Power
LT1236
Precision Bandgap Reference, 5V
0.05% Max, 5ppm/°C Drift
LT1461
Micropower Precision LDO Reference
High Accuracy 0.04% Max, 3ppm/°C Max Drift
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410
24-Bit, Fully Differential, No Latency ∆Σ ADC
0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2411
24-Bit, No Latency ∆Σ ADC in MSOP
1.45µVRMS Noise, 2ppm INL
LTC2411-1
24-Bit, Simultaneous 50Hz/60Hz Rejection ∆Σ ADC
0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411
LTC2412
2-Channel, 24-Bit, Pin Compatible with LTC2439-1
800nV Noise, 2ppm INL, 3ppm TUE, 200µA
LTC2413
24-Bit, No Latency ∆Σ ADC
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2414/LTC2418 8-/16-Channel, 24-Bit No Latency ∆Σ ADC
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2415
24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate
Pin Compatible with the LTC2410
LTC2420
20-Bit, No Latency ∆Σ ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2424/LTC2428 4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408
LTC2433-1
Differential Single Channel 16-Bit ∆Σ ADC
Low Noise, 16-Bits at ±50mV Input Range
LTC2436-1
2-Channel Differential 16-Bit ∆Σ ADC
Low Noise, 16-Bits at ±50mV Input Range
LTC2440
High Speed, Low Noise 24-Bit ADC
4kHz Output Rate, 200nV Noise, 24.6 ENOBs
LTC2444/LTC2445/ 8-/16-Channel High Speed, Low Noise 24-Bit ADC
LTC2448/LTC2449
4kHz MUX Rate, 200nV Noise
24391fb
30 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2439-1
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2439-1
LT 0915 REV B • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2005
