LTC2444/LTC2445/
LTC2448/LTC2449
24-Bit High Speed
8-/16-Channel ∆∑ ADCs with
Selectable Speed/Resolution
Description
Features
Up to 8 Differential or 16 Single-Ended Input Channels
nn Up to 8kHz Output Rate (External f )
O
nn Up to 4kHz Multiplexing Rate (External f )
O
nn Selectable Speed/Resolution
nn 2µV
RMS Noise at 1.76kHz Output Rate
nn 200nV
RMS Noise at 13.8Hz Output Rate with
Simultaneous 50Hz/60Hz Rejection
nn Guaranteed Modulator Stability and Lock-Up
Immunity for any Input and Reference Conditions
nn 0.0005% INL, No Missing Codes
nn Autosleep Enables 20µA Operation at 6.9Hz
nn < 5µV Offset (4.5V < V
CC < 5.5V, –40°C to 85°C)
nn Differential Input and Differential Reference with
GND to VCC Common Mode Range
nn No Latency Mode, Each Conversion is Accurate Even
After a New Channel is Selected
nn Internal Oscillator—No External Components
nn LTC2445/LTC2449 Include MUXOUT/ADCIN for
External Buffering or Gain
nn Tiny QFN 5mm × 7mm Package
nn
Applications
High Speed Multiplexing
Weight Scales
nn Auto Ranging 6-Digit DVMs
nn Direct Temperature Measurement
nn High Speed Data Acquisition
nn
The LTC®2444/LTC2445/LTC2448/LTC2449 are 8-/16channel (4-/8-differential) high speed 24-bit No Latency
∆Σ™ ADCs. They use a proprietary delta-sigma architecture enabling variable speed/resolution. Through a simple
4-wire serial interface, ten speed/resolution combinations
6.9Hz/280nVRMS to 3.5kHz/25µVRMS (4kHz with external
oscillator) can be selected with no latency between conversion results or shift in DC accuracy (offset, full-scale,
linearity, drift). Additionally, a 2X speed mode can be
selected enabling output rates up to 7kHz (8kHz if an
external oscillator is used) with one cycle latency.
Any combination of single-ended or differential inputs
can be selected with a common mode input range from
ground to VCC, independent of VREF. While operating in
the 1X speed mode the first conversion following a new
speed, resolution, or channel selection is valid. Since
there is no settling time between conversions, all 8 differential channels can be scanned at a rate of 500Hz.
At the conclusion of each conversion, the converter is
internally reset eliminating any memory effects between
successive conversions and assuring stability of the high
order delta-sigma modulator.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency ∆∑ and SoftSpan are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
nn
Typical Application
LTC2444/LTC2448
RMS Noise vs Speed
Simple 24-Bit Variable Speed Data Acquisition System
100
4.5V TO 5.5V
VCC = 5V
VREF = 5V
VIN+ = VIN– = 0V
2X SPEED MODE
NO LATENCY MODE
THERMOCOUPLE
REF +
VCC
FO
16-CHANNEL
MUX
+
–
VARIABLE SPEED/
RESOLUTION
DIFFERENTIAL
24-BIT ∆∑ ADC
SDI
SCK
SDO
CS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE)
4-WIRE
SPI INTERFACE
RMS NOISE (µV)
1µF
CH0
CH1
•
•
•
CH7
CH8
•
•
•
CH15
10
2.8µV AT 880Hz
1
280nV AT 6.9Hz
(50/60Hz REJECTION)
COM
0.1
REF –
GND
LTC2448
1
1000
10
100
CONVERSION RATE (Hz)
10000
2440 TA01b
2444 TA01a
2444589fc
For more information www.linear.com/LTC2444
1
LTC2444/LTC2445/
LTC2448/LTC2449
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (VCC) to GND........................ – 0.3V to 6V
Analog Input Pins Voltage
to GND.......................................–0.3V to (VCC + 0.3V)
Reference Input Pins Voltage
to GND.......................................–0.3V to (VCC + 0.3V)
Digital Input Voltage to GND..........–0.3V to (VCC + 0.3V)
Digital Output Voltage to GND........–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2444C/LTC2445C/
LTC2448C/LTC2449C................................ 0°C to 70°C
LTC2444I/LTC2445I/
LTC2448I/LTC2449I..............................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Pin Configuration
LTC2444
LTC2445
38 37 36 35 34 33 32
GND
GND
SDI
FO
CS
SDO
SCK
GND
TOP VIEW
GND
SDI
FO
CS
SDO
SCK
TOP VIEW
38 37 36 35 34 33 32
GND 1
31 GND
GND 1
31 GND
BUSY 2
30 REF–
BUSY 2
30 REF–
EXT 3
29 REF+
EXT 3
29 REF+
GND 4
28 VCC
GND 4
28 VCC
GND 5
27 NC
GND 5
26 NC
GND 6
COM 7
25 NC
COM 7
NC 8
24 NC
NC 8
CH0 9
23 NC
CH0 9
23 NC
CH1 10
22 CH7
CH1 10
22 CH7
NC 11
21 CH6
NC 11
21 CH6
NC 12
20 NC
NC 12
27 MUXOUTN
39
24 MUXOUTP
20 NC
NC
CH5
CH4
NC
CH2
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
NC
13 14 15 16 17 18 19
NC
CH5
CH4
NC
NC
CH3
13 14 15 16 17 18 19
CH2
26 ADCINN
25 ADCINP
CH3
39
GND 6
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
LTC2448
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
LTC2449
38 37 36 35 34 33 32
GND
GND
SDI
FO
CS
SDO
SCK
GND
TOP VIEW
GND
SDI
FO
CS
SDO
SCK
TOP VIEW
38 37 36 35 34 33 32
GND 1
31 GND
GND 1
31 GND
BUSY 2
30 REF–
BUSY 2
30 REF–
EXT 3
29 REF+
EXT 3
29 REF+
GND 4
28 VCC
GND 4
28 VCC
GND 5
27 NC
GND 5
26 NC
GND 6
COM 7
25 NC
COM 7
25 ADCINP
CH0 8
24 NC
CH0 8
24 MUXOUTP
CH1 9
23 CH15
CH1 9
23 CH15
CH2 10
22 CH14
CH2 10
22 CH14
CH3 11
21 CH13
CH3 11
21 CH13
CH4 12
20 CH12
CH4 12
26 ADCINN
20 CH12
CH11
CH10
CH9
CH5
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
CH8
13 14 15 16 17 18 19
CH11
CH10
CH9
CH8
CH7
CH6
CH5
13 14 15 16 17 18 19
27 MUXOUTN
39
CH7
39
CH6
GND 6
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
2444589fc
2
For more information www.linear.com/LTC2444
LTC2444/LTC2445/
LTC2448/LTC2449
Order Information
http://www.linear.com/product/LTC2444#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2444CUHF#PBF
LTC2444CUHF#TRPBF
2444
38-Lead Plastic QFN
0°C to 70°C
LTC2444IUHF#PBF
LTC2444IUHF#TRPBF
2444
38-Lead Plastic QFN
–40°C to 85°C
LTC2445CUHF#PBF
LTC2445CUHF#TRPBF
2445
38-Lead Plastic QFN
0°C to 70°C
LTC2445IUHF#PBF
LTC2445IUHF#TRPBF
2445
38-Lead Plastic QFN
–40°C to 85°C
LTC2448CUHF#PBF
LTC2448CUHF#TRPBF
2448
38-Lead Plastic QFN
0°C to 70°C
LTC2448IUHF#PBF
LTC2448IUHF#TRPBF
2448
38-Lead Plastic QFN
–40°C to 85°C
LTC2449CUHF#PBF
LTC2449CUHF#TRPBF
2449
38-Lead Plastic QFN
0°C to 70°C
LTC2449IUHF#PBF
LTC2449IUHF#TRPBF
2449
38-Lead Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5)
Integral Nonlinearity
VCC = 5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6)
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC (Note 12)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC
REF + = 5V, REF– = GND, IN+ = 3.75V, IN– = 1.25V
Offset Error
Offset Error Drift
Positive Full-Scale Error
MIN
REF+ = 2.5V, REF– = GND, IN+ = 1.875V, IN– = 0.625V
l
TYP
MAX
24
UNITS
Bits
l
5
3
15
ppm of VREF
ppm of VREF
l
2.5
5
µV
20
l
l
10
10
nV/°C
50
50
ppm of VREF
ppm of VREF
Positive Full-Scale Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75 • REF+, IN– = 0.25 • REF+
Negative Full-Scale Error
REF+ = 5V, REF– = GND, IN+ = 1.25V, IN– = 3.75V
REF+ = 2.5V, REF– = GND, IN+ = 0.625V, IN– = 1.875V
Negative Full-Scale Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
0.2
ppm of VREF/°C
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
15
15
15
ppm of VREF
ppm of VREF
ppm of VREF
Input Common Mode Rejection DC
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC
120
dB
0.2
l
l
10
10
ppm of VREF/°C
50
50
ppm of VREF
ppm of VREF
2444589fc
For more information www.linear.com/LTC2444
3
LTC2444/LTC2445/
LTC2448/LTC2449
Analog Input and Reference
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
CONDITIONS
l
GND – 0.3V
VCC + 0.3V
V
IN–
Absolute/Common Mode IN– Voltage
l
GND – 0.3V
VCC + 0.3V
V
VIN
Input Differential Voltage Range
(IN+ – IN–)
l
–VREF/2
VREF/2
V
REF+
Absolute/Common Mode REF+ Voltage
l
0.1
VCC
V
REF–
Absolute/Common Mode REF– Voltage
l
GND
VCC – 0.1V
V
VREF
Reference Differential Voltage Range
(REF+ – REF–)
l
0.1
VCC
V
CS(IN+)
IN+ Sampling Capacitance
2
pF
CS(IN–)
IN– Sampling Capacitance
2
pF
CS(REF+)
REF+ Sampling Capacitance
2
pF
CS(REF–)
REF– Sampling Capacitance
2
pF
IDC_LEAK(IN+, IN–, Leakage Current, Inputs and Reference
REF+, REF–)
MIN
CS = VCC, IN+ = GND, IN– = GND,
REF+ = 5V, REF– = GND
l
ISAMPLE(IN+, IN–, Average Input/Reference Current
During Sampling
REF+, REF–)
tOPEN
MUX Break-Before-Make
QIRR
MUX Off Isolation
–15
TYP
1
MAX
UNITS
15
nA
Varies, See Applications Section
VIN = 2VP-P DC to 1.8MHz
nA
50
ns
120
dB
Digital Inputs and Digital Outputs
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage, CS, FO, SDI
4.5V ≤ VCC ≤ 5.5V
l
VIL
Low Level Input Voltage, CS, FO, SDI
4.5V ≤ VCC ≤ 5.5V
l
VIH
High Level Input Voltage SCK
4.5V ≤ VCC ≤ 5.5V (Note 8)
l
VIL
Low Level Input Voltage SCK
4.5V ≤ VCC ≤ 5.5V (Note 8)
l
IIN
Digital Input Current, CS, FO, EXT, SDI
0V ≤ VIN ≤ VCC
l
–10
IIN
Digital Input Current, SCK
0V ≤ VIN ≤ VCC (Note 8)
l
–10
CIN
Digital Input Capacitance, CS, FO, SDI
CIN
Digital Input Capacitance, SCK
(Note 8)
VOH
High Level Output Voltage, SDO, BUSY
IO = –800µA
l
VOL
Low Level Output Voltage, SDO, BUSY
IO = 1.6mA
l
VOH
High Level Output Voltage, SCK
IO = –800µA (Note 9)
l
VOL
Low Level Output Voltage, SCK
IO = 1.6mA (Note 9)
l
IOZ
Hi-Z Output Leakage, SDO
l
TYP
MAX
UNITS
2.5
V
0.8
V
2.5
V
0.8
V
10
µA
10
µA
10
pF
10
pF
VCC – 0.5V
V
0.4V
V
VCC – 0.5V
V
–10
0.4V
V
10
µA
Power Requirements
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
CONDITIONS
MIN
l
CS = 0V (Note 7)
CS = VCC (Note 7)
l
l
TYP
4.5
8
8
MAX
UNITS
5.5
V
11
30
mA
µA
2444589fc
4
For more information www.linear.com/LTC2444
LTC2444/LTC2445/
LTC2448/LTC2449
Timing Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
fEOSC
External Oscillator Frequency Range
l
0.1
12
tHEO
External Oscillator High Period
l
25
10000
ns
tLEO
External Oscillator Low Period
l
25
10000
ns
tCONV
Conversion Time
OSR = 256 (SDI = 0)
OSR = 32768 (SDI = 1)
l
l
0.99
126
1.33
170
ms
ms
External Oscillator, 1X Mode
(Notes 10, 13)
l
1.13
145
MAX
40 • OSR +178
fEOSC (kHz)
fISCK
Internal SCK Frequency
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
l
0.8
DISCK
Internal SCK Duty Cycle
(Note 9)
l
45
0.9
fEOSC/10
UNITS
MHz
ms
1
MHz
Hz
55
%
20
MHz
fESCK
External SCK Frequency Range
(Note 8)
l
tLESCK
External SCK Low Period
(Note 8)
l
25
ns
tHESCK
External SCK High Period
(Note 8)
l
25
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
l
l
41.6
tDOUT_ESCK
35.3
320/fEOSC
30.9
µs
s
External SCK 32-Bit Data Output Time
(Note 8)
l
t1
CS ↓ to SDO Low Z
(Note 12)
l
0
32/fEOSC
25
ns
t2
CS ↑ to SDO High Z
(Note 12)
l
0
25
ns
t3
CS ↓ to SCK ↓
(Note 9)
t4
CS ↓ to SCK ↑
(Notes 8, 12)
tKQMAX
SCK ↓ to SDO Valid
tKQMIN
SDO Hold After SCK ↓
t5
t6
t7
SDI Set-Up Before SCK ↑
(Note 5)
l
10
ns
t8
SDI Hold After SCK ↑
(Note 5)
l
10
ns
5
l
ns
25
l
15
SCK Set-Up Before CS ↓
l
50
SCK Hold After CS ↓
l
(Note 5)
µs
25
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 4.5V to 5.5V unless otherwise specified.
VREF = REF + – REF–, VREFCM = (REF+ + REF–)/2;
VIN = IN+ – IN –, VINCM = (IN + + IN –)/2.
Note 4: FO pin tied to GND or to external conversion clock source with
fEOSC = 10MHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
s
ns
ns
ns
50
ns
Note 7: The converter uses the internal oscillator.
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of CLOAD = 20pF.
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in Hz.
Note 11: The converter uses the internal oscillator. FO = 0V.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 5 to 15 fO cycles
to the conversion time.
2444589fc
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5
LTC2444/LTC2445/
LTC2448/LTC2449
Pin Functions
GND (Pins 1, 4, 5, 6, 31, 32, 33): Ground. Multiple ground
pins internally connected for optimum ground current flow
and VCC decoupling. Connect each one of these pins to
a common ground plane through a low impedance connection. All seven pins must be connected to ground for
proper operation.
BUSY (Pin 2): Conversion in Progress Indicator. This pin
is HIGH while the conversion is in progress and goes LOW
indicating the conversion is complete and data is ready.
It remains LOW during the sleep and data output states.
At the conclusion of the data output state, it goes HIGH
indicating a new conversion has begun.
EXT (Pin 3): Internal/External SCK Selection Pin. This
pin is used to select internal or external SCK for outputting/inputting data. If EXT is tied low, the device is in the
external SCK mode and data is shifted out of the device
under the control of a user applied serial clock. If EXT is
tied high, the internal serial clock mode is selected. The
device generates its own SCK signal and outputs this on
the SCK pin. A framing signal BUSY (Pin 2) goes low
indicating data is being output.
COM (Pin 7): The common negative input (IN –) for all
single ended multiplexer configurations. The voltage on
CH0 to CH15 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN–) provide a bipolar input range
(VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside
this input range, the converter produces unique overrange
and underrange output codes.
CH0 to CH15 (Pins 8 to 23): LTC2448/LTC2449 Analog
Inputs. May be programmed for single-ended or differential mode.
CH0 to CH7 (Pins 9, 10, 13, 14, 17, 18, 21, 22): LTC2444/
LTC2445 Analog Inputs. May be programmed for singleended or differential mode.
NC (Pins 8, 11, 12, 15, 16, 19, 20, 23): LTC2444/LTC2445
No Connect/Channel Isolation Shield. May be left floating
or tied to any voltage 0 to VCC in order to provide isolation
for pairs of differential input channels.
NC (Pins 24, 25, 26, 27): LTC2444/LTC2448 No Connect.
These pins can either be tied to ground or left floating.
MUXOUTP (Pin 24): LTC2445/LTC2449 Positive Multiplexer Output. Used to drive the input to an external
buffer/amplifier.
ADCINP (Pin 25): LTC2445/LTC2449 Positive ADC Input.
Tie to output of buffer/amplifier driven by MUXOUTP.
ADCINN (Pin 26): LTC2445/LTC2449 Negative ADC Input.
Tie to output of buffer/amplifier driven by MUXOUTN.
MUXOUTN (Pin 27): LTC2445/LTC2449 Negative Multiplexer Output. Used to drive the input to an external
buffer/amplifier.
VCC (Pin 28): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.
REF+ (Pin 29), REF– (Pin 30): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
is maintained more positive than the negative reference
input, REF+, by at least 0.1V.
SDI (Pin 34): Serial Data Input. This pin is used to select
the speed, 1X or 2X mode, resolution, and input channel,
for the next conversion cycle. At initial power up, the
default mode of operation is CH0 to CH1, OSR of 256,
and 1X mode. The serial data input contains an enable
bit which determines if a new channel/speed is selected.
If this bit is low the following conversion remains at the
same speed and selected channel. The serial data input
is applied to the device under control of the serial clock
(SCK) during the data output cycle. The first conversion
following a new channel/speed is valid.
FO (Pin 35): Frequency Control Pin. Digital input that controls the internal conversion clock. When FO is connected
to VCC or GND, the converter uses its internal oscillator.
2444589fc
6
For more information www.linear.com/LTC2444
LTC2444/LTC2445/
LTC2448/LTC2449
Pin Functions
CS (Pin 36): Active Low Chip Select. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output aborts the data transfer and starts a
new conversion.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in
a high impedance state. During the conversion and sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
This signal is HIGH while the conversion is in progress
and goes LOW once the conversion is complete.
SCK (Pin 38): Bidirectional Digital Clock Pin. In internal
serial clock operation mode, SCK is used as a digital
output for the internal serial interface clock during the
data output period. In the external serial clock operation
mode, SCK is used as the digital input for the external
serial interface clock during the data output period. The
serial clock operation mode is determined by the logic
level applied to the EXT pin.
Exposed Pad (Pin 39): Ground. The exposed pad on the
bottom of the package must be soldered to the PCB ground.
For prototyping purposes, this pin may remain floating.
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7
LTC2444/LTC2445/
LTC2448/LTC2449
functional Block Diagram
INTERNAL
OSCILLATOR
VCC
GND
CH0
CH1
CH15
COM
FO
(INT/EXT)
AUTOCALIBRATION
AND CONTROL
REF +
REF –
•
•
•
IN +
MUX
IN –
–
+
DIFFERENTIAL
3RD ORDER
∆∑ MODULATOR
SDI
SCK
SDO
CS
SERIAL
INTERFACE
DECIMATING FIR
ADDRESS
2444589 F01
Figure 1. Functional Block Diagram
Test Circuit
VCC
SDO
1.69k
1.69k
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
SDO
CLOAD = 20pF
2444589 TC01
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
2444589 TC02
2444589fc
8
For more information www.linear.com/LTC2444
LTC2444/LTC2445/
LTC2448/LTC2449
Applications Information
Converter Operation
Converter Operation Cycle
The LTC2444/LTC2445/LTC2448/LTC2449 are multichannel, high speed, delta-sigma analog-to-digital converters with an easy to use 3- or 4-wire serial interface (see
Figure 1). Their operation is made up of three states. The
converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data
output/input (see Figure 2). The 4-wire interface consists
of serial data input (SDI), serial data output (SDO), serial
clock (SCK) and chip select (CS). The interface, timing,
operation cycle and data out format is compatible with
Linear’s entire family of ∆Σ converters.
POWER UP
IN+=CH0, IN–=CH1
OSR=256,1X MODE
corresponds to the conversion just performed. This result
is shifted out on the serial data out pin (SDO) under the
control of the serial clock (SCK). Data is updated on the
falling edge of SCK allowing the user to reliably latch data
on the rising edge of SCK (see Figure 3). The data output
state is concluded once 32 bits are read out of the ADC
or when CS is brought HIGH. The device automatically
initiates a new conversion and the cycle repeats.
Through timing control of the CS, SCK and EXT pins, the
LTC2444/LTC2445/LTC2448/LTC2449 offer several flexible modes of operation (internal or external SCK). These
various modes do not require programming configuration
registers; moreover, they do not disturb the cyclic operation
described above. These modes of operation are described
in detail in the Serial Interface Timing Modes section.
Ease of Use
The LTC2444/LTC2445/LTC2448/LTC2449 data output
has no latency, filter settling delay or redundant data
associated with the conversion cycle while operating
in the 1X mode. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog voltages is easy. Speed/
resolution adjustments may be made seamlessly between
two conversions without settling errors.
CONVERT
SLEEP
CS = LOW
AND
SCK
CHANNEL SELECT
SPEED SELECT
DATA OUTPUT
2444589 F02
Figure 2. LTC2444/LTC2445/LTC2448/LTC2449
State Transition Diagram
Initially, the LTC2444/LTC2445/LTC2448/LTC2449 perform a conversion. Once the conversion is complete, the
device enters the sleep state. While in this sleep state, power
consumption is reduced below 10µA. The part remains
in the sleep state as long as CS is HIGH. The conversion
result is held indefinitely in a static shift register while the
converter is in the sleep state.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result while operating in the 1x mode. The data output
The LTC2444/LTC2445/LTC2448/LTC2449 perform offset
and full-scale calibrations every conversion cycle. This
calibration is transparent to the user and has no effect
on the cyclic operation described above. The advantage
of continuous calibration is extreme stability of offset and
full-scale readings with respect to time, supply voltage
change and temperature drift.
Power-Up Sequence
The LTC2444/LTC2445/LTC2448/LTC2449 automatically
enter an internal reset state when the power supply voltage VCC drops below approximately 2.2V. This feature
guarantees the integrity of the conversion result and of
the serial interface mode selection.
When the VCC voltage rises above this critical threshold, the
converter creates an internal power-on-reset (POR) signal
with a duration of approximately 0.5ms. The POR signal
2444589fc
For more information www.linear.com/LTC2444
9
LTC2444/LTC2445/
LTC2448/LTC2449
Applications Information
Input Voltage Range
clears all internal registers. The conversion immediately
following a POR is performed on the input channel IN+
= CH0, IN– = CH1 at an OSR = 256 in the 1X mode. Following the POR signal, the LTC2444/LTC2445/LTC2448/
LTC2449 start a normal conversion cycle and follow the
succession of states described above. The first conversion
result following POR is accurate within the specifications
of the device if the power supply voltage is restored within
the operating range (4.5V to 5.5V) before the end of the
POR time interval.
Refer to Figure 4. The analog input is truly differential with an
absolute/common mode range for the CH0 to CH15 and COM
input pins extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase rapidly. Within these limits, the LTC2444/LTC2445/LTC2448/
LTC2449 convert the bipolar differential input signal, VIN =
IN+ – IN– (where IN+ and IN– are the selected input channels), from – FS = –0.5 • VREF to +FS = 0.5 • VREF where
VREF = REF+ – REF–. Outside this range, the converter
indicates the overrange or the underrange condition using
distinct output codes.
Reference Voltage Range
These converters accept a truly differential external
reference voltage. The absolute/common mode voltage
specification for the REF + and REF – pins covers the entire
range from GND to VCC. For correct converter operation, the
REF + pin must always be more positive than the REF – pin.
MUXOUT/ADCIN
There are two differences between the LTC2444/LTC2448
and the LTC2445/LTC2449. The first is the RMS noise
performance. For a given OSR, the LTC2445/LTC2449
noise level is approximately √2 times lower (0.5 effective
bits)than that of the LTC2444/LTC2448.
The LTC2444/LTC2445/LTC2448/LTC2449 can accept a
differential reference voltage from 0.1V to VCC. The converter output noise is determined by the thermal noise of
the front-end circuits, and as such, its value in microvolts
is nearly constant with reference voltage. A decrease in
reference voltage will not significantly improve the converter’s effective resolution. On the other hand, a reduced
reference voltage will improve the converter’s overall INL
performance.
The second difference is the LTC2445/LTC2449 includes
MUXOUT/ADCIN pins. These pins enable an external buffer or gain block to be inserted between the output of the
multiplexer and the input to the ADC. Since the buffer is
driven by the output of the multiplexer, only one circuit is
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
SCK
SDI
SDO
1
Hi-Z
0
EN
SGL
ODD
A2
A1
A0
OSR3
OSR2
OSR1
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
EOC
“0”
SIG
OSR0
TWOX
BIT 20 BIT 19
BIT 0
LSB
MSB
Hi-Z
BUSY
2444589 F03
Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing
2444589fc
10
For more information www.linear.com/LTC2444
LTC2444/LTC2445/
LTC2448/LTC2449
Applications Information
required for all 16 input channels. Additionally, the transparent calibration feature of the LTC244X family automatically
removes the offset errors of the external buffer.
In order to achieve optimum performance, the MUXOUT
and ADCIN pins should not be shorted together. In applications where the MUXOUT and ADCIN need to be shorted
together, the LTC2444/LTC2448 should be used because
the MUXOUT and ADCIN are internally connected for
optimum performance.
Output Data Format
The LTC2444/LTC2445/LTC2448/LTC2449 serial output
data stream is 32 bits long. The first 3 bits represent status information indicating the sign and conversion state.
The next 24 bits are the conversion result, MSB first. The
remaining 5 bits are sub LSBs beyond the 24-bit level that
may be included in averaging or discarded without loss of
resolution. In the case of ultrahigh resolution modes, more
than 24 effective bits of performance are possible (see
Table 5). Under these conditions, sub LSBs are included
in the conversion result and represent useful information
VCC + 0.3V
VCC
VREF
2
GND
–0.3V
beyond the 24-bit level. The third and fourth bit together
are also used to indicate an underrange condition (the
differential input voltage is below –FS) or an overrange
condition (the differential input voltage is above +FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is 120dB
1000000
2000000
0
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
–20
–40
–60
–80
–100
–120
–140
2444589 F13
Figure 13. LTC2444/LTC2445/LTC2448/LTC2449 Normal
Mode Rejection (Internal Oscillator)
2
4
6
10
8
0
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2444589 F14
Figure 14. LTC2444/LTC2445/LTC2448/LTC2449 Normal
Mode Rejection (External Oscillator at 90kHz)
2444589fc
24
For more information www.linear.com/LTC2444
LTC2444/LTC2445/
LTC2448/LTC2449
Applications Information
Reduced Power Operation
Input Bandwidth and Frequency Rejection
In addition to adjusting the speed/resolution of the
LTC2444/LTC2445/LTC2448/LTC2449, the speed/resolution/power dissipation may also be adjusted using the
automatic sleep mode. During the conversion cycle, the
LTC2444/LTC2445/LTC2448/LTC2449 draw 8mA supply
current independent of the programmed speed. Once the
conversion cycle is completed, the device automatically
enters a low power sleep state drawing 8µA. The device
remains in this state as long as CS is HIGH and data is not
shifted out. By adjusting the duration of the sleep state
(hold CS HIGH longer) and the duration of the conversion
cycle (programming OSR) the DC power dissipation can
be reduced, see Figure 15.
The combined effect of the internal SINC4 digital filter and
the digital and analog autocalibration circuits determines
the LTC2444/LTC2445/LTC2448/LTC2449 input bandwidth
IREF+
The LTC2444/LTC2448 switch the input and reference to
a 2pF capacitor at a frequency of 1.8MHz. A simplified
equivalent circuit is shown in Figure 16. The sample capacitor for the LTC2445/LTC2449 is 4pF, and its average
input current is externally buffered from the input source.
RSW (TYP)
500Ω
ILEAK
VREF+
ILEAK
VCC
IIN+
ILEAK
VIN+
IIN –
VIN –
Average Input Current
VCC
IREF –
ILEAK
CEQ
5pF
(TYP)
(CEQ = 2pF
SAMPLE CAP
+ PARASITICS)
MUX
VCC
RSW (TYP)
500Ω
ILEAK
ILEAK
MUX
VCC
ILEAK
VREF –
The average input and reference currents can be expressed
in terms of the equivalent input resistance of the sample
capacitor, where: Req = 1/(fSW • Ceq)
RSW (TYP)
500Ω
RSW (TYP)
500Ω
ILEAK
2444589 F16
SWITCHING FREQUENCY
fSW = 1.8MHz INTERNAL OSCILLATOR
fSW = fEOSC/5 EXTERNAL OSCILLATOR
Figure 16. LTC2444/LTC2448 Input Structure
When using the internal oscillator, fSW is 1.8MHz and the
equivalent resistance is approximately 110kΩ.
CONVERTER
STATE
SLEEP
CONVERT
SLEEP
DATA
OUT
CONVERT
SLEEP
DATA
OUT
CS
SUPPLY
CURRENT
8µA
8mA
8µA
8mA
8µA
2444589 F15
Figure 15. Reduced Power Timing Mode
2444589fc
For more information www.linear.com/LTC2444
25
LTC2444/LTC2445/
LTC2448/LTC2449
Applications Information
4.5V TO 5.5V
1µF
28
29
REFERENCE
VOLTAGE
0.1V TO VCC
30
8
ANALOG INPUT
–0.5VREF TO
0.5VREF
9
1,4,5,6,31,32,33,39
VCC
BUSY
2
LTC2448
35
fO
REF +
38
REF –
SCK
37
CH0
SDO
36
CH1
CS
•
•
•
3
EXT
GND
RSET
LTC1799
V+
OUT
0.1µF
3-WIRE
SPI INTERFACE
NC
GND
DIV
SET
2444589 F17
Figure 17. Simple External Clock Source
and rejection characteristics. The digital filter’s response
can be adjusted by setting the oversample ratio (OSR)
through the SPI interface or by supplying an external
conversion clock to the FO pin.
Maximum Conversion Rate
Table 8 lists the properties of the LTC2444/LTC2445/
LTC2448/LTC2449 with various combinations of oversample ratio and clock frequency. Understanding these
properties is the key to fine tuning the characteristics of the
LTC2444/LTC2445/LTC2448/LTC2449 to the application.
First Notch Frequency
The maximum conversion rate is the fastest possible rate
at which conversions can be performed.
This is the first notch in the SINC4 portion of the digital filter
and depends on the FO clock frequency and the oversample
ratio. Rejection at this frequency and its multiples (up to
the modulator sample rate of 1.8MHz) exceeds 120dB.
This is 8 times the maximum conversion rate.
Table 8. Performance vs Oversample Ratio
ENOB
(VREF = 5V)
OVERSAMPLE
*RMS
NOISE
*RMS
NOISE
64
23µV
23µV
17
128
4.5µV
3.5µV
256
2.8µV
2µV
512
2µV
1024
2048
MAXIMUM CONVERSION
RATE (sps)
FIRST NOTCH
FREQUENCY (Hz)
EFFECTIVE
NOISE BW (Hz)
–3dB POINT (Hz)
External fO External fO
Internal
RATIO LTC2444/ LTC2445/ LTC2444 LTC2445/ Internal (1X Mode) (2X Mode) Internal External fO 9MHz External fO Internal External fO
[fO/x]
[fO/x]
Clock
[fO/x]
Clock
[fO/x]
Clock
[fO/x]
(OSR) LTC2448 LTC2449 LTC2449 LTC2449 Clock
fo/1458
28125
fo/320
3148
fo/5298
fo/2738
fo/10418
fo/5298
14062.5
fo/640
1574
fo/5720
848
fo/10600
7031.3
fo/1280
787
fo/11440
424
fo/21200
fo/20658
fo/10418
3515.6
fo/2560
394
fo/22840
212
fo/42500
187.45
93.93
fo/41138
fo/20658
1757.8
fo/5120
197
fo/45690
106
fo/84900
fo/82098
fo/41138
878.9
fo/10200
98.4
fo/91460
53
fo/170000
23.4
24
47.01
fo/164018 fo/82098
439.5
fo/20500
49.2
fo/183000
26.5
fo/340000
23.52
fo/327858 fo/164018
219.7
fo/41000
24.6
fo/366000
13.2
fo/679000
23.8
24.4
11.76
fo/655538 fo/327858
109.9
fo/81900
12.4
fo/731000
6.6
fo/1358000
24.1
24.6
5.88
fo/1310898 fo/655538
54.9
fo/163800
6.2
fo/1463000
3.3
fo/2717000
17
2816.35
20.1
20
1455.49
20.8
21.3
740.18
1.4µV
21.3
21.8
373.28
1.4µV
1µV
21.8
22.4
1.1µV
750nV
22.1
22.9
4096
720nV
510nV
22.7
8192
530nV
375nV
23.2
16384
350nV
250nV
32768
280nV
200nV
fø/2738
fo/2860
1696
fo/5310
*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 128 and OSR 64
include effects from internal modulator quantization noise.
2444589fc
26
For more information www.linear.com/LTC2444
LTC2444/LTC2445/
LTC2448/LTC2449
Applications Information
Effective Noise Bandwidth
The LTC2444/LTC2445/LTC2448/LTC2449 has extremely
good input noise rejection from the first notch frequency
all the way out to the modulator sample rate (typically
1.8MHz). Effective noise bandwidth is a measure of how
the ADC will reject wideband input noise up to the modulator sample rate. The example on the following page
shows how the noise rejection of the LTC2444/LTC2445/
LTC2448/LTC2449 reduces the effective noise of an amplifier driving its input.
Example: If an amplifier (e.g. LT1219) driving the input of
an LTC2444/LTC2445/LTC2448/LTC2449 has wideband
noise of 33nV/√Hz, band-limited to 1.8MHz, the total noise
entering the ADC input is:
33nV/√Hz • √1.8MHz = 44.3µV.
When the ADC digitizes the input, its digital filter filters
out the wideband noise from the input signal. The noise
reduction depends on the oversample ratio which defines
the effective bandwidth of the digital filter.
At an oversample of 256, the noise bandwidth of the ADC
is 787Hz which reduces the total amplifier noise to:
33nV/√Hz • √787Hz = 0.93µV.
The total noise is the RMS sum of this noise with the 2µV
noise of the ADC at OSR=256.
√(0.93µV)2 + (2µV)2 = 2.2µV.
Increasing the oversample ratio to 32768 reduces the
noise bandwidth of the ADC to 6.2Hz which reduces the
total amplifier noise to:
33nV/√Hz • √6.2Hz = 82nV.
The total noise is the RMS sum of this noise with the
200nV noise of the ADC at OSR = 32768.
In this way, the digital filter with its variable oversampling
ratio can greatly reduce the effects of external noise sources.
Automatic Offset Calibration of External
Buffers/Amplifiers
The LTC2445/LTC2449 enable an external amplifier to
be inserted between the multiplexer output and the ADC
input. This enables one external buffer/amplifier circuit to
be shared between all 17 analog inputs (16 single-ended
or 8 differential). The LTC2445/LTC2449 perform an
internal offset calibration every conversion cycle in order
to remove the offset and drift of the ADC. This calibration
is performed through a combination of front end switching and digital processing. Since the external amplifier is
placed between the multiplexer and the ADC, it is inside
the correction loop. This results in automatic offset correction and offset drift removal of the external amplifier.
The LT1368 is an excellent amplifier for this function. It
has rail-to-rail inputs and outputs, and it operates on a
single 5V supply. Its open-loop gain is 1M and its input
bias current is 10nA. It also requires at least a 0.1µF load
capacitor for compensation. It is this feature that sets it
apart from other amplifiers—the load capacitor attenuates
sampling glitches from the LTC2445/LTC2449 ADCIN
terminals, allowing it to achieve full performance of the
ADC with high impedance at the multiplexer inputs.
Another benefit of the LT1368 is that it can be powered
from supplies equal to or greater than that of the ADC.
This can allow the inputs to span the entire absolute
maximum of GND – 0.3V to VCC + 0.3V. Using a positive
supply of 7.5V to 10V and a negative supply of –2.5 to –5V
gives the amplifier plenty of headroom over the LTC2445/
LTC2449 input range.
√(82nV)2 + (200nV)2 = 216nV.
2444589fc
For more information www.linear.com/LTC2444
27
LTC2444/LTC2445/
LTC2448/LTC2449
Package Description
Please refer to http://www.linear.com/product/LTC2444#packaging for the most recent package drawings.
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 ±0.05
5.50 ±0.05
5.15 ±0.05
4.10 ±0.05
3.00 REF
3.15 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
5.5 REF
6.10 ±0.05
7.50 ±0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 ±0.05
5.00 ±0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ±0.10
5.50 REF
7.00 ±0.10
3.15 ±0.10
(UH) QFN REF C 1107
0.200 REF 0.25 ±0.05
0.50 BSC
R = 0.125
TYP
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2444589fc
28
For more information www.linear.com/LTC2444
LTC2444/LTC2445/
LTC2448/LTC2449
Revision History
(Revision history begins at Rev C)
REV
DATE
DESCRIPTION
C
01/17
Updated Max values for fEOSC
PAGE NUMBER
5
Updated formula for tCONV
5
Updated Note 13
5
Inserted Figure 4, Input Range
11
Revised Table 8, Performance vs Oversample Ratio
26
2444589fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC2444
29
LTC2444/LTC2445/
LTC2448/LTC2449
Typical Application
External Buffers Provide High Impedance Inputs and Amplifier Offsets are Cancelled
SDI
LTC2449
CH0-CH15/
COM
SCK
HIGH
SPEED
∆∑ ADC
SDO
ADCINN
ADCINP
MUXOUTP
MUX
MUXOUTN
17
CS
2444589 TA02
2
3
–
1/2 LT1368
+
1
0.1µF
(EXTERNAL AMPLIFIERS)
6
5
–
5V
8
1/2 LT1368
+
4
7
0.1µF
0V
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2444589fc
30 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2444
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2444
LT 0117 REV C • PRINTED IN USA
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