LTC2451
Ultra-Tiny, 16-Bit ∆∑ ADC
with I2C Interface
DESCRIPTION
FEATURES
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GND to VCC Single-Ended Input Range
0.02LSB RMS Noise
2LSB INL, No Missing Codes
1LSB Offset Error
4LSB Full-Scale Error
Programmable 30/60 Conversions per Second
Single Conversion Settling Time for Multiplexed
Applications
Single-Cycle Operation with Auto Shutdown
400µA Supply Current
0.2µA Sleep Current
Internal Oscillator—No External Components Required
Single Supply, 2.7V to 5.5V Operation
2-Wire I2C Interface
Ultra-Tiny 3mm × 2mm DFN or TSOT-23 Package
APPLICATIONS
System Monitoring
Environmental Monitoring
n Direct Temperature Measurements
n Instrumentation
n Industrial Process Control
n Data Acquisition
n Embedded ADC Upgrades
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. No Latency ∆∑ and Easy Drive are trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by U.S.
Patents, including 6208279, 6411242, 7088280, 7164378.
The LTC®2451 is an ultra-tiny, 16-bit, analog-to-digital
converter. The LTC2451 uses a single 2.7V to 5.5V supply, accepts a single-ended analog input voltage and
communicates through an I2C interface. The converter
is available in an 8-pin, 3mm × 2mm DFN or TSOT-23
package. It includes an integrated oscillator that does not
require any external components. It uses a delta-sigma
modulator as a converter core and provides single-cycle
settling time for multiplexed applications. The LTC2451
includes a proprietary input sampling scheme that reduces the average input sampling current several orders
of magnitude lower than conventional ∆∑ converters.
The LTC2451 is capable of up to 60 conversions per
second and, due to the very large oversampling ratio,
has extremely relaxed antialiasing requirements. In the
30Hz mode, the LTC2451 includes continuous internal
offset calibration algorithms which are transparent to the
user, ensuring accuracy over time and over the operating
temperature range. The converter has external REF+ and
REF – pins and the input voltage can range from VREF– to
VREF+. If VREF+ = VCC and VREF– = GND, the input voltage
can range from GND to VCC.
Following a single conversion, the LTC2451 can auto
matically enter sleep mode and reduce its power to less
than 0.2µA. If the user reads the ADC once per second,
the LTC2451 consumes an average of less than 50µW
from a 2.7V supply.
TYPICAL APPLICATION
Integral Nonlinearity, VCC = 3V
3
2
2.7V TO 5.5V
REF +
1k
IN
SENSOR
0.1µF
VCC
LTC2451
REF –
SCL
SDA
GND
2-WIRE I2C
INTERFACE
1
10µF
INL (LSB)
0.1µF
0
TA = 90°C
–1
TA = – 45°C, 25°C
–2
2451 TA01a
–3
0
0.5
1
1.5
2
INPUT VOLTAGE (V)
2.5
3
2451 TA01b
2451fg
1
LTC2451
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC).................................... –0.3V to 6V
Analog Input Voltage (VIN)............. –0.3V to (VCC + 0.3V)
Reference Voltage (VREF+, VREF –)....–0.3V to (VCC + 0.3V)
Digital Voltage (VSDA, VSCL)........... –0.3V to (VCC + 0.3V)
Storage Temperature Range.................... –65°C to 150°C
Operating Temperature Range
LTC2451C................................................. 0°C to 70°C
LTC2451I.............................................. –40°C to 85°C
PIN CONFIGURATION
TOP VIEW
GND
1
REF–
2
REF+
3
VCC
4
9
8
SDA
7
SCL
6
IN
5
GND
TOP VIEW
GND 1
REF– 2
REF+ 3
VCC 4
8 SDA
7 SCL
6 IN
5 GND
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
DDB PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
C/I GRADE TJMAX = 125°C, θJA = 140°C/W
C/I GRADE TJMAX = 125°C, θJA = 76°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2451CDDB#TRMPBF
LTC2451CDDB#TRPBF
LDGQ
8-Lead Plastic (3mm × 2mm) DFN
LTC2451IDDB#TRMPBF
LTC2451IDDB#TRPBF
LDGQ
8-Lead Plastic (3mm × 2mm) DFN
LTC2451CTS8#TRMPBF
LTC2451CTS8#TRPBF
LTDNS
8-Lead Plastic TSOT-23
LTC2451ITS8#TRMPBF
LTC2451ITS8#TRPBF
LTDNS
8-Lead Plastic TSOT-23
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
Integral Nonlinearity
Offset Error
Offset Error
Offset Error Drift
(Note 3)
(Note 4)
30Hz Mode
60Hz Mode
Gain Error
Gain Error Drift
MIN
l
l
l
l
l
Transition Noise
TYP
MAX
UNITS
2
0.08
0.5
0.02
10
0.5
2
Bits
LSB
mV
mV
LSB/°C
0.01
0.02
0.02
16
% of FS
LSB/°C
1.4
µVRMS
Power Supply Rejection DC
30Hz Mode
80
dB
Power Supply Rejection DC
60Hz Mode
80
dB
2451fg
2
LTC2451
The
ANALOG
INPUT AND REFERENCES l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
VIN
VREF+
VREF–
CIN
IDC_LEAK(VIN)
PARAMETER
Input Voltage Range
Positive Reference Voltage Range
Negative Reference Voltage Range
IN Sampling Capacitance
IN DC Leakage Current
IDC_LEAK(REF+, REF–) REF+, REF– DC Leakage Current
ICONV
Input Sampling Current (Note 5)
CONDITIONS
MIN
VREF–
l VCC – 2.5
l
0
TYP
l
VREF+ – VREF– ≥ 2.5V
VREF+ – VREF– ≥ 2.5V
VIN = GND (Note 8)
VIN = VCC (Note 8)
VREF = 5V (Note 8)
l
l
l
–10
–10
–10
0.35
1
1
1
50
MAX
VREF+
VCC
VCC – 2.5
10
10
10
UNITS
V
V
V
pF
nA
nA
nA
nA
POWER
REQUIREMENTS l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
VCC
ICC
PARAMETER
Supply Voltage
Supply Current
Conversion
Sleep
CONDITIONS
l
MIN
2.7
l
l
TYP
MAX
5.5
UNITS
V
400
0.2
700
0.5
µA
µA
2C INPUTS AND OUTPUTS
I The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (Note 2)
SYMBOL
VIH
VIL
VHYS
VOL
IIN
CI
CB
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Hysteresis of Schmidt Trigger Inputs
Low Level Output Voltage (SDA)
Input Leakage
Capacitance for Each I/O Pin
Capacitance Load for Each Bus Line
CONDITIONS
l
MIN
0.7VCC
TYP
0.3VCC
l
(Note 3)
I = 3mA
0.1VCC ≤ VIN ≤ 0.9VCC
l
0.05VCC
0.4
1
l
l
l
MAX
–1
10
400
l
UNITS
V
V
V
V
µA
pF
pF
2C TIMING CHARACTERISTICS
I The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (Notes 2, 7)
SYMBOL
tCONV
tCONV
fSCL
tHD(SDA)
tLOW
tHIGH
tSU(STA)
tHD(DAT)
tSU(DAT)
tr
tf
tSU(STO)
tBUF
PARAMETER
Conversion Time
Conversion Time
SCL Clock Frequency
Hold Time (Repeated) START Condition
LOW Period of the SCL Pin
HIGH Period of the SCL Pin
Set-Up Time for a Repeated START Condition
Data Hold Time
Data Set-Up Time
Rise Time for SDA/SCL Signals
Fall Time for SDA/SCL Signals
Set-Up Time for STOP Condition
Bus Free Time Between a STOP and START
Condition
CONDITIONS
30Hz Mode
60Hz Mode
l
l
l
l
l
l
l
l
l
(Note 6)
(Note 6)
l
l
l
l
MIN
26
13
0
0.6
1.3
0.6
0.6
0
100
20 + 0.1CB
20 + 0.1CB
0.6
1.3
TYP
33.2
16.6
MAX
46
23
400
0.9
300
300
UNITS
ms
ms
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
2451fg
3
LTC2451
2C TIMING CHARACTERISTICS
I The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7)
SYMBOL
tOF
PARAMETER
Output Fall Time VIH(MIN) to VIL(MAX)
tSP
Input Spike Suppression
CONDITIONS
Bus Load CB 10pF to
400pF (Note 6)
l
MIN
20 + 0.1CB
TYP
MAX
250
50
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V,
unless otherwise specified. Specifications apply to both 30Hz and 60Hz
modes unless otherwise specified.
VREF = VREF+ – VREF–, VREFCM = (VREF+ + VREF–)/2, FS = VREF+ – VREF–;
VREF– ≤ VIN ≤ VREF+
Note 3. Guaranteed by design, not subject to test.
UNITS
ns
ns
Note 4. Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band. Guaranteed by design, test correlation and 3-point transfer curve
measurement.
Note 5. Input sampling current is the average input current drawn from
the input sampling network while the LTC2451 is actively sampling the
input. CB = capacitance of one bus line in pF.
Note 6. CB = capacitance of one bus line in pF.
Note 7. All values refer to VIH(MIN) and VIL(MAX) levels.
Note 8. A positive current is flowing into the DUT pin.
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C; graphs apply to both 30Hz and 60Hz modes, unless otherwise noted.
3
Integral Nonlinearity
VCC = 5V, VREF+ = 3V
3
2
2
1
1
1
0
TA = – 45°C, 25°C, 90°C
–1
0
INL (LSB)
2
INL (LSB)
INL (LSB)
3
Integral Nonlinearity
VCC = VREF+ = 5V
TA = – 45°C, 25°C, 90°C
Integral Nonlinearity
VCC = VREF+ = 3V
0
–1
–1
–2
–2
TA = 90°C
TA = – 45°C, 25°C
–2
–3
0
1
2
3
INPUT VOLTAGE (V)
4
5
2451 G01
–3
0
0.5
1
1.5
2
INPUT VOLTAGE (V)
2.5
3
2451 G02
–3
0
0.5
1
1.5
2
INPUT VOLTAGE (V)
2.5
3
2451 G03
2451fg
4
LTC2451
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C; graphs apply to both 30Hz and 60Hz modes, unless otherwise noted.
Offset Error vs Temperature
30Hz Mode
Offset Error vs Temperature
60Hz Mode
0.50
0.50
4.5
0.45
0.45
4.0
0.40
0.40
3.5
0.35
0.35
3.0
2.5
VCC = 4.1V
2.0
VCC = 5V
1.5
1.0
0.30
0.25
0.20
0.10
VCC = 3V
–25
VCC = 4.1V
0.15
25
50
0
TEMPERATURE (°C)
0.00
–50
100
75
VCC = 5V
–25
0.10
0.05
25
50
0
TEMPERATURE (°C)
9
TRANSITION NOISE RMS (µV)
GAIN ERROR (LSB)
7
VCC = 3V
5
3
VCC = 5V
2
1
0
–50
–25
25
50
0
TEMPERATURE (°C)
3.0
2.5
2.5
2.0
1.5
VCC = 5V
1.0
VCC = 3V
0.5
–25
0
25
50
TEMPERATURE (°C)
75
2451 G07
VCC = 4.1V
200
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
2451 G10
16384
0
32768
49152
OUTPUT CODE
2451 G09
1000
150
VCC = 4.1V
100
0
–50
65536
Average Power Dissipation vs
Temperature VCC = 3V, 30Hz Mode
VCC = 5V
50
100
VCC = 3V
0.5
0
AVERAGE POWER DISSIPATION (µW)
VCC = 3V
VCC = 5V
1.0
10000
200
SLEEP CURRENT (nA)
CONVERSION CURRENT (µA)
500
300
1.5
100
250
400
2.0
Sleep Mode Power Supply
Current vs Temperature
600
100
75
2451 G08
Conversion Mode Power Supply
Current vs Temperature
VCC = 5V
25
50
0
TEMPERATURE (°C)
Transition Noise vs Output Code
3.0
0
–50
100
75
–25
2451 G06
TRANSITION NOISE RMS (µV)
10
VCC = 4.1V
0.00
–50
100
75
Transition Noise vs Temperature
8
VCC = 5V, 4.1V, 3V
0.20
2451 G05
Gain Error vs Temperature
4
0.25
0.15
2451 G04
6
0.30
VCC = 3V
0.05
0.5
0
–50
OFFSET (mV)
5.0
OFFSET (mV)
INL (LSB)
Maximum INL vs Temperature
VCC = 3V
–25
0
25
50
TEMPERATURE (°C)
75
100
2451 G11
25Hz OUTPUT SAMPLE RATE
10Hz OUTPUT SAMPLE RATE
100
1Hz OUTPUT SAMPLE RATE
10
1
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
2451 G12
2451fg
5
LTC2451
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C; graphs apply to both 30Hz and 60Hz
modes, unless otherwise noted.
Average Power Dissipation vs
Temperature VCC = 3V, 60Hz Mode
Power Supply Rejection
vs Frequency at VCC
0
–20
1000
25Hz OUTPUT SAMPLE RATE
REJECTIOIN (dB)
AVERAGE POWER DISSIPATION (µW)
10000
10Hz OUTPUT SAMPLE RATE
100
1Hz OUTPUT SAMPLE RATE
–40
–60
–80
30Hz MODE, 60Hz MODE
10
–100
1
–50
–25
0
25
50
TEMPERATURE (°C)
75
–120
100
1
10
100 1k 10k 100k
FREQUENCY AT VCC (Hz)
1M
2451 G13
2451 G14
Conversion Period vs Temperature
60Hz Mode
44
22
42
21
CONVERSION TIME (ms)
CONVERSION TIME (ms)
Conversion Period vs Temperature
30Hz Mode
40
38
VCC = 5.5V, 4.1V, 2.7V
36
34
32
30
–45 –25
10M
20
19
VCC = 5.5V, 4.1V, 2.7V
18
17
16
35
15
55
–5
TEMPERATURE (°C)
75
95
2451 G15
15
–45 –25
35
15
55
–5
TEMPERATURE (°C)
75
95
2451 G16
2451fg
6
LTC2451
PIN FUNCTIONS
GND (Pin 1, 5): Ground. Connect to a ground plane through
a low impedance connection.
REF– (Pin 2), REF+ (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 2.5V. The differential reference voltage
(VREF = REF+ to REF–) sets the full-scale range.
VCC (Pin 4): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10µF capacitor in parallel with a low series
inductance 0.1µF capacitor located as close to the part
as possible.
IN (Pin 6): Analog Input. IN’s single-ended input range
is VREF– to VREF+.
SCL (Pin 7): Serial Clock Input of the I2C Interface. The
LTC2451 can only act as a slave and the SCL pin only
accepts an external serial clock. Data is shifted into the
SDA pin on the rising edges of SCL and output through
the SDA pin on the falling edges of SCL.
SDA (Pin 8): Bidirectional Serial Data Line of the I2C Interface. The conversion result is output through the SDA
pin. The pin is high impedance unless the LTC2451 is in
the data output mode. While the LTC2451 is in the data
output mode, SDA is an open-drain pull-down (which
requires an external 1.7k pull-up resistor to VCC).
Exposed Pad (Pin 9): Ground. Must be soldered to PCB
ground.
BLOCK DIAGRAM
3
REF +
4
VCC
I2C
INTERFACE
6
IN
16-BIT ∆∑
A/D CONVERTER
SCL
SDA
7
8
INTERNAL
OSCILLATOR
2
REF –
1
GND
1, 5, 9
2451 BD
2451fg
7
LTC2451
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2451 is a low power, delta-sigma analog-todigital converter with an I2C interface. Its operation, as
shown in Figure 1, is composed of three successive states:
conversion, sleep, and data input/output.
Initially, at power-up, the LTC2451 is set to its default 60Hz
mode and performs a conversion. Once the conversion is
complete, the device enters the sleep state. While in the
sleep state, power consumption is reduced by several
orders of magnitude. The part remains in the sleep state
as long it is not addressed for a read or write operation.
The conversion result is held indefinitely in a static shift
register while the part is in the sleep state.
The device will not acknowledge an external request during the conversion state. After a conversion is finished,
the device is ready to accept a read/write request. The
LTC2451’s address is hard wired at 0010100. Once the
LTC2451 is addressed for a read operation, the device
begins outputting the conversion result under the control
of the serial clock (SCL). There is no latency in the conversion result. The data output is 16 bits long and outputs
from MSB to LSB. Data is updated on the falling edges of
POWER-ON RESET
CONVERSION
SLEEP
NO
READ/WRITE
ACKNOWLEDGE
YES
DATA INPUT/OUTPUT
NO
STOP
OR READ
16 BITS
YES
2451 F01
Figure 1. State Diagram
SCL, allowing the user to reliably latch data on the rising
edge of SCL. In write operation, the device accepts one
configuration byte and the data is shifted in on the rising
edges of SCL. A new conversion is initiated by a STOP
condition following a valid read or write operation, or by
the conclusion of a complete read cycle (all 16 bits read
out of the device).
Power-Up Sequence
When the power supply voltage, VCC, applied to the converter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
When VCC rises above this threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2451 starts
a conversion cycle and follows the succession of states
described in Figure 1. The first conversion result following POR is accurate within the specifications of the device
if the power supply voltage, VCC, is restored within the
operating range (2.7V to 5.5V) before the end of the POR
time interval.
Ease of Use
The LTC2451 data output has no latency, filter settling
delay, or redundant results associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog input voltages requires no special actions.
In the 30Hz mode, the LTC2451 performs offset calibrations
during every conversion. This calibration is transparent to
the user and has no effect upon the cyclic operation previously described. The advantage of continuous calibration
is stability of the ADC performance with respect to time
and temperature.
The LTC2451 includes a proprietary input sampling scheme
that reduces the average input current by several orders
of magnitude when compared to traditional delta-sigma
architectures. This allows external filter networks to interface
directly to the LTC2451. Since the average input sampling
current is 50nA, an external RC lowpass filter using a 1kΩ
and 0.1µF results in less than 1LSB additional error.
2451fg
8
LTC2451
APPLICATIONS INFORMATION
Reference Voltage Range
This converter accepts a truly differential external reference
voltage. The voltage range for the REF+ and REF– pins
covers the entire operating range of the device (GND to
VCC). For correct converter operation, VREF+ – VREF– ≥ 2.5V.
The LTC2451 differential reference input range is 2.5V to
VCC. For the simplest operation, REF+ can be shorted to
VCC and REF– can be shorted to GND.
Input Voltage Range
Ignoring offset and full-scale errors, the converter will
theoretically output an “all zero” digital result when the
input is at VREF– (a zero scale input) and an “all one” digital
result when the input is at VREF+ (a full-scale input). In an
underrange condition, for all input voltages less than the
voltage corresponding to output code 0, the converter will
generate the output code 0. In an overrange condition,
for all input voltages greater than the voltage corresponding to output code 65535, the converter will generate the
output code 65535.
I2C INTERFACE
The LTC2451 communicates through an I2C interface. The
I2C interface is a 2-wire open-drain interface supporting
multiple devices and masters on a single bus. The connected devices can only pull the data line (SDA) LOW and
never drive it HIGH. SDA is externally connected to the
supply through a pull-up resistor. When the data line is
free, it is pulled HIGH through this resistor. Data on the
I2C bus can be transferred at rates up to 100k/s in the
standard mode and up to 400k/s in the fast mode. The
VCC power should not be removed from the device when
the I2C bus is active to avoid loading the I2C bus lines
through the internal ESD protection diodes.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate either as
a transmitter or receiver, depending on the function of
the device. In addition to transmitters and receivers,
devices can also be considered as masters or slaves when
performing data transfers. A master is the device which
initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Devices addressed
by the master are considered a slave. The address of the
LTC2451 is 0010100.
The LTC2451 can only be addressed as a slave. It can only
transmit the last conversion result. The serial clock line,
SCL, is always an input to the LTC2451 and the serial data
line, SDA, is bidirectional. Figure 2 shows the definition
of the I2C timing.
The START and STOP Conditions
A START (S) condition is generated by transitioning SDA
from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from LOW to HIGH while SCL is pulled
HIGH. The bus is free after a STOP is generated. START
and STOP conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated START (Sr) conditions are functionally identical
to the START (S).
SDA
tf
tLOW
tSU(DAT)
tr
tf
tHD(SDA)
tSP
tr
tBUF
SCL
S
tHD(STA)
tHD(DAT)
tHIGH
tSU(STA)
Sr
tSU(STO)
P
S
2451 F02
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
2451fg
9
LTC2451
APPLICATIONS INFORMATION
Data Transferring
and 0 for a write request. If the 7-bit address agrees with
the LTC2451’s address, the device is selected. When the
device is addressed during the conversion state, it does
not accept the request and issues a NACK by leaving the
SDA line high. If the conversion is complete, the LTC2451
issues an ACK by pulling the SDA line LOW.
After the START condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a not-acknowledge (NACK) by leaving the
SDA line high impedance (the external pull-up resistor will
hold the line high). Change of data only occurs while the
clock line (SCL) is low.
Data Format
The user can send one byte of data into the LTC2451 following a write request and an ACK. The sequence is shown
in Figure 3. The write sequence is used solely to set the
conversion speed. The default conversion speed is 60Hz.
The user can specify a 30Hz conversion speed by setting
the eighth bit (S30) = 1, or specify a 60Hz conversion
speed by setting the eighth bit (S30) = 0.
After a START condition, the master sends a 7-bit address
(factory set at 0010100), followed by a read request (R)
or write request (W) bit. The bit R is 1 for a read request
After a read request and an ACK, the LTC2451 can output
data, as shown in Figure 4. The data output stream is 16
bits long and is shifted out on the falling edges of SCL.
1
7
8
9
1
2
3
4
5
6
7
8
9
SCL
7-BIT
ADDRESS
SDA
W
S30
ACK BY
LTC2451
START BY
MASTER
S30 = 1: 30Hz MODE
S30 = 0: 60Hz MODE
ACK BY
MASTER
SLEEP
DATA INPUT
2451 F03
Figure 3. Timing Diagram for Write Sequence
1
7
8
9
1
2
3
D15
D14
D13
8
9
1
2
3
8
D7
D6
D5
D0
9
SCL
SDA
7-BIT
ADDRESS
R
D8
MSB
ACK BY
LTC2451
START BY
MASTER
SLEEP
LSB
ACK BY
MASTER
DATA OUTPUT
NACK BY
MASTER
CONVERT
2451 F04
Figure 4. Timing Diagram for Read Sequence
2451fg
10
LTC2451
APPLICATIONS INFORMATION
The first bit is the MSB (D15) and is followed by successively less significant bits (D14, D13 ...) until the LSB (D0)
is output by the LTC2451. This sequence is summarized
in Figure 5.
not concluded and a valid address selects the device, the
LTC2451 generates a NACK signal indicating the conversion cycle is in progress.
OPERATION SEQUENCE
Continuous Read
Once the conversion cycle is concluded, the LTC2451
can be written to, and then read from, using the repeated
START (Sr) command.
Conversions from the LTC2451 can be continuously read
(see Figure 7). At the end of a read operation, a new
conversion automatically begins. At the conclusion of
the conversion cycle, the next result may be read using
the method described above. If the conversion cycle is
Figure 7 shows a cycle which begins with a data write, a
repeated START, followed by a read, and concluded with a
STOP command. The following conversion begins after all
16 bits are read out of the device, or after the STOP com
mand, and uses the newly programmed configuration.
S
7-BIT ADDRESS
(0010100)
CONVERSION
R
Continuous Read/Write
ACK
READ
P
DATA OUTPUT
SLEEP
CONVERSION
2451 F05
Figure 5. Conversion Sequence
S
CONVERSION
7-BIT ADDRESS
(0010100)
R
ACK
SLEEP
READ
P
DATA OUTPUT
S
CONVERSION
7-BIT ADDRESS
(0010100)
R
ACK
SLEEP
READ
P
DATAOUTPUT
CONVERSION
2451 F06
Figure 6. Consecutive Reading at the Same Configuration
S
CONVERSION
7-BIT ADDRESS
(0010100)
SLEEP
W ACK
WRITE
DATA INPUT
Sr
7-BIT ADDRESS
(0010100)
R
ADDRESS
ACK
READ
DATA OUTPUT
P
CONVERSION
2451 F07
Figure 7. Write, Read, START Conversion
2451fg
11
LTC2451
APPLICATIONS INFORMATION
Discarding a Conversion Result and Initiating a New
Conversion with Optional Configuration Updating
At the conclusion of a conversion cycle, a write cycle
can be initiated. Once the write cycle is acknowledged, a
STOP (P) command initiates a new conversion. If a new
configuration is required, this data can be written into the
device and a STOP command initiates a new conversion
(see Figure 8).
Synchronizing the LTC2451 with the Global Address Call
The LTC2451 can also be synchronized with the global
address call (see Figure 9). To achieve this, the LTC2451
must first have completed the conversion cycle. The
master issues a START, followed by the LTC2451 global
address 1110111, and a write request. The LTC2451 will
be selected and acknowledge the request. If desired, the
master then sends the write byte to program the 30Hz
or 60Hz mode. After the optional write byte, the master
ends the write operation with a STOP. This will update
the configuration registers (if a write byte was sent) and
initiate a new conversion on the LTC2451, as shown in
Figure 9. In order to synchronize the start of the conversion without affecting the configuration registers, the
write operation can be aborted with a STOP. This initiates
a new conversion on the LTC2451 without changing the
configuration registers.
7-BIT ADDRESS
(0010100)
S
CONVERSION
SLEEP
PRESERVING THE CONVERTER ACCURACY
The LTC2451 is designed to dramatically reduce the conversion result’s sensitivity to device decoupling, PCB layout,
antialiasing circuits, line and frequency perturbations.
Nevertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable.
Digital Signal Levels
Due to the nature of CMOS logic, it is advisable to keep
input digital signals near GND or VCC. Voltages in the
range of 0.5V to VCC – 0.5V may result in additional current leakage from the part.
Driving VCC and GND
In relation to the VCC and GND pins, the LTC2451 combines internal high frequency decoupling with damping
elements, which reduce the ADC performance sensitivity
to PCB layout and external components. Nevertheless, the
very high accuracy of this converter is best preserved by
careful low and high frequency power supply decoupling.
A 0.1µF, high quality, ceramic capacitor in parallel with a
10µF ceramic capacitor should be connected between the
VCC and GND pins, as close as possible to the package.
The 0.1µF capacitor should be placed closest to the ADC.
W ACK
WRITE
(OPTIONAL)
DATA INPUT
P
CONVERSION
2451 F08
Figure 8. Start a New Conversion without Reading Old Conversion Result
S
GLOBAL ADDRESS
(1110111)
SLEEP
W
ACK
WRITE (OPTIONAL)
DATA INPUT
P
CONVERSION
2451 F09
Figure 9. Synchronize the LTC2451 with the Global Address Call
2451fg
12
LTC2451
APPLICATIONS INFORMATION
It is also desirable to avoid any via in the circuit path,
starting from the converter VCC pin, passing through these
two decoupling capacitors, and returning to the converter
GND pin. The area encompassed by this circuit path, as
well as the path length, should be minimized.
A 0.1µF, high quality, ceramic capacitor in parallel with
a 10µF ceramic capacitor should be connected between
the REF +/REF – and GND pins, as close as possible to the
package. The 0.1µF capacitor should be placed closest
to the ADC.
Very low impedance ground and power planes, and star
connections at both VCC and GND pins, are preferable. The
VCC pin should have three distinct connections: the first to
the decoupling capacitors described above, the second to
the ground return for the input signal source, and the third
to the ground return for the power supply voltage source.
Driving IN
Driving REF+ and REF –
A simplified equivalent circuit for REF+ and REF – is shown
in Figure 10. Like all other A/D converters, the LTC2451
is only as accurate as the reference it is using. Therefore,
it is important to keep the reference line quiet by careful
low and high frequency power supply decoupling.
The LT6660 reference is an ideal match for driving the
LTC2451’s REF+ pin. The LTC6660 is available in a 2mm
× 2mm DFN package with 2.5V, 3V, 3.3V and 5V options.
VCC
ILEAK
REF +
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 11. The input signal, VSIG, is
connected to the ADC input pin (IN) through an equivalent
source resistance RS . This resistor includes both the actual
generator source resistance and any additional optional
resistors connected to the input pin. An optional input
capacitor, CIN, is also connected between the ADC input
pin and GND. This capacitor is placed in parallel with the
ADC input parasitic capacitance, CPAR. Depending on the
PCB layout, CPAR has typical values between 2pF and 15pF.
In addition, the equivalent circuit of Figure 11 includes the
converter equivalent internal resistor, RSW, and sampling
capacitor, CEQ.
VCC
RSW
15k
(TYP)
ILEAK
RS
+
–
ILEAK
VSIG
IN
CIN
CPAR
ILEAK
RSW
15k
(TYP)
CEQ
0.35pF
(TYP)
ICONV
2451 F11
VCC
ILEAK
CEQ
0.35pF
(TYP)
RSW
15k
(TYP)
IN
Figure 11. LTC2451 Input Drive Equivalent Circuit
ILEAK
VCC
ILEAK
REF –
RSW
15k
(TYP)
2451 F10
ILEAK
Figure 10. LTC2451 Analog Input and
Reference Pins Equivalent Circuit
2451fg
13
LTC2451
APPLICATIONS INFORMATION
There are some immediate trade-offs in RS and CIN without
needing a full circuit analysis. Increasing RS and CIN can
provide the following benefits:
1. Due to the LTC2451’s input sampling algorithm, the
input current drawn by the input pin (IN) over a conversion cycle is 50nA. A high RS • CIN attenuates the
high frequency components of the input current, and
RS values up to 1k result in
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