LTC2452
Ultra-Tiny, Differential, 16-Bit
∆Σ ADC with SPI Interface
Description
Features
±VCC Differential Input Range
n 16-Bit Resolution (Including Sign), No Missing
Codes
n 2LSB Offset Error
n 4LSB Full-Scale Error
n 60 Conversions Per Second
n Single Conversion Settling Time for Multiplexed
Applications
n Single-Cycle Operation with Auto Shutdown
n 800µA Supply Current
n 0.2µA Sleep Current
n Internal Oscillator—No External Components
Required
n SPI Interface
n Ultra-Tiny 3mm × 2mm DFN and TSOT-23 Packages
n
Applications
n
n
n
n
n
n
n
System Monitoring
Environmental Monitoring
Direct Temperature Measurements
Instrumentation
Industrial Process Control
Data Acquisition
Embedded ADC Upgrades
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No
Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242,
7088280, 7164378.
The LTC®2452 is an ultra-tiny, fully differential, 16-bit,
analog-to-digital converter. The LTC2452 uses a single
2.7V to 5.5V supply and communicates through an SPI
interface. The ADC is available in an 8-pin, 3mm × 2mm
DFN package or TSOT-23 package. It includes an integrated
oscillator that does not require any external components.
It uses a delta-sigma modulator as a converter core and
has no latency for multiplexed applications. The LTC2452
includes a proprietary input sampling scheme that reduces
the average input sampling current several orders of
magnitude when compared to conventional delta-sigma
converters. Additionally, due to its architecture, there is
negligible current leakage between the input pins.
The LTC2452 can sample at 60 conversions per second,
and due to the very large oversampling ratio, has extremely
relaxed anti-aliasing requirements. The LTC2452 includes
continuous internal offset and full-scale calibration algorithms which are transparent to the user, ensuring accuracy
over time and over the operating temperature range. The
converter has an external REF pin and the differential input
voltage range can extend up to ±VREF .
Following a single conversion, the LTC2452 can automatically enter a sleep mode and reduce its supply current to
less than 0.2µA. If the user reads the ADC once a second,
the LTC2452 consumes an average of less than 50µW
from a 2.7V supply.
Typical Application
Integral Nonlinearity, VCC = 3V
3
2.7V TO 5.5V
0.1µF
10k
IN+
10k
IN–
10k
R
0.1µF
REF
VCC
1
CS
LTC2452
SCK
SDO
3-WIRE SPI
INTERFACE
INL (LSB)
0.1µF
2
10µF
TA = –45°C, 25°C, 90°C
0
–1
GND
–2
2452 TA01a
–3
–3
1
2
–2
–1
0
DIFFERENTIAL INPUT VOLTAGE (V)
3
2452 TA01b
2452fd
For more information www.linear.com/LTC2452
1
LTC2452
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (VCC).................................... –0.3V to 6V
Analog Input Voltage (VIN+, VIN –)..–0.3V to (VCC + 0.3V)
Reference Voltage (VREF)...............–0.3V to (VCC + 0.3V)
Digital Voltage (VSDO, VSCK, VCS)..–0.3V to (VCC + 0.3V)
Storage Temperature Range................... –65°C to 150°C
Operating Temperature Range
LTC2452C................................................. 0°C to 70°C
LTC2452I..............................................–40°C to 85°C
Pin Configuration
TOP VIEW
SCK
1
GND
2
REF
3
VCC
4
9
8
SDO
7
CS
6
IN
+
5
IN–
TOP VIEW
SCK 1
GND 2
REF 3
VCC 4
8 SDO
7 CS
6 IN+
5 IN–
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
C/I GRADE TJMAX = 125°C, θJA = 140°C/W
DD8 PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
C/I GRADE TJMAX = 125°C, θJA = 76°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
Order Information
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2452CDDB#TRMPBF
LTC2452CDDB#TRPBF
LDNJ
8-Lead Plastic (3mm × 2mm) DFN
LTC2452IDDB#TRMPBF
LTC2452IDDB#TRPBF
LDNJ
8-Lead Plastic (3mm × 2mm) DFN
LTC2452CTS8#TRMPBF
LTC2452CTS8#TRPBF
LTDPK
8-Lead Plastic TSOT-23
LTC2452ITS8#TRMPBF
LTC2452ITS8#TRPBF
LTDPK
8-Lead Plastic TSOT-23
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
16
UNITS
Bits
Resolution (No Missing Codes)
(Note 3)
l
Integral Nonlinearity
(Note 4)
l
1
10
LSB
l
2
10
LSB
Offset Error
Offset Error Drift
0.02
Gain Error
l
0.01
LSB/°C
0.02
% of FS
Gain Error Drift
0.02
LSB/°C
Transition Noise
2.2
µVRMS
Power Supply Rejection DC
80
dB
2
2452fd
For more information www.linear.com/LTC2452
LTC2452
Analog
Inputs And References
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0
VREF
V
l
0
VREF
V
l
2.5
+
Positive Input Voltage Range
l
VIN
–
Negative Input Voltage Range
VREF
Reference Voltage Range
VOR+ + VUR+
Overrange + Underrange Voltage, IN+
VREF = 5V, VIN– = 2.5V (See Figure 3)
31
LSB
VOR– + VUR–
Overrange + Underrange Voltage, IN–
VREF = 5V, VIN+ = 2.5V (See Figure 3)
31
LSB
CIN
IN+, IN– Sampling Capacitance
IDC_LEAK(IN+)
IN+ DC Leakage Current
VIN = GND (Note 10)
VIN = VCC (Note 10)
l
l
–10
–10
1
1
10
10
nA
nA
IDC_LEAK(IN–)
IN– DC Leakage Current
VIN = GND (Note 10)
VIN = VCC (Note 10)
l
l
–10
–10
1
1
10
10
nA
nA
IDC_LEAK(REF)
REF DC Leakage Current
VREF = 3V (Note 10)
l
–10
1
10
nA
ICONV
Input Sampling Current (Note 5)
VIN
VCC
V
0.35
pF
50
nA
Power Requirements
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion
Sleep
CONDITIONS
MIN
l
CS = GND (Note 6)
CS = VCC (Note 6)
TYP
2.7
800
0.2
l
l
MAX
UNITS
5.5
V
1200
0.6
µA
µA
Digital Inputs And Digital Outputs
The l denotes the specifications which apply over the full
operating temperature range,otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
l
–10
VCC – 0.5
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –800µA
l
VOL
Low Level Output Voltage
IO = 1.6mA
l
IOZ
Hi-Z Output Leakage Current
TYP
MAX
VCC – 0.3
V
0.3
V
10
µA
10
l
–10
UNITS
pF
V
0.4
V
10
µA
2452fd
For more information www.linear.com/LTC2452
3
LTC2452
Timing
Characteristics The l denotes the specifications which apply over the full operating temperature
range,otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
tCONV
Conversion Time
CONDITIONS
l
fSCK
SCK Frequency Range
l
tlSCK
SCK Low Period
l
250
ns
thSCK
SCK High Period
l
250
ns
t1
CS Falling Edge to SDO Low-Z
(Notes 7, 8)
l
0
100
ns
t2
CS Rising Edge to SDO Hi-Z
(Notes 7, 8)
l
0
100
ns
t3
CS Falling Edge to SCK Falling Edge
l
100
tKQ
SCK Falling Edge to SDO Valid
l
0
(Note 7)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V
unless otherwise specified.
VREFCM = VREF/2, FS = VREF
VIN = VIN+ – VIN–, –VREF ≤ VIN ≤ VREF; VINCM = (VIN+ + VIN–)/2.
Note 3. Guaranteed by design, not subject to test.
Note 4. Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
Guaranteed by design and test correlation.
Integral Nonlinearity, VCC = 5V
3
2
2
TA = 90°C
Integral Nonlinearity, VCC = 3V
TA = –45°C, 25°C
0
–2
–2
2452 G01
4
MHz
ns
100
ns
–3
1
2
–2
–1
0
DIFFERENTIAL INPUT VOLTAGE (V)
3
2452 G02
VCC = VREF = 5V, 4.1V, 3V
0
–2
–3
2
1
TA = –45°C, 25°C, 90°C
–1
5
ms
2
–1
–5 –4 –3 –2 –1 0 1 2 3 4
DIFFERENTIAL INPUT VOLTAGE (V)
UNITS
Maximum INL vs Temperature
–1
–3
23
3
INL (LSB)
0
MAX
16.6
(TA = 25°C, unless otherwise noted)
1
INL (LSB)
INL (LSB)
1
TYP
13
Note 5: CS = VCC. A positive current is flowing into the DUT pin.
Note 6: SCK = VCC or GND. SDO is high impedance.
Note 7: See Figure 4.
Note 8: See Figure 5.
Note 9: Input sampling current is the average input current drawn from the
input sampling network while the LTC2452 is actively sampling the input.
Note 10: A positive current is flowing into the DUT pin.
Typical Performance Characteristics
3
MIN
–3
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
2452 G03
2452fd
For more information www.linear.com/LTC2452
LTC2452
Typical Performance Characteristics
Gain Error vs Temperature
5
4
4
3
3
2
2
1
VCC = VREF = 5V
0
–1
–2
VCC = VREF = 3V
–3
VCC = VREF = 4.1V
Transition Noise vs Temperature
10
9
VCC = VREF = 3V
TRANSITION NOISE RMS (µV)
5
GAIN ERROR (LSB)
OFFSET ERROR (LSB)
Offset Error vs Temperature
(TA = 25°C, unless otherwise noted)
VCC = VREF = 4.1V
1
0
VCC = VREF = 5V
–1
–2
–3
–4
–4
–5
–50
–25
25
50
0
TEMPERATURE (°C)
75
–25
25
50
0
TEMPERATURE (°C)
75
2452 G04
VCC = 4.1V
100
50
75
VCC = 3V
0
–50
100
–25
25
50
0
TEMPERATURE (°C)
2452 G07
25
50
0
TEMPERATURE (°C)
75
100
75
100
25Hz OUTPUT SAMPLE RATE
10Hz OUTPUT SAMPLE RATE
100
1Hz OUTPUT SAMPLE RATE
10
0
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
2452 G09
2452 G08
Power Supply Rejection
vs Frequency at VCC
Conversion Time vs Temperature
21
0
20
CONVERSION TIME (ms)
–20
–40
–60
–80
–100
–120
–25
2452 G06
AVERAGE POWER DISSIPATION (µW)
SLEEP CURRENT (nA)
150
100
25
50
0
TEMPERATURE (°C)
VCC = 3V
1000
VCC = 5V
200
REJECTION (dB)
CONVERSION CURRENT (µA)
VCC = 4.1V
300
–25
2
10000
200
VCC = 5V
400
0
–50
3
Average Power Dissipation
vs Temperature, VCC = 3V
250
VCC = 3V
VCC = 5V
4
0
–50
100
800
500
5
Sleep Mode Power Supply
Current vs Temperature
900
600
6
2452 G05
Conversion Mode Power Supply
Current vs Temperature
700
7
1
–5
–50
100
8
19
VCC = 5V, 4.1V, 3V
18
17
16
15
1
10
100 1k 10k 100k
FREQUENCY AT VCC (Hz)
1M
10M
14
–50
–25
2452 G10
25
50
0
TEMPERATURE (°C)
75
100
2452 G11
2452fd
For more information www.linear.com/LTC2452
5
LTC2452
Pin Functions
SCK (Pin 1): Serial Clock Input. SCK synchronizes the
serial data output. While digital data is available (the ADC
is not in CONVERT state) and CS is LOW (ADC is not in
SLEEP state) a new data bit is produced at the SDO output
pin following every falling edge applied to the SCK pin.
GND (Pin 2): Ground. Connect to a ground plane through
a low impedance connection.
REF (Pin 3): Reference Input. The voltage on REF can have
any value between 2.5V and VCC. The reference voltage
sets the full-scale range.
VCC (Pin 4): Positive Supply Voltage. Bypass to GND
(Pin 2) with a 10µF capacitor in parallel with a low-seriesinductance 0.1µF capacitor located as close to the LTC2452
as possible.
IN– (Pin 5), IN+ (Pin 6): Differential Analog Input.
CS (Pin 7): Chip Select (Active LOW) Digital Input. A LOW
on this pin enables the SDO digital output. A HIGH on this
pin places the SDO output pin in a high impedance state.
SDO (Pin 8): Three-State Serial Data Output. SDO is used
for serial data output during the DATA OUTPUT state and
can be used to monitor the conversion status.
Exposed Pad (Pin 9): Ground. Must be soldered to PCB
ground. For prototyping purposes, this pad may remain
floating.
Block Diagram
3
4
REF
VCC
CS
6
IN
+
SPI
INTERFACE
16-BIT ΔΣ
A/D CONVERTER
–
5
IN–
16-BIT ΔΣ
A/D CONVERTER
2, 9
SDO
SCK
7
8
1
DECIMATING
SINC FILTER
INTERNAL
OSCILLATOR
GND
2452 BD
Figure 1. Functional Block Diagram
Applications Information
Converter Operation
Converter Operation Cycle
The LTC2452 is a low power, fully differential, delta-sigma
analog-to-digital converter with a simple 3-wire SPI interface (see Figure 1). Its operation is composed of three
successive states: CONVERT, SLEEP and DATA OUTPUT.
6
The operating cycle begins with the CONVERT state, is
followed by the SLEEP state, and ends with the DATA OUTPUT state (see Figure 2). The 3-wire interface consists of
serial data output (SDO), serial clock input (SCK), and the
active low chip select input (CS).
The CONVERT state duration is determined by the LTC2452
conversion time (nominally 16.6 milliseconds). Once
2452fd
For more information www.linear.com/LTC2452
LTC2452
applications information
of data appears at the SDO pin following each falling edge
detected at the SCK input pin and appears from MSB to
LSB. The user can reliably latch this data on every rising
edge of the external serial clock signal driving the SCK
pin (see Figure 3).
POWER-ON RESET
CONVERT
SLEEP
NO
The DATA OUTPUT state concludes in one of two different
ways. First, the DATA OUTPUT state operation is completed
once all 16 data bits have been shifted out and the clock
then goes low. This corresponds to the 16th falling edge
of SCK. Second, the DATA OUTPUT state can be aborted
at any time by a LOW-to-HIGH transition on the CS input.
Following either one of these two actions, the LTC2452 will
enter the CONVERT state and initiate a new conversion cycle.
SCK = LOW
AND
CS = LOW?
YES
DATA OUTPUT
Power-Up Sequence
NO
16TH FALLING
EDGE OF SCK
OR
CS = HIGH?
When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
YES
2452 F02
Figure 2. LTC2452 State Transition Diagram
started, this operation can not be aborted except by a low
power supply condition (VCC < 2.1V) which generates an
internal power-on reset signal.
After the completion of a conversion, the LTC2452 enters
the SLEEP state and remains there until both the chip
select and serial clock inputs are low (CS = SCK = LOW).
Following this condition, the ADC transitions into the DATA
OUTPUT state.
While in the SLEEP state, whenever the chip select input
is pulled high (CS = HIGH), the LTC2452’s power supply
current is reduced to less than 200nA. When the chip select
input is pulled low (CS = LOW), and SCK is maintained at a
HIGH logic level, the LTC2452 will return to a normal power
consumption level. During the SLEEP state, the result of
the last conversion is held indefinitely in a static register.
Upon entering the DATA OUTPUT state, SDO outputs the
sign (D15) of the conversion result. During this state,
the ADC shifts the conversion result serially through the
SDO output pin under the control of the SCK input pin.
There is no latency in generating this data and the result
corresponds to the last completed conversion. A new bit
When VCC rises above this critical threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2452 starts a
conversion cycle and follows the succession of states shown
in Figure 2. The first conversion result following POR is
accurate within the specifications of the device if the power
supply voltage VCC is restored within the operating range
(2.7V to 5.5V) before the end of the POR time interval.
Ease of Use
The LTC2452 data output has no latency, filter settling
delay or redundant results associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog input voltages requires no special actions.
The LTC2452 performs offset calibrations every conversion. This calibration is transparent to the user and has
no effect upon the cyclic operation described previously.
The advantage of continuous calibration is stability of the
ADC performance with respect to time and temperature.
The LTC2452 includes a proprietary input sampling scheme
that reduces the average input current by several orders
2452fd
For more information www.linear.com/LTC2452
7
LTC2452
applications information
of magnitude when compared to traditional delta-sigma
architectures. This allows external filter networks to interface directly to the LTC2452. Since the average input
sampling current is 50nA, an external RC lowpass filter
using 1kΩ and 0.1µF results in
工商网监
湘ICP备2023018690号
