LTC2473CDD#PBF

LTC2471/LTC2473 Selectable 208sps/833sps, 16-Bit I2C ΔΣ ADCs with 10ppm/°C Max Precision Reference Description Features n n n n n n 16-Bit Resolution Internal, High Accuracy Reference—10ppm/°C (Max) Single-Ended (LTC2471) or Differential (LTC2473) Selectable 208sps/833sps Output Rate 1mV Offset Error 0.01% Gain Error Single Conversion Settling Time Simplifies Multiplexed Applications n Single-Cycle Operation with Auto Shutdown n 3.5mA (Typ) Supply Current n 2µA (Max) Sleep Current n Internal Oscillator—No External Components Required n I2C Interface n Small 12-Lead, 3mm × 3mm DFN and MSOP Packages The LTC®2471/LTC2473 are small, 16-bit analog-to-digital converters with an integrated precision reference and a selectable 208sps or 833sps output rate. They use a single 2.7V to 5.5V supply and communicate through an I2C Interface. The LTC2471 is single-ended with a 0V to VREF input range and the LTC2473 is differential with a ±VREF input range. Both ADCs include a 1.25V integrated reference with 2ppm/°C drift performance and 0.1% initial accuracy. The converters are available in a 12-pin DFN 3mm × 3mm package or an MSOP-12 package. They include an integrated oscillator and perform conversions with no latency for multiplexed applications. The LTC2471/ LTC2473 include a proprietary input sampling scheme that reduces the average input current several orders of magnitude when compared to conventional delta sigma converters. Applications Following a single conversion, the LTC2471/LTC2473 automatically power down the converter and can also be configured to power down the reference. When both the ADC and reference are powered down, the supply current is reduced to 200nA. n System Monitoring Environmental Monitoring n Direct Temperature Measurements n Instrumentation n Industrial Process Control n Data Acquisition n Embedded ADC Upgrades n n L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation and Easy Drive and No Latency ∆∑ is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378. The LTC2471/LTC2473 include a user selectable 208sps or 833sps output rate and due to a large oversampling ratio (8,192 at 208sps and 2,048 at 833sps) have relaxed anti-aliasing requirements. Typical Application VREF vs Temperature 1.2520 0.1µF 0.1µF 0.1µF 10k REFOUT SCL LTC2473 IN– 10k R 0.1µF REF– 10µF COMP VCC IN+ 10k 0.1µF AO SDA GND 2 I C INTERFACE REFERENCE OUTPUT VOLTAGE (V) 2.7V TO 5.5V 1.2515 1.2510 1.2505 1.2500 1.2495 1.2490 1.2485 24713 TA01a 1.2480 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 24713 TA01b 24713fb For more information www.linear.com/LTC2471 1 LTC2471/LTC2473 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage (VCC).................................... –0.3V to 6V Analog Input Voltage (VIN+, VIN –, VIN, VREF –, VCOMP, VREFOUT )...........–0.3V to (VCC + 0.3V) Digital Voltage (VSDA, VSCL, VAO).....–0.3V to (VCC + 0.3V) Storage Temperature Range................... –65°C to 150°C Operating Temperature Range LTC2471C/LTC2473C................................ 0°C to 70°C LTC2471I/LTC2473I..............................–40°C to 85°C Pin Configuration LTC2473 LTC2473 TOP VIEW REFOUT 1 12 VCC COMP 2 11 GND 10 IN– AO 3 GND 4 SCL 5 8 REF– SDA 6 7 GND 13 GND TOP VIEW REFOUT COMP AO GND SCL SDA 9 IN+ DD PACKAGE 12-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) PCB GROUND CONNECTION 1 2 3 4 5 6 12 11 10 9 8 7 VCC GND IN– IN+ REF– GND MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 130°C/W LTC2471 LTC2471 TOP VIEW TOP VIEW 12 VCC REFOUT 1 COMP 2 AO 3 GND 4 SCL 5 8 REF– SDA 6 7 GND REFOUT COMP AO GND SCL SDA 11 GND 13 GND 10 GND 9 IN DD PACKAGE 12-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) PCB GROUND CONNECTION 1 2 3 4 5 6 12 11 10 9 8 7 VCC GND GND IN REF– GND MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 130°C/W Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2471CDD#PBF LTC2471CDD#TRPBF LFPW 12-Lead Plastic (3mm × 3mm) DFN 0°C to 70°C LTC2471IDD#PBF LTC2471IDD#TRPBF LFPW 12-Lead Plastic (3mm × 3mm) DFN –40°C to 85°C LTC2471CMS#PBF LTC2471CMS#TRPBF 2471 12-Lead Plastic MSOP 0°C to 70°C LTC2471IMS#PBF LTC2471IMS#TRPBF 2471 12-Lead Plastic MSOP –40°C to 85°C LTC2473CDD#PBF LTC2473CDD#TRPBF LFPX 12-Lead Plastic (3mm × 3mm) DFN 0°C to 70°C LTC2473IDD#PBF LTC2473IDD#TRPBF LFPX 12-Lead Plastic (3mm × 3mm) DFN –40°C to 85°C LTC2473CMS#PBF LTC2473CMS#TRPBF 2473 12-Lead Plastic MSOP 0°C to 70°C LTC2473IMS#PBF LTC2473IMS#TRPBF 2473 12-Lead Plastic MSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 24713fb 2 For more information www.linear.com/LTC2471 LTC2471/LTC2473 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) PARAMETER CONDITIONS MIN TYP Resolution MAX UNITS 16 Integral Nonlinearity Output Rate 208sps (Note 4) Output Rate 833sps (Note 4) Offset Error l Offset Error Drift Bits 2 8 8.5 16 ±1 ±2.5 l l 0.05 LSB LSB mV LSB/°C Gain Error l ±0.01 Gain Error Drift l 0.15 ±0.25 % of FS LSB/°C Transition Noise 3 µVRMS Power Supply Rejection DC 80 dB The Analog Inputs l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MAX UNITS VIN+ Positive Input Voltage Range LTC2473 l 0 VREF V VIN Negative Input Voltage Range LTC2473 l 0 VREF V VIN Input Voltage Range LTC2471 l 0 VOR+, VUR+ Overrange/Underrange Voltage, IN+ VIN– = 0.625V VOR–, VUR– Overrange/Underrange Voltage, IN– VIN+ = 0.625V CIN IN+, IN–, IN Sampling Capacitance IDC_LEAK(IN+, IN–, IN) IN+, IN– DC Leakage Current (LTC2473) ICONV Input Sampling Current (Notes 5, 8) VREF Reference Output Voltage – TYP VREF V 8 LSB 8 LSB 0.35 IN DC Leakage Current (LTC2471) Reference Voltage Coefficient MIN VIN = GND (Note 8) VIN = VCC (Note 8) l l –10 –10 ±1 ±1 pF 10 10 nA nA 50 l (Note 9) C-Grade I-Grade 1.247 l nA 1.25 1.253 ±2 ±5 ±10 V ppm/°C ppm/°C Reference Line Regulation 2.7V ≤ VCC ≤ 5.5V –90 dB Reference Short-Circuit Current VCC = 5.5, Forcing Output to GND (Note 8) l 35 mA COMP Pin Short-Circuit Current VCC = 5.5, Forcing Output to GND (Note 8) l 200 µA Reference Load Regulation 2.7V ≤ VCC ≤ 5.5V, IOUT = 100μA Sourcing 3.5 mV/mA Reference Output Noise Density CCOMP= 0.1μF, CREFOUT = 0.1μF, At f = 1ksps 30 nV/√Hz Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER VCC Supply Voltage ICC Supply Current Conversion Conversion Nap Sleep CONDITIONS MIN l LTC2473 (Note 8) LTC2471 (Note 8) (Note 8) (Note 8) l l l l TYP 2.7 MAX 5.5 3.5 2.5 800 0.2 5 4 1500 2 UNITS V mA mA µA µA 24713fb For more information www.linear.com/LTC2471 3 LTC2471/LTC2473 2C Inputs and Outputs I The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7) SYMBOL PARAMETER VIH High Level Input Voltage CONDITIONS l MIN VIL Low Level Input Voltage l II Digital Input Current (Note 8) l –10 0.05VCC TYP MAX UNITS 0.7VCC V 0.3VCC V 10 µA VHYS Hysteresis of Schmidt Trigger Inputs (Note 3) l VOL Low Level Output Voltage (SDA) I = 3mA l 0.4 V V IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l 1 µA CI Capacitance for Each I/O Pin l CB Capacitance Load for Each Bus Line l VIH(A0) High Level Input Voltage for Address Pin l VIL(A0) Low Level Input Voltage for Address Pin l 10 pF 400 pF 0.95VCC V 0.05VCC V I2C Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7) SYMBOL PARAMETER CONDITIONS TYP MAX tCONV1 Conversion Time SPD = 0 l MIN 4 4.8 UNITS ms tCONV2 Conversion Time SPD = 1 l 1 1.2 ms fSCL 400 kHz tHD(SDA,STA) SCL Clock Frequency l 0 Hold Time (Repeated) START Condition l 0.6 µs tLOW LOW Period of the SCL Pin l 1.3 µs tHIGH HIGH Period of the SCL Pin l 0.6 µs tSU(STA) Set-Up Time for a Repeated START Condition l 0.6 µs tHD(DAT) Data Hold Time l 0 0.9 µs tSU(DAT) Data Set-Up Time l 100 tr Rise Time for SDA, SCL Signals (Note 6) l 20 + 0.1CB 300 ns ns tf Fall Time for SDA, SCL Signals (Note 6) l 20 + 0.1CB 300 ns tSU(STO) Set-Up Time for STOP Condition l 0.6 µs tBUF Bus Free Time Between a STOP and START Condition l 1.3 µs tOF Output Fall Time VIHMIN to VILMAX l 20 + 0.1CB tSP Input Spike Suppression Bus Load CB = 10pF to 400pF (Note 6) l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V unless otherwise specified. VREFCM = VREF/2, FS = VREF, –VREF ≤ VIN ≤ VREF VIN = VIN+ – VIN –, VINCM = (VIN+ + VIN –)/2. (LTC2473) Note 3. Guaranteed by design, not subject to test. 250 ns 50 ns Note 4. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. Note 5: Input sampling current is the average input current drawn from the input sampling network while the LTC2471/LTC2473 are converting. Note 6: CB = capacitance of one bus line in pF. Note 7: All values refer to VIH(MIN) and VIL(MAX) levels. Note 8: A positive current is flowing into the DUT pin. Note 9: Voltage temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 24713fb 4 For more information www.linear.com/LTC2471 LTC2471/LTC2473 Typical Performance Characteristics Integral Nonlinearity (TA = 25°C, unless otherwise noted) Integral Nonlinearity 3 VCC = 2.7V TA = –45°C, 25°C, 90°C 2 OUTPUT RATE = 208sps Maximum INL vs Temperature 3 6 2 4 1 2 OUTPUT RATE = 208sps INL (LSB) 0 –1 –2 –2 –2 VCC = 5.5V TA = –45°C, 25°C, 90°C OUTPUT RATE = 208sps –3 0.25 0.75 –1.25 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) –4 –3 –1.25 0.25 0.75 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) 1.25 24713 G01 Offset Error vs Temperature ADC Gain Error vs Temperature VCC = 4.1V 15 10 VCC = 2.7V 0 –50 –30 50 –10 10 30 TEMPERATURE (°C) 30 20 VCC = 4.1V 10 VCC = 2.7V –10 10 30 50 TEMPERATURE (°C) 70 VCC = 5.5V 3.7 VCC = 4.1V 3.6 3.5 3.4 VCC = 2.7V 3.3 3.2 250 200 VCC = 4.1V 150 50 –10 10 30 TEMPERATURE (°C) 70 90 100 24713 G07 0 –50 VCC = 2.7V –30 VCC = 5.5V 5 4 3 VCC = 2.7V 2 50 –10 10 30 TEMPERATURE (°C) –30 24713 G05 VCC = 5.5V 50 3.1 –30 6 1.2508 300 SLEEP CURRENT (nA) 3.8 7 0 –50 90 350 3.9 24713 G03 8 Sleep Mode Power Supply Current vs Temperature 4.0 90 1 24713 G04 Conversion Mode Power Supply Current vs Temperature 3.0 –50 VCC = 5.5V –10 –50 –30 90 70 9 0 70 30 50 –10 10 TEMPERATURE (°C) Transition Noise vs Temperature TRANSITION NOISE RMS (µV) ADC GAIN ERROR (LSB) OFFSET ERROR (LSB) 20 –30 10 40 25 5 CONVERSION CURRENT (mA) –6 –50 1.25 50 VCC = 5.5V VCC = 2.7V 24713 G02 35 30 VCC = 4.1V 0 –1 REFERENCE OUTPUT VOLTAGE (V) INL (LSB) 0 INL (LSB) VCC = 5.5V 1 70 90 24713 G08 50 –10 10 30 TEMPERATURE (°C) 70 90 24713 G06 VREF vs Temperature 1.2507 1.2506 1.2505 1.2504 1.2503 1.2502 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 24713 G09 24713fb For more information www.linear.com/LTC2471 5 LTC2471/LTC2473 Typical Performance Characteristics Power Supply Rejection vs Frequency Applied to VCC Conversion Time vs Temperature 4.4 TA = 25°C CONVERSION TIME (ms) REJECTION (dB) –40 –60 –80 –120 VCC = 2.7V 1 10 100 1k 10k 100k FREQUENCY AT VCC (Hz) 1M 10M 1.250335 4.2 1.250330 VCC = 4.1V 4.1 1.250325 1.250320 4.0 3.8 –50 1.250315 VCC = 5.5V 3.9 –100 TA = 25°C 1.250340 4.3 –20 VREF vs VCC 1.250345 VREF (V) 0 (TA = 25°C, unless otherwise noted) 1.250310 –25 25 50 0 TEMPERATURE (°C) 24713 G010 75 100 24713 G11 1.250305 2.0 2.5 3.0 3.5 4.0 4.5 VCC (V) 5.0 5.5 6.0 24713 G12 Pin Functions REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V, this voltage sets the full-scale input range of the ADC. For noise and reference stability connect to a 0.1µF capacitor tied to GND. This capacitor value must be less than or equal to the capacitor tied to the reference compensation pin (COMP). REFOUT must not be overdriven by an external reference. COMP (Pin 2): Internal Reference Compensation Pin. For low noise and reference stability, tie a 0.1μF capacitor to GND. A0 (Pin 3): Chip Address Control Pin. The A0 pin can be tied to GND or VCC. If A0 is tied to GND, the LTC2471/ LTC2473 I2C address is 0010100. If A0 is tied to VCC, the LTC2471/LTC2473 I2C address is 1010100. GND (Pins 4, 7, 11, (Exposed Pad Pin 13 – DFN Package Only)): Ground. Connect exposed pad directly to the ground plane through a low impedance connection. I 2C Interface. The SCL (Pin 5): Serial Clock Input of the LTC2471/LTC2473 can only act as an I2C slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of SCL and output through the SDA pin on the falling edges of SCL. SDA (Pin 6): Bidirectional Serial Data Line of the I2C Interface. The conversion result is output through the SDA pin. The pin is high impedance unless the LTC2471/LTC2473 is in the data output mode. While the LTC2471/LTC2473 is in the data output mode, SDA is an open drain pull down (which requires an external 1.7k pull-up resistor to VCC). REF– (Pin 8): Negative Reference Input to the ADC. The voltage on this pin sets the zero input to the ADC. This pin should tie directly to ground or the ground sense of the input sensor. IN+ (LTC2473), IN (LTC2471) (Pin 9): Positive input voltage for the LTC2473 differential device. ADC input for the LTC2471 single-ended device. IN– (LTC2473), GND (LTC2471) (Pin 10): Negative input voltage for the LTC2473 differential device. GND for the LTC2471 single-ended device. VCC (Pin 12): Positive Supply Voltage. Bypass to GND with a 10μF capacitor in parallel with a low-series-inductance 0.1μF capacitor located as close to pin 12 as possible. 24713fb 6 For more information www.linear.com/LTC2471 LTC2471/LTC2473 Block Diagram 1 9 10 IN+ (IN) IN– (GND) 2 REFOUT COMP 12 AO INTERNAL REFERENCE ΔΣ A/D CONVERTER – VCC SPI INTERFACE DECIMATING SINC FILTER SCL SDA 3 5 6 ΔΣ A/D CONVERTER INTERNAL OSCILLATOR 8 REF– ( ) PARENTHESIS INDICATE LTC2471 4, 7, 11, 13 DD PACKAGE GND 4, 7, 11 MS PACKAGE 24713 BD Figure 1. Functional Block Diagram Applications Information Converter Operation POWER-ON RESET Converter Operation Cycle CONVERT The LTC2471/LTC2473 are low power, delta sigma, analog to digital converters with a simple I2C interface and a user selected 208sps/833sps output rate (see Figure 1). The LTC2473 has a fully differential input while the LTC2471 is single-ended. Both are pin and software compatible. Their operation is composed of three distinct states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT. The operation begins with the CONVERT state (see Figure 2). Once the conversion is finished, the converter automatically powers down (NAP) or under user control, both the converter and reference are powered down (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT state. Once all 16-bits are read or an abort is initiated, the device begins a new conversion. The CONVERT state duration is determined by the LTC2471/ LTC2473 conversion time (nominally 4.8ms or 1.2ms depending on the selected output rate). Once started, this operation can not be aborted except by a low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. SLEEP/NAP NO READ/WRITE ACKNOWLEDGE YES DATA INPUT/OUTPUT NO STOP OR READ 16 BITS YES 24713 F02 Figure 2. LTC2471/LTC2473 State Transition Diagram 24713fb For more information www.linear.com/LTC2471 7 LTC2471/LTC2473 applications information After the completion of a conversion, the LTC2471/LTC2473 enters the SLEEP/NAP state and remains there until a valid read/write is acknowledged. Following this condition, the ADC transitions into the DATA INPUT/OUTPUT state. While in the SLEEP/NAP state, the LTC2471/LTC2473’s converters are powered down. This reduces the supply current by approximately 70%. While in the NAP state the reference remains powered up. The user can power down both the reference and the converter by enabling the sleep mode during the DATA INPUT/OUTPUT state. Once the next conversion is complete with the sleep mode enabled, the SLEEP state is entered and power is reduced to 2μA (maximum). The reference is powered up once a valid read/write is acknowledged. The reference startup time is 12ms (if the reference and compensation capacitor values are both 0.1μF). As the reference and compensation capacitors are decreased, the startup time is reduced (see Figure 3), but the transition noise increases (see Figure 4). Power-Up Sequence When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. For proper operation VDD needs to be restored to normal operating range (2.7V to 5.5V) before the conclusion of the POR cycle. The POR signal clears all internal registers. Following the POR signal, the LTC2471/ LTC2473 start a conversion cycle and follow the succession of states shown in Figure 2. The reference startup time following a POR is 12ms (CCOMP = CREFOUT = 0.1μF). The first conversion following power-up will be invalid if the reference voltage has not completely settled (see Figure 3). The first conversion following power up can be discarded using the data abort command or simply read and ignored. Depending on the value chosen for CCOMP and CREFOUT, the reference startup can take more than one conversion period, see Figure 3. If the startup time is less than 1.2ms (833sps output rate) or 4.8ms (208sps output rate) then conversions following the first period are accurate to the device specifications. If the startup time exceeds 1.2ms or 4.8ms then the user can wait the appropriate time or use the fixed conversion period as a startup timer by ignoring results within the unsettled period. Once the reference has settled, all subsequent conversion results are valid. If the user places the device into the sleep mode (SLP = 1, reference powered down) the reference will require a startup time proportional to the value of CCOMP and CREFOUT (see Figure 3). 25 200 TRANSITION NOISE (µV RMS) 250 VCC = 2.7V TIME (ms) 150 VCC = 4.1V 100 50 VCC = 5.5V 0 –50 1 0.1 0.01 CAPACITANCE (µF) 0.001 20 15 10 5 0 0.0001 24713 F03 Figure 3. Reference Start-Up Time vs VREF and Compensation Capacitance 0.001 0.01 0.1 CAPACITANCE (µF) 1 10 24713 F04 Figure 4. Transition Noise RMS vs COMP and Reference Capacitance 24713fb 8 For more information www.linear.com/LTC2471 LTC2471/LTC2473 Applications Information Ease of Use I2C INTERFACE The LTC2471/LTC2473 data output has no latency, filter settling delay, or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. The LTC2471/LTC2473 communicate through an I2C interface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. The connected devices can only pull the data line (SDA) LOW and can never drive it HIGH. SDA must be externally connected to the supply through a pull-up resistor. When the data line is free, it is HIGH. Data on the I2C bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. The LTC2471/LTC2473 include a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional deltasigma architectures. This allows external filter networks to interface directly to the LTC2471/LTC2473. Since the average input sampling current is 50nA, an external RC lowpass filter using 1kΩ and 0.1µF results in