LTC2496
16-Bit 8-/16-Channel
ΔΣ ADC with Easy Drive
Input Current Cancellation
Features
Description
Up to 8 Differential or 16 Single-Ended Inputs
Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
n Directly Digitizes High Impedance Sensors with
Full Accuracy
n 600nV RMS Noise (0.02 LSB Transition Noise)
n GND to V
CC Input/Reference Common Mode Range
n Simultaneous 50Hz/60Hz Rejection
n 2ppm INL, No Missing Codes
n 1ppm Offset and 15ppm Full-Scale Error
n No Latency: Digital Filter Settles in a Single Cycle,
Even After a New Channel is Selected
n Single Supply 2.7V to 5.5V Operation (0.8mW)
n Internal Oscillator
n QFN 5mm × 7mm Package
The LTC®2496 is a 16-channel (8-differential) 16-bit No
Latency ΔΣ™ ADC with Easy Drive™ technology. The patented sampling scheme eliminates dynamic input current
errors and the shortcomings of on-chip buffering through
automatic cancellation of differential input current. This
allows large external source impedances, and rail-to-rail
input signals to be directly digitized while maintaining
exceptional DC accuracy.
n
n
The LTC2496 includes an integrated oscillator. This device
can be configured to measure an external signal (from
combinations of 16 analog input channels operating in
single ended or differential modes). It automatically rejects
line frequencies of 50Hz and 60Hz, simultaneously.
The LTC2496 allows a wide common mode input range
(0V to VCC), independent of the reference voltage. Any
combination of single-ended or differential inputs can be
selected and the first conversion after a new channel is
selected is valid. Access to the multiplexer output enables
optional external amplifiers to be shared between all analog
inputs and auto calibration continuously removes their
associated offset and drift.
Applications
Direct Sensor Digitizer
Direct Temperature Measurement
n Instrumentation
n Industrial Process Control
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
Data Acquisition System
+FS Error vs RSOURCE
80
2.7V TO 5.5V
MUXOUT/
ADCIN
REF+
IN+
16-BIT ∆∑ ADC
WITH EASY-DRIVE
IN–
COM
0.1µF
VCC
REF–
SDI
SCK
SDO
CS
10µF
4-WIRE
SPI INTERFACE
+FS ERROR (ppm)
CH0
CH1
•
•
•
CH7
CH8 16-CHANNEL
MUX
•
•
•
CH15
VCC = 5V
= 5V
60 VREF
VIN+ = 3.75V
– = 1.25V
V
40 IN
fO = GND
20 TA = 25°C
CIN = 1µF
0
–20
–40
–60
MUXOUT/
ADCIN
f0
OSC
2496 TA01a
–80
1
10
100
1k
RSOURCE (Ω)
10k
100k
2498 TA01b
2496fc
For more information www.linear.com/LTC2496
1
LTC2496
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
GND
GND
SDI
fO
CS
SCK
SDO
TOP VIEW
Supply Voltage (VCC).................................... –0.3V to 6V
Analog Input Voltage
(CH0 to CH15, COM)......................–0.3V to (VCC + 0.3V)
Reference Input Voltage.................–0.3V to (VCC + 0.3V)
ADCINN, ADCINP, MUXOUTP,
MUXOUTN.....................................–0.3V to (VCC + 0.3V)
Digital Input Voltage......................–0.3V to (VCC + 0.3V)
Digital Output Voltage....................–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2496C................................................. 0°C to 70°C
LTC2496I..............................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
38 37 36 35 34 33 32
GND 1
31 GND
NC 2
30 REF–
GND 3
29 REF+
GND 4
28 VCC
GND 5
27 MUXOUTN
GND 6
26 ADCINN
39
COM 7
25 ADCINP
CH0 8
24 MUXOUTP
CH1 9
23 CH15
CH2 10
22 CH14
CH3 11
21 CH13
20 CH12
CH4 12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2496CUHF#PBF
LTC2496CUHF#TRPBF
2496
38-Lead (5mm × 7mm) Plastic QFN
0°C to 70°C
LTC2496IUHF#PBF
LTC2496IUHF#TRPBF
2496
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
l
2
1
20
ppm of VREF
ppm of VREF
l
0.5
5
µV
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
Offset Error
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14)
Offset Error Drift
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
2
16
UNITS
Bits
10
nV/ºC
32
l
0.1
32
l
0.1
ppm of VREF
ppm of VREF/°C
ppm of VREF
ppm of VREF/°C
2496fc
For more information www.linear.com/LTC2496
LTC2496
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
15
15
15
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise
5.5V ≤ VCC ≤ 2.7V, 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13)
0.6
µVRMS
Converter
Characteristics l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
VREF = 2.5V, IN+ = IN– = GND
VREF = 2.5V, IN+ = IN– = GND (Notes 7, 9)
VREF = 2.5V, IN+ = IN– = GND (Notes 8, 9)
Input Common Mode Rejection 60Hz ±2%
Input Common Mode Rejection 50Hz ±2%
Input Normal Mode Rejection 50Hz ±2%
Input Normal Mode Rejection 60Hz ±2%
Input Normal Mode Rejection 50Hz/60Hz ±2%
Reference Common Mode Rejection DC
Power Supply Rejection DC
Power Supply Rejection, 50Hz ±2%
Power Supply Rejection, 60Hz ±2%
MIN
TYP
MAX
UNITS
l
140
dB
l
140
dB
l
140
l
110
120
dB
l
110
120
dB
l
87
l
120
dB
dB
140
dB
120
dB
120
dB
120
dB
Analog
Input and Reference l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
(IN+ Corresponds to the Selected Positive Input Channel)
CONDITIONS
MIN
TYP
MAX
UNITS
GND – 0.3V
VCC + 0.3V
V
IN–
Absolute/Common Mode IN– Voltage
(IN– Corresponds to the Selected Positive Input Channel or COM)
GND – 0.3V
VCC + 0.3V
V
VIN
Input Voltage Range (IN+ – IN–)
Differential/Single-Ended
l
–FS
+FS
V
FS
Full Scale of the Input (IN+ – IN–)
Differential/Single Ended
l
0.5 VREF
V
LSB
Least Significant Bit of the Output Code
l
FS/216
REF+
Absolute/Common Mode REF+ Voltage
l
0.1
REF–
Absolute/Common Mode REF– Voltage
l
VREF
Reference Voltage Range (REF+ – REF–)
l
CS(IN+)
IN+ Sampling Capacitance
11
pF
CS(IN–)
IN– Sampling Capacitance
11
pF
11
pF
CS(VREF)
GND
VCC
+
REF – 0.1V
V
0.1
VCC
V
VREF Sampling Capacitance
V
IDC_LEAK
(IN+)
IN+ DC Leakage Current
Sleep Mode, IN+ = GND
l
IDC_LEAK
(IN–)
IN– DC Leakage Current
Sleep Mode, IN– = GND
l
–10
1
10
nA
IDC_LEAK (REF+) REF+ DC Leakage Current
Sleep Mode, REF+ = VCC
l
–100
1
100
nA
IDC_LEAK (REF–) REF– DC Leakage Current
Sleep Mode, REF– = GND
l
–100
1
100
nA
tOPEN
MUX Break-Before-Make
QIRR
MUX Off Isolation
VIN = 2VP-P DC to 1.8MHz
–10
1
10
nA
50
ns
120
dB
2496fc
For more information www.linear.com/LTC2496
3
LTC2496
Digital
Inputs and Digital Outputs
The
l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage (CS, fO, SDI)
2.7V ≤ VCC ≤ 5.5V (Note 18)
l
MIN
VIL
Low Level Input Voltage (CS, fO, SDI)
2.7V ≤ VCC ≤ 5.5V
l
VIH
High Level Input Voltage (SCK)
2.7V ≤ VCC ≤ 5.5V (Notes 10, 15)
l
TYP
MAX
UNITS
VCC – 0.5
V
0.5
V
VCC – 0.5
V
VIL
Low Level Input Voltage (SCK)
2.7V ≤ VCC ≤ 5.5V (Notes 10, 15)
l
0.5
V
IIN
Digital Input Current (CS, fO, SDI)
0V ≤ VIN ≤ VCC
l
–10
10
µA
IIN
Digital Input Current (SCK)
0V ≤ VIN ≤ VCC (Notes 10, 15)
l
–10
10
µA
CIN
Digital Input Capacitance (CS, fO, SDI)
CIN
Digital Input Capacitance (SCK)
(Notes 10, 17)
VOH
High Level Output Voltage (SDO)
IO = –800µA
l
VOL
Low Level Output Voltage (SDO)
IO = 1.6mA
l
VOH
High Level Output Voltage (SCK)
IO = –800µA (Notes 10, 17)
l
VOL
Low Level Output Voltage (SCK)
IO = 1.6mA (Notes 10, 17)
l
IOZ
Hi-Z Output Leakage (SDO)
10
pF
10
pF
VCC – 0.5
V
0.4
V
VCC – 0.5
V
–10
l
0.4
V
10
µA
Power
Requirements l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
CONDITIONS
MIN
l
Conversion Current (Note 12)
Sleep Mode (Note 12)
TYP
2.7
160
1
l
l
MAX
UNITS
5.5
V
275
2
µA
µA
Digital
Inputs and Digital Outputs
The
l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
fEOSC
External Oscillator Frequency Range
(Note 16)
MAX
UNITS
l
tHEO
MIN
10
TYP
1000
kHz
External Oscillator High Period
l
0.125
100
µs
tLEO
External Oscillator Low Period
l
0.125
100
µs
tCONV
Conversion Time
Simultaneous 50/60Hz
External Oscillator
l
144.1
149.9
ms
ms
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
l
146.9
41036/fEOSC (in kHz)
38.4
fEOSC /8
45
kHz
kHz
55
%
4000
kHz
fESCK
External SCK Frequency Range
(Note 10)
l
tLESCK
External SCK Low Period
(Note 10)
l
125
ns
tHESCK
External SCK High Period
(Note 10)
l
125
ns
tDOUT_ISCK
Internal SCK 24-Bit Data Output Time
Internal Oscillator
External Oscillator
l
0.61
tDOUT_ESCK
External SCK 24-Bit Data Output Time
(Note 10)
4
0.625
192/fEOSC (in kHz)
24/fESCK (in kHz)
0.64
ms
ms
ms
2496fc
For more information www.linear.com/LTC2496
LTC2496
Digital
Inputs and Digital Outputs
The
l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
t1
MAX
UNITS
CS↓ to SDO Low
l
0
200
ns
t2
CS↑ to SDO High Z
l
0
200
ns
t3
CS↓ to SCK↓
Internal SCK Mode
l
0
200
ns
External SCK Mode
l
50
200
ns
t4
CS↓ to SCK↑
tKQMAX
SCK↓ to SDO Valid
tKQMIN
SDO Hold After SCK↓
t5
SCK Set-Up Before CS↓
t6
SCK Hold After CS↓
t7
t8
CONDITIONS
MIN
l
(Note 5)
TYP
ns
l
15
ns
l
50
ns
50
l
ns
SDI Setup Before SCK↑
(Note 5)
l
100
ns
SDI Hold After SCK↑
(Note 5)
l
100
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREFCM = VREF/2, FS = 0.5VREF
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2, where IN+ and IN– are the
selected input channels
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless other wise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: fEOSC = 256kHz ±2% (external oscillator).
Note 8: fEOSC = 307.2kHz ±2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or fEOSC = 280kHz
±2% (external oscillator).
Note 10: The SCK can be configured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as a digital input and the
driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a
digital output and the output clock signal during the data output is fISCK.
Note 11: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses its internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 16: Refer to Applications Information section for performance vs
data rate graphs.
Note 17: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output.
Note 18: For VCC < 3V, VIH is 2.5V for pin fO.
2496fc
For more information www.linear.com/LTC2496
5
LTC2496
Typical Performance Characteristics
–45°C
1
2
25°C
0
85°C
–1
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
1
2
INL (ppm OF VREF)
2
–45°C, 25°C, 90°C
0
–2
–1
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
–3
–1.25
2.5
–0.75
4
12
8
85°C
25°C
0
TUE (ppm OF VREF)
–45°C
–4
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
VCC = 5V
VREF = 5V
VIN(CM) = 1.25V
fO = GND
85°C
–45°C
0
–4
–12
–1.25
2.5
0.1
0
–0.75
–0.2
6
0
1
3
2
VIN(CM) (V)
4
5
6
2496 G25
85°C
25°C
–45°C
0
–4
–0.75
0.1
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
0
–0.3
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2496 G26
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2496 G24
0.3
–0.2
–1
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
–12
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–0.1
–0.1
–0.3
0.2
1.25
2496 G21
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
4
Offset Error vs Temperature
0.3
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.2
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2496 G23
Offset Error vs VIN(CM)
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
–0.75
–8
2496 G22
0.3
8
–8
2
–1
25°C
4
–8
–12
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
–45°C, 25°C, 90°C
0
12
OFFSET ERROR (ppm OF VREF)
TUE (ppm OF VREF)
8
1
2496 G20
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
–3
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2496 G19
12
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
–2
–2
TUE (ppm OF VREF)
INL (ppm OF VREF)
3
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
INL (ppm OF VREF)
3
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
0.2
0.1
Offset Error vs VCC
REF+ = 2.5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
0
–0.1
–0.2
–0.3
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
2496 G27
2496fc
For more information www.linear.com/LTC2496
LTC2496
Typical Performance Characteristics
0.1
0
–0.1
0
2
3
VREF (V)
4
308
306
304
2496 G28
–20
–40
–60
–80
On-Chip Oscillator Frequency
vs VCC
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
306
304
302
0 15 30 45 60
TEMPERATURE (°C)
75
300
90
2.5
PSRR vs Frequency at VCC
0
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–60
–80
–120
–120
–140
2496 G31
2496 G32
Conversion Current
vs Temperature
180
fO = GND
CS = GND
SCK = NC
SDO = NC
2.0
SLEEP MODE CURRENT (µA)
CONVERSION CURRENT (µA)
200
VCC = 5V
160
140
VCC = 2.7V
120
Sleep Mode Current
vs Temperature
500
fO = GND
1.8 CS = VCC
SCK = NC
1.6
SDO = NC
1.4
1.2
VCC = 5V
0.8
VCC = 2.7V
0.4
0 15 30 45 60
TEMPERATURE (°C)
75
90
2496 G34
0
–45 –30 –15
30650
30700
30750
FREQUENCY AT VCC (Hz)
30800
2496 G33
Conversion Current
vs Data Output Rate
VREF = VCC
IN+ = GND
IN– = GND
400 SCK = NC
SDO = NC
350 CS = GND
fO = EXT OSC
TA = 25°C
300
VCC = 5V
VCC = 3V
250
200
150
0.2
100
–45 –30 –15
2496 G30
450
1.0
0.6
5.5
PSRR vs Frequency at VCC
–140
30600
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
SUPPLY CURRENT (µA)
1M
5.0
–80
–120
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
4.5
–60
–100
10
4.0
VCC (V)
VCC = 4.1V DC ±0.7V
VREF = 2.5V
IN+ = GND
IN– = GND
–40 fO = GND
TA = 25°C
–100
0
3.5
–20
–100
–140
3.0
2496 G29
0
VCC = 4.1V DC
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–40
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
300
–45 –30 –15
5
PSRR vs Frequency at VCC
–20
REJECTION (dB)
1
REJECTION (dB)
0
308
302
–0.2
–0.3
310
FREQUENCY (kHz)
0.2
310
REJECTION (dB)
VCC = 5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
FREQUENCY (kHz)
OFFSET ERROR (ppm OF VREF)
0.3
On-Chip Oscillator Frequency
vs Temperature
Offset Error vs VREF
0 15 30 45 60
TEMPERATURE (°C)
75
90
2496 G35
100
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
30
2496 G36
2496fc
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7
LTC2496
Pin Functions
GND (Pins 1, 3, 4, 5, 6, 31, 32, 33): Ground. Multiple
ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these
pins to a common ground plane through a low impedance
connection. All 8 pins must be connected to ground for
proper operation.
NC (Pin 2): No Connection, this pin can be left floating
or tied to GND.
COM (Pin 7): The common negative input (IN–) for all
single-ended multiplexer configurations. The voltage on
CH0 to CH15 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN–) provide a bipolar input range
(VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF . Outside
this input range, the converter produces unique over-range
and under-range output codes.
CH0 to CH15 (Pins 8 to 23): Analog Inputs. May be programmed for single-ended or differential mode.
MUXOUTP (Pin 24): Positive Multiplexer Output. Used
to drive an external buffer/amplifier or can be shorted
directly to ADCINP.
ADCINP (Pin 25): Positive ADC Input. Tie to the output of
a buffer/amplifier driven by MUXOUTP or short directly
to MUXOUTP.
ADCINN (Pin 26): Negative ADC Input. Tie to the output
of a buffer/amplifier driven by MUXOUTN or short directly
to MUXOUTN.
MUXOUTN (Pin 27): Negative Multiplexer Output. Used
to drive an external buffer/amplifier or can be shorted
directly to ADCINN.
VCC (Pin 28): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.
REF+ (Pin 29), REF– (Pin 30): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage (REF = REF+
– REF–) sets the full-scale range for all input channels.
8
SDI (Pin 34): Serial Data Input. This pin is used to select
the input channel. The serial data input is applied under
control of the serial clock (SCK) during the data output
operation. The first conversion following a new input is
valid.
fO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock rate. When fO is
connected to VCC or GND, the converter uses its internal
oscillator running at 307.2kHz. The conversion clock may
also be overridden by driving the fO pin with an external
clock in order to change the output rate and the digital
filter rejection null.
CS (Pin 36): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output aborts the data transfer and starts
a new conversion.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select pin is HIGH, the SDO pin is in a high
impedance state. During the conversion and sleep periods,
this pin is used as the conversion status output. When
the conversion is in progress this pin is HIGH; once the
conversion is complete SDO goes low. The conversion
status is monitored by pulling CS LOW.
SCK (Pin 38): Bidirectional, Digital I/O, Clock Pin. In Internal
Serial Clock Operation mode, SCK is generated internally
and is seen as an output on the SCK pin. In External Serial
Clock Operation mode, the digital I/O clock is externally
applied to the SCK pin. The Serial Clock operation mode
is determined by the logic level applied to the SCK pin at
power up and during the most recent falling edge of CS.
GND (Exposed Pad Pin 39): Ground. This pin is ground
and must be soldered to the PCB ground plane. For prototyping purposes, this pin may remain floating.
2496fc
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LTC2496
Functional Block Diagram
INTERNAL
OSCILLATOR
VCC
MUXOUTP ADCINP
GND
CH0
CH1
CH15
COM
–
•
•
•
fO
(INT/EXT)
AUTOCALIBRATION
AND CONTROL
REF+
REF–
+
DIFFERENTIAL
3RD ORDER
∆∑ MODULATOR
MUX
SDI
SCK
SDO
CS
SERIAL
INTERFACE
DECIMATING FIR
ADDRESS
2496 BD
MUXOUTN ADCINN
Figure 1. Functional Block Diagram
Test Circuits
SDO
VCC
1.69k
CLOAD = 20pF
1.69k
SDO
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
2496 TC01
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
2496 TC02
2496fc
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9
LTC2496
Timing Diagrams
Timing Diagram Using Internal SCK (SCK HIGH with CS↓)
CS
t1
t2
SDO
tKQMIN
t3
tKQMAX
SCK
t7
t8
SDI
2496 TD01
SLEEP
DATA IN/OUT
CONVERSION
Timing Diagram Using External SCK (SCK LOW with CS↓)
CS
t1
t2
SDO
t5
SCK
tKQMIN
t6
t4
t7
tKQMAX
t8
SDI
2496 TD02
SLEEP
10
DATA IN/OUT
CONVERSION
2496fc
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LTC2496
Applications Information
CONVERTER OPERATION
The LTC2496 is a multi-channel, low power, delta-sigma
analog-to-digital converter with an easy to use 4-wire interface and automatic differential input current cancellation.
Its operation is made up of three states (See Figure 2).
The converter operating cycle begins with the conversion,
followed by the sleep state and ends with the data input/
output cycle. The 4-wire interface consists of serial data
output (SDO), serial clock (SCK), chip select (CS) and
serial data input (SDI).The interface, timing, operation
cycle, and data output format is compatible with Linear’s
entire family of ΔΣ converters.
If CS is brought HIGH after the first rising edge of SCK, the
data output cycle is aborted and a new conversion cycle
begins. The data output corresponds to the conversion
just completed. This result is shifted out on the serial
data output pin (SDO) under the control of the serial
clock pin (SCK). Data is updated on the falling edge of
SCK allowing the user to reliably latch data on the rising
edge of SCK (See Figure 3). The channel selection data for
the next conversion is also loaded into the device at this
time. Data is loaded from the serial data input pin (SDI)
on each rising edge of SCK. The data input/output cycle is
concluded once 24 bits are read out of the ADC or when
CS is brought HIGH. The device automatically initiates a
new conversion and the cycle repeats.
Initially, at power up, the LTC2496 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, if CS is HIGH, power
consumption is reduced by two orders of magnitude. The
part remains in the sleep state as long as CS is HIGH. The
conversion result is held indefinitely in a static shift register
while the part is in the sleep state.
Through timing control of the CS and SCK pins, the LTC2496
offers several flexible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming and do not
disturb the cyclic operation described above. These modes
of operation are described in detail in the Serial Interface
Timing Modes section.
Once CS is pulled LOW, the device powers up, exits the
sleep mode, and enters the data input/output state. If CS
is brought HIGH before the first rising edge of SCK, the
device returns to the sleep state and the power is reduced.
Ease of Use
Converter Operation Cycle
POWER UP
IN+= CH0, IN–= CH1
CONVERT
The LTC2496 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conversion,
immediately following a newly selected input, is valid and
accurate to the full specifications of the device.
The LTC2496 automatically performs offset and full scale
calibration every conversion cycle independent of the
input channel selected. This calibration is transparent to
the user and has no effect with the operation cycle described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage variation, input channel,
and temperature drift.
SLEEP
CS = LOW
AND
SCK
Easy Drive Input Current Cancellation
CHANNEL SELECT
DATA OUTPUT
2496 F02
Figure 2. LTC2496 State Transition Diagram
The LTC2496 combines a high precision delta-sigma ADC
with an automatic, differential, input current cancellation
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11
LTC2496
Applications Information
front end. A proprietary front end passive sampling network
transparently removes the differential input current. This
enables external RC networks and high impedance sensors to directly interface to the LTC2496 without external
amplifiers. The remaining common mode input current
is eliminated by either balancing the differential input
impedances or setting the common mode input equal to
the common mode reference (see Automatic Differential
Input Current Cancellation Section). This unique architecture does not require on-chip buffers thereby enabling
signals to swing beyond ground or up to VCC. Moreover, the
cancellation does not interfere with the transparent offset
and full-scale auto-calibration and the absolute accuracy
(full-scale + offset + linearity + drift) is maintained even
with external RC networks.
Power-Up Sequence
The LTC2496 automatically enters an internal reset state
when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of
the conversion result, input channel selection, and serial
clock mode.
When VCC rises above this threshold, the converter creates
an internal power-on-reset (POR) signal with a duration
of approximately 4ms. The POR signal clears all internal
registers. The conversion immediately following a POR
cycle is performed on the input channel IN+ = CH0, IN– =
CH1. The first conversion following a POR cycle is accurate
within the specification of the device if the power supply
voltage is restored to (2.7V to 5.5V) before the end of the
POR interval. A new input channel, can be programmed
into the device during this first data input/output cycle.
Reference Voltage Range
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage range for
REF+ and REF– pins covers the entire operating range of
the device (GND to VCC). For correct converter operation,
VREF must be positive (REF+ > REF–)
to VCC and REF– can be shorted to GND. The converter
output noise is determined by the thermal noise of the
front end circuits. Since the transition noise is well below
1LSB (0.02LSB), a decrease in reference voltage will
proportionally improve the converter’s effective resolution
and improve the INL.
Input Voltage Range
The LTC2496 input measurement range is –0.5 • VREF to
+0.5 • VREF in both differential and single-ended configurations as shown in Figure 29. Highest linearity is achieved
with Fully Differential drive and a constant common mode
voltage (Figure 29b). Other drive schemes may incur an
INL error of approximately 50ppm. This error can be
calibrated out using a three point calibration and a second-order curve fit.
The analog input is truly differential with an absolute,
common mode range for CH0 to CH15 and COM input pins
extending from GND – 0.3V to VCC + 0.3V. Outside these
limits, the ESD protection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2496 converts the bipolar differential
input signal VIN = IN+ – IN– (where IN+ and IN– are the
selected input channels), from –FS = –0.5 • VREF to +FS =
0.5 • VREF where VREF = REF+ – REF–. Outside this range,
the converter indicates the over range or the under range
condition using distinct output codes.
Signals applied to the input (CH0 to CH15, COM) may
extend 300mV below ground and above VCC. In order to
limit any fault current, resistors of up to 5k may be added
in series with the input. The effect of series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent error due to input leakage current. A 1nA
input leakage current will develop a 1ppm offset error
on a 5k resistor if VREF = 5V. This error has a very strong
temperature dependency.
The LTC2496 differential reference input range is 0.1V
to VCC. For the simplest operation, REF+ can be shorted
12
2496fc
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LTC2496
Applications Information
MUXOUT/ADCIN
sleep states.
The output of the multiplexer (MUXOUT) and the input
to the ADC (ADCIN) can be used to perform input signal
conditioning on any of the selected input channels or simply shorted together for direct digitization. If an external
amplifier is used, the LTC2496 automatically calibrates
both the offset and drift of this circuit and the Easy Drive
sampling scheme enables a wide variety of amplifiers to
be used.
When CS is HIGH, the SDO driver is switched to a high
impedance state in order to share the data output line with
other devices. If CS is brought LOW during the conversion
phase, the EOC bit (SDO pin) will be driven HIGH. Once
the conversion is complete, if CS is brought LOW EOC will
be driven LOW indicating the conversion is complete and
the result is ready to be shifted out of the device.
In order to achieve optimum performance, if an external
amplifier is not used, short these pins directly together
(ADCINP to MUXOUTP and ADCINN to MUXOUTN) and
minimize their capacitance to ground.
SERIAL INTERFACE PINS
The LTC2496 transmits the conversion result, reads the
input channel selection, and receives a start of conversion
command through a synchronous 3- or 4-wire interface.
During the conversion and sleep states, this interface can be
used to access the converter status. During the data output
state, it is used to read the conversion result and program
the input channel for the next conversion cycle.
Serial Clock Input/Output (SCK)
The serial clock pin (SCK) is used to synchronize the data
input/output transfer. Each bit is shifted out of the SDO
pin on the falling edge of SCK and data is shifted into the
SDI pin on the rising edge of SCK.
The serial clock pin (SCK) can be configured as either a
master (SCK is an output generated internally) or a slave
(SCK is an input and applied externally). Master mode
(Internal SCK) is selected by simply floating the SCK pin.
Slave mode (External SCK) is selected by driving SCK low
during power up and each falling edge of CS. Specific
details of these SCK modes are described in the Serial
Interface Timing Modes section.
Serial Data Output (SDO)
The serial data output pin (SDO) provides the result of the
last conversion as a serial bit stream (MSB first) during
the data output state. In addition, the SDO pin is used as
an end of conversion indicator during the conversion and
Chip Select (CS)
The active low CS pin is used to test the conversion status,
enable I/O data transfer, initiate a new conversion, control
the duration of the sleep state, and set the SCK mode.
At the conclusion of a conversion cycle, while CS is HIGH,
the device remains in a low power sleep state where the
supply current is reduced several orders of magnitude. In
order to exit the sleep state and enter the data output state,
CS must be pulled low. Data is now shifted out the SDO pin
under control of the SCK pin as described previously.
A new conversion cycle is initiated either at the conclusion
of the data output cycle (all 24 data bits read) or by pulling
CS HIGH any time between the first and 24th rising edges
of the serial clock (SCK). In this case, the data output is
aborted and a new conversion begins.
Serial Data Input (SDI)
The serial data input (SDI) is used to select the input channel.
Data is shifted into the device during the data output/input
state on the rising edge of SCK while CS is low.
OUTPUT DATA FORMAT
The LTC2496 serial output stream is 24 bits long. The
first bit indicates the conversion status, the second bit is
always zero, and the third bit conveys sign information.
The next 17 bits are the conversion result, MSB first. The
remaining 4 bits are always LOW.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available on the SDO pin during the
conversion and sleep states whenever CS is LOW. This bit
is HIGH during the conversion cycle, goes LOW once the
conversion is complete, and is HIGH-Z when CS is HIGH.
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13
LTC2496
Applications Information
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
Bit 21 (third output bit) is the conversion result sign indicator (SIG). If the selected input (VIN = IN+ – IN–) is greater
than 0V, this bit is HIGH. If VIN < 0, this bit is LOW.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the first
rising edge of SCK. Bit 22 is shifted out of the device on
the first falling edge of SCK. The final data bit (Bit 0) is
shifted out on the on the falling edge of the 23rd SCK and
may be latched on the rising edge of the 24th SCK pulse.
On the falling edge of the 24th SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 23) for the next conversion cycle.
Table 2 summarizes the output data format.
Bit 20 (fourth output bit) is the most significant bit (MSB) of
the result. This bit in conjunction with Bit 21 also provides
under range and over range indication. If both Bit 21 and
Bit 20 are HIGH, the differential input voltage is above
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2496 Status Bits
Input Range
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
VIN ≥ 0.5 • VREF
0
0
1
1
0V ≤ VIN < 0.5 • VREF
0
0
1
0
–0.5 • VREF ≤ VIN < 0V
0
0
0
1
VIN < –0.5 • VREF
0
0
0
0
As long as the voltage on the IN+ and IN– pins remains
between –0.3V and VCC + 0.3V (absolute maximum operating range) a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS = 0.5 • VREF. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to +FS + 1LSB. For differential input voltages below –FS, the conversion result is clamped to the
value –FS – 1LSB.
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB first.
Bit 4 is the least significant bit (LSB16).
Bits 3 to 0 are always LOW.
CS
1
2
3
4
5
6
7
8
1
0
EN
SGL
ODD
A2
A1
A0
EOC
“0”
SIG
MSB
9
19
20
21
22
23
24
SCK
(EXTERNAL)
DON'T CARE
SDI
Hi-Z
SDO
SLEEP
Hi-Z
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15
CONVERSION
DON'T CARE
DATA INPUT/OUTPUT
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CONVERSION
2496 F03
Figure 3. Channel Selection and Data Output Timing
14
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LTC2496
Applications Information
Table 2. LTC2496 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
VIN*
BIT 23
EOC
BIT 22
DMY
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
…
BIT 4
BITS 3 TO 0
VIN* ≥ FS**
0
0
1
1
0
0
0
…
0
0000
FS** – 1LSB
0
0
1
0
1
1
1
…
1
0000
0.5 • FS**
0
0
1
0
1
0
0
…
0
0000
0.5 • FS** – 1LSB
0
0
1
0
0
1
1
…
1
0000
0
0
0
1
0
0
0
0
…
0
0000
–1LSB
0
0
0
1
1
1
1
…
1
0000
–0.5 • FS**
0
0
0
1
1
0
0
…
0
0000
–0.5 • FS** – 1LSB
0
0
0
1
0
1
1
…
1
0000
–FS**
0
0
0
1
0
0
0
…
0
0000
VIN* < –FS**
0
0
0
0
1
1
1
…
1
0000
*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF.
INPUT DATA FORMAT
The LTC2496 serial input word is 8 bits long. The input
data (SGL, ODD, A2, A1, A0) is used to select the input
channel. After power up, the device initiates an internal
reset cycle which sets the input channel to CH0 – CH1
(IN+ = CH0, IN– = CH1), The first conversion automatically
begins at power up using the default input channel. Once
the conversion is complete a new word can be written
into the device in order to select the input channel for the
next conversion cycle.
The first 3 bits shifted into the device consist of two preenable bits and one enable bit. As demonstrated in Figure 3,
the first three bits shifted into the device enable the device
input channel selection. Valid settings for these three bits
are 000, 100, and 101. Other combinations should be
avoided. If the first three bits are 000 or 100, the following
data is ignored (don’t care) and the previously selected
input channel remains valid for the next conversion
If the first 3 bits shifted into the device are 101, then the
next 5 bits select the input channel for the next conversion
cycle, see Table 3.
The first input bit following the 101 sequence (SGL) determines if the input selection is differential (SGL = 0) or
single-ended (SGL = 1). For SGL = 0, two adjacent channels can be selected to form a differential input. For SGL
= 1, one of 16-channels is selected as the positive input.
The negative input is COM for all single ended operations.
The remaining 4 bits (ODD, A2, A1, A0) determine which
channel(s) is/are selected and the polarity (for a differential
input). This data sequence is backward compatible with
the LTC2448 and LTC2418 families of delta sigma ADCs.
SERIAL INTERFACE TIMING MODES
The LTC2496’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes
of operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion. The
following sections describe each of these timing modes
in detail. In all cases, the converter can use the internal
oscillator (fO = LOW or fO = HIGH) or an external oscillator
connected to the fO pin. For each mode, the operating cycle,
data input format, data output format, and performance
remain the same. Refer to Table 4 for a summary.
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15
LTC2496
Applications Information
Table 3. Channel Selection
MUX ADDRESS
CHANNEL SELECTION
ODD/
SGL SIGN
A2
A1
A0
0
1
*0
0
0
0
0
IN+
IN–
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
IN–
2
3
IN+
IN–
4
5
IN+
IN–
6
7
IN+
IN–
8
9
IN+
IN–
10
11
IN+
IN–
12
13
IN+
IN–
14
15
IN+
IN–
IN–
IN+
COM
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
*Default at power up
16
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LTC2496
Applications Information
Table 4. Serial Interface Timing Modes
SCK
CONVERSION
DATA OUTPUT CONNECTION AND
SOURCE CYCLE CONTROL
CONTROL
WAVEFORMS
CONFIGURATION
External SCK, Single Cycle
Conversion
External
CS and SCK
CS and SCK
Figures 4, 5
External SCK, 3-Wire I/O
External
SCK
SCK
Figure 6
Internal SCK, Single Cycle
Conversion
Internal
CS↓
CS↓
Figures 7, 8
Internal SCK, 3-Wire I/O,
Continuous Conversion
Internal
Continuous
Internal
Figure 9
External Serial Clock, Single Cycle Operation
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle, see Figure 4.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
The external serial clock mode is selected during the powerup sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
2.7V TO 5.5V
10µF
28
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
fO
LTC2496
0.1µF
29
REFERENCE
VOLTAGE
0.1V TO VCC
30
8
•
•
•
15
16
ANALOG
INPUTS
•
•
•
23
7
REF+
34
SDI
REF–
38
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
4-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
1
0
EN
SGL
ODD
A2
A1
A0
EOC
“0”
SIG
MSB
9
19
20
21
22
23
24
SCK
(EXTERNAL)
SDI
DON'T CARE
SDO
SLEEP
Hi-Z
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15
CONVERSION
DON'T CARE
DATA INPUT/OUTPUT
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CONVERSION
2496 F04
Figure 4. External Serial Clock, Single Cycle Operation
2496fc
For more information www.linear.com/LTC2496
17
LTC2496
Applications Information
When the device is in the sleep state, its conversion result is held in an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK
is seen while CS is LOW. The input data is then shifted
in via the SDI pin on each rising edge of SCK (including
the first rising edge). The channel selection will be used
for the following conversion cycle. If the input channel is
changed during this I/O cycle, the new settings take effect
on the conversion cycle following the data input/output
cycle. The output data is shifted out the SDO pin on each
falling edge of SCK. This enables external circuitry to
latch the output on the rising edge of SCK. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 24th rising
edge of SCK. On the 24th falling edge of SCK, the device
begins a new conversion and SDO goes HIGH (EOC = 1)
indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 24th falling edge of SCK, see Figure 5. On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge
of SCK, the new input channel is loaded and valid for the
next conversion cycle.
2.7V TO 5.5V
10µF
28
VCC
fO
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
LTC2496
0.1µF
REFERENCE
VOLTAGE
0.1V TO VCC
REF+
SDI
30
REF–
SCK
8
•
•
•
ANALOG
INPUTS
29
15
16
•
•
•
23
7
CH0
•
•
•
CH7
SDO
CH8
•
CS
34
38
4-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
1
0
EN
SGL
ODD
A2
A1
A0
EOC
“0”
SIG
MSB
SCK
(EXTERNAL)
SDI
DON'T CARE
SDO
Hi-Z
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16
CONVERSION
SLEEP
DON'T CARE
DATA INPUT/OUTPUT
BIT 15
CONVERSION
SLEEP
2496 F05
Figure 5. External Serial Clock, Reduced Output Data Length and Valid Channel Selection
18
2496fc
For more information www.linear.com/LTC2496
LTC2496
Applications Information
External Serial Clock, 3-Wire I/O
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
On the falling edge of EOC, the conversion result is loading into an internal static shift register. The output data
can now be shifted out the SDO pin under control of the
externally applied SCK signal. Data is updated on the falling edge of SCK. The input data is shifted into the device
through the SDI pin on the rising edge of SCK. On the
24th falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as EOC
for the next conversion.
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an externally
generated serial clock (SCK) signal, see Figure 6. CS is
permanently tied to ground, simplifying the user interface
or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is typically
concluded 4ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
2.7V TO 5.5V
10µF
28
VCC
fO
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
LTC2496
0.1µF
29
REFERENCE
VOLTAGE
0.1V TO VCC
30
8
•
•
•
ANALOG
INPUTS
15
16
•
•
•
23
7
REF+
REF–
SDI
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
34
38
3-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
1
0
EN
SGL
ODD
A2
A1
A0
EOC
“0”
SIG
MSB
9
19
20
21
22
23
24
BIT 2
BIT 1
BIT 0
SCK
(EXTERNAL)
SDI
DON'T CARE
SDO
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15
CONVERSION
SLEEP
DON'T CARE
BIT 4
DATA INPUT/OUTPUT
BIT 3
CONVERSION
2496 F06
Figure 6. External Serial Clock, 3-Wire Operation (CS = 0)
2496fc
For more information www.linear.com/LTC2496
19
LTC2496
Applications Information
Internal Serial Clock, Single Cycle Operation
When testing EOC, if the conversion is complete (EOC =
0), the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, CS must
be pulled HIGH before the device pulls SCK HIGH. When
the device is using its own internal oscillator (fO is tied
LOW), the first rising edge of SCK occurs 12µs (tEOCTEST
= 12µs) after the falling edge of CS. If fO is driven by an
external oscillator of frequency fEOSC, then tEOCTEST =
3.6/fEOSC.
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle, see Figure 7.
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
If CS remains LOW longer than tEOCTEST, the first rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC =1 while the conversion is in progress
and EOC = 0 if the device is in the sleep state
After the 24th rising edge of SCK a new conversion automatically begins. SDO goes HIGH (EOC = 1) and SCK
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
2.7V TO 5.5V
10µF
28
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
fO
LTC2496
0.1µF
REFERENCE
VOLTAGE
0.1V TO VCC
29
REF+
30
REF–
8
•
•
•
15
16
ANALOG
INPUTS
•
•
•
23
7
1µF
2496fc
For more information www.linear.com/LTC2496
LTC2496
Applications Information
The user can expect to achieve this level of performance using the internal oscillator, as shown in Figure 19. Measured
values of normal mode rejection are shown superimposed
over the theoretical rejection.
Traditional high order delta-sigma modulators suffer
from potential instabilities at large input signal levels.
The proprietary architecture used for the LTC2496 third
order modulator resolves this problem and guarantees
stability with input signals 150% of full-scale. In many
industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted error
sources with several volts of peak-to-peak noise. Figure
20 shows measurement results for the rejection of a 7.5V
peak-to-peak noise source (150% of full scale) applied
to the LTC2496. From these curves, it is shown that the
rejection performance is maintained even in extremely
noisy environments.
When using its internal oscillator, the LTC2496 produces up
to 6.9 samples per second (sps) with a notch frequency of
55Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignificantly short. When
operating with an external conversion clock (fO connected
to an external oscillator), the LTC2496 output data rate
can be increased. The duration of the conversion cycle
is 41036/fEOSC. If fEOSC = 307.2kHz, the converter notch
frequency is 60Hz.
An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output
data rate (up to a maximum of 100sps). The increase in
output rate leads to degradation in offset, full-scale error,
and effective resolution as well as a shift in frequency
rejection.
0
fN = fEOSC/5120
–10
–20
NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
0
Output Data Rate
–30
–40
–50
–60
–70
–80
–90
–100
MEASURED DATA
CALCULATED DATA
–20
–40
–60
–80
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
–120
8fN
20
0
40
60
80
100
120
140
INPUT FREQUENCY (Hz)
160
180
200
220
2496 F19
2496 F17
Figure 17. Input Normal Mode Rejection at DC
Figure 19. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz/60Hz Notch)
0
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–10
–20
NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–30
–40
–50
–60
–70
–80
–90
–100
–20
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
–40
–60
–80
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2496 F20
2496 F18
Figure 18. Input Normal Mode Rejection at fS = 256 • fN
Figure 20. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 150% (60Hz Notch)
2496fc
For more information www.linear.com/LTC2496
27
LTC2496
Applications Information
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN+ and IN– pins will continue to reject line
frequency noise.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
3500
40
30
10
2500
–1500
–2000
1000
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
0
30
–3000
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
30
–3500
Figure 22. +FS Error vs Output Data
Rate and Temperature
Figure 23.–FS Error vs Output Data
Rate and Temperature
16
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
14
12
0
10
20
30
OUTPUT DATA RATE (READINGS/SEC)
2496 F24
Figure 24. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
28
OFFSET ERROR (ppm OF VREF)
18
30
20
20
RESOLUTION (BITS)
20
10
20
OUTPUT DATA RATE (READINGS/SEC)
2496 F23
22
TA = 25°C
TA = 85°C
TA = 25°C, 85°C
0
2496 F22
24
22
TA = 25°C
TA = 85°C
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
–2500
500
Figure 21. Offset Error vs Output Data
Rate and Temperature
RESOLUTION (BITS)
–1000
1500
2496 F21
10
–500
2000
0
–10
0
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
TA = 25°C
TA = 85°C
3000
20
Once the external oscillator frequency is increased above
1MHz (a more than 3x increase in output rate) the effectiveness of internal auto calibration circuits begins to degrade.
This results in larger offset errors, full-scale errors, and
decreased resolution, see Figures 21 to 28.
–FS ERROR (ppm OF VREF)
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
TA = 25°C
TA = 85°C
+FS ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
50
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
18
16
TA = 25°C
TA = 85°C
VIN(CM) = VREF(CM)
12 VCC = VREF = 5V
fO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
10
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
14
30
2496 F25
Figure 25. Resolution (INLMAX ≤ 1LSB) vs
Output Data Rate and Temperature
VIN(CM) = VREF(CM)
VIN = 0V
15 fO = EXT CLOCK
TA = 25°C
VCC = 5V, VREF = 2.5V
10
VCC = VREF = 5V
5
0
–5
–10
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
30
2496 F26
Figure 26. Offset Error vs Output Data
Rate and Reference Voltage
2496fc
For more information www.linear.com/LTC2496
LTC2496
Applications Information
18
22
16
RESOLUTION (BITS)
RESOLUTION (BITS)
VCC = 5V, VREF = 2.5V
VCC = VREF = 5V
20
VCC = 5V, VREF = 2.5V, 5V
14
VIN(CM) = VREF(CM)
12 VIN = 0V
fO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/NOISERMS)
10
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
30
18
16
14 VIN(CM) = VREF(CM)
VIN = 0V
REF– = GND
12 fO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
10
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
2496 F28
2496 F27
Figure 27. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
Figure 28. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
VCC + 0.3V
VCC
VREF
2
GND
–0.3V
30
VCC
VREF
2
–VREF
2
VREF
2
–VREF
2
GND
(a) Arbitrary
(b) Fully Differential
VCC
VCC
VREF
2
VREF
2
–VREF
2
GND
(c) Pseudo Differential Bipolar
IN– or COM Biased
Selected IN+ Ch
Selected IN– Ch or COM
–0.3V
GND
–0.3V
(d) Pseudo-Differential Unipolar
IN– or COM Grounded
2496 F29
Figure 29. Input Range
2496fc
For more information www.linear.com/LTC2496
29
LTC2496
Package Description
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 ± 0.05
5.50 ± 0.05
5.15 ± 0.05
4.10 ± 0.05
3.00 REF
3.15 ± 0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
5.5 REF
6.10 ± 0.05
7.50 ± 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ± 0.10
0.75 ± 0.05
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ± 0.10
5.50 REF
7.00 ± 0.10
3.15 ± 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 ± 0.05
0.50 BSC
R = 0.125
TYP
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
30
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2496fc
For more information www.linear.com/LTC2496
LTC2496
Revision History
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
7/10
Revised Typical Application drawing
C
11/14
Added Note 18
1
4,5
Clarify performance vs f0 frequency, reduced external oscillator max frequency to 1MHz
Clarify Input Voltage Range
4, 7, 28, 29
3, 12, 29
2496fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2496
Typical Application
External Buffers Provide High Impedance Inputs and Amplifier Offsets are Automatically Cancelled.
LTC2496
∆∑ ADC
WITH
EASY DRIVE
INPUTS
MUXOUTN
INPUT
MUX
MUXOUTP
ANALOG 17
INPUTS
SDI
SCK
SDO
CS
2
–
1/2 LT6078
3
+
6
–
5
1
1/2 LT6078
1k
0.1µF
7
1k
0.1µF
+
2496 TA02
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PART NUMBER
DESCRIPTION
COMMENTS
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LTC2400
24-Bit, No Latency ΔΣ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
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®
LTC2411/LTC2411-1 24-Bit, No Latency ΔΣ ADCs with Differential Inputs in MSOP
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24-Bit, No Latency ΔΣ ADC with Differential Inputs
LTC2415/LTC2415-1 24-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate
Pin Compatible with the LTC2410
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0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200µA
LTC2440
High Speed, Low Noise 24-Bit ΔΣ ADC
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LTC2480
16-Bit ΔΣ ADC with Easy Drive Inputs, 600nVRMS Noise,
Programmable Gain, and Temperature Sensor
Pin Compatible with LTC2482/LTC2484
LTC2481
16-Bit ΔΣ ADC with Easy Drive Inputs, 600nVRMS Noise, I2C
Interface, Programmable Gain, and Temperature Sensor
Pin Compatible with LTC2483/LTC2485
LTC2482
16-Bit ΔΣ ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2484
LTC2483
16-Bit ΔΣ ADC with Easy Drive Inputs, and I2C Interface
Pin Compatible with LTC2481/LTC2485
LTC2484
24-Bit ΔΣ ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2482
LTC2485
24-Bit ΔΣ ADC with Easy Drive Inputs, I2C Interface, and
Pin Compatible with LTC2481/LTC2483
LTC2498
24-Bit 8-/16-Channel ΔS ADC with Easy Drive Input Current
Cancellation
Pin Compatible with LTC2496/LTC2449
Temperature Sensor
32 Linear Technology Corporation
2496fc
LT 1114 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2496
LINEAR TECHNOLOGY CORPORATION 2006
