LTC2497
16-Bit 8-/16-Channel
DS ADC with Easy Drive Input Current
Cancellation and I2C Interface
Features
Description
Up to Eight Differential or 16 Single-Ended Inputs
Easy DriveTM Technology Enables Rail-to-Rail
Inputs with Zero Differential Input Current
n Directly Digitizes High Impedance Sensors with
Full Accuracy
n 2-Wire I2C Interface with 27 Addresses Plus One
Global Address for Synchronization
n 600nV RMS Noise (0.02LSB Transition Noise)
n GND to V
CC Input/Reference Common Mode Range
n Simultaneous 50Hz/60Hz Rejection
n 2ppm INL, No Missing Codes
n 1ppm Offset and 15ppm Full-Scale Error
n No Latency: Digital Filter Settles in a Single Cycle,
Even After a New Channel Is Selected
n Single Supply, 2.7V to 5.5V Operation (0.8mW)
n Internal Oscillator
n Tiny 5mm × 7mm QFN Package
The LTC®2497 is a 16-channel (eight differential), 16-bit,
No Latency DSTM ADC with Easy Drive technology and
a 2-wire, I2C interface. The patented sampling scheme
eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of
differential input current. This allows large external source
impedances and rail-to-rail input signals to be directly
digitized while maintaining exceptional DC accuracy.
n
n
The LTC2497 includes an integrated oscillator. This device
can be configured to measure an external signal from combinations of 16 analog input channels operating in singleended or differential modes. It automatically rejects line
frequencies of 50Hz and 60Hz simultaneously.
The LTC2497 allows a wide, common mode input range
(0V to VCC), independent of the reference voltage. Any
combination of single-ended or differential inputs can be
selected and the first conversion, after a new channel is
selected, is valid. Access to the multiplexer output enables
optional external amplifiers to be shared between all
analog inputs and auto calibration continuously removes
their associated offset and drift.
Applications
Direct Sensor Digitizer
Direct Temperature Measurement
n Instrumentation
n Industrial Process Control
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency ∆∑ and Easy Drive are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Typical Application
+FS Error vs RSOURCE at IN+ and IN–
Easy Drive Data Acquisition System
80
2.7V TO 5.5V
MUXOUT/
ADCIN
VCC
10µF
REF+
IN+
1.7k
16-BIT ∆∑ ADC
WITH EASY DRIVE
IN–
MUXOUT/
ADCIN
REF
0.1µF
SDA
SCL
2-WIRE
I2C INTERFACE
–
+FS ERROR (ppm)
CH0
CH1
•
•
•
CH7
CH8 16-CHANNEL
MUX
•
•
•
CH15
COM
VCC = 5V
= 5V
60 VREF
VIN+ = 3.75V
V – = 1.25V
40 IN
fO = GND
20 TA = 25°C
CIN = 1mF
0
–20
–40
fO
OSC
–60
–80
2497 TA01
1
10
100
1k
RSOURCE (Ω)
10k
100k
2497 TA01b
2497fb
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1
LTC2497
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
GND
GND
GND
fO
CA0
CA2
CA1
TOP VIEW
Supply Voltage (VCC).................................... –0.3V to 6V
Analog Input Voltage
(CH0-CH15, COM)......................–0.3V to (VCC + 0.3V)
REF+, REF –.................................–0.3V to (VCC + 0.3V)
ADCINN, ADCINP,
MUXOUTP MUXOUTN...............–0.3V to (VCC + 0.3V)
Digital Input Voltage......................–0.3V to (VCC + 0.3V)
Digital Output Voltage....................–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2497C..................................................0ºC to 70ºC
LTC2497I.............................................. –40ºC to 85ºC
Storage Temperature Range....................–65ºC to 150ºC
38 37 36 35 34 33 32
GND 1
31 GND
SCL 2
30 REF–
SDA 3
29 REF+
GND 4
28 VCC
27 MUXOUTN
NC 5
GND 6
26 ADCINN
39
COM 7
25 ADCINP
CH0 8
24 MUXOUTP
CH1 9
23 CH15
CH2 10
22 CH14
CH3 11
21 CH13
20 CH12
CH4 12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2497CUHF#PBF
LTC2497CUHF#TRPBF
2497
38-Lead (5mm × 7mm) Plastic QFN
0°C to 70°C
LTC2497IUHF#PBF
LTC2497IUHF#TRPBF
2497
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2497fb
2
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LTC2497
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
MIN
TYP
MAX
UNITS
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
Offset Error
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13)
Offset Error Drift
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
Positive Full-Scale Error
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
Positive Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
Negative Full-Scale Error
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
Negative Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
0.1
ppm of VREF/°C
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
15
15
15
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise
2.7V < VCC < 5.5V, 2.5V ≤ VREF ≤ VCC,
GND ≤ IN+ = IN– ≤ VCC (Note 12)
0.6
µVRMS
16
Bits
l
2
1
20
ppm of VREF
ppm of VREF
l
0.5
2.5
µV
10
nV/°C
32
l
0.1
ppm of VREF
ppm of VREF/°C
32
l
ppm of VREF
Converter
Characteristics l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
MIN
, GND ≤ IN+ = IN– ≤ V
Input Normal Mode Rejection 50Hz/60Hz ±2%
2.5V ≤ VREF ≤ VCC
Reference Common Mode Rejection DC
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
l
CC (Notes 5, 9)
TYP
MAX
UNITS
140
l
87
l
120
= 2.5V, IN+ = IN– = GND
dB
dB
140
dB
Power Supply Rejection DC
VREF
120
dB
Power Supply Rejection, 50Hz ±2%
VREF = 2.5V, IN+ = IN– = GND (Notes 7, 9)
120
dB
Power Supply Rejection, 60Hz ±2%
= 2.5V, IN+ = IN– = GND (Notes 8, 9)
120
dB
VREF
Analog
Input and Reference l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
(IN+ Corresponds to the Selected Positive Input Channel)
GND – 0.3V
VCC + 0.3V
V
IN–
Absolute/Common Mode IN– Voltage
(IN– Corresponds to the Selected Negative Input Channel
or COM)
GND – 0.3V
VCC + 0.3V
V
VIN
Input Voltage Range (IN+ – IN–)
Differential/Single-Ended
l
–FS
+FS
V
FS
Full Scale of the Input (IN+ – IN–)
Differential/Single-Ended
l
0.5VREF
LSB
Least Significant Bit of the Output Code
l
FS/216
REF+
Absolute/Common Mode REF+ Voltage
l
0.1
VCC
REF–
Absolute/Common Mode REF– Voltage
l
GND
REF+ – 0.1V
V
VREF
Reference Voltage Range (REF+ – REF–)
l
0.1
VCC
V
CS(IN+)
IN+ Sampling Capacitance
11
pF
CS(IN–)
IN– Sampling Capacitance
11
pF
CS(VREF)
VREF Sampling Capacitance
IDC_LEAK(IN+) IN+ DC Leakage Current
CONDITIONS
MIN
TYP
MAX
V
11
Sleep Mode, IN+ = GND
l
–10
UNITS
1
V
pF
10
nA
2497fb
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3
LTC2497
Analog
Input and Reference l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
IDC_LEAK(IN–) IN– DC Leakage Current
Sleep Mode, IN– = GND
l
–10
1
10
nA
IDC_
REF+ DC Leakage Current
Sleep Mode, REF+ = VCC
l
–100
1
100
nA
IDC_
REF– DC Leakage Current
Sleep Mode, REF– = GND
l
–100
1
100
nA
tOPEN
MUX Break-Before-Make
QIRR
MUX Off Isolation
+
LEAK(REF )
–
LEAK(REF )
VIN = 2VP-P DC to 1.8MHz
50
ns
120
dB
2C Inputs And Digital Outputs
I The
l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
l
MIN
TYP
MAX
UNITS
VIL
Low Level Input Voltage
l
VIHA
High Level Input Voltage for Address Pins CA0, CA1, CA2,
and Pin fO
l
VILA
Low Level Input Voltage for Address Pins CA0, CA1, CA2
l
0.05VCC
RINH
Resistance from CA0, CA1, CA2 to VCC to Set Chip Address
Bit to 1
l
10
kW
RINL
Resistance from CA0, CA1, CA2 to GND to Set Chip Address
Bit to 0
l
10
kW
RINF
Resistance from CA0, CA1, CA2 to GND or VCC to Set Chip
Address Bit to Float
l
II
Digital Input Current
l
–10
VHYS
Hysteresis of Schmidt Trigger Inputs
(Note 5)
l
0.05VCC
VOL
Low Level Output Voltage (SDA)
I = 3mA
l
tOF
Output Fall Time VIH(MIN) to VIL(MAX)
Bus Load CB 10pF to
400pF (Note 14)
l
IIN
Input Leakage
0.1VCC ≤ VIN ≤ VCC
CCAX
External Capacitative Load on Chip Address Pins (CA0, CA1,
CA2) for Valid Float
0.7VCC
V
0.3VCC
V
0.95VCC
V
V
2
MW
10
µA
V
0.4
V
250
ns
l
1
µA
l
10
pF
20 + 0.1CB
Power
Requirements l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
CONDITIONS
MIN
l
Conversion Current (Note 11)
Sleep Mode (Note 11)
l
l
TYP
2.7
160
1
MAX
UNITS
5.5
V
275
2
µA
µA
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LTC2497
Digital
Inputs And Digital Outputs l denotes the specifications which apply over the
The
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
fEOSC
External Oscillator Frequency Range
(Note 16)
MAX
UNITS
l
tHEO
tLEO
tCONV
Conversion Time
MIN
10
1000
kHz
External Oscillator High Period
l
0.125
100
µs
External Oscillator Low Period
l
0.125
100
µs
l
144.1
149.9
ms
ms
Internal Oscillator
External Oscillator (Note 10)
TYP
146.9
41036/fEOSC (in kHz)
2C Timing Characteristics
I The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3, 15)
SYMBOL
PARAMETER
fSCL
SCL Clock Frequency
CONDITIONS
l
MIN
0
TYP
MAX
UNITS
400
kHz
tHD(SDA)
Hold Time (Repeated) Start Condition
l
0.6
µs
tLOW
Low Period of the SCL Pin
l
1.3
µs
tHIGH
High Period of the SCL Pin
l
0.6
µs
tSU(STA)
Set-Up Time for a Repeated Start Condition
l
0.6
µs
tHD(DAT)
Data Hold Time
l
0
tSU(DAT)
Data Set-Up Time
l
100
tr
Rise Time for SDA Signals
(Note 14)
l
20 + 0.1CB
300
ns
tf
Fall Time for SDA Signals
(Note 14)
l
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for Stop Condition
l
0.6
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREFCM = VREF/2, FS = 0.5VREF
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,
where IN+ and IN– are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: fEOSC = 256kHz ±2% (external oscillator).
0.9
µs
ns
µs
Note 8: fEOSC = 307.2kHz ±2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or fEOSC = 280kHz
±2% (external oscillator).
Note 10: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses its internal oscillator.
Note 12: The output noise includes the contribution of the internal
calibration operations.
Note 13: Guaranteed by design and test correlation.
Note 14: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).
Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 16: Refer to Applications Information section for performance versus
data rate graphs.
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5
LTC2497
Typical Performance Characteristics
–45°C
25°C
0
85°C
–1
–2
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
1
2
–45°C, 25°C, 85°C
0
–1
2
–3
–1.25
2.5
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2497 G01
4
0
25°C
12
8
85°C
TUE (ppm OF VREF)
TUE (ppm OF VREF)
8
–45°C
–4
–8
–12
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2.5
2497 G04
1
–45°C, 25°C, 85°C
0
–1
–3
–1.25
1.25
–0.75
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
12
85°C
8
25°C
4
–45°C
0
–4
–12
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2497 G03
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
–8
2
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
2497 G02
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
–2
–2
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
12
INL (ppm OF VREF)
1
2
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
TUE (ppm OF VREF)
INL (ppm OF VREF)
2
3
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
INL (ppm OF VREF)
3
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
4
25°C
85°C
–45°C
0
–4
–8
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
1.25
2497 G05
–12
–1.25
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
1.25
2497 G06
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LTC2497
Typical Performance Characteristics
Offset Error vs VIN(CM)
Offset Error vs Temperature
0.2
0.1
0
–0.2
0.1
0
–0.2
0
1
3
2
VIN(CM) (V)
2497 G07
0
–0.1
1
2
3
VREF (V)
90
–0.1
–0.2
–0.3
2.7
310
310
308
308
306
304
302
–0.2
0
75
4
5
2497 G10
REF+ = 2.5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
fO = GND
0
On-Chip Oscillator Frequency
vs Temperature
VCC = 5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
fO = GND
0.1
0 15 30 45 60
TEMPERATURE (°C)
0.1
Offset Error vs VCC
3.1
3.5
2497 G08
Offset Error vs VREF
0.2
–0.3
–0.3
–45 –30 –15
6
5
4
0.2
FREQUENCY (kHz)
–1
0.3
OFFSET ERROR (ppm OF VREF)
VCC = 5V
VREF = 5V
VIN = 0V
fO = GND
–0.1
–0.1
–0.3
0.2
OFFSET ERROR (ppm OF VREF)
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
fO = GND
0.3
OFFSET ERROR (ppm OF VREF)
0.3
FREQUENCY (kHz)
OFFSET ERROR (ppm OF VREF)
0.3
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
300
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
3.9 4.3
VCC (V)
4.7
5.1
5.5
2497 G09
On-Chip Oscillator Frequency
vs VCC
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
306
304
302
75
90
2497 G11
300
2.7 3.0
3.5
4.0
4.5
VCC (V)
5.0
5.5
2497 G12
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LTC2497
Typical Performance Characteristics
VCC = 4.1V DC
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–40
–20
–40
REJECTION (dB)
–20
REJECTION (dB)
PSRR vs Frequency at VCC
0
–60
–80
PSRR vs Frequency at VCC
0
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
VCC = 4.1V DC ±0.7V
VREF = 2.5V
IN+ = GND
IN– = GND
–40 fO = GND
TA = 25°C
–20
REJECTION (dB)
PSRR vs Frequency at VCC
0
–60
–80
–60
–80
–100
–100
–100
–120
–120
–120
1
10
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
1M
–140
2497 G14
2497 G13
Conversion Current
vs Temperature
180
Sleep Mode Current
vs Temperature
VCC = 5V
160
140
VCC = 2.7V
120
VCC = 5V
1.0
0.8
VCC = 2.7V
0.4
0 15 30 45 60
TEMPERATURE (°C)
75
90
2497 G16
0
–45 –30 –15
2497 G15
VREF = VCC
IN+ = GND
IN– = GND
400 SCL = 0
SDA = 1
350 TA = 25°C
300
250
VCC = 5V
200
150
0.2
100
–45 –30 –15
30800
450
1.4
0.6
30700
30750
FREQUENCY AT VCC (Hz)
500
fO = GND
1.8 SCL = 0
SDA = 1
1.6
1.2
30650
Conversion Current
vs Output Data Rate
2.0
fO = GND
SCL = 0
SDA = 1
SLEEP MODE CURRENT (µA)
CONVERSION CURRENT (µA)
200
–140
30600
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
SUPPLY CURRENT (µA)
–140
0 15 30 45 60
TEMPERATURE (°C)
75
90
2497 G17
100
VCC = 3V
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
30
2497 G18
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LTC2497
Pin Functions
GND (Pins 1, 4, 6, 31, 32, 33, 34): Ground. Multiple
ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these
pins to a common ground plane through a low impedance
connection. All seven pins must be connected to ground
for proper operation.
SCL (Pin 2): Serial Clock Pin of the I2C Interface. The
LTC2497 can only act as a slave and the SCL pin only
accepts an external serial clock. Data is shifted into the
SDA pin on the rising edges of the SCL clock and output
through the SDA pin on the falling edges of the SCL clock.
SDA (Pin 3): Bidirectional Serial Data Line of the I2C Interface. In the transmitter mode (Read), the conversion result
is output through the SDA pin, while in the receiver mode
(Write), the device channel select bits are input through the
SDA pin. The pin is high impedance during the data input
mode and is an open drain output (requires an appropriate pull-up device to VCC) during the data output mode.
NC (Pin 5): No Connect. This pin can be left floating or
tied to GND.
COM (Pin 7): The Common Negative Input (IN –) for All
Single-Ended Multiplexer Configurations. The voltage on
CH0-CH15 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN– ) provide a bipolar input
range (VIN = IN+ – IN– ) from –0.5 • VREF to 0.5 • VREF .
Outside this input range, the converter produces unique
over-range and under-range output codes.
CH0 to CH15 (Pin 8-Pin 23): Analog Inputs. May be programmed for single-ended or differential mode.
MUXOUTP (Pin 24): Positive Multiplexer Output. Connect
to the input of external buffer/amplifier or short directly
to ADCINP.
ADCINP (Pin 25): Positive ADC Input. Connect to the
output of a buffer/amplifier driven by MUXOUTP or short
directly to MUXOUTP.
ADCINN (Pin 26): Negative ADC Input. Connect to the
output of a buffer/amplifier driven by MUXOUTN or short
directly to MUXOUTN
MUXOUTN (Pin 27): Negative Multiplexer Output. Connect to the input of an external buffer/amplifier or short
directly to ADCINN.
VCC (Pin 28): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.
REF+, REF – (Pin 29, Pin 30): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage (VREF = REF+
– REF –) sets the full-scale range for all input channels.
fO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock rate. When fO is
connected to GND, the converter uses its internal oscillator running at 307.2kHz. The conversion clock may also
be overridden by driving the fO pin with an external clock
in order to change the output rate and the digital filter
rejection null.
CA0, CA1, CA2 (Pins 36, 37, 38): Chip Address Control
Pins. These pins are configured as a three-state (LOW,
HIGH, Floating) address control bits for the device I2C
address.
GND (Exposed Pad Pin 39): Ground. This pin is ground
and must be soldered to the PCB ground plane. For prototyping purposes, this pin may remain floating.
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9
LTC2497
Functional Block Diagram
INTERNAL
OSCILLATOR
VCC
MUXOUTP ADCINP
GND
CH0
CH1
CH15
COM
–
•
•
•
+
DIFFERENTIAL
3RD ORDER
∆∑ MODULATOR
MUX
fO
(INT/EXT)
AUTOCALIBRATION
AND CONTROL
REF+
REF–
I2C
2-WIRE
INTERFACE
SDA
SCL
DECIMATING FIR
ADDRESS
2497 BD
MUXOUTN ADCINN
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LTC2497
Applications Information
CONVERTER OPERATION
Converter Operation Cycle
The LTC2497 is a multichannel, low power, delta-sigma
analog-to-digital converter with a 2-wire, I2C interface. Its
operation is made up of four states (see Figure 1). The
converter operating cycle begins with the conversion,
followed by the sleep state and ends with the data input/
output cycle.
POWER-ON RESET
DEFAULT INPUT CHANNEL:
IN+ = CH0, IN– = CH1
CONVERSION
Ease of Use
The LTC2497 data output has no latency, filter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conversion,
immediately following a newly selected input is valid and
accurate to the full specifications of the device.
SLEEP
NO
ACKNOWLEDGE
YES
The LTC2497 automatically performs offset and full-scale
calibration every conversion cycle independent of the input
channel selected. This calibration is transparent to the user
and has no effect on the operation cycle described above.
The advantage of continuous calibration is extreme stability
of offset and full-scale readings with respect to time, supply voltage variation, input channel, and temperature drift.
DATA OUTPUT/INPUT
NO
The device will not acknowledge an external request during the conversion state. After a conversion is finished,
the device is ready to accept a read/write request. Once
the LTC2497 is addressed for a read operation, the device
begins outputting the conversion result under the control
of the serial clock (SCL). There is no latency in the conversion result. The data output is 24 bits long and contains a
16-bit plus sign conversion result. Data is updated on the
falling edges of SCL allowing the user to reliably latch data
on the rising edge of SCL. A new conversion is initiated
by a stop condition following a valid write operation or an
incomplete read operation. The conversion automatically
begins at the conclusion of a complete read cycle (all 24
bits read out of the device).
STOP
OR READ
24 BITS
YES
2497 F01
Easy Drive Input Current Cancellation
Figure 1. State Transition Table
Initially, at power-up, the LTC2497 performs a conversion. Once the conversion is complete, the device enters
the sleep state. In the sleep state, power consumption is
reduced by two orders of magnitude. The part remains
in the sleep state as long it is not addressed for a read/
write operation. The conversion result is held indefinitely
in a static shift register while the part is in the sleep state.
The LTC2497 combines a high precision, delta-sigma ADC
with an automatic, differential, input current cancellation
front end. A proprietary front end passive sampling network
transparently removes the differential input current. This
enables external RC networks and high impedance sensors to directly interface to the LTC2497 without external
amplifiers. The remaining common mode input current
is eliminated by either balancing the differential input impedances or setting the common mode input equal to the
common mode reference (see the Automatic Differential
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LTC2497
Applications Information
Input Current Cancellation section). This unique architecture does not require on-chip buffers, thereby enabling
signals to swing beyond ground and VCC. Moreover, the
cancellation does not interfere with the transparent offset
and full-scale auto-calibration and the absolute accuracy
(full scale + offset + linearity + drift) is maintained even
with external RC networks.
Power-Up Sequence
The LTC2497 automatically enters an internal reset state
when the power supply voltage VCC drops below approximately 2.0V. This feature guarantees the integrity of the
conversion result and input channel selection.
When VCC rises above this threshold, the converter creates
an internal power-on-reset (POR) signal with a duration
of approximately 4ms. The POR signal clears all internal
registers. The conversion immediately following a POR
cycle is performed on the input channel IN+ = CH0, IN – =
CH1. The first conversion following a POR cycle is accurate
within the specification of the device if the power supply
voltage is restored to (2.7V to 5.5V) before the end of the
POR interval. A new input channel can be programmed
into the device during this first data input/output cycle.
Reference Voltage Range
This converter accepts a truly differential, external reference
voltage. The absolute/common mode voltage range for
REF+ and REF – pins covers the entire operating range of
the device (GND to VCC). For correct converter operation,
VREF must be positive (REF+ > REF –).
The LTC2497 differential reference input range is 0.1V to
VCC. For the simplest operation, REF+ can be shorted to
VCC and REF – can be shorted to GND. The converter output noise is determined by the thermal noise of the front
end circuits. Since the transition noise is well below 1LSB
(0.02LSB), a decrease in reference voltage will proportionally improve the converter resolution and improve INL.
Input Voltage Range
The LTC2497 input measurement range is –0.5 • VREF to
+0.5 • VREF in both differential and single-ended configurations as shown in Figure 28. Highest linearity is achieved
with fully differential drive and a constant common-mode
voltage (Figure 28b). Other drive schemes may incur
an INL error of approximately 50ppm. This error can
be calibrated out using a three point calibration and a
second-order curve fit.
The analog inputs are truly differential with an absolute,
common mode range for the CH0-CH15 and COM input
pins extending from GND – 0.3V to VCC + 0.3V. Within
these limits, the LTC2497 converts the bipolar differential input signal VIN = IN+ – IN– (where IN+ and IN – are
the selected input channels), from – FS = – 0.5 • VREF
to + FS = 0.5 • VREF where VREF = REF+ - REF–. Outside this
range, the converter indicates the overrange or the underrange condition using distinct output codes (see Table 1).
Signals applied to the input (CH0-CH15, COM) may extend
300mV below ground and above VCC. In order to limit any
fault current due to input ESD leakage current, resistors
of up to 5k may be added in series with the input. The effect of series resistance on the converter accuracy can be
evaluated from the curves presented in the Input Current/
Reference Current sections. In addition, series resistors
will introduce a temperature dependent error due to input
leakage current. A 1nA input leakage current will develop a
1ppm offset error on a 5k resistor if VREF = 5V. This error
has a very strong temperature dependency.
MUXOUT/ADCIN
The outputs of the multiplexer (MUXOUTP/MUXOUTN) and
the inputs to the ADC (ADCINP/ADCINN) can be used to
perform input signal conditioning on any of the selected
input channels or simply shorted together for direct
digitization. If an external amplifier is used, the LTC2497
automatically calibrates both the offset and drift of this
circuit and the Easy Drive sampling scheme enables a
wide variety of amplifiers to be used.
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Applications Information
In order to achieve optimum performance, if an external
amplifier is not used, short these pins directly together
(ADCINP to MUXOUTP and ADCINN to MUXOUTN) and
minimize their capacitance to ground.
I2C INTERFACE
The LTC2497 communicates through an I2C interface. The
I2C interface is a 2-wire open-drain interface supporting
multiple devices and multiple masters on a single bus. The
connected devices can only pull the data line (SDA) low
and can never drive it high. SDA is required to be externally connected to the supply through a pull-up resistor.
When the data line is not being driven, it is high. Data on
the I2C bus can be transferred at rates up to 100kbits/s in
the standard mode and up to 400kbits/s in the fast mode.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate either as a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. Devices addressed by the master
are considered a slave.
The LTC2497 can only be addressed as a slave. Once addressed, it can receive channel selection bits or transmit
the last conversion result. The serial clock line, SCL, is
always an input to the LTC2497 and the serial data line
SDA is bidirectional. The device supports the standard
mode and the fast mode for data transfer speeds up to
400kbits/s. Figure 2 shows the definition of the I2C timing.
The Start and Stop Conditions
A Start (S) condition is generated by transitioning SDA from
high to low while SCL is high. The bus is considered to be
busy after the Start condition. When the data transfer is
finished, a Stop (P) condition is generated by transitioning
SDA from low to high while SCL is high. The bus is free
after a Stop is generated. Start and Stop conditions are
always generated by the master.
When the bus is in use, it stays busy if a Repeated Start
(Sr) is generated instead of a Stop condition. The repeated
Start timing is functionally identical to the Start and is
used for writing and reading from the device before the
initiation of a new conversion.
Data Transferring
After the Start condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit.
The master releases the SDA line during the ninth SCL
clock cycle. The slave device can issue an ACK by pulling
SDA low or issue a Not Acknowledge (NAK) by leaving
the SDA line high impedance (the external pull-up resistor
will hold the line high). Change of data only occurs while
the clock line (SCL) is low.
DATA FORMAT
After a Start condition, the master sends a 7-bit address
followed by a read/write (R/W) bit. The R/W bit is 1 for a
read request and 0 for a write request. If the 7-bit address
matches the hard wired, LTC2497’s address (one of 27
SDA
tLOW
tf
tr
tSU(DAT)
tHD(SDA)
tf
tSP
tBUF
tr
SCL
S
tHD(SDA)
tHD(DAT)
tHIGH
tSU(STA)
Sr
tSU(STO)
P
S
2497 F02
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
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LTC2497
Applications Information
pin-selectable addresses) the device is selected. When
the device is addressed during the conversion state, it will
not acknowledge R/W requests and will issue a NAK by
leaving the SDA line high. If the conversion is complete,
the LTC2497 issues an ACK by pulling the SDA line low.
second bit is the most significant bit (MSB) of the result.
The first two bits (SIG and MSB) can be used to indicate
over and under range conditions (see Table 2). If both bits
are HIGH, the differential input voltage is equal to or above
+FS. If both bits are set low, the input voltage is below –FS.
The function of these bits is summarized in Table 2. The
16 bits following the MSB bit are the conversion result in
binary two’s complement format. The remaining six bits
are always 0.
The LTC2497 has two registers. The output register (24
bits long) contains the last conversion result. The input
register (8 bits long) sets the input channel.
As long as the voltage on the selected input channels (IN+
and IN–) remains between –0.3V and VCC + 0.3V (absolute
maximum operating range) a conversion result is generated for any differential input voltage VIN from –FS = –0.5
• VREF to +FS = 0.5 • VREF . For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to +FS. For differential input voltages below –FS, the conversion result is clamped to the
value –FS – 1LSB.
DATA OUTPUT FORMAT
The output register contains the last conversion result.
After each conversion is completed, the device automatically enters the sleep state where the supply current is
reduced to 1µA. When the LTC2497 is addressed for a read
operation, it acknowledges (by pulling SDA low) and acts
as a transmitter. The master/receiver can read up to three
bytes from the LTC2497. After a complete read operation
(3 bytes), a new conversion is initiated. The device will
NAK subsequent read operations while a conversion is
being performed.
Table 2. LTC2497 Status Bits
Input Range
The data output stream is 24 bits long and is shifted out
on the falling edges of SCL (see Figure 3a). The first bit
is the conversion result sign bit (SIG) (see Tables 1 and
2). This bit is high if VIN ≥ 0 and low if VIN < 0 (where VIN
corresponds to the selected input signal IN+ – IN–). The
VIN ≥ FS
Bit 23
SIG
Bit 22
MSB
1
1
0V ≤ VIN < FS
1
0
–FS ≤ VIN < 0V
0
1
VIN < –FS
0
0
Table 1. Output Data Format
Differential Input Voltage
VIN*
Bit 23
SIG
Bit 22
MSB
Bit 21
Bit 20
Bit 19
…
Bit 6
LSB
Bits 5-0
Always 0
VIN* ≥ FS**
1
1
0
0
0
…
0
000000
FS** – 1LSB
1
0
1
1
1
…
1
000000
0.5 • FS**
1
0
1
0
0
…
0
000000
0.5 • FS** – 1LSB
1
0
0
1
1
…
1
000000
0
1
0
0
0
0
…
0
000000
–1LSB
0
1
1
1
1
…
1
000000
–0.5 • FS**
0
1
1
0
0
…
0
000000
–0.5 • FS** – 1LSB
0
1
0
1
1
…
1
000000
–FS**
0
1
0
0
0
…
0
000000
VIN* < –FS**
0
0
1
1
1
…
1
000000
*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF .
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LTC2497
Applications Information
INPUT DATA FORMAT
If the first three bits are 000 or 100, the following data
is ignored (don’t care) and the previously selected input
channel remains valid for the next conversion.
The LTC2497 serial input is 8 bits long and is written into
the device in one 8-bit word. SGL, ODD, A2, A1, A0 are
used to select the input channel.
If the first three bits shifted into the device are 101, then
the next five bits select the input channel for the next
conversion cycle (see Table 3).
After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN+ = CH0, IN– =
CH1). The first conversion automatically begins at powerup using this default input channel. Once the conversion
is complete, a new channel may be written into the device.
The first input bit (SGL) following the 101 sequence determines if the input selection is differential (SGL = 0) or
single-ended (SGL = 1). For SGL = 0, two adjacent channels
can be selected to form a differential input. For SGL = 1,
one of 16 channels is selected as the positive input. The
negative input is COM for all single-ended operations.
The remaining four bits (ODD, A2, A1, A0) determine
which channel(s) is/are selected and the polarity (for a
differential input).
The first three bits of the input word consist of two preamble bits and one enable bit. These three bits are used
to enable the input channel selection. Valid settings for
these three bits are 000, 100, and 101. Other combinations
should be avoided.
1
SCL
…
7
8
9
1
2
SGN
MSB
…
9
1
2
3
4
5
6
7
8
9
SDA
7-BIT
ADDRESS
R
D15
ACK BY
LTC2497
START BY
MASTER
LSB
ACK BY
MASTER
NAK BY
MASTER
ALWAYS LOW
SLEEP
DATA OUTPUT
2497 F03a
Figure 3a. Timing Diagram for Reading from the LTC2497
1
SCL
2
…
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
X
X
6
7
8
9
SDA
7-BIT ADDRESS
START BY
MASTER
1
W
ACK BY
LTC2497
SLEEP
0
EN
SGL ODD
A2
A1
A0
X
ACK BY
LTC2497
X
X
X
X
X
NAK BY
LTC2497
DATA INPUT
2497 F03b
Figure 3b. Timing Diagram for Writing to the LTC2497
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LTC2497
Applications Information
Table 3. Channel Selection
MUX ADDRESS
ODD/
SGL SIGN
A2
A1
CHANNEL SELECTION
A0
0
1
IN+
IN–
*0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
IN–
2
3
IN+
IN–
4
5
IN+
IN–
6
7
IN+
IN–
8
9
IN+
IN–
10
11
IN+
IN–
12
13
IN+
IN–
14
15
IN+
IN–
IN–
IN+
COM
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
1
IN–
*Default at power up
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LTC2497
Applications Information
Initiating a New Conversion
Table 4. Address Assignment
When the LTC2497 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device is
ready for a read operation. After the device acknowledges
a read request, the device exits the sleep state and enters
the data output state. The data output state concludes and
the LTC2497 starts a new conversion once a Stop condition is issued by the master or all 24 bits of data are read
out of the device.
During the data read cycle, a Stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This Stop command must be
issued during the ninth clock cycle of a byte read when
the bus is free (the ACK/NAK cycle).
LTC2497 Address
The LTC2497 has three address pins (CA0, CA1, CA2).
Each may be tied high, low, or left floating enabling one
of 27 possible addresses (see Table 4).
In addition to the configurable addresses listed in Table 4,
the LTC2497 also contains a global address (1110111)
which may be used for synchronizing multiple LTC2497s or
other LTC24XX delta-sigma I2C devices, (See Synchronizing Multiple LTC2497s with Global Address Call section).
Operation Sequence
The LTC2497 acts as a transmitter or receiver, as shown
in Figure 4. The device may be programmed to select
an input channel, differential or single-ended mode, and
channel polarity.
Continuous Read
In applications where the input channel does not need to
change for each cycle, the conversion can be continuously
performed and read without a write cycle (see Figure 5).
The input channel remains unchanged from the last value
written into the device. If the device has not been written
to since power up, the channel selection is set to the default value of CH0 = IN+, CH1 = IN–. At the end of a read
operation, a new conversion automatically begins. At the
CA2
CA1
CA0
ADDRESS
LOW
LOW
LOW
0010100
LOW
LOW
HIGH
0010110
LOW
LOW
FLOAT
0010101
LOW
HIGH
LOW
0100110
LOW
HIGH
HIGH
0110100
LOW
HIGH
FLOAT
0100111
LOW
FLOAT
LOW
0010111
LOW
FLOAT
HIGH
0100101
LOW
FLOAT
FLOAT
0100100
HIGH
LOW
LOW
1010110
HIGH
LOW
HIGH
1100100
HIGH
LOW
FLOAT
1010111
HIGH
HIGH
LOW
1110100
HIGH
HIGH
HIGH
1110110
HIGH
HIGH
FLOAT
1110101
HIGH
FLOAT
LOW
1100101
HIGH
FLOAT
HIGH
1100111
HIGH
FLOAT
FLOAT
1100110
FLOAT
LOW
LOW
0110101
FLOAT
LOW
HIGH
0110111
FLOAT
LOW
FLOAT
0110110
FLOAT
HIGH
LOW
1000111
FLOAT
HIGH
HIGH
1010101
FLOAT
HIGH
FLOAT
1010100
FLOAT
FLOAT
LOW
1000100
FLOAT
FLOAT
HIGH
1000110
FLOAT
FLOAT
FLOAT
1000101
conclusion of the conversion cycle, the next result may
be read using the method described above. If the conversion cycle is not concluded and a valid address selects the
device, the LTC2497 generates a NAK signal indicating the
conversion cycle is in progress.
Continuous Read/Write
Once the conversion cycle is concluded, the LTC2497 can
be written to and then read from using the Repeated Start
(Sr) command.
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LTC2497
Applications Information
Discarding a Conversion Result and Initiating a New
Conversion with Optional Write
Figure 6 shows a cycle which begins with a data Write,
a repeated Start, followed by a Read and concluded with
a Stop command. The following conversion begins after
all 24 bits are read out of the device or after a Stop command. The following conversion will be performed using
the newly programmed data.
S
R/W
7-BIT ADDRESS
CONVERSION
ACK
At the conclusion of a conversion cycle, a write cycle
can be initiated. Once the write cycle is acknowledged, a
Stop command will start a new conversion. If a new input
channel is required, this data can be written into the device
and a Stop command will initiate the next conversion (see
Figure 7).
DATA
SLEEP
Sr
DATA TRANSFERRING
P
DATA INPUT/OUTPUT
CONVERSION
2497 F04
Figure 4. Conversion Sequence
S
7-BIT ADDRESS
CONVERSION
R ACK
SLEEP
READ
P
S
7-BIT ADDRESS
CONVERSION
DATA OUTPUT
R ACK
SLEEP
READ
P
DATA OUTPUT
CONVERSION
2497 F05
Figure 5. Consecutive Reading with the Same Input/Configuration
S
7-BIT ADDRESS
W ACK
SLEEP
CONVERSION
WRITE
Sr
DATA INPUT
7-BIT ADDRESS
R ACK
ADDRESS
READ
DATA OUTPUT
P
CONVERSION
2497 F06
Figure 6. Write, Read, Start Conversion
S
7-BIT ADDRESS
CONVERSION
W ACK
SLEEP
WRITE (OPTIONAL)
DATA INPUT
P
CONVERSION
2497 F07
Figure 7. Start a New Conversion without Reading Old Conversion Result
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LTC2497
Applications Information
Synchronizing Multiple LTC2497s with a Global
Address Call
Driving the Input and Reference
In applications where several LTC2497s (or other I2C deltasigma ADCs from Linear Technology Corporation) are used
on the same I2C bus, all converters can be synchronized
through the use of a global address call. Prior to issuing the
global address call, all converters must have completed a
conversion cycle. The master then issues a Start, followed
by the global address 1110111, and a write request. All
converters will be selected and acknowledge the request.
The master then sends a write byte (optional) followed by
the Stop command. This will update the channel selection
(optional) and simultaneously initiate a start of conversion
for all delta-sigma ADCs on the bus (see Figure 8). In order
to synchronize multiple converters without changing the
channel, a Stop may be issued after acknowledgement of
the global write command. Global read commands are not
allowed and the converters will NAK a global read request.
The input and reference pins of the LTC2497 are connected
directly to a switched capacitor network. Depending on
the relationship between the differential input voltage and
the differential reference voltage, these capacitors are
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount
of charge is transferred. A simplified equivalent circuit is
shown in Figure 9.
When using the LTC2497’s internal oscillator, the input
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the input/
reference pins. If the total external RC time constant is less
than 580ns the errors introduced by the sampling process
are negligible since complete settling occurs.
SCL
SDA
LTC2497
S
LTC2497
W ACK
GLOBAL ADDRESS
ALL LTC2497s IN SLEEP
…
WRITE (OPTIONAL)
DATA INPUT
LTC2497
P
CONVERSION OF ALL LTC2497s
2497 F08
Figure 8. Synchronize Multiple LTC2497s with a Global Address Call
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19
LTC2497
Applications Information
Typically, the reference inputs are driven from a low
impedance source. In this case, complete settling occurs
even with large external bypass capacitors. The inputs
(CH0-CH15, COM), on the other hand, are typically driven
from larger source resistances. Source resistances up
to 10k may interface directly to the LTC2497 and settle
completely; however, the addition of external capacitors
at the input terminals in order to filter unwanted noise
(anti-aliasing) results in incomplete settling.
The LTC2497 offers two methods of removing these
errors. The first is an automatic differential input current
cancellation (Easy Drive) and the second is the insertion
of an external buffer between the MUXOUT and ADCIN
pins, thus isolating the input switching from the source
resistance.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kW with no external bypass capacitor or up
to 500W with 0.001µF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization is possible.
IIN+
IN+
INPUT
MULTIPLEXER
100Ω
EXTERNAL
CONNECTION
MUXOUTP
ADCINP
For many applications, the sensor output impedance
combined with external input bypass capacitors produces
RC time constants much greater than the 580ns required
for 1ppm accuracy. For example, a 10kW bridge driving a
0.1µF capacitor has a time constant an order of magnitude
greater than the required maximum.
The LTC2497 uses a proprietary switching algorithm
that forces the average differential input current to zero
independent of external settling errors. This allows direct
digitization of high impedance sensors without the need
for buffers.
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current on the negative input (IIN–). Over the complete
conversion cycle, the average differential input current
(IIN+ – IIN–) is zero. While the differential input current is
zero, the common mode input current (IIN+ + IIN–)/2 is
proportional to the difference between the common mode
input voltage (VIN(CM)) and the common mode reference
voltage (VREF(CM)).
INTERNAL
SWITCH
NETWORK
( )
I IN+
10kΩ
(
I REF +
IREF+
)
( )
= I IN–
AVG
≈
AVG
VIN(CM) − VREF(CM)
=
0.5 • REQ
(
1.5VREF + VREF(CM) – VIN(CM)
0.5 • REQ
)–
VIN2
VREF • REQ
where :
IIN–
IN–
AVG
100Ω
MUXOUTN
ADCINN
VREF = REF + − REF −
10kΩ
REF + – REF −
VREF(CM) =
2
EXTERNAL
CONNECTION
REF+
CEQ
12µF
10kΩ
VIN = IN+ − IN− , WHERE IN+ AND IN− ARE THE SELECTED INPUT CHANNELS
IN+ – IN−
VIN(CM) =
2
REQ = 2.98MΩ INTERNAL OSCILLATOR
IREF–
REF–
(
)
REQ = 0.833 • 1012 /fEOSC EXTERNAL OSCILLATOR
10kΩ
2497 F09
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR
Figure 9. Equivalent Analog Input Circuit
2497fb
20
For more information www.linear.com/LTC2497
LTC2497
Applications Information
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balanced bridge, both the differential and common mode input current are zero. The accuracy of the
converter is not compromised by settling errors.
impedances lead to gain errors proportional to the difference between the common mode input and common
mode reference. 1% mismatches in 1k source resistances
lead to gain errors on the order of 15ppm. Based on the
stability of the internal sampling capacitors and the accuracy of the internal oscillator, a one-time calibration will
remove this error.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between VIN(CM) and VREF(CM). For a reference
common mode voltage of 2.5V and an input common
mode of 1.5V, the common mode input current is approximately 0.74µA. This common mode input current
does not degrade the accuracy if the source impedances
tied to IN+ and IN– are matched. Mismatches in source
impedance lead to a fixed offset error but do not effect
the linearity or full-scale reading. A 1% mismatch in a 1k
source resistance leads to a 74µV shift in offset voltage.
In addition to the input sampling current, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and a 10µV maximum offset voltage.
Automatic Offset Calibration of External Buffers/
Amplifiers
In addition to the Easy Drive input current cancellation,
the LTC2497 allows an external amplifier to be inserted
between the multiplexer output and the ADC input (see
Figure 10). This is useful in applications where balanced
source impedances are not possible. One pair of external
buffers/amplifiers can be shared between all 17 analog
inputs. The LTC2497 performs an internal offset calibration
every conversion cycle in order to remove the offset and
drift of the ADC. This calibration is performed through a
In applications where the common mode input voltage
varies as a function of the input signal level (single-ended
type sensors), the common mode input current varies
proportionally with input voltage. For the case of balanced
input impedances, the common mode input current effects
are rejected by the large CMRR of the LTC2497, leading
to little degradation in accuracy. Mismatches in source
LTC2497
∆∑ ADC
WITH
EASY DRIVE
INPUTS
MUXOUTN
INPUT
MUX
MUXOUTP
ANALOG 17
INPUTS
2
–
1/2 LTC6078
3
+
6
–
5
1/2 LTC6078
+
1
SDA
SCL
1k
0.1µF
7
1k
2497 F10
0.1µF
Figure 10. External Buffers Provide High Impedance Inputs
and Amplifier Offsets are Automatically Cancelled.
2497fb
For more information www.linear.com/LTC2497
21
LTC2497
Applications Information
combination of front end switching and digital processing. Since the external amplifier is placed between the
multiplexer and the ADC, it is inside this correction loop.
This results in automatic offset correction and offset drift
removal of the external amplifier.
The LTC6078 is an excellent amplifier for this function.
It operates with supply voltages as low as 2.7V and its
noise level is 18nV/√Hz. The Easy Drive input technology
of the LTC2497 enables an RC network to be added directly
to the output of the LTC6078. The capacitor reduces the
magnitude of the current spikes seen at the input to the
ADC and the resistor isolates the capacitor load from the
op-amp output enabling stable operation. The LTC6078
can also be biased at supply rails beyond those used by
the LTC2497. This allows the external sensor to swing railto-rail (–0.3V to VCC + 0.3V) without the need of external
level shift circuitry.
90
60
50
30
20
–10
10
0
–10
0
10
In cases where large bypass capacitors are required on
the reference inputs (CREF > 0.01µF), full-scale and linearity errors are proportional to the value of the reference
resistance. Every ohm of reference resistance produces
a full-scale error of approximately 0.5ppm (while operat-
0
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
40
For relatively small values of external reference capacitance
(CREF < 1nF), the voltage on the sampling capacitor settles
for reference impedances of many kW (if CREF = 100pF up
to 10kW will not degrade the performance) (see Figures
11 and 12).
–FS ERROR (ppm)
+FS ERROR (ppm)
70
Similar to the analog inputs, the LTC2497 samples the
differential reference pins (REF+ and REF–) transferring
small amounts of charge to and from these pins, thus
producing a dynamic reference current. If incomplete settling occurs (as a function the reference source resistance
and reference bypass capacitance) linearity and gain errors
are introduced.
10
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
fO = GND
TA = 25°C
80
Reference Current
1k
100
RSOURCE (Ω)
10k
100k
–20
–30
–40
–50
VCC = 5V
–60 VREF = 5V
V + = 1.25V
–70 VIN– = 3.75V
IN
–80 fO = GND
TA = 25°C
–90
10
0
2497 F11
Figure 11. +FS Error vs RSOURCE at VREF (Small CREF)
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
1k
100
RSOURCE (Ω)
10k
100k
2497 F12
Figure 12. –FS Error vs RSOURCE at VREF (Small CREF)
2497fb
22
For more information www.linear.com/LTC2497
LTC2497
Applications Information
ing with the internal oscillator) (see Figures 13 and 14). If
the input common mode voltage is equal to the reference
common mode voltage, a linearity error of approximately
0.67ppm per 100W of reference resistance results (see
Figure 15). In applications where the input and reference
common mode voltages are different, the errors increase.
A 1V difference in between common mode input and
common mode reference results in a 6.7ppm INL error
for every 100W of reference resistance.
In addition to the reference sampling charge, the reference
ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA
max) results in a small, gain error. A 100W reference
resistance will create a 0.5µV full-scale error.
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
fO = GND
TA = 25°C
+FS ERROR (ppm)
400
300
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversample ratio, the LTC2497 significantly
simplifies anti-aliasing filter requirements. Additionally,
the input current cancellation feature allows external low
pass filtering without degrading the DC performance of
the device.
The SINC4 digital filter provides excellent normal mode
rejection at all frequencies except DC and integer multiples
of the modulator sampling frequency (fS). The modulator
sampling frequency is fS = 15,360Hz while operating with
its internal oscillator and fS = fEOSC/20 when operating
with an external oscillator of frequency fEOSC .
0
CREF = 1µF, 10µF
–100
–FS ERROR (ppm)
500
Normal Mode Rejection and Anti-Aliasing
CREF = 0.1µF
200
CREF = 0.01µF
–200
CREF = 1µF, 10µF
–300
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
fO = GND
TA = 25°C
–400
100
0
CREF = 0.01µF
0
200
600
400
RSOURCE (Ω)
800
–500
1000
0
2497 F13
Figure 13. +FS Error vs RSOURCE at VREF (Large CREF)
200
CREF = 0.1µF
600
400
RSOURCE (Ω)
800
1000
2497 F14
Figure 14. –FS Error vs RSOURCE at VREF (Large CREF)
INL (ppm OF VREF)
10
VCC = 5V
8 VREF = 5V
VIN(CM) = 2.5V
6 T = 25°C
A
4 CREF = 10µF
R = 1k
2
R = 500Ω
0
R = 100Ω
–2
–4
–6
–8
–10
–0.5
–0.3
0.1
–0.1
VIN/VREF
0.3
0.5
2497 F15
Figure 15. INL vs Differential Input Voltage and
Reference Source Resistance for CREF > 1µF
2497fb
For more information www.linear.com/LTC2497
23
LTC2497
Applications Information
The user can expect to achieve this level of performance using the internal oscillator, as shown in Figure 18. Measured
values of normal mode rejection are shown superimposed
over the theoretical values.
Traditional high order delta-sigma modulators suffer from
potential instabilities at large input signal levels. The
proprietary architecture used for the LTC2497 third order
modulator resolves this problem and guarantees stability
with input signals 150% of full scale. In many industrial
applications, it is not uncommon to have microvolt level
INPUT NORMAL MODE REJECTION (dB)
0
fN = fEOSC/5120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
signals superimposed over unwanted error sources with
several volts if peak-to-peak noise. Figure 19 shows measurement results for the rejection of a 7.5V peak-to-peak
noise source (150% of full scale) applied to the LTC2497.
This curve shows that the rejection performance is maintained even in extremely noisy environments.
Output Data Rate
When using its internal oscillator, the LTC2497 produces
up to 7.5 samples per second (sps) with a notch frequency
of 60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignificantly short. When
operating with an external conversion clock (fO connected
to an external oscillator), the LTC2497 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
0
INPUT NORMAL MODE REJECTION (dB)
When using the internal oscillator, the LTC2497 is designed
to reject line frequencies. As shown in Figure 16, rejection
nulls occur at multiples of frequency fN, where fN = 55Hz
for simultaneous 50Hz/60Hz rejection. Multiples of the
modulator sampling rate (fS = fN • 256) only reject noise
to 15dB (see Figure 17); if noise sources are present at
these frequencies anti-aliasing will reduce their effects.
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
2497 F16
Figure 16. Input Normal Mode Rejection at DC
fN = fEOSC/5120
2497 F17
Figure 17. Input Normal Mode Rejection at fS = 256 • fN
2497fb
24
For more information www.linear.com/LTC2497
LTC2497
Applications Information
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–120
0
20
40
60
80
100
120
140
INPUT FREQUENCY (Hz)
160
180
200
220
0
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
–40
–60
–80
–100
–120
0
15
30
45
2497 F18
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2497 F19
Figure 18. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz/60Hz Notch)
Figure 19. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (60Hz Notch)
An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output
data rate (up to a maximum of 100sps). The increase in
output rate leads to degradation in offset, full-scale error,
and effective resolution as well as a shift in frequency
rejection.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN+ and IN– pins will continue to reject line
frequency noise.
Once the external oscillator frequency is increased above
1MHz (a more than 3X increase in output rate) the effectiveness of internal auto calibration circuits begins to
degrade. This results in larger offset errors, full-scale errors,
and decreased resolution, as shown in Figures 20 to 27.
2497fb
For more information www.linear.com/LTC2497
25
LTC2497
Applications Information
3500
40
30
3000
20
10
2500
–500
–1000
–1500
2000
–2000
1500
1000
0
500
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
0
30
0
20
10
OUTPUT DATA RATE (READINGS/SEC)
2497 F20
Figure 22.–FS Error vs Output Data
Rate and Temperature
20
18
RESOLUTION (BITS)
TA = 25°C, 85°C
16
14
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
12
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
30
TA = 25°C, 85°C
16
14
12 VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
10
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
2497 F23
5
0
–5
–10
30
0
20
10
OUTPUT DATA RATE (READINGS/SEC)
30
2497 F25
Figure 24. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 25. Offset Error vs Output
Data Rate and Reference Voltage
18
18
VCC = VREF = 5V
VCC = 5V, VREF = 2.5V, 5V
16
RESOLUTION (BITS)
RESOLUTION (BITS)
VIN(CM) = VREF(CM)
VIN = 0V
15 fO = EXT CLOCK
TA = 25°C
VCC = 5V, VREF = 2.5V
10 V = V
CC
REF = 5V
2497 F24
Figure 23. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
30
2497 F22
Figure 21. +FS Error vs Output Data
Rate and Temperature
18
RESOLUTION (BITS)
30
2497 F21
Figure 20. Offset Error vs Output Data
Rate and Temperature
10
–2500 TA = 25°C
TA = 85°C
V
= VREF(CM)
–3000 IN(CM)
VCC = VREF = 5V
fO = EXT CLOCK
–3500
10
20
0
OUTPUT DATA RATE (READINGS/SEC)
OFFSET ERROR (ppm OF VREF)
–10
0
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
TA = 25°C
TA = 85°C
–FS ERROR (ppm OF VREF)
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
TA = 25°C
TA = 85°C
+FS ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
50
14
VIN(CM) = VREF(CM)
12 VIN = 0V
fO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/NOISERMS)
10
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
30
16
VCC = 5V, VREF = 2.5V
14
VIN(CM) = VREF(CM)
VIN = 0V
12 REF– = GND
fO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
10
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
2497 F27
2497 F26
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
30
Figure 27. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
2497fb
26
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LTC2497
Applications Information
VCC + 0.3V
VCC
VREF
2
GND
–0.3V
VCC
VREF
2
–VREF
2
VREF
2
–VREF
2
GND
(a) Arbitrary
(b) Fully Differential
VCC
VCC
VREF
2
VREF
2
–VREF
2
GND
(c) Pseudo Differential Bipolar
IN– or COM Biased
Selected IN+ Ch
Selected IN– Ch or COM
–0.3V
GND
–0.3V
(d) Pseudo-Differential Unipolar
IN– or COM Grounded
2497 F28
Figure 28. Input Range
2497fb
For more information www.linear.com/LTC2497
27
LTC2497
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 ±0.05
5.50 ±0.05
5.15 ±0.05
4.10 ±0.05
3.00 REF
3.15 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
5.5 REF
6.10 ±0.05
7.50 ±0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 ±0.05
5.00 ±0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ±0.10
5.50 REF
7.00 ±0.10
3.15 ±0.10
(UH) QFN REF C 1107
0.200 REF 0.25 ±0.05
R = 0.125
TYP
0.50 BSC
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2497fb
28
For more information www.linear.com/LTC2497
LTC2497
Revision History
REV
DATE
DESCRIPTION
PAGE NUMBER
A
7/10
Revised Typical Application drawing
Revised Parameter for VIHA
B
11/14
in I2C Inputs and Digital Outputs section
1
4
Clarified performance vs frequency, reduced External Oscillator Max frequency to 1MHz
5, 8, 26
Clarified Input Voltage Range
3, 12, 27
2497fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC2497
29
LTC2497
Typical Application
External Buffers Provide High Impedance Inputs and
Amplifier Offsets are Automatically Cancelled
∆∑ ADC
WITH
EASY DRIVE
INPUTS
MUXOUTN
INPUT
MUX
MUXOUTP
LTC2497
ANALOG 17
INPUTS
2
–
1/2 LTC6078
3
+
6
–
5
1/2 LTC6078
1
SDA
SCL
1k
0.1µF
7
+
1k
2497 TA02
0.1µF
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0.8µVRMS Noise, 2ppm INL
LTC2411/LTC2411-1 24-bit, No Latency ΔΣ ADCs with Differential Inputs in MSOP
1.45µVRMS Noise, 2ppm INL, Simultaneous 50Hz/60Hz
Rejection (LTC2411-1)
LTC2413
24-bit, No Latency ΔΣ ADC with Differential Inputs
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2440
High Speed, Low Noise 24-bit ΔΣ ADC
3.5kHz Output Rate, 200nVRMS Noise, 24.6 ENOBs
LTC2442
24-Bit, High Speed, 4-Channel/2-Channel ΔΣ ADC with
Integrated Amplifier
8kHz Output Rate, 220nVRMS Noise, Simultaneous 50Hz/60Hz
Rejection
LTC2449
24-Bit, High Speed, 8-Channel/16-Channel ΔΣ ADC
8kHz Output Rate, 200nVRMS Noise, Simultaneous 50Hz/60Hz
Rejection
LTC2480/LTC2482/
LTC2484
16-Bit/24-Bit ΔΣ ADCs with Easy Drive Inputs, 600nVRMS
Noise, Programmable Gain, and Temperature Sensor
Pin-Compatible with 16-Bit and 24-Bit Versions
LTC2481/LTC2483/
LTC2485
16-Bit/24-Bit ΔΣ ADCs with Easy Drive Inputs, 600nVRMS
Noise, I2C Interface, Programmable Gain, and Temperature
Sensor
Pin-Compatible with 16-Bit and 24-Bit Versions
LTC2496
16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Inputs and
SPI Interface
Pin-Compatible with LTC2498/LTC2449
LTC2498
24-bit 8-/16-Channel ΔΣ ADC with Easy Drive Inputs and
SPI Interface
Pin-Compatible with LTC2496/LTC2449
LTC2499
24-bit 8-/16-Channel ΔΣ ADC with Easy Drive Inputs and
I2C Interface, and Temperature Sensor
Pin-Compatible with LTC2497
2497fb
30 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2497
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2497
LT 1114 REV B • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2006
