LTC2600/LTC2610/LTC2620
Octal 16-/14-/12-Bit
Rail-to-Rail DACs in 16-Lead SSOP
DESCRIPTION
FEATURES
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Smallest Pin-Compatible Octal DACs:
LTC2600: 16 Bits
LTC2610: 14 Bits
LTC2620: 12 Bits
Guaranteed 16-Bit Monotonic Over Temperature
Wide 2.5V to 5.5V Supply Range
Low Power Operation: 250μA per DAC at 3V
Individual Channel Power-Down to 1μA, Max
Ultralow Crosstalk Between DACs ( 1GΩ)
when all eight DACs are powered down.
Normal operation can be resumed by executing any
command which includes a DAC update, as shown in
Table 1. The selected DAC is powered up as its voltage
output is updated.
There is an initial delay as the DAC powers up before it
begins its usual settling behavior. If less than eight DACs
are in a powered-down state prior to the update command,
the power-up delay is 5μs. If, on the other hand, all eight
DACs are powered down, then the master bias generation circuit is also disabled and must be restarted. In this
case, the power-up delay is greater: 12μs for VCC = 5V,
30μs for VCC = 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.025Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 25Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
25Ω • 1mA = 25mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The amplifiers are stable driving capacitive loads of up
to 1000pF.
Board Layout
The excellent load regulation and DC crosstalk performance
of these devices is achieved in part by keeping “signal”
and “power” grounds separated internally and by reducing
shared internal resistance to just 0.005Ω.
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14
LTC2600/LTC2610/LTC2620
OPERATION
The GND pin functions both as the node to which the reference and output voltages are referred and as a return path
for power currents in the device. Because of this, careful
thought should be given to the grounding scheme and
board layout in order to ensure rated performance.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here will
add directly to the effective DC output impedance of the
device (typically 0.025Ω), and will degrade DC crosstalk.
Note that the LTC2600/LTC2610/LTC2620 are no more
susceptible to these effects than other parts of their type;
on the contrary, they allow layout-based performance
improvements to shine rather than limiting attainable
performance with excessive internal resistance.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown
in Figure 3b. Similarly, limiting can occur near full scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 3c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
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15
16
X
X
SDI
SDO
SCK
CS/LD
1
X
X
2
X
X
3
X
4
X
X
X
DON’T CARE
5
C3
SDI
C2
2
C1
3
X
X
6
X
X
7
C3
C2
10
C1
11
C2
C1
COMMAND WORD
9
C3
A1
7
ADDRESS WORD
A2
6
A0
8
D15
9
D14
10
D12
12
D11
13
D10
14
24-BIT INPUT WORD
D13
11
D9
15
D7
17
DATA WORD
D8
16
D6
18
D5
C0
C0
A3
A3
A2
14
A1
15
A2
A1
ADDRESS WORD
13
A0
A0
16
17
D15
D15
PREVIOUS 32-BIT INPUT WORD
12
D14
D14
18
t2
t8
D9
D9
t4
23
PREVIOUS D15
t3
17
D10
D10
22
SDO
t1
D11
D11
21
D15
D12
D12
20
SDI
SCK
D13
D13
19
25
18
D7
PREVIOUS D14
D14
D8
DATA WORD
D6
D5
D4
D3
D2
D2
30
YYYY F02a
29
D3
24
D0
28
D4
23
D1
27
D5
22
D2
26
D6
21
D3
D7
20
D4
24
D8
19
Figure 2a. LTC2600 24-Bit Load Sequence (Minimum Input Word).
LTC2610 SDI Data Word: 14-Bit Input Code + 2 Don’t-Care Bits;
LTC2620 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits
A3
5
D1
D1
31
YYYY F02b
CURRENT
32-BIT
INPUT WORD
D0
D0
32
OPERATION
Figure 2b. LTC2600 32-Bit Load Sequence (Required for Daisy-Chain Operation).
LTC2610 SDI/SDO Data Word: 14-Bit Input Code + 2 Don’t-Care Bits;
LTC2620 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t-Care Bits
X
X
4
C0
8
COMMAND WORD
1
SCK
CS/LD
LTC2600/LTC2610/LTC2620
2600fe
LTC2600/LTC2610/LTC2620
OPERATION
VREF = VCC
VREF = VCC
POSITIVE
FSE
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
(c)
OUTPUT
VOLTAGE
0
0V
NEGATIVE
OFFSET
32, 768
INPUT CODE
(a)
65, 535
INPUT CODE
(b)
2600 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2600fe
17
LTC2600/LTC2610/LTC2620
PACKAGE DESCRIPTION
UFD Package
20-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)
0.70 p0.05
4.50 p 0.05
1.50 REF
3.10 p 0.05
2.65 p 0.05
3.65 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
2.50 REF
4.10 p 0.05
5.50 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 p 0.10
(2 SIDES)
0.75 p 0.05
PIN 1 NOTCH
R = 0.20 OR
C = 0.35
1.50 REF
R = 0.05 TYP
19
20
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 p 0.10
(2 SIDES)
2.50 REF
3.65 p 0.10
2.65 p 0.10
(UFD20) QFN 0506 REV B
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 p 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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18
LTC2600/LTC2610/LTC2620
REVISION HISTORY
(Revision history begins at Rev D)
REV
DATE
DESCRIPTION
PAGE NUMBER
D
03/10
Revise GN Part Markings in Order Information
E
05/10
Changed “No Connect” pins to “Do Not Connect” in Pin Configuration and Pin Functions sections
2
2, 10
2600fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2600/LTC2610/LTC2620
TYPICAL APPLICATION
Schematic for LTC2600 Demonstration Circuit DC579. The Outputs Are Measured by an Onboard LTC2428
1
4
3
2
1
VSS SDA
A2
SCL
A1
WP
A0
VCC
VREF
VCC
1
TP1
TP2
5
R1, R3, R4
R1 are 4.99k, 1%
6
R3
R2
7.5k
R4
11
7
C3
0.1μF
8
C2
0.1μF
6
REF
CLR
VCC
VOUTA
U1
24LC025
VOUTB
14
12
10
8
6
4
2
5V
VCC
C1
0.1μF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
13
11
9
7
5
3
1
SCK
8
CS
7
9
10
MOSI
MISO
VOUTC
SCK
VOUTD
LS/LD
VOUTE
VOUTF
SDI
VOUTG
SDO
VOUTH
16
2
1
TP16
VIN
TP3
DAC A
1
TP14
GND
4
1
TP4
DAC B
1
TP15
GND
1
TP5
DAC C
1
TP6
DAC D
1
TP7
DAC E
1
TP8
DAC F
1
TP9
DAC G
5
12
13
14
15
GND
1
1
3
U2
LTC2600CGN
J1
HD2X7
1
VIN
TP10
DAC H
VREF
VOUT
VIN
6
9
1
C6
0.1μF
1
5V
4.096V
2
3 JP2
TP11
VREF
C7
4.7μF
6.3V
VREF
U5
LT1461ACS8-4
2
3
C9
0.1μF
VIN
VOUT
6
VCC
1
SHDN
GND
4
C5
0.1μF
R8
22Ω
C10
100pF
7
4
MUXOUT
ADCIN
3
3
2
2
8
1
JP1
ON/OFF
DISABLE
ADC
VCC VCC
FSSET
VREF
GND
4
VCC
C4
0.1μF
R5
7.5k
U4
LT1236ACS8-5
2
VCC
1
5VREF
C8 REGULATOR
1μF
16V
2
3 JP3
1
VCC
TP12
VCC
TP13
GND
CH0
10
CH1
11
CH2
12
CH3
13
CH4
14
CH5
15
CH6
17
CH7
5
ZSSET
CSADC
CSMUX
4-/8-CHANNEL
MUX
+
20-BIT
ADC
SCK
CLK
DIN
–
LTC2424/LTC2428
SD0
FO
GND GND GND GND GND GND GND
1
U3
LTC2428CG
6
16
18
22
27
28
23
20
R6
7.5k
CS
25
19
SCK
21
24
26
R7
7.5k
5V
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1654
Dual 14-Bit Rail-to-Rail VOUT DAC
Programmable Speed/Power, 3.5μs/750μA, 8μs/450μA
LTC1655/LTC1655L
Single 16-Bit VOUT DAC with Serial Interface in SO-8
VCC = 5V(3V), Low Power, Deglitched
LTC1657/LTC1657L
Parrallel 5V/3V 16-Bit VOUT DAC
Low Power, Deglitched, Rail-to-Rail VOUT
LTC1660/LTC1665
Octal 10/8-Bit VOUT DAC in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1821
Parallel 16-Bit Voltage Output DAC
Precision 16-Bit Settling in 2μs for 10V Step
2600fe
20 Linear Technology Corporation
LT 0510 REV E • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003
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