LTC2637IDE-HMX12#PBF

LTC2637 Octal 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference DESCRIPTION FEATURES Integrated Precision Reference: 2.5V Full-Scale 10ppm/°C (LTC2637-L) 4.096V Full-Scale 10ppm/°C (LTC2637-H) nn Maximum INL Error: 2.5LSB (LTC2637-12) nn Low Noise: 0.75mV P-P 0.1Hz to 200kHz nn Guaranteed Monotonic Over –40°C to 125°C Temperature Range nn Selectable Internal or External Reference nn 2.7V to 5.5V Supply Range (LTC2637-L) nn Ultralow Crosstalk Between DACs ( 4V requires VCC slew rates to be no greater than 110mV/µs. Note 4: Linearity and monotonicity are defined from code kL to code 2N–1, where N is the resolution and kL is given by kL = 0.016•(2N/ VFS), rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16 and linearity is defined from code 16 to code 4,095. Note 5: Inferred from measurement at code 16 (LTC2637-12), code 4 (LTC2637-10) or code 1 (LTC2637-8), and at full-scale. Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. MIN TYP MAX UNITS 400 kHz µs 0.9 µs ns Note 7: Digital inputs at 0V or VCC. Note 8: Guaranteed by design and not production tested. Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND. Note 10: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 11: Maximum VIH = VCC(MAX) + 0.5V. Note 12: CB = Capacitance of one bus line in pF. Note 13: All values refer to VIH = VIN(MIN) and VIL = VIL(MAX) levels. Note 14: Minimum VIL exceeds Absolute Maximum rating. This condition won’t damage the IC, but could degrade performance. Note 15: Thermal resistance of MSOP package limits IOUT to –5mA ≤ IOUT ≤ 5mA for H-grade MSOP parts and VCC = 5V ±10%. Rev D 10 For more information www.analog.com LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637-L12 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 3V 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 VCC = 3V 0 –0.5 1024 0 3072 2048 CODE –1.0 4095 1024 0 3072 2048 CODE 4095 2637 G01 INL vs Temperature INL (POS) 0.5 0 INL (NEG) –0.5 –1.0 –50 –25 1.260 VCC = 3V DNL (POS) 0 DNL (NEG) –0.5 0 25 50 75 100 125 150 TEMPERATURE (°C) 1.250 1.245 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G03 1.240 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G04 Settling to ±1LSB Rising 2637 G05 Settling to ±1LSB Falling 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV VCC = 3V 1.255 VREF (V) INL (LSB) 1.0 VCC = 3V 0.5 Reference Output Voltage vs Temperature DNL vs Temperature DNL (LSB) 1.0 2637 G02 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS VOUT 1LSB/DIV 4.5µs 3.6µs VOUT 1LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2µs/DIV SCL 5V/DIV 2637 G06 9TH CLOCK OF 3RD DATA BYTE 2µs/DIV 2637 G07 Rev D For more information www.analog.com 11 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637-H12 (Internal Reference, VFS = 4.096V) Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 5V 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 VCC = 5V 0 –0.5 1024 0 3072 2048 CODE –1.0 4095 1024 0 3072 2048 CODE 4095 2637 G08 INL vs Temperature 1.0 VCC = 5V INL (POS) INL (NEG) –0.5 DNL (POS) 0 DNL (NEG) 25 50 75 100 125 150 TEMPERATURE (°C) –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G10 2.028 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G12 2637 G11 Settling to ±1LSB Rising Settling to ±1LSB Falling 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV 2.048 2.038 –0.5 0 VCC = 5V 2.058 0.5 0 –1.0 –50 –25 2.068 VCC = 5V VREF (V) INL (LSB) 0.5 Reference Output Voltage vs Temperature DNL vs Temperature DNL (LSB) 1.0 2637 G09 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS VOUT 1LSB/DIV 5µs 4.1µs VOUT 1LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2µs/DIV SCL 5V/DIV 2637 G13 9TH CLOCK OF 3RD DATA BYTE 2µs/DIV 2637 G14 Rev D 12 For more information www.analog.com LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637-10 Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 3V VFS = 2.5V INTERNAL REF. 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 0 –0.5 256 0 768 512 CODE –1.0 1023 VCC = 3V VFS = 2.5V INTERNAL REF. DNL (LSB) INL (LSB) –0.25 64 0 192 128 CODE –0.50 255 64 0 192 128 CODE 2637 G17 Current Limiting 0.20 VCC = 5V (LTC2637-H) VCC = 5V (LTC2637-L) VCC = 3V (LTC2637-L) 0.15 0.10 4 ∆VOUT (V) 2 0 –2 –4 Offset Error vs Temperature 3 VCC = 5V (LTC2637-H) VCC = 5V (LTC2637-L) VCC = 3V (LTC2637-L) 2 0.05 0 –0.05 –0.01 –6 INTERNAL REF. CODE = MID-SCALE –8 –20 –10 0 10 IOUT (mA) 20 30 2637 G19 –0.15 –0.20 –30 INTERNAL REF. CODE = MID-SCALE –20 255 2637 G18 OFFSET ERROR (mV) Load Regulation ∆VOUT (mV) 0 –0.25 LTC2637 –10 –30 VCC = 3V VFS = 2.5V INTERNAL REF. 0.25 0 –0.50 1023 Differential Nonlinearity (DNL) 0.50 0.25 6 768 512 CODE 2637 G16 Integral Nonlinearity (INL) 0.50 8 256 0 2637 G15 LTC2637-8 10 VCC = 3V VFS = 2.5V INTERNAL REF. –10 0 10 IOUT (mA) 20 30 2637 G20 1 0 –1 –2 –3 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G21 Rev D For more information www.analog.com 13 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637 Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch LTC2637-L 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV VCC 2V/DIV VOUT 0.5V/DIV LTC2637-H12 VCC = 5V, 3nV•s TYP VOUT 5mV/DIV ZERO-SCALE VOUT 5mV/DIV LTC2637-L12 VCC = 3V, 2.1nV•s TYP VFS = VCC = 5V 1/4 SCALE to 3/4 SCALE 2µs/DIV 2637 G23 2µs/DIV 200µs/DIV 2637 G22 2637 G24 Headroom at Rails vs Output Current Exiting Power-Down to Mid-Scale Power-On Reset to Mid-Scale 5.0 5V SOURCING 4.5 3.5 3V (LTC2637-L) SOURCING 3.0 LTC2637-H 2.5 2.0 1.5 DACs A TO G IN POWER-DOWN MODE 5V SINKING 1.0 0 0 1 2 3 4 5 6 IOUT (mA) 7 8 9 200µs/DIV 2637 G27 DAC to DAC Crosstalk (Dynamic) Multiplying Bandwidth 2 9TH CLOCK OF 3RD DATA BYTE 0 –2 SCL LTC2637-H12 5V/DIV VCC = 5V, 3nV•s TYP CREF = 0.1µF 1 DAC SWITCH 0 TO FS 2V/DIV 1.4 VCC = 5V 1.2 1.0 VCC = 3V (LTC2637-L) –4 –6 –8 –10 –12 VOUT 2mV/DIV 0.8 0.6 2637 G26 2637 G25 SWEEP SDA, SCL, BETWEEN 0V AND VCC 1.6 LTC2637-L LTC2637H VCC = 5V INTERNAL REF 5µs/DIV 10 Supply Current vs Logic Voltage 1.8 VOUT 0.5V/DIV VOUT 0.5V/DIV 3V (LTC2637-L) SINKING 0.5 ICC (mA) VCC 2V/DIV dB VOUT (V) 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV 4.0 VCC = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL-SCALE –14 –16 0 1 2 3 LOGIC VOLTAGE (V) 4 5 2µs/DIV 2637 G29 –18 1k 10k 100k FREQUENCY (Hz) 1M 2637 G30 2637 G28 Rev D 14 For more information www.analog.com LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637 Gain Error vs. Temperature Noise Voltage vs. Frequency 500 0.5 NOISE VOLTAGE (nV/√Hz) GAIN ERROR (%FSR) 1.0 0 –0.5 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 400 VCC = 5V CODE = MID-SCALE INTERNAL REF. 300 LTC2637-H 200 LTC2637-L 100 0 100 1k 10k 100k FREQUENCY (Hz) 2637 G31 2637 G32 0.1Hz to 10Hz Voltage Noise Gain Error vs Reference Input 1.0 VCC = 5V, VFS = 2.5V CODE = MID-SCALE INTERNAL REF. VCC = 5.5V 0.8 GAIN ERROR OF 8 CHANNELS 0.6 GAIN ERROR (%FSR) 1M 0.4 0.2 10µV/DIV 0 –0.2 –0.4 –0.6 –0.8 –1.0 1 1.5 2 2.5 3 3.5 4 4.5 REFERENCE VOLTAGE (V) 5 5.5 1s/DIV 2637 G35 2637 G34 Rev D For more information www.analog.com 15 LTC2637 PIN FUNCTIONS (DFN/MSOP) VCC (Pin 1/Pin 1): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V (LTC2637-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2637-H). Bypass to GND with a 0.1µF capacitor. VOUTA to VOUTH (Pins 2–5, 10–13/Pins 2–5, 12–15): DAC Analog Voltage Outputs. CAO (Pin 6/Pin 7): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (See Tables 1 and 2). SCL (Pin 7/Pin 8): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC. SDA (Pin 8/Pin 9): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This pin is high impedance while data is shifted in. Open drain N-channel output during acknowledgment. SDA requires a pull-up resistor or current source to VCC. REF (Pin 9/Pin 11): Reference Voltage Input or Output. When External Reference mode is selected, REF is an input (1V ≤ VREF ≤ VCC) where the voltage supplied sets the full-scale DAC output voltage. When Internal Reference is selected, the 10ppm/°C 1.25V (LTC2637-L) or 2.048V (LTC2637-H) internal reference (half full-scale) is available at the pin. This output may be bypassed to GND with up to 10µF, and must be buffered when driving external DC load current. GND (Pin 14/Pin 16): Ground. CA2 (Pin 6, MSOP only): Chip Address Bit 2. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (See Table 1). CA1 (Pin 10, MSOP only): Chip Address Bit 1. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (See Table 1). Exposed Pad (Pin 15, DFN Only): Ground. Must be soldered to PCB Ground. Rev D 16 For more information www.analog.com LTC2637 BLOCK DIAGRAM SWITCH INTERNAL REFERENCE REF VREF GND REGISTER REGISTER DAC A REGISTER VOUTA REGISTER VCC DAC H VREF REGISTER REGISTER REGISTER REGISTER DAC G REGISTER REGISTER REGISTER REGISTER DAC F REGISTER REGISTER REGISTER DAC B REGISTER VREF VOUTB DAC C VREF VOUTD DAC D DAC E (CA2) VOUTF VREF VOUTE POWER-ON RESET CAO (CA1) VOUTG VREF VREF VOUTC VOUTH DECODE I2C ADDRESS DECODE SCL SDA I2C INTERFACE ( ) MSOP PACKAGE ONLY 2637 BD Rev D For more information www.analog.com 17 LTC2637 TEST CIRCUITS Test Circuit 1 100Ω CAn VIH(CAn)/VIL(CAn) 2637 TC01 Test Circuit 2 VDD RINH/RINL/RINF CAn GND 2637 TC01b Rev D 18 For more information www.analog.com SCL START For more information www.analog.com A5 2 A6 1 3 A4 4 A3 5 A2 SLAVE ADDRESS 6 A1 tf 7 A0 SCL SDA tHD(STA) tHD(DAT) tr tHIGH tSU(DAT) tf tSU(STA) 8 W 9 ACK 1 C3 2 C2 3 C1 5 A3 6 A2 7 A1 8 A0 9 ACK 1 2 3 4 5 2ND DATA BYTE tHD(STA) 6 7 tSU(STO) tSP Figure 2. Typical LTC2637 Write Transaction 4 C0 1ST DATA BYTE Sr Figure 1. I2C Timing ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS S tLOW tr 8 P 9 ACK tBUF 1 S 2 2637 F01 3 4 5 X 3RD DATA BYTE 6 X 7 X 8 X 9 ACK 2637 F02 LTC2637 TIMING DIAGRAM Rev D 19 LTC2637 OPERATION The LTC2637 is a family of octal voltage output DACs in 14-lead DFN and 16-lead MSOP packages. Each DAC can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. Eighteen combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zero-scale, mid-scale in internal reference mode, or mid-scale in external reference mode), and fullscale voltage (2.5V or 4.096V) are available. The LTC2637 is controlled using a 2-wire I2C interface. Power-On Reset The LTC2637-HZ/LTC2637-LZ clear the output to zeroscale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2637 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mV above zeroscale during power on. In general, the glitch amplitude decreases as the power supply ramp time is increased. See Power-On Reset Glitch in the Typical Performance Characteristics section. Transfer Function The digital-to-analog transfer function is: ⎛ k ⎞ VOUT(IDEAL) = ⎜ N ⎟ VREF ⎝2 ⎠ where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is either 2.5V (LTC2637-LMI/LTC2637-LMX/LTC2637-LZ) or 4.096V (LTC2637-HMI/LTC2637-HMX/LTC2637-HZ) when in Internal Reference mode, and the voltage at REF when in External Reference mode. I2C Serial Interface The LTC2637 communicates with a host using the standard 2-wire I2C interface. The timing diagrams (Figures 1 and 2) show the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The LTC2637-HMI/LTC2637-HMX/LTC2637-LMI/ LTC2637‑LMX provide an alternative reset, setting the output to mid-scale when power is first applied. The LTC2637-LMI and LTC2637-HMI power up in internal reference mode, with the output set to a mid-scale voltage of 1.25V and 2.048V, respectively. The LTC2637LMX and LTC2637-HMX power-up in external reference mode, with the output set to mid-scale of the external reference. Default reference mode selection is described in the Reference Modes section. The LTC2637 is a receive-only (slave) device. The master can write to the LTC2637. The LTC2637 will not acknowledge (NAK) a read request from the master. Power Supply Sequencing When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. The voltage at REF (Pin 9, DFN; Pin 11, MSOP) must be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turnon and turn-off sequences, when the voltage at VCC is in transition. START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. Rev D 20 For more information www.analog.com LTC2637 OPERATION Acknowledge Table 1. Slave Address Map (MSOP Package) The Acknowledge (ACK) signal is used for handshaking between the master and the slave. An ACK (active LOW) generated by the slave lets the master know that the latest byte of information was properly received. The ACK related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the ACK clock pulse. The slave-receiver must pull down the SDA bus line during the ACK clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2637 responds to a write by a master in this manner but does not acknowledge a read operation; in that case, SDA is retained HIGH during the period of the ACK clock pulse. Chip Address The state of pins CA0, CA1 and CA2 (CA1 and CA2 are only available on the MSOP package) determines the slave address of the part. These pins can each be set to any one of three states: VCC, GND or float. This results in 27 (MSOP Package) or 3 (DFN Package) selectable addresses for the part. The slave address assignments are shown in Tables 1 and 2. In addition to the address selected by the address pins, the part also responds to a global address. This address allows a common write to all LTC2637 parts to be accomplished using one 3-byte write transaction on the I2C bus. The global address, listed at the end of Tables 1 and 2, is a 7-bit hardwired address not selectable by CA0, CA1 or CA2. If another global address is required, please consult the factory. The maximum capacitive load allowed on the address pins (CA0, CA1 and CA2) is 10pF, as these pins are driven during address detection to determine if they are floating. CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0 GND GND GND 0 0 1 0 0 0 0 GND GND FLOAT 0 0 1 0 0 0 1 GND GND VCC 0 0 1 0 0 1 0 GND FLOAT GND 0 0 1 0 0 1 1 GND FLOAT FLOAT 0 1 0 0 0 0 0 GND FLOAT VCC 0 1 0 0 0 0 1 GND VCC GND 0 1 0 0 0 1 0 GND VCC FLOAT 0 1 0 0 0 1 1 GND VCC VCC 0 1 1 0 0 0 0 FLOAT GND GND 0 1 1 0 0 0 1 FLOAT GND FLOAT 0 1 1 0 0 1 0 FLOAT GND VCC 0 1 1 0 0 1 1 FLOAT FLOAT GND 1 0 0 0 0 0 0 FLOAT FLOAT FLOAT 1 0 0 0 0 0 1 FLOAT FLOAT VCC 1 0 0 0 0 1 0 FLOAT VCC GND 1 0 0 0 0 1 1 FLOAT VCC FLOAT 1 0 1 0 0 0 0 FLOAT VCC VCC 1 0 1 0 0 0 1 VCC GND GND 1 0 1 0 0 1 0 VCC GND FLOAT 1 0 1 0 0 1 1 VCC GND VCC 1 1 0 0 0 0 0 VCC FLOAT GND 1 1 0 0 0 0 1 VCC FLOAT FLOAT 1 1 0 0 0 1 0 VCC FLOAT VCC 1 1 0 0 0 1 1 VCC VCC GND 1 1 1 0 0 0 0 VCC VCC FLOAT 1 1 1 0 0 0 1 VCC VCC VCC 1 1 1 0 0 1 0 1 1 1 0 0 1 1 GLOBAL ADDRESS Table 2. Slave Address Map (DFN Package) CA0 A6 A5 A4 A3 A2 A1 A0 GND 0 0 1 0 0 0 0 FLOAT 0 0 1 0 0 0 1 VCC 0 0 1 0 0 1 0 GLOBAL ADDRESS 1 1 1 0 0 1 1 Rev D For more information www.analog.com 21 LTC2637 OPERATION Write Word Protocol Table 3. Command Codes The master initiates communication with the LTC2637 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2637 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by CA0, CA1 or CA2) or the global address. The master then transmits three bytes of data. The LTC2637 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2637 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2637 does not acknowledge the extra bytes of data (SDA is high during the 9th clock). The format of the three data bytes is shown in Figure 3. The first byte of the input word consists of the 4-bit command, followed by the 4-bit DAC address. The next two bytes contain the 16-bit data word, which consists of the 12-, 10- or 8-bit input code, MSB to LSB, followed by 4, 6 or 8 don’t-care bits (LTC2637-12, LTC2637-10 and LTC2637-8, respectively). A typical LTC2637 write transaction is shown in Figure 4. The command bit assignments (C3-C0) and address (A3A0) assignments are shown in Tables 3 and 4. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register. In an update operation, the data word is copied from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 12-, 10-, or 8-bit input code, and is converted to an analog voltage at the DAC output. Write to and Update combines the first two commands. The Update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. COMMAND* C3 C2 C1 C0 0 0 0 0 Write to Input Register n 0 0 0 1 Update (Power Up) DAC Register n 0 0 1 0 Write to Input Register n, Update (Power Up) All 0 0 1 1 Write to and Update (Power Up) DAC Register n 0 1 0 0 Power Down n 0 1 0 1 Power Down Chip (All DAC’s and Reference) 0 1 1 0 Select Internal Reference (Power Up Reference) 0 1 1 1 Select External Reference (Power Down Internal Reference) 1 1 1 1 No Operation *Command codes not shown are reserved and should not be used. Table 4. Address Codes ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 0 1 0 0 DAC E 0 1 0 1 DAC F 0 1 1 0 DAC G 0 1 1 1 DAC H 1 1 1 1 All DACs *Address codes not shown are reserved and should not be used. Reference Modes For applications where an accurate external reference is either not available, or not desirable due to limited space, the LTC2637 has a user-selectable, integrated reference. The integrated reference voltage is internally amplified by 2x to provide the full-scale DAC output voltage range. Rev D 22 For more information www.analog.com LTC2637 OPERATION Write Word Protocol for LTC2637 S SLAVE ADDRESS W ACK 1ST DATA BYTE ACK 2ND DATA BYTE ACK 3RD DATA BYTE ACK INPUT WORD Input Word (LTC2637-12) C3 C2 C1 C0 A3 A2 P A1 A1 D11 D10 D9 1ST DATA BYTE D8 D7 D6 D5 D4 D3 D2 D1 2ND DATA BYTE D0 X X X X X X X X 3RD DATA BYTE Input Word (LTC2637-10) C3 C2 C1 C0 A3 A2 A1 A0 D9 D8 1ST DATA BYTE D7 D6 D5 D4 D3 D2 D1 D0 X 2ND DATA BYTE X X X 3RD DATA BYTE Input Word (LTC2637-8) C3 C2 C1 C0 A3 A2 1ST DATA BYTE A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X X X 2ND DATA BYTE X X X 3RD DATA BYTE 2637 F03 Figure 3. Command and Data Input Format The LTC2637-LMI/LTC2637-LMX/ LTC2637-LZ provides a full-scale output of 2.5V. The LTC2637-HMI/LTC2637HMX/LTC2637-HZ provides a full-scale output of 4.096V. The internal reference can be useful in applications where the supply voltage is poorly regulated. Internal Reference mode can be selected by using command 0110b, and is the power-on default for LTC2637-HZ/ LTC2637-LZ, as well as for LTC2637-HMI/LTC2637-LMI. The 10ppm/°C, 1.25V (LTC2637-LMI/LTC2637-LMX/ LTC2637-LZ) or 2.048V (LTC2637-HMI/LTC2637-HMX/ LTC2637-HZ) internal reference is available at the REF pin. Adding bypass capacitance to the REF pin will improve noise performance; and up to 10µF can be driven without oscillation. The REF output must be buffered when driving an external DC load current. Alternatively, the DAC can operate in External Reference mode using command 0111b. In this mode, an input voltage supplied externally to the REF pin provides the reference (1V ≤ VREF ≤ VCC) and the supply current is reduced. The external reference voltage supplied sets the full-scale DAC output voltage. External Reference mode is the power-on default for LTC2637-HMX/LTC2637-LMX. The reference mode of LTC2637-HZ/LTC2637-LZ/ LTC2637-HMI/LTC2637-LMI (internal reference poweron default), can be changed by software command after power up. The same is true for LTC2637-HMX/LTC2637LMX (external reference power-on default). Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight DAC outputs are needed. When in powerdown, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 200kΩ resistors. Input and DAC register contents are not disturbed during power down. Any DAC channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The supply current is reduced approximately 10% for each DAC powered down. The integrated reference is automatically powered down when external reference is selected using Rev D For more information www.analog.com 23 LTC2637 OPERATION command 0111b. In addition, all the DAC channels and the integrated reference together can be put into powerdown mode using Power Down Chip command 0101b. When the integrated reference and all DAC channels are in power-down mode, the REF pin becomes high impedance (typically > 1GΩ). For all power-down commands the 16-bit data word is ignored. Normal operation resumes after executing any command that includes a DAC update, (as shown in Table 1). The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than eight DACs are in a powered-down state prior to the update command, the power-up delay time is 10µs. However, if all eight DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the DAC amplifiers and reference buffers. In this case, the power up delay time is 12µs. The power-up of the integrated reference depends on the command that powered it down. If the reference is powered down using the Select External Reference Command (0111b), then it can only be powered back up using Select Internal Reference Command (0110b). However, if the reference was powered down using Power Down Chip Command (0101b), then in addition to Select Internal Reference Command (0110b), any command that powers up the DACs will also power up the integrated reference. Voltage Output The LTC2637’s DAC output integrated rail-to-rail amplifiers have guaranteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to ohms. The amplifier’s DC output impedance is 0.1Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is 50Ω • 1mA, or 50mV). See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 500pF. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the DAC cannot go below ground, it may limit for the lowest codes as shown in Figure 5b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 5c. No full-scale limiting can occur if VREF is less than VCC–FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Board Layout The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents Rev D 24 For more information www.analog.com LTC2637 OPERATION and the analog section of the ground plane. The resistance from the LTC2637 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1Ω). Note that the LTC2637 is no more susceptible to this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When the LTC2637 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. It is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. Another technique for minimizing errors is to use a separate power ground return trace on another board layer. The trace should run between the point where the power SLAVE ADDRESS COMMAND/ADDRESS A6 A5 A4 A3 A2 A1 A0 SDA A6 A5 A4 A3 A2 A1 A0 SCL 1 2 3 4 5 6 7 START VOUT W 8 MS DATA C3 C2 C1 C0 A3 A2 A1 A0 ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK 2 3 4 5 6 7 8 9 1 D11 D10 D9 9 D8 D7 LS DATA D6 D5 D4 D3 D2 D1 D0 X X X X ACK 1 2 3 4 5 6 7 8 9 STOP ACK 1 2 3 4 5 6 7 8 9 FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE X = DON’T CARE 2637 F04 Figure 4. Typical LTC2637 Input Waveform—Programming DAC Output for Full-Scale VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0V NEGATIVE OFFSET 0V 0 2,048 INPUT CODE (a) 2637 F04 4,095 INPUT CODE (b) Figure 5. Effects of Rail-to-Rail Operation On a DAC Transfer Curve (Shown for 12 Bits). (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale Rev D For more information www.analog.com 25 LTC2637 TYPICAL APPLICATION LTC2637 DACs Adjust LTC2755-16 Offsets, Amplified with LT1991 PGA to ±5V 5V 15 15V 0.1µF 0.1µF 8 7 + 5 VDD LTC2755 IOUT1A 59 63 RCOM1 DAC A 1/2 LT1469 4 – IOUT2A 2 6 0.1µF 2 3 – 8 1/2 LT1469 + 15V 1 OUTA 4 2 3 + – 30k –15V + – LT1634-1.25 – + DAC C DAC B 30k 0.1µF LTC2637MS-LMI12 DAC A DAC H DAC B DAC G 15 OUTB GND 8 M9 9 M3 10 M1 1 P1 2 P3 3 P9 7 VCC LT1991 0.1µF OUT 6 VOUT = ±5V REF VEE 5 4 14 0.1µF –15V 4 DAC C DAC F DAC D DAC E 13 –15V 5 30k –15V 1 LT1634-1.25 30k OUTC VCC LT1634-1.25 LT1634-1.25 –15V REF 0.1µF –15V DAC D 5V 11 0.1µF RVOSA 58 62 REFA + – 0.1µF –15V OUTD LTC6240 15V RFBA 60 61 ROFSA 64 RIN1 12 19 I2C BUS 9 SDA 8 SCL 7 CA0 10 CA1 CA2 6 16 GND 2637 TA02 Rev D 26 For more information www.analog.com LTC2637 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC2637#packaging for the most recent package drawings. DE Package 14-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1708 Rev B) 0.70 ±0.05 3.30 ±0.05 3.60 ±0.05 2.20 ±0.05 1.70 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 (2 SIDES) R = 0.115 TYP 8 R = 0.05 TYP 0.40 ±0.10 14 3.30 ±0.10 3.00 ±0.10 (2 SIDES) 1.70 ±0.10 PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF (DE14) DFN 0806 REV B 7 0.75 ±0.05 1 0.25 ±0.05 0.50 BSC 3.00 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev D For more information www.analog.com 27 LTC2637 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC2637#packaging for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev A) 0.889 ±0.127 (.035 ±.005) 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 4.039 ±0.102 (.159 ±.004) (NOTE 3) 0.50 (.0197) BSC 0.305 ±0.038 (.0120 ±.0015) TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL “A” 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) 0° – 6° TYP 0.280 ±0.076 (.011 ±.003) REF 16151413121110 9 GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 0.18 (.007) SEATING PLANE 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 1234567 8 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 0.1016 ±0.0508 (.004 ±.002) MSOP (MS16) 0213 REV A Rev D 28 For more information www.analog.com LTC2637 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 10/09 Update LTC2637-12 Maximum Limits. B 06/10 Added details to Note 3. 10 Revised Typical Application circuit. 25 5, 6, 8 Added Typical Application drawing and revised Related Parts. 28 C 06/17 Updated Note 3. 10 D 04/18 Edits to Note 3. 10 Rev D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 29 LTC2637 TYPICAL APPLICATION LTC2637 DACs Adjust LTC2755-16 Offsets, Amplified with LT®1991 PGA to ±5V 5V 15 15V 0.1µF 0.1µF 8 7 + 5 VDD LTC2755 IOUT1A 59 63 RCOM1 DAC A 1/2 LT1469 4 – IOUT2A 2 6 0.1µF 2 3 – 8 1/2 LT1469 + 15V 1 OUTA 5V 4 11 0.1µF RVOSA 58 62 REFA + – 0.1µF DAC D 2 3 + – 30k –15V – + DAC C DAC B + – LT1634-1.25 1 0.1µF LTC2637MS-LMI12 DAC A DAC H DAC B DAC G 15 30k OUTB GND 1 P1 2 P3 3 P9 0.1µF 7 VCC LT1991 OUT 6 VOUT = ±5V REF VEE 5 4 0.1µF –15V 4 DAC C DAC F DAC D DAC E 13 –15V 5 30k 8 M9 9 M3 10 M1 14 LT1634-1.25 30k OUTC VCC LT1634-1.25 LT1634-1.25 –15V REF 0.1µF –15V –15V OUTD LTC6240 15V RFBA 60 61 ROFSA 64 RIN1 19 I2C BUS –15V 9 SDA 8 SCL 12 7 CA0 10 CA1 CA2 6 16 GND 2637 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2636 Octal 12-/10-/8-Bit, SPI VOUT DACs with 10ppm/°C Reference 125μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, 14-Lead 4mm × 3mm DFN and 16-Lead MSOP Packages LTC1660/LTC1665 Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output LTC2605/LTC2615/ Octal 16-/14-/12-Bit VOUT DACs with I2C Interface LTC2625 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface LTC2600/LTC2610/ Octal 16-/14-/12-Bit VOUT DACs in 16-Lead Narrow SSOP LTC2620 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2656/LTC2657 Octal 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/°C Max Reference ±4LSB INL max at 16-Bits and ±2mV Offset Error, Rail-to-Rail Output, 20-Lead 4mm × 5mm QFN and 16-Lead TSSOP Packages LTC2654/LTC2655 Quad 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/°C Max Reference ±4LSB INL max at 16-Bits and ±2mV Offset Error, Rail-to-Rail Output, 20-Lead 4mm × 4mm QFN and 16-Lead Narrow SSOP Packages LTC2634/LTC2635 Quad 12-/10-/8-Bit SPI/I2C VOUT DACs with 10ppm/°C Reference ±2.5 LSB INL, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, 16-Pin 3mm × 3mm QFN and 10-Lead MSOP Packages LTC2630/LTC2632 Single 12-/10-/8-Bit, SPI/ I2C VOUT DACs with 10ppm/°C Reference 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output, in SC70 (LTC2630)/ ThinSOT™ (LTC2631) LTC2640 Single 12-/10-/8-Bit, SPI VOUT DACs with 10ppm/°C Reference 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, in ThinSOT LT1991 Precision, 100µA Gain Selectable Amplifier Gain Accuracy of 0.04%, Gains from –13 to 14, 100μA Precision Op-Amp LT1469 Dual 90MHz, 22V/µs 16-Bit Accurate Operational Amplifier 90MHz Gain Bandwidth, 125µV offset, 900ns , 22V/µs Slew Rate Precision Op-Amp Amplifiers Rev D 30 D16869-0-5/18(D) For more information www.analog.com www.analog.com  ANALOG DEVICES, INC. 2009-2018