LTC2645
Quad 12-/10-/8-Bit PWM to VOUT
DACs with 10ppm/°C Reference
FEATURES
DESCRIPTION
No Latency PWM-to-Voltage Conversion
nn Voltage Output Updates and Settles within 8µs
nn 100kHz to 30Hz PWM Input Frequency
nn ±2.5LSB Max INL; ±1LSB Max DNL (LTC2645-12)
nn Guaranteed Monotonic
nn Pin-Selectable Internal or External Reference
nn 2.7V to 5.5V Supply Range
nn 1.71V to 5.5V Input Voltage Range
nn Low Power: 4mA at 3V, 1GΩ).
Normal operating current resumes when PD returns high
for transparent operation (IDLSEL = GND). For sample/
hold operation (IDLSEL = VCC), the LTC2645 remains
in full power-down until the first rising edge is received
on any PWM input. Any pair of PWM input rising edges
separated by less than the idle mode timeout delay t3
(50ms minimum) will cause the DAC code to be updated.
The DAC output(s) will remain in Hi-Z until the channel
is updated following the second rising PWM input edge.
Voltage Output
The LTC2645’s integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change
in units from LSB/mA to Ω. The amplifier’s DC output
impedance is 0.1Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage
is 50Ω • 1mA, or 50mV). See the graph Headroom at
Rails vs Output Current in the Typical Performance
Characteristics section.
The amplifier is stable driving capacitive loads of up
to 500pF.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited to voltages within the supply range.
Since the analog output of the DAC cannot go below
ground, it may limit the lowest codes reachable as shown
in Figure 2b. Similarly, limiting can occur near full-scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC, as shown in Figure 2c. No full-scale
limiting will occur if VREF is less than VCC–FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.
Board Layout
The PC board should have separate areas for the analog
and digital sections of the circuit. A single, solid ground
plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps
digital signals away from sensitive analog signals and
minimizes the interaction between digital ground currents
and the analog section of the ground plane. The resistance
from the LTC2645 GND pin to the ground plane should
be as low as possible. Resistance here will add directly to
the effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2645 is no more susceptible to
this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements
to shine rather than limiting attainable performance with
excessive internal resistance.
Rev. B
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15
LTC2645
OPERATION
Another technique for minimizing errors is to use a separate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2645 is sinking large currents, this current flows
out of the ground pin and directly into the power ground
trace without affecting the analog ground plane voltage.
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
VREF = VCC
POSITIVE
FSE
VREF = VCC
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
2645 F02
(c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
0V
0
2048
INPUT CODE
(a) Overall Transfer Function
4095
INPUT CODE
(b) Effect of Negative Offset for Codes Near Zero
Figure 2. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12 Bits)
16
Rev. B
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LTC2645
TYPICAL APPLICATIONS
2.7V TO 5.5V
C3
0.1µF
EXT INPUT: 1V TO VCC
C4
0.1µF
5V
C2
0.1µF
IOVCC
ISOLATION BARRIER
ANALOG PWM
DUTY CYCLE
CONTROL
(0V TO 1V)
PS9851-1
LTC6992
MOD
OUT
GND
V+
SET
DIV
RSET
50k
REF
LTC2645 -12
INA
PWM TO
BINARY
DAC A
INB
PWM TO
BINARY
DAC B
INC
PWM TO
BINARY
DAC C
IND
PWM TO
BINARY
DAC D
2.25V TO 5.5V
C1
0.1µF
VCC IDLSEL REFSEL
PD
VOUTA
VOUTB
VOUTC
VOUTD
DAC CONTROL
VOLTAGE OUTPUT
(0V TO VREF)
VOUTB = Hi-Z
VOUTC = Hi-Z
VOUTD = Hi-Z
GND
2645 F03
Figure 3. Analog Control Voltage with PWM Transmission to DAC Control Voltage Output
Rev. B
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17
LTC2645
PACKAGE DESCRIPTION
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev A)
0.889 ±0.127
(.035 ±.005)
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.50
(.0197)
BSC
0.305 ±0.038
(.0120 ±.0015)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
DETAIL “A”
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
0° – 6° TYP
0.280 ±0.076
(.011 ±.003)
REF
16151413121110 9
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
0.18
(.007)
SEATING
PLANE
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
1234567 8
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
18
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS16) 0213 REV A
Rev. B
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LTC2645
REVISION HISTORY
REV
DATE
DESCRIPTION
A
02/17
Corrected VOUT(IDEAL) equation
PAGE NUMBER
13
B
11/18
Corrected Units of Output Voltage Noise
5
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
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19
LTC2645
TYPICAL APPLICATION
5V
C3
0.1µF
C4
0.1µF
0.1µF
4.7µF
2.2k
IOVCC
PD
INA
VCC IDLSEL REFSEL
REF
0.1µF
LTC2645 -12
PWM TO
BINARY
DAC A
VOUTA
10k
INC
IND
PWM TO
BINARY
DAC B
PWM TO
BINARY
DAC C
PWM TO
BINARY
DAC D
VOUTB
PGOOD INTVCC
LTC3850EUF
RJK0305DPB
TG1
BOOST1
FREQ
0.1µF
2.2µH
0.008k
VOUT
3.3V ±10%
SW1
VOUTB = Hi-Z
RJK0301DPB
BG1
3.32k
PGND
VOUTC = Hi-Z
VOUTD = Hi-Z
1nF
500kHz
100pF
10k
GND
10k
SENSE1+
ITH1
VOUTD
CMDSH-3
100k
10k
1nF
VOUTC
VIN
ILM
143k
0.1µF
INB
VIN
6.5V
TO 14V
MODE/PLLIN
RUN1
1nF
SENSE1–
TKSS1
10nF
10k
VFB1
SGND
63.4k
15pF
2645 F04
FOR NO MARGINING, KEEP INA LOW. (VOUTA = Hi-Z)
TO MARGIN 10% HIGH, SET INA DUTY CYCLE TO 1/4096. (VOUTA = 0V)
TO MARGIN 10% LOW, SET INA DUTY CYCLE TO 2621/4096. (VOUTA = 1.6V)
20k
Figure 4. Voltage Margining Application with LTC3850 (3.3V ±10%)
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC2644
Dual 12-/10-/8-Bit PWM to VOUT DACs with
10ppm°/C Reference
Zero Latency Bus Update, 100kHz to 30Hz Input Frequency, ±2.5LSB INL, 2.7V to
5.5V Supply Range, 12-Lead MSOP Package
LT®1991
Precision, 100µA Gain Selectable Amplifier
Gain Accuracy of 0.04%, Gains from –13 to 14, 100µA Precision Op Amp
LT1469-2
Dual 200MHz, 30V/µs 16-Bit Accurate Op Amp 200MHz Gain Bandwidth, 125µV Offset, 30V/µs Slew Rate Precision Op Amp
LTC2055
Dual Micropower Zero-Drift Op Amp
2.7V Minimum Supply Voltage, 150µA Supply Current per Amplifier, Zero-Drift
Op Amp
LTC6992
Timer Blox: Voltage-Controlled Pulse Width
Modulator (PWM)
3.8Hz to 1MHz Output Frequency Range, 0V to 1V Analog Input, < 1.7% Maximum
Frequency Error
LTC2634/LTC2635 Quad 12-/10-/8-Bit SPI/I2C VOUT DACs with
10ppm/°C Reference
20
±2.5LSB INL, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,
16-Pin 3mm × 3mm QFN and 10-Lead MSOP Packages
Rev. B
11/18
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For more information www.analog.com
ANALOG DEVICES, INC. 2014-2018
