LTC2751
Current Output
12-/14-/16-Bit SoftSpan
DACs with Parallel I/O
Features
Description
Six Programmable Output Ranges
Unipolar: 0V to 5V, 0V to 10V
Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V
n Maximum 16-Bit INL Error: ±1 LSB over Temperature
n Low 1µA (Maximum) Supply Current
n Guaranteed Monotonic over Temperature
n Low Glitch Impulse 1nV • s
n 2.7V to 5.5V Single Supply Operation
n 2µs Settling Time to ±1 LSB
n Reference Input: ±15V
n Parallel Interface with Readback of All Registers
n Asynchronous CLR Pin Clears DAC Output to 0V in
Any Output Range
n Power-On Reset to 0V
n 38-Pin 5mm × 7mm QFN Package
The LTC®2751 is a family of 12-, 14-, and 16-bit multiplying parallel-input, current-output DACs. They operate
from a single 2.7V to 5.5V supply. All parts are guaranteed
monotonic over temperature. The LTC2751A-16 provides
16-bit performance (±1LSB INL and DNL) over temperature
without any adjustments. These SoftSpan™ DACs offer six
output ranges—two unipolar and four bipolar—that can be
programmed through the parallel interface, or pinstrapped
for operation in a single range.
n
Applications
n
n
n
n
These parts use a bidirectional input/output parallel interface that allows readback of any on-chip register. A
power-on circuit resets the DAC output to 0V when power is
initially applied. A logic low on the CLR pin asynchronously
clears the DAC to 0V in any output range.
The parts are specified over commercial and industrial
temperature ranges.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
High Resolution Offset and Gain Adjustment
Process Control and Industrial Automation
Automatic Test Equipment
Data Acquisition Systems
Typical Application
16-Bit DAC with Software Selectable Ranges
REF
5V
LTC2751-16 Integral Nonlinearity
1.0
VDD = 5V
0.8 VREF = 5V
±10V RANGE
0.6
+
1/2 LT®1469
C2
150pF
RIN
R1
RCOM
0.4
REF ROFS RFB
R2
LTC2751-16
WR
C1
15pF
IOUT1
WR
UPD
UPD
READ
READ
D/S
D/S
CLR
CLR
16-BIT DAC WITH SPAN SELECT
INL (LSB)
–
IOUT2
3
16
RVOS
SPAN I/O
S2-S0
DATA I/O
D15-D0
VDD
–0.6
VOUT
1/2 LT1469
+
C3
0.1µF
0.0
–0.2
–0.4
–
25°C
90°C
–45°C
–0.8
–1.0
GND
MSPAN
0.2
0
16384
32768
CODE
49152
65535
2751 TA01b
5V
2751 TA01
2751fa
1
LTC2751
Absolute Maximum Ratings
(Notes 1, 2)
Operating Temperature Range
LTC2751C...................................................... 0°C to 70°C
LTC2751I...................................................–40°C to 85°C
Maximum Junction Temperature........................... 125°C
Storage Temperature Range................... –65°C to 150°C
IOUT1, IOUT2, RCOM to GND......................................±0.3V
RFB, ROFS, RIN, REF, RVOS to GND............................ ±15V
VDD to GND................................................... –0.3V to 7V
S2, S1, S0, D15-D0, MSPAN, READ, D/S,WR,
UPD, CLR to GND......... –0.3V to VDD + 0.3V (7V Max)
Pin Configuration
RCOM 1
RCOM 1
S0
S1
RVOS
IOUT1
38 37 36 35 34 33 32
38 37 36 35 34 33 32
31 WR
ROFS
REF
S0
S1
RVOS
IOUT1
RFB
ROFS
REF
S0
38 37 36 35 34 33 32
RFB
TOP VIEW
TOP VIEW
S1
RVOS
IOUT1
RFB
ROFS
REF
TOP VIEW
RCOM 1
31 WR
31 WR
RIN 2
30 UPD
RIN 2
30 UPD
RIN 2
30 UPD
S2 3
29 READ
S2 3
29 READ
S2 3
29 READ
IOUT2 4
28 D/S
IOUT2 4
28 D/S
IOUT2 4
NC 5
27 NC
NC 5
27 NC
NC 5
D11 6
26 NC
D13 6
26 NC
D15 6
25 NC
D12 7
25 NC
D14 7
D9 8
24 NC
D11 8
24 NC
D13 8
24 D1
D8 9
23 NC
D10 9
23 D0
D12 9
23 D2
22 D3
21 D4
D7 10
22 NC
D9 10
22 D1
D11 10
D6 11
21 D0
D8 11
21 D2
D10 11
D5 12
20 D1
D7 12
20 D3
D9 12
25 D0
20 D5
D6
MSPAN
CLR
GND
D8
D4
MSPAN
CLR
GND
VDD
D5
D6
26 NC
13 14 15 16 17 18 19
13 14 15 16 17 18 19
D2
MSPAN
CLR
GND
VDD
D3
D4
13 14 15 16 17 18 19
VDD
39
27 NC
39
D7
39
D10 7
28 D/S
LTC2751-12 UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
LTC2751-14 UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
LTC2751-16 UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2751CUHF-12#PBF
LTC2751CUHF-12#TRPBF
275112
38-Lead (5mm × 7mm) Plastic QFN
0°C to 70°C
LTC2751IUHF-12#PBF
LTC2751IUHF-12#TRPBF
275112
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 85°C
LTC2751CUHF-14#PBF
LTC2751CUHF-14#TRPBF
275114
38-Lead (5mm × 7mm) Plastic QFN
0°C to 70°C
LTC2751IUHF-14#PBF
LTC2751IUHF-14#TRPBF
275114
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 85°C
LTC2751BCUHF-16#PBF
LTC2751BCUHF-16#TRPBF
275116
38-Lead (5mm × 7mm) Plastic QFN
0°C to 70°C
LTC2751BIUHF-16#PBF
LTC2751BIUHF-16#TRPBF
275116
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 85°C
LTC2751ACUHF-16#PBF
LTC2751ACUHF-16#TRPBF
275116
38-Lead (5mm × 7mm) Plastic QFN
0°C to 70°C
LTC2751AIUHF-16#PBF
LTC2751AIUHF-16#TRPBF
275116
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2751fa
2
LTC2751
Electrical
Characteristics
VDD = 5V, VREF = 5V unless otherwise specified. The l denotes the
specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC2751-12
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
LTC2751-14
MIN
TYP
LTC2751B-16
MAX
MIN
TYP
MAX
LTC2751A-16
MIN
TYP
MAX
UNITS
Static Performance
Resolution
l
12
12
14
16
14
16
16
Bits
16
Bits
Monotonicity
l
DNL
Differential
Nonlinearity
l
±1
±1
±1
±0.2
±1
LSB
INL
Integral
Nonlinearity
l
±1
±1
±2
±0.4
±1
LSB
GE
Gain Error
All Output
Ranges
±5
±20
±4
±14
LSB
GETC
Gain Error Temperature Coefficient
DGain/DTemp
BZE
Bipolar Zero Error
All Bipolar
Ranges
BZSTC
Bipolar Zero Temperature Coefficient
PSR
Power Supply
Rejection
VDD = 5V, ±10%
VDD = 3V, ±10%
l
l
ILKG
IOUT1 Leakage
Current
TA = 25°C
TMIN to TMAX
l
Output
Capacitance
Full-Scale
Zero Scale
CIOUT1
l
±0.5
±2
±0.6
l
±0.2
±1.5
±0.6
±1
±0.5
±0.6
±3
±0.5
±0.025
±0.06
±0.05
±0.6
±2
±5
±12
75
45
±2
±5
75
45
±8
±0.5
±0.4
±1
±0.05
ppm/°C
±2
±0.5
±0.1
±0.25
±0.05
±0.6
ppm/°C
±0.03 ±0.2
±0.1 ±0.5
±2
±5
±0.05
75
45
LSB
LSB/V
±2
±5
nA
75
45
pF
pF
VDD = 5V, VREF = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
R1/R2
Reference Inverting Resistors
(Note 4)
RREF
DAC Input Resistance
RFB
Feedback Resistor
ROFS
Bipolar Offset Resistor
RVOS
Offset Adjust Resistor
MAX
UNITS
l
16
20
kW
l
8
10
kW
(Note 3)
l
8
10
kW
(Note 3)
l
16
20
kW
l
800
1000
kW
Resistances (Note 3)
Dynamic Performance
THD
Output Settling Time
0V to 10V Range, 10V Step. To ±0.0015% FS
(Note 5)
2
μs
Glitch Impulse
(Note 6)
1
nV•s
Digital-to-Analog Glitch Impulse
(Note 7)
1
nV•s
Multiplying Feedthrough Error
0V to 10V Range, VREF = ±10V, 10kHz
Sine Wave
Total Harmonic Distortion
(Note 8) Multiplying
Output Noise Voltage Density
(Note 9) at IOUT1
0.5
mV
–110
dB
13
nV/√Hz
Power Supply
VDD
Supply Voltage
IDD
Supply Current, VDD
l
Digital Inputs = 0V or VDD
l
2.7
0.5
5.5
V
1
μA
2751fa
3
LTC2751
Electrical
Characteristics
VDD = 5V, VREF = 5V unless otherwise specified. The l denotes the
specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
Digital Input High Voltage
3.3V ≤ VDD ≤ 5.5V
2.7V ≤ VDD < 3.3V
l
l
VIL
Digital Input Low Voltage
4.5V < VDD ≤ 5.5V
2.7V ≤ VDD ≤ 4.5V
l
l
0.8
0.6
V
V
IIN
Digital Input Current
VIN = GND to VDD
l
±1
µA
CIN
Digital Input Capacitance
VIN = 0V (Note 10)
l
6
pF
Digital Inputs
2.4
2
V
V
Digital Outputs
VOH
IOH = 200µA
l
VOL
IOL = 200µA
l
VDD – 0.4
V
0.4
V
Timing
Characteristics
VDD = 5V, VREF = 5V unless otherwise specified. The l denotes specifications that
apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD = 4.5V to 5.5V
Write and Update Timing
t1
I/O Valid to WR Rising Edge Set-Up
l
9
ns
t2
I/O Valid to WR Rising Edge Hold
l
9
ns
t3
WR Pulse Width
l
20
ns
t4
UPD Pulse Width
l
20
ns
t5
UPD Falling Edge to WR Falling Edge
No Data Shoot-Through
l
0
ns
t6
WR Rising Edge to UPD Rising Edge
(Note 10)
l
0
ns
t7
D/S Valid to WR Falling Edge Set-Up Time
l
9
ns
t8
WR Rising Edge to D/S Valid Hold Time
l
9
ns
l
9
ns
20
ns
Readback Timing
t13
WR Rising Edge to READ Rising Edge
t14
READ Falling Edge to WR Falling Edge
(Note 10)
l
t15
READ Rising Edge to I/O Propagation Delay
CL = 10pF
l
30
ns
t17
UPD Valid to I/O Propagation Delay
CL = 10pF
l
30
ns
t18
D/S Valid to READ Rising Edge
(Note 10)
l
9
ns
t19
READ Rising Edge to UPD Rising Edge
No Update
l
9
ns
t20
UPD Falling Edge to READ Falling Edge
No Update
l
9
ns
t22
READ Falling Edge to UPD Rising Edge
(Note 10)
l
9
ns
t23
I/O Bus Hi-Z to READ Rising Edge
(Note 10)
l
0
ns
t24
READ Falling Edge to I/O Bus Active
(Note 10)
l
20
ns
l
20
ns
CLR Timing
t25
CLR Pulse Width Low
2751fa
4
LTC2751
timing
Characteristics
VDD = 5V, VREF = 5V unless otherwise specified. The l denotes specifications that
apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD = 2.7V to 3.3V
Write and Update Timing
t1
I/O Valid to WR Rising Edge Set-Up
l
18
ns
t2
I/O Valid to WR Rising Edge Hold
l
18
ns
t3
WR Pulse Width
l
30
ns
t4
UPD Pulse Width
l
30
ns
t5
UPD Falling Edge to WR Falling Edge
No Data Shoot-Through
l
0
ns
t6
WR Rising Edge to UPD Rising Edge
(Note 10)
l
0
ns
t7
D/S Valid to WR Falling Edge Set-Up Time
l
18
ns
t8
WR Rising Edge to D/S Valid Hold Time
l
18
ns
l
18
ns
40
ns
Readback Timing
t13
WR Rising Edge to Read Rising Edge
t14
Read Falling Edge to WR Falling Edge
(Note 10)
l
t15
Read Rising Edge to I/O Propagation Delay
CL = 10pF
l
t17
UPD Valid to I/O Propagation Delay
CL = 10pF
l
t18
D/S Valid to Read Rising Edge
(Note 10)
l
18
ns
t19
Read Rising Edge to UPD Rising Edge
No Update
l
9
ns
t20
UPD Falling Edge to Read Falling Edge
No Update
l
9
ns
t22
READ Falling Edge to UPD Rising Edge
(Note 10)
l
18
ns
t23
I/O Bus Hi-Z to Read Rising Edge
(Note 10)
l
0
ns
t24
Read Falling Edge to I/O Bus Active
(Note 10)
l
40
ns
l
30
ns
40
40
ns
ns
CLR Timing
t25
CLR Pulse Width Low
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Because of the proprietary SoftSpan switching architecture, the
measured resistance looking into each of the specified pins is constant for
all output ranges if the IOUT1 and IOUT2 pins are held at ground.
Note 4: R1 is measured from RIN to RCOM ; R2 is measured from REF to
RCOM .
Note 5: Using LT1469 with CFEEDBACK = 15pF. A ±0.0015% settling time
of 1.7μs can be achieved by optimizing the time constant on an individual
basis. See Application Note 74, “Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.”
Note 6: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1469; CFB = 27pF.
Note 7. Full-scale transition; REF = 0V.
Note 8. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifier = LT1469.
Note 9. Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (W), T = temperature (°K), and B =
bandwidth (Hz).
Note 10. Guaranteed by design. Not production tested.
2751fa
5
LTC2751
Typical Performance Characteristics
TA = 25°C, unless otherwise noted.
LTC2751-16
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
1.0
VDD = 5V
0.8 VREF = 5V
±10V RANGE
0.6
0.4
0.4
0.2
0.2
DNL (LSB)
INL (LSB)
VDD = 5V
0.8 VREF = 5V
±10V RANGE
0.6
0.0
–0.2
0.0
–0.2
–0.4
–0.4
–0.6
–0.6
– 0.8
–0.8
–1.0
0
16384
32768
CODE
–1.0
65535
49152
16384
0
32768
CODE
2751 G01
INL vs Temperature
0.2
0.0
–0.4
–0.6
–0.6
– 0.8
–0.8
80
–DNL
–1.0
–40
Gain Error vs Temperature
–20
20
40
0
60
TEMPERATURE (°C)
INL (LSB)
GE (LSB)
0
–4
–8
–12
80
2751 G07
20
40
0
60
TEMPERATURE (°C)
1.0
0.6
0.6
0.2
0.0
–0.2
VDD = 5V
0.8 ±5V RANGE
0.4
+INL
+INL
–INL
–INL
0.2
0.0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
–10 –8 –6
80
DNL vs VREF
1.0
0.4
0.6ppm/°C (TYP)
–20
2751 G06
VDD = 5V
0.8 ±5V RANGE
8
20
40
0
60
TEMPERATURE (°C)
8
–40
80
INL vs VREF
VDD = 5V
12 VREF = 5V
±10V RANGE
–20
2
2751 G05
16
–16
–40
0
6
2751 G04
4
0.5ppm/°C (TYP)
2
4
INL (LSB)
20
40
0
60
TEMPERATURE (°C)
+DNL
–0.2
–0.4
–20
4
BZE (LSB)
–INL
–1.0
–40
VDD = 5V
6 VREF = 5V
±10V RANGE
0.4
DNL (LSB)
INL (LSB)
0.0
–0.2
8
VDD = 5V
0.8 VREF = 5V
±10V RANGE
0.6
+INL
0.2
Bipolar Zero vs Temperature
1.0
VDD = 5V
0.8 VREF = 5V
±10V RANGE
0.6
0.4
2751 G02
DNL vs Temperature
1.0
65535
49152
4
2 0 2
VREF (V)
4
6
8
10
2751 G08
+DNL
+DNL
–DNL
–DNL
–1.0
–10 –8 –6
4
2 0 2
VREF (V)
4
6
8
10
2751 G09
2751fa
6
LTC2751
Typical Performance Characteristics
TA = 25°C, unless otherwise noted.
LTC2751-16
INL vs VDD
Settling 0V to 10V
1.0
0.8
UPD
5V/DIV
0.6
INL (LSB)
0.4
+INL
0.2
0.0
GATED
SETTLING
WAVEFORM
250µV/DIV
–INL
–0.2
–0.4
–0.6
–1.0
2.5
3
3.5
4
4.5
VDD (V)
5
2751 G10
500ns/DIV
USING LT1469 AMP
CFEEDBACK = 12pF
0V TO 10V STEP
– 0.8
5.5
2751 G09b
LTC2751-14
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
1.0
VDD = 5V
0.8 VREF = 5V
±10V RANGE
0.6
0.4
0.4
0.2
0.2
DNL (LSB)
INL (LSB)
VDD = 5V
0.8 VREF = 5V
±10V RANGE
0.6
0.0
–0.2
0.0
–0.2
–0.4
–0.4
–0.6
–0.6
– 0.8
–0.8
–1.0
0
4096
8192
CODE
12288
–1.0
16383
0
4096
8192
CODE
16383
12288
2751 G11
2751 G12
LTC2751-12
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
1.0
VDD = 5V
0.8 VREF = 5V
±10V RANGE
0.6
0.4
0.4
0.2
0.2
DNL (LSB)
INL (LSB)
VDD = 5V
0.8 VREF = 5V
±10V RANGE
0.6
0.0
–0.2
0.0
–0.2
–0.4
–0.4
–0.6
–0.6
– 0.8
–0.8
–1.0
0
1024
2048
CODE
3072
4095
2751 G13
–1.0
0
1024
2048
CODE
3072
4095
2751 G14
2751fa
7
LTC2751
Typical Performance Characteristics
LTC2751-12, LTC2751-14, LTC2751-16
TA = 25°C, unless otherwise noted.
Supply Current vs
Logic Input Voltage
Midscale Glitch
12
10
UPD
5V/DIV
8
IDD (mA)
1nV•s (TYP)
VOUT
2mV/DIV
VDD = 5V
6
4
2
2751 G15
500ns/DIV
USING AN LT1469
VDD = 5V
CFEEDBACK = 27pF
VREF = 5V
0V TO 5V RANGE
0
VDD = 3V
0
1
2
3
LOGIC VOLTAGE (V)
4
ALL DIGITAL PINS TIED TOGETHER
(EXCEPT READ TIED TO GND)
Logic Threshold
vs Supply Voltage
5
2751 G16
Supply Current
vs Update Frequency
1000
2
1.5
SUPPLY CURRENT (µA)
LOGIC THRESHOLD (V)
1.75
RISING
1.25
FALLING
1
100
10
1
VDD = 5V
0.75
0.5
2.5
3
3.5
4
4.5
VDD (V)
5
5.5
2751 G17
0.1
VDD = 3V
10
100
10k
100k
1k
UPD FREQUENCY (Hz)
1M
2751 G18
ALTERNATING ZERO-SCALE/FULL-SCALE
(LTC2751-16)
2751fa
8
LTC2751
Pin Functions
RCOM (Pin 1): Center Tap Point of RIN and REF. Normally
tied to the negative input of the external reference inverting amplifier.
RIN (Pin 2): Input Resistor for External Reference Inverting
Amplifier. Normally tied to the external reference voltage
VREF and to ROFS (Pin 37). Typically 5V; accepts up to ±15V.
S2 (Pin 3): Span I/O Bit 2. Pins S0, S1 and S2 are used
to program and to read back the output range of the DAC.
IOUT2 (Pin 4): DAC Current Output Complement. Tie IOUT2
to GND.
NC (Pin 5): No Connection. Must be tied to GND, provides
necessary shielding for IOUT2.
D3-D11 (Pins 6-14): LTC2751-12 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D11 is the MSB.
D5-D13 (Pins 6-14): LTC2751-14 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D13 is the MSB.
D7-D15 (Pins 6-14): LTC2751-16 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D15 is the MSB.
VDD (Pin 15): Positive Supply Input 2.7V ≤ VDD ≤ 5.5V.
Requires a 0.1µF bypass capacitor to GND.
GND (Pin 16): Ground. Tie to ground.
CLR (Pin 17): Asynchronous Clear. When CLR is taken
to a logic low, the data registers are reset to the zero-volt
code for the present output range (VOUT = 0V).
MSPAN (Pin 18): Manual Span Control Pin. MSPAN is used
to configure the LTC2751 for operation in a single, fixed
output range. When configured for single-span operation,
the output range is set via hardware pin strapping. The
span input and DAC registers are transparent and do not
respond to write or update commands.
To configure the part for single-span use, tie MSPAN
directly to VDD . If MSPAN is instead connected to GND
(SoftSpan configuration), the output ranges are set and
verified by using write, update and read operations. See
Manual Span Configuration in the Operation section.
MSPAN must be connected either directly to GND (SoftSpan configuration) or VDD (single-span configuration).
D0-D2 (Pins 19-21): LTC2751-12 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.
D0-D4 (Pins 19-23): LTC2751-14 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.
D0-D6 (Pins 19-25): LTC2751-16 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.
NC (Pins 22-27): LTC2751-12 Only. No Connection.
NC (Pins 24-27): LTC2751-14 Only. No Connection.
NC (Pins 26, 27): LTC2751-16 Only. No Connection.
D/S (Pin 28): Data/Span Select. This pin is used to select
activation of the data or span I/O pins (D0 to D15 or S0
to S2, respectively), along with their respective dedicated
registers, for write or read operations. Update operations
ignore D/S, since all updates affect both data and span
registers. For single-span operation, tie D/S to GND.
READ (Pin 29): Read Pin. When READ is asserted high, the
data I/O pins (D0-D15) or span I/O pins (S0-S2) output the
contents of the selected register (see Table 1). For singlespan operation, readback of the span I/O pins is disabled.
UPD (Pin 30): Update and Buffer Select Pin. When READ
is held low and UPD is asserted high, the contents of the
input registers (both data and span) are copied into their
respective DAC registers. The output of the DAC is updated,
reflecting the new DAC register values.
When READ is held high, the update function is disabled
and the UPD pin functions as a buffer selector—logic low
to select the input register, high for the DAC register. See
Readback in the Operation section.
WR (Pin 31): Active Low Write Pin. A Write operation
copies the data present on the data or span I/O pins (D0D15 or S0-S2, respectively) into the input register. When
READ is high, the Write function is disabled.
S0 (Pin 32): Span I/O Bit 0. Pins S0, S1 and S2 are used
to program and to read back the output range of the DAC.
2751fa
9
LTC2751
Pin Functions
S1 (Pin 33): Span I/O Bit 1. Pins S0, S1 and S2 are used
to program and to read back the output range of the DAC.
RVOS (Pin 34): DAC Offset Adjust. Nominal input range is
±5V. If not used, RVOS should be shorted to IOUT2 .
IOUT1 (Pin 35): DAC current output; normally tied to the
negative input of the I/V converter amplifier.
RFB (Pin 36): DAC Feedback Resistor; normally tied to
the output of the I/V converter amplifier. The DAC output
current from IOUT1 flows through the feedback resistor
to the RFB pin.
ROFS (Pin 37): Bipolar Offset Network. This pin provides
the translation of the output voltage range for bipolar
spans. Accepts up to ±15V; normally tied to the positive
reference voltage at RIN (Pin 2).
REF (Pin 38): Feedback Resistor for the Reference Inverting
Amplifier, and Reference Input for the DAC. Normally tied
to the output of the reference inverting amplifier. Typically
–5V. Accepts up to ±15V.
Exposed Pad (Pin 39): Ground. The Exposed Pad must
be soldered to the PCB.
2751fa
10
LTC2751
Block Diagram
1
RIN
2
38
RCOM
R1
READ
37
REF
ROFS
36
RFB
R2
IOUT1
16-BIT DAC WITH SPAN SELECT
29
WR
3
31
IOUT2
35
4
16
UPD
30
D/S
28
CONTROL
LOGIC
DAC
REGISTER
3
DAC
REGISTER
16
CLR
17
MSPAN
INPUT
REGISTER
INPUT
REGISTER
I/O
PORT
I/O
PORT
18
3
16
3, 32, 33
6-14, 19-25
SPAN I/O
S2-S0
2751 BD
DATA I/O
D15-D0
2751fa
11
LTC2751
Timing Diagrams
Write, Update and Clear Timing
t3
t1
WR
t2
I/O
INPUT
t5
UPD
t6
t4
t7
t8
D/S
t25
CLR
2751 TD01
Readback Timing
READ
WR
t14
t13
t23
t24
I/O
INPUT
t15
I/O
OUTPUT
t17
t19
t20
t22
UPD
t18
D/S
2751 TD02
Operation
Output Ranges
Digital Section
The LTC2751 is a current-output, parallel-input precision
multiplying DAC with software-programmable output
ranges. SoftSpan provides two unipolar output ranges
(0V to 5V and 0V to 10V), and four bipolar ranges (±2.5V,
±5V, ±10V and –2.5V to 7.5V). These ranges are obtained
when an external precision 5V reference is used. When
a reference voltage of 2V is used, the SoftSpan ranges
become: 0V to 2V, 0V to 4V, ±1V, ±2V, ±4V and –1V to
3V. The output ranges are linearly scaled for references
other than 2V and 5V.
The LTC2751 family has four internal interface registers
(see Block Diagram). Two of these—one input and one
DAC register—are dedicated to the data I/O port, and two
to the span I/O port. Each port is thus double-buffered.
The double-buffered feature provides the capability to
simultaneously update the span and code, which allows
smooth voltage transitions when changing output ranges.
It also permits the simultaneous updating of multiple DACs.
12
2751fa
LTC2751
Operation
Write and Update Operations
Table 1 shows the functions of the LTC2751.
The data input register is loaded directly from a 16-bit
microprocessor bus by holding the D/S pin low and then
pulsing the WR pin low. The second register (DAC register) is loaded by pulsing the UPD pin high, which copies
the data held in the input register into the DAC register.
Note that updates always include both data and span; but
the DAC register values will not change unless the input
register values have been changed by writing.
Table 1. Write, Update and Read Functions
Loading the span input register is accomplished in a similar
manner, by holding the D/S pin high and then bringing
the WR pin low. The span and data register structures
are the same except for the number of parallel bits—the
span registers have three bits, while the data registers
have 12, 14, or 16 bits.
To make both registers transparent for flowthrough mode,
tie WR low and UPD high. However, this defeats the deglitcher operation and output glitch impulse may increase.
The deglitcher is activated on the rising edge of the UPD pin.
The interface also allows the use of the input and DAC
registers in a master-slave, or edge-triggered, configuration. This mode of operation occurs when WR and UPD
are tied together and driven by a single clock signal. The
data bits are loaded into the input register on the falling
edge of the clock and then loaded into the DAC register
on the rising edge.
The separation of data and span for write and read operations makes it possible to control both data and span on
one 16-bit wide data bus by allowing span pins S2 to S0
to share bus lines with the data LSBs (D2 to D0). Since
no write or read operation includes both span and data,
there cannot be a conflict.
READ D/S
WR UPD
DATA I/O
0
0
0
0
-
Write to Input Register
0
0
0
1
-
Write/Update
(Transparent)
0
0
1
0
-
-
0
0
1
1
Update DAC Register
Update DAC Register
0
1
0
0
Write to Input Register
-
0
1
0
1
Write/Update
(Transparent)
-
0
1
1
0
-
-
0
1
1
1
Update DAC register
Update DAC Register
1
0
X
0
-
Read Input Register
1
0
X
1
-
Read DAC Register
1
1
X
0
Read Input Register
-
1
1
X
1
Read DAC Register
-
X = Don’t Care
Manual Span Configuration
Multiple output ranges are not needed in some applications.
To configure the LTC2751 for single-span operation, tie the
MSPAN pin to VDD and the D/S pin to GND. The desired
output range is then specified by the span I/O pins (S0, S1
and S2) as usual, but the pins are programmed by tying
directly to GND or VDD (see Figure 1 and Table 2). In this
configuration, the part will initialize to the chosen output
range at power-up, with VOUT = 0V.
When configured for manual span operation, span pin
readback is disabled.
VDD
The asynchronous clear pin resets the LTC2751 to 0V
(zero-, half- or quarter-scale code) in any output range.
CLR resets both the input and DAC data registers, while
leaving the span registers undisturbed.
These devices also have a power-on reset. If configured
for SoftSpan operation, the part initializes to zero scale in
the 0V to 5V output range. If configured for single-span
operation, the part initializes to the zero-volt code in the
chosen output range.
SPAN I/O
MSPAN
VDD
S2
LTC2751-16
S1
S0
D/S
WR
UPD
READ
16
2751 F01
DATA I/O
Figure 1. Configuring the LTC2751 for
Single-Span Operation (±10V Range)
2751fa
13
LTC2751
Operation
Table 2. Span Codes
S2
S1
S0
SPAN
0
0
0
Unipolar 0V to 5V
0
0
1
Unipolar 0V to 10V
0
1
0
Bipolar –5V to 5V
0
1
1
Bipolar –10V to 10V
1
0
0
Bipolar –2.5V to 2.5V
1
0
1
Bipolar –2.5V to 7.5V
Codes not shown are reserved and should not be used.
Readback
The contents of any one of the four interface registers can
be read back by using the READ pin in conjunction with
the D/S and UPD pins.
A readback operation is initiated by bringing READ to logic
high. The I/O pins, which are high-impedance digital inputs
when READ is low, selectively change to low-impedance
logic outputs during readback.
The I/O pins comprise two ports, data and span. The data
I/O port consists of pins D0-D11, D0-D13 or D0-D15
(LTC2751-12, LTC2751-14 or LTC2751-16, respectively).
The span I/O port consists of pins S0, S1 and S2 for all
parts.
Each I/O port has one dedicated input register and one
dedicated DAC register. The register structure is shown
in the Block Diagram.
The D/S pin is used to select which I/O port (data or span)
is configured to read back the contents of its registers. The
unselected I/O port’s pins remain high-impedance inputs.
Once the I/O port is selected, its input or DAC register is
selected for readback by using the UPD pin. Note that UPD
is a two-function pin. The update function is disabled when
READ is high, and the UPD pin instead selects the input
or DAC register for readback. Table 1 shows the readback
functions for the LTC2751.
The most common readback task is to check the contents
of an input register after writing to it, before updating the
new data to the DAC register. To do this, bring READ high
while holding UPD low. The contents of the selected port’s
input register are output by the data or span I/O pins.
To read back the contents of a DAC register, bring READ
high, then bring UPD high. The contents of the selected
data or span DAC register are output by the data or span
I/O pins. Note: if no update is desired after the readback
operation, UPD must be returned low before bringing
READ low, otherwise the UPD pin will revert to its primary
function and update the DAC.
System Offset Adjustment
Many systems require compensation for overall system
offset. The RVOS offset adjustment pin is provided for this
purpose. For noise immunity and ease of adjustment, the
control voltage is attenuated to the DAC output:
VOS = –0.01 • V(RVOS) [0V to 5V, ±2.5V spans]
VOS = –0.02 • V(RVOS) [0V to 10V, ±5V,
–2.5V to 7.5V spans]
VOS = –0.04 • V(RVOS) [±10V span]
The nominal input range of this pin is ±5V; other reference voltages of up to ±15V may be used if needed. The
RVOS pin has an input impedance of 1MW. To preserve the
settling performance of the LTC2751, this pin should be
driven with a Thevenin-equivalent impedance of 10kW or
less. If not used, RVOS should be shorted to IOUT2.
2751fa
14
LTC2751
Operation—Examples
1. Load ±5V range with the output at 0V. Note that since span and code are updated together, the output, if started at
0V, will stay there.
WR
SPAN I/O
INPUT
010
DATA I/O
INPUT
8000 H
UPD
UPDATE
(5V RANGE, VOUT = 0V)
D/S
READ = LOW
2751 TD03
2. Load ±10V range with the output at 5V, changing to –5V.
WR
SPAN I/O
INPUT
DATA I/O
INPUT
011
C000 H
4000 H
UPD
UPDATE (5V)
UPDATE (–5V)
D/S
READ = LOW
2751 TD04
3. Write and update mid-scale code in 0V to 5V range (VOUT = 2.5V) using readback to check the contents of the input
and DAC registers before updating.
WR
DATA I/O
INPUT
DATA I/O HI-Z
OUTPUT
8000 H
HI-Z
8000 H
INPUT REGISTER
UPD
0000 H
DAC REGISTER
UPDATE (2.5V)
D/S
READ
2751 TD05
2751fa
15
LTC2751
Applications Information
Op Amp Selection
when programmed in a unipolar or bipolar output range.
These are the changes the op amp can cause to the INL,
DNL, unipolar offset, unipolar gain error, bipolar zero
and bipolar gain error. Tables 3 and 4 can also be used
to determine the effects of op amp parameters on the
LTC2751-14 and the LTC2751-12. However, the results
obtained from Tables 3 and 4 are in 16-bit LSBs. Divide
these results by 4 (LTC2751-14) and 16 (LTC2751-12) to
obtain the correct LSB sizing.
Because of the extremely high accuracy of the 16-bit
LTC2751-16, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 3 and 4 contain equations for evaluating the effects of op amp parameters on the LTC2751’s accuracy
Table 5 contains a partial list of LTC precision op amps
recommended for use with the LTC2751. The easy-to-use
design equations simplify the selection of op amps to meet
the system’s specified error budget. Select the amplifier
from Table 5 and insert the specified op amp parameters
in Table 4. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the
part. Arithmetic summation gives an (unlikely) worst-case
effect. A root-sum-square (RMS) summation produces a
more realistic estimate.
Table 3. Variables for Each Output Range That Adjust the
Equations in Table 4
OUTPUT RANGE
A1
A2
A3
5V
1.1
2
1
A4
A5
1
10V
2.2
3
0.5
1.5
±5V
2
2
1
1
1.5
±10V
4
4
0.83
1
2.5
±2.5V
1
1
1.4
1
1
–2.5V to 7.5V
1.9
3
0.7
0.5
1.5
Table 4. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1
Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.
OP AMP
INL (LSB)
DNL (LSB)
( )
( )
( )
( )
( )
( )
UNIPOLAR
OFFSET (LSB)
( )
( )
5V
5V
5V
VOS1 • 0.82 • V
A3 • VOS1 • 13.2 • V
VOS1 • 3.2 • V
REF
REF
REF
5V
5V
5V
IB1 (nA) IB1 • 0.0003 • V
IB1 • 0.00008 • V
IB1 • 0.13 • V
REF
REF
REF
16.5k
1.5k
AVOL1 (V/V)
A1 • A
A2 • A
0
VOL1
VOL1
VOS1 (mV)
VOS2 (mV)
0
0
0
IB2 (mV)
0
0
0
AVOL2 (V/V)
0
0
0
BIPOLAR ZERO
ERROR (LSB)
( )
( )
5V
A3 • VOS1 • 19.8 • V
REF
5V
IB1 • 0.13 • V
REF
0
(
(V5V ) )
5V
A4 • (I • 0.13 • (
V ))
A4 • ( 66k )
A
A4 • VOS2 • 13.1 •
B2
REF
REF
VOL2
UNIPOLAR GAIN
ERROR (LSB)
5V
VOS1 • 13.2 • V
REF
5V
IB1 • 0.0018 • V
REF
131k
A5 •
AVOL1
5V
VOS2 • 26.2 •
VREF
5V
IB2 • 0.26 •
VREF
131k
AVOL2
( )
( )
( )
( )
( )
( )
BIPOLAR GAIN
ERROR (LSB)
5V
VOS1 • 13.2 • V
REF
5V
IB1 • 0.0018 • V
REF
131k
A5 •
AVOL1
5V
VOS2 • 26.2 •
VREF
5V
IB2 • 0.26 •
VREF
131k
AVOL2
( )
( )
( )
( )
( )
( )
Table 5. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2751 with Relevant Specifications
AMPLIFIER SPECIFICATIONS
AMPLIFIER
VOS
µV
IB
nA
A VOL
V/mV
VOLTAGE
NOISE
nV/√Hz
LT1001
25
2
800
10
CURRENT
NOISE
pA/√Hz
SLEW
RATE
V/µs
GAIN BANDWIDTH
PRODUCT
MHz
tSETTLING
with
LTC2751
µs
POWER
DISSIPATION
mW
0.12
0.25
0.8
120
46
LT1097
50
0.35
1000
14
0.008
0.2
0.7
120
11
LT1112 (Dual)
60
0.25
1500
14
0.008
0.16
0.75
115
10.5/Op Amp
LT1124 (Dual)
70
20
4000
2.7
0.3
4.5
12.5
19
69/Op Amp
LT1468
75
10
5000
5
0.6
22
90
2
117
LT1469 (Dual)
125
10
2000
5
0.6
22
90
2
123/Op Amp
2751fa
16
LTC2751
Applications Information
Op amp offset will contribute mostly to output offset and
gain error and has minimal effect on INL and DNL. For
the LTC2751-16, a 250µV op amp offset will cause about
0.8LSB INL degradation and 0.2LSB DNL degradation
with a 5V reference. For the LTC2751 programmed in 5V
unipolar mode, the same 250µV op amp offset will cause
a 3.3LSB zero-scale error and a 3.3LSB gain error.
While not directly addressed by the simple equations in
Tables 3 and 4, temperature effects can be handled just
as easily for unipolar and bipolar applications. First, consult an op amp’s data sheet to find the worst-case VOS
and IB over temperature. Then, plug these numbers in
the VOS and IB equations from Table 4 and calculate the
temperature-induced effects.
For applications where fast settling time is important,
Application Note 74, “Component and Measurement
Advances Ensure 16-Bit DAC Settling Time,” offers a
thorough discussion of 16-bit DAC settling time and op
amp selection.
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifier
for use with the LTC2751 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC2751 is
directly affected by the voltage reference; thus, any voltage
reference error will appear as a DAC output voltage error.
There are three primary error sources to consider when
selecting a precision voltage reference for 16-bit applications: output voltage initial tolerance, output voltage
temperature coefficient and output voltage noise.
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
(±0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for
system zero- and full-scale error is always recommended.
A reference’s output voltage temperature coefficient affects
not only the full-scale error, but can also affect the circuit’s
INL and DNL performance. If a reference is chosen with
a loose output voltage temperature coefficient, then the
DAC output voltage along its transfer characteristic will
be very dependent on ambient conditions. Minimizing
the error due to reference temperature coefficient can be
achieved by choosing a precision reference with a low
output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize
temperature gradients.
As precision DAC applications move to 16-bit and higher
performance, reference output voltage noise may contribute a dominant share of the system’s noise floor. This in
turn can degrade system dynamic range and signal-tonoise ratio. Care should be exercised in selecting a voltage
reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage
references, like the LT1236, produce low output noise in
the 0.1Hz to 10Hz region, well below the 16-bit LSB level
in 5V or 10V full-scale systems. However, as the circuit
bandwidths increase, filtering the output of the reference
may be required to minimize output noise.
Table 6. Partial List of LTC Precision References Recommended
for Use with the LTC2751 with Relevant Specifications
INITIAL
TOLERANCE
TEMPERATURE
DRIFT
0.1Hz to 10Hz
NOISE
LT1019A-5,
LT1019A-10
±0.05%
5ppm/°C
12µVP-P
LT1236A-5,
LT1236A-10
±0.05%
5ppm/°C
3µVP-P
LT1460A-5,
LT1460A-10
±0.075%
10ppm/°C
20µVP-P
LT1790A-2.5
±0.05%
10ppm/°C
12µVP-P
REFERENCE
Grounding
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding techniques should be used. IOUT2 must be tied
to the star ground with as low a resistance as possible.
When it is not possible to locate star ground close to
IOUT2, a low resistance trace should be used to route this
pin to star ground. This minimizes the voltage drop from
this pin to ground caused by the code dependent current
flowing to ground. When the resistance of this circuit
board trace becomes greater than 1W, a force/sense amplified configuration should be used to drive this pin (see
Figure 2). This preserves the excellent accuracy (1LSB
INL and DNL) of the LTC2751-16.
2751fa
17
LTC2751
Applications Information
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
6
3
6
IOUT2
3
LT1001
+
+
2
1000pF
LT1468
ZETEX
BAT54S
200Ω
200Ω
–
6
1
2
–
IOUT2
1
REF
5V
5
6
2
RIN
R1
WR
UPD
READ
D/S
CLR
30
29
+
1/2 LT®1469
2
7
C2**
150pF
–
1
RCOM
28
17
18
3
*SCHOTTKY BARRIER DIODE
37
36
REF ROFS RFB
38
R2
C1
15pF
15V 0.1µF
IOUT1
8
35
WR
UPD
16-BIT DAC WITH SPAN SELECT
IOUT2 4
READ
GND
D/S
CLR
3
ZETEX*
BAT54S
LTC2751-16
31
2
3
16
MSPAN
RVOS
3, 33, 32
SPAN I/O
S2-S0
6-14, 19-25
DATA I/O
D15-D0
**FOR MULTIPLYING APPLICATIONS C2 = 15pF
34
VDD
2
–
3
+
16
15
5V
C3
0.1µF
1
1/2 LT1469
4
–15V
VOUT
0.1µF
2751 F02
Figure 2. Basic Connections for SoftSpan VOUT DAC with Two Optional Circuits
for Driving IOUT2 from GND with a Force/Sense Amplifier
2751fa
18
LTC2751
Typical Applications
16-Bit DAC with Software-Selectable Ranges
REF
5V
5
6
2
RIN
R1
+
1/2 LT1469
7
C2**
150pF
–
1
RCOM
37
36
REF ROFS RFB
38
R2
LTC2751-16
WR
UPD
READ
D/S
CLR
31
30
29
28
17
18
C1
15pF
IOUT1
35
WR
UPD
16-BIT DAC WITH SPAN SELECT
IOUT2 4
READ
GND
D/S
CLR
3
16
MSPAN
RVOS
3, 33, 32
SPAN I/O
S2-S0
6-14, 19-25
DATA I/O
D15-D0
34
VDD
2
–
3
+
15V
8
0.1µF
1
1/2 LT1469
16
15
C3
0.1µF
VOUT
4
–15V
0.1µF
5V
2751 TA02
**FOR MULTIPLYING APPLICATIONS C2 = 15pF
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19
LTC2751
Package Description
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 ±0.05
5.50 ±0.05
5.15 ±0.05
4.10 ±0.05
3.00 REF
3.15 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
5.5 REF
6.10 ±0.05
7.50 ±0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ±0.10
0.75 ±0.05
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ±0.10
5.50 REF
7.00 ±0.10
3.15 ±0.10
(UH) QFN REF C 1107
0.200 REF 0.25 ±0.05
0.50 BSC
R = 0.125
TYP
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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20
LTC2751
Revision History
REV
DATE
DESCRIPTION
A
11/12
Correction made in the Typical Application diagram.
PAGE NUMBER
1, 18
2751fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
LTC2751
Typical Application
Offset and Gain Trim Circuits. Powering VDD from LT1027 Ensures Quiet Supply
V+
2
IN
C20
10µF
U3 OUT
6
LT1027
TRIM
5
GND
4
2
1
R2
10k
C13
10µF
2
GND
GND
C23
0.1µF
C22
0.001µF
GND
6
7
8
9
10
11
12
13
14
19
20
21
22
23
24
25
DATA I/O
15
D15 VDD
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
3
S2
33
S1
32
S0
SPAN I/O
2
1
8
V+
U2A
LT®1469
+
GND
4
2
R1
10k
1
1
3
V–
38
RIN RCOM
37
C1
30pF
36
ROFS RFB
REF
IOUT1
IOUT2
U1
RVOS
35
29
30
D/S READ UPD
WR
31
WR
CLR
17
6
4
5
–
U2B
LT1469
7
+
VOUT
34
LTC2751-16
D/S READ UPD
28
3
–
GND
MSPAN NC
18
5
GND GND
16
39
2751 TA03
CLR
GND
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LT1027
Precision Reference
2ppm/°C Maximum Drift
LT1236A-5
Precision Reference
0.05% Maximum Tolerance, 1ppm 0.1Hz to 10Hz Noise
LT1468
16-Bit Accurate Op-Amp
90MHz GBW, 22V/µs Slew Rate
LT1469
Dual 16-Bit Accurate Op-Amp
90MHz GBW, 22V/µs Slew Rate
LTC1588/LTC1589/ Serial 12-/14-/16-Bit IOUT Single DACs
LTC1592
Software-Selectable (SoftSpan) Ranges, ±1LSB INL, DNL, 16-Lead SSOP Package
LTC1591/LTC1597
Parallel 14-/16-Bit IOUT Single DAC
Integrated 4-Quadrant Resistors
LTC1821
Parallel 16-Bit VOUT Single DAC
±1LSB INL, DNL, 0V to 10V, 0V to –10V, ±10V Output Ranges
LTC2601/LTC2611/ Serial 12-/14-/16-Bit VOUT Single DACs
LTC2621
Single DACs, SPI-Compatible, Single Supply, 0V to 5V Outputs in 3mm × 3mm
DFN-10 Package
LTC2606/LTC2616/ Serial 12-/14-/16-Bit VOUT Single DACs
LTC2626
Single DACs, I2C-Compatible, Single Supply, 0V to 5V Outputs in 3mm × 3mm
DFN-10 Package
LTC2641/LTC2642
Serial 12-/14-/16-Bit Unbuffered VOUT Single
DACs
±2LSB INL, ±1LSB DNL, 1µs Settling, Tiny MSOP-10, 3mm × 3mm DFN-10
Packages
LTC2704
Serial 12-/14-/16-Bit VOUT Quad DACs
Software-Selectable (SoftSpan) Ranges, Integrated Amplifiers
2751fa
22 Linear Technology Corporation
LT 1112 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2007