LTC2862MPS8-1#PBF

SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER FEATURES • • • • • • • • • • • • Low-Voltage Differential Driver and Receiver for Half-Duplex Operation Designed for Signaling Rates of 400 Mbit/s ESD Protection Exceeds 15 kV on Bus Pins Operates From a Single 3.3-V Supply Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 50-Ω Load Valid Output With as Little as 50 mV Input Voltage Difference Propagation Delay Times – Driver: 1.7 ns Typ – Receiver: 3.7 ns Typ Power Dissipation at 200 MHz – Driver: 50 mW Typical – Receiver: 60 mW Typical LVTTL Levels Are 5-V Tolerant Bus Pins Are High Impedance When Disabled or With VCC Less Than 1.5 V Open-Circuit Fail-Safe Receiver Surface-Mount Packaging – D Package (SOIC) – DGK Package (MSOP) SN65LVDM176D (Marked as DM176 or LVM176) SN65LVDM176DGK (Marked as M76) (TOP VIEW) R RE DE D 1 8 2 7 3 6 4 5 VCC B A GND logic diagram (positive logic) DE D RE R 3 4 2 6 1 7 A B DESCRIPTION The SN65LVDM176 is a differential line driver and receiver configured as a transceiver that uses low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbit/s. These circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50-Ω load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of less than 50 mV with up to 1 V of ground potential difference between a transmitter and receiver. The intended application of this device and signaling technique is for half-duplex or multiplex baseband data transmission over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics). The SN65LVDM176 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2000, Texas Instruments Incorporated SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PACKAGE (1) TA SMALL OUTLINE (D) (1) MSOP (DGK) (1) –40°C to 85°C SN65LVDM176D SN65LVDM176DGK The D package is available taped and reeled. Add the suffix R to the device type(e.g., SN65LVDM176DR). FUNCTION TABLES DRIVER (1) (1) OUTPUTS INPUT D ENABLE DE A B L H L H H H H L Open H L H X L Z Z H = high level, L = low level, X = irrelevant, Z = high impedance RECEIVER (1) (1) 2 DIFFERENTIAL INPUTS VID = VA - VB ENABLE RE OUTPUT R VID ≥ 50 mV L H 50 mV < VID < 50 mV L ? VID ≤ -50 mV L L Open L H X H Z H = high level, L = low level, X = irrelevant, Z = high impedance Submit Documentation Feedback SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC VCC 300 kΩ 50 Ω 5Ω 10 kΩ D or RE Input Y or Z Output 50 Ω DE Input 7V 7V 7V 300 kΩ VCC VCC 300 kΩ 300 kΩ 5Ω A Input R Output B Input 7V 7V 7V ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage (2) Input voltage range Electrostatic discharge –0.5 V to 4 V D, R, DE, RE A or B A, B , and GND (3) All terminals Continuous total power dissipation –0.5 V to 6 V –0.5 V to 4 V CLass 3, A:15 kV, B:600 V Class 3, A:7 kV, B:500 V See Dissipation Rating Table TA Operating free-air temperature range –40°C to 85°C Tstg Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal. Tested in accordance with MIL-STD-883C Method 3015.7. Submit Documentation Feedback 3 SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING D 725 mW 5.8 mW/°C 377 mW DGK 424 mW 3.4 mW/°C 220 mW RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 3.3 3.6 VCC Supply voltage 3 VIH High-level input voltage 2 VIL Low-level input voltage |VID| Magnitude of differential input voltage VIC Common-mode input voltage (see Figure 1) TA Operating free-air temperature ID 2 V V 0.1
V
UNIT 0.8 V 0.6 V V  2.4
ID 2 V VCC–0.8 –40 85 °C COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 2.5 V IC – Common-Mode Input Voltage – V Max at VCC > 3.15 V Max at VCC = 3 V 2 1.5 1 0.5 Min 0 0 0.1 0.2 0.3 0.4 0.5 0.6 |VID| – Differential Input Voltage – V Figure 1. DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Driver and receiver enabled, no receiver load, driver RL = 50 Ω ICC (1) 4 Supply current MIN TYP (1) MAX 10 15 9 15 Driver disabled, receiver enabled, no load 1.8 5 Disabled 0.5 2 Driver enabled, receiver disabled, RL = 50 Ω All typical values are at 25°C and with a 3.3-V supply. Submit Documentation Feedback UNIT mA SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS |VOD| Differential output voltage magnitude ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage IIH High-level input current (1) IIL Low-level input current (1) IOS Short-circuit output current (1) CI Input capacitance (1) DE D DE D RL = 50 Ω, See Figure 2 and Figure 3 See Figure 4 MIN TYP MAX 247 340 UNIT 454 mV –50 50 1.125 1.37 5 –50 50 mV mV VIH = 5 V VIL = 0.8 V 50 150 0.5 10 2 20 –0.5 –10 2 10 VOA or VOB = 0 V –10 VOD = 0 V –10 3 V µA µA mA pF The non-algebraic convention, where the more positive (least negative) limit is designated maximum, is used in this data sheet for this parameter. RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going differential input voltage threshold VIT– Negative-going differential input voltage threshold VOH High-level output voltage IOH = –8 mA VOL Low-level output voltage IOL = 8 mA See Figure 6 VI = 0 V MIN TYP ( 1) MAX 50 –50 2.4 mV V 0.4 –2 UNIT –20 V II Input current (A or B inputs) (2) II(OFF) Power-off input current (A or B inputs) VCC = 0 V or 1.8 V 20 µA IIH High-level input current (enables) VIH = 5 V 10 µA IIL Low-level input current (enables) VIL = 0.8 V 10 µA IOZ High-impedance output current (2) VO = 0 V or 5 V ±1 µA (1) (2) VI = 2.4 V –1.2 µA All typical values are at 25°C and with a 3.3-V supply. The non-algebraic convention, where the more positive (least negative) limit is designated maximum, is used in this data sheet for this parameter. Submit Documentation Feedback 5 SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP (1) MAX TEST CONDITIONS tPLH Propagation delay time, low-to-high-level output 0.5 1.7 2.7 tPHL Propagation delay time, high-to-low-level output 0.5 1.7 2.7 tsk(p) Pulse skew (|tpHL– tpLH|) tr Differential output signal rise time 0.6 1 tf Differential output signal fall time 0.6 1 tsk(pp) (2) Part-to-part skew tPZH Propagation delay time, high-impedance-to-high-level output 8 12 tPZL Propagation delay time, high-impedance-to-low-level output 7 10 tPHZ Propagation delay time, high-level-to-high-impedance output 3 10 tPLZ Propagation delay time, low-level-to-high-impedance output 4 10 (1) (2) RL = 50 Ω, CL = 10 pF, See Figure 3 0.2 ns ns 1 See Figure 5 UNIT ns ns ns All typical values are at 25°C and with a 3.3 V supply. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP ( 1) MAX tPLH Propagation delay time, low-to-high-level output 2.3 3.7 4.5 tPHL Propagation delay time, high-to-low-level output 2.3 3.7 4.5 tsk(p) Pulse skew (|tpHL– tpLH|) tr Output signal rise time 0.8 1.5 tf Output signal fall time 0.8 1.5 tsk(pp) (2) Part-to-part skew tPZH Propagation delay time, high-level-to-high-impedance output 3 10 tPZL Propagation delay time, low-level-to-low-impedance output 3 10 tPHZ Propagation delay time, high-impedance-to-high-level output 4 10 tPLZ Propagation delay time, low-impedance-to-high-level output 6 10 (1) (2) CL = 10 pF, See Figure 7 ns 0.4 1 See Figure 8 ns ns ns All typical values are at 25°C and with a 3.3-V supply. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. PARAMETER MEASUREMENT INFORMATION DRIVER IOA Driver Enabled A II D IOB VOD V VOA B VI OA
V 2 VOC VOB Figure 2. Driver Voltage and Current Definitions 6 UNIT Submit Documentation Feedback OB SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION (continued) 3.75 kΩ A Input DA 50 Ω VOD + _ B 0 ≤ Vtest ≤ 2.4 V 3.75 kΩ 2V 1.4 V 0.8 V Input tPHL tPLH 100% 80% VOD(H) Output 0V VOD(L) 20% 0% tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 3. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal 25 Ω, ±1% (2 Places) Driver Enabled A 3V D D Input 0V B VOC VOC(PP) CL = 10 pF (2 Places) VOC(SS) VO A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300 MHz. Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage Submit Documentation Feedback 7 SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION (continued) 25 Ω, ±1% (2 Places) A 0.8 V or 2 V B 1.2 V DE CL = 10 pF (2 Places) VOA 2V 1.4 V 0.8 V DE ~1.4 V 1.25 V 1.2 V VOA or VOB tPZH tPHZ 1.2 V 1.15 V ~1 V VOB or VOA tPZL A. VOB tPLZ All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 5. Enable and Disable Time Circuit and Definitions RECEIVER A V IA
V IB VID 2 R VIA VIC B VIB Figure 6. Receiver Voltage Definitions 8 Submit Documentation Feedback VO SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES (V) RESULTING DIFFERENTIAL INPUT VOLTAGE (mV) RESULTING COMMONMODE INPUT VOLTAGE (V) VID VIC 1.2 VIA VIB 1.225 1.175 50 1.175 1.225 –50 1.2 2.41 2.36 50 2.385 2.36 2.41 –50 2.385 0.05 0 50 0.025 0 0.05 –50 0.025 1.5 0.9 600 1.2 0.9 1.5 –600 1.2 2.4 1.8 600 2.1 1.8 2.4 –600 2.1 0.6 0 600 0.3 0 0.6 –600 0.3 VID VIA VIB CL 10 pF VO VIA 1.4 V VIB 1V VID 0.4 V 0V –0.4 V tPHL VO tPLH VOH 2.4 V 1.4 V 0.4 V VOL tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 7. Timing Test Circuit and Waveforms Submit Documentation Feedback 9 SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 B 1.2 V 500 Ω A Inputs A. CL 10 pF RE + – VO VTEST All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 5000 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. 2.5 V VTEST A 1V 2V RE 1.4 V 0.8 V tPZL tPZL tPLZ 2.5 V 1.4 V R VOL +0.5 V VOL 0V VTEST A 1.4 V 2V RE 1.4 V 0.8 V tPZH R tPZH tPHZ VOH –0.5 V VOH 1.4 V 0V Figure 8. Enable/Disable Time Test Circuit and Waveforms 10 Submit Documentation Feedback SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 TYPICAL CHARACTERISTICS DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 3.5 VCC = 3.3 V TA = 25°C V OH− High-Level Output Voltage − V V OL − Low-Level Output Voltage − V VCC = 3.3 V TA = 25°C 3 2 1 0 3 2.5 2 1.5 1 .5 0 0 4 2 6 8 10 0 12 −2 IOL − Low-Level Output Current − mA −6 −8 IOH − High-Level Output Current − mA Figure 9. Figure 10. RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 5 VCC = 3.3 V TA = 25°C VCC = 3.3 V TA = 25°C VOL − Low-Level Output Votlage − V VOH − High-Level Output Voltage − V −4 3 2 1 0 0 −20 −40 −60 IOH − High-Level Output Current − mA −80 4 3 2 1 0 0 Figure 11. 10 20 30 40 50 IOL − Low-Level Output Current − mA 60 Figure 12. Submit Documentation Feedback 11 SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 TYPICAL CHARACTERISTICS (continued) DRIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE DRIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2 t PLH − Low-To-High Propagation Delay Time − ns 2.5 VCC = 3.3 V VCC = 3 V VCC = 3.6 V 1.5 −50 −30 −10 50 30 70 TA − Free-Air Temperature − °C 10 90 2 VCC = 3 V VCC = 3.6 V 1.5 −50 −30 −10 50 10 30 70 TA − Free-Air Temperature − °C 90 Figure 14. RECEIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE RECEIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 4.5 VCC = 3.3 V 4 VCC = 3 V 3.5 VCC = 3.6 V 3 2.5 −50 −30 −10 50 30 70 TA − Free−Air Temperature − °C 10 90 4.5 VCC = 3 V 4 VCC = 3.3 V 3.5 VCC = 3.6 V 3 2.5 −50 Figure 15. 12 VCC = 3.3 V Figure 13. t PLH − Low-To-High Level Propagation Delay Time − ns t PLH − High-To-Low Level Propagation Dealy Time − ns t PLH − High-To-Low Propagation Delay Time − ns 2.5 −30 −10 50 10 30 70 TA − Free-Air Temperature − °C Figure 16. Submit Documentation Feedback 90 SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 APPLICATION INFORMATION The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground differences are less than 1 V with a low common-mode output and balanced interface for very low noise emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL speeds without the power and dual supply requirements. Transmission Distance – m 1000 30% Jitter 100 5% Jitter 10 1 24 AWG UTP 96 Ω (PVC Dielectric) 0.1 100k 1M 10M 100M Data Rate – Hz Figure 17. Data Transmission Distance Versus Rate FAIL SAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –50 mV and 50 mV and within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 18. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt = 100 Ω (Typ) Y B VIT ≈ 2.3 V Figure 18. Open-Circuit Fail Safe of the LVDS Receiver Submit Documentation Feedback 13 SN65LVDM176 www.ti.com SLLS320D – DECEMBER 1998 – REVISED JULY 2000 APPLICATION INFORMATION (continued) It is only under these conditions that the output of the receiver will be valid with less than a 50-mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. A 100 Ω D A 100 Ω D B DE B DE RE R RE + _ + _ R Bidirectional Half-Duplex Applications D/R D/R D/R D/R 100 Ω 100 Ω D/R D/R D/R Multipoint Bus Applications Note A: Keep drivers and receivers as close to the LVDS bus side connector as possible. Figure 19. Bidirectional Half-Duplex and Multipoint Bus Applications 14 Submit Documentation Feedback D/R PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVDM176D ACTIVE SOIC D 8 75 RoHS & Green SN65LVDM176DGK ACTIVE VSSOP DGK 8 80 SN65LVDM176DGKG4 ACTIVE VSSOP DGK 8 80 SN65LVDM176DGKR ACTIVE VSSOP DGK 8 2500 SN65LVDM176DGKRG4 ACTIVE VSSOP DGK 8 SN65LVDM176DR ACTIVE SOIC D 8 NIPDAU Level-1-260C-UNLIM -40 to 85 DM176 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 M76 RoHS & Green Level-1-260C-UNLIM -40 to 85 M76 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 M76 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 M76 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DM176 NIPDAU (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of