LTC2943-1
1A Multicell Battery Gas
Gauge with Temperature,
Voltage and Current Measurement
Features
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Description
Measures Accumulated Battery Charge and Discharge
3.6V to 20V Operating Range for Multiple Cells
Integrated 50mΩ High Side Sense Resistor
±1A Current Sense Range
14-Bit ADC Measures Voltage, Current and
Temperature
1% Voltage, Current and Charge Accuracy
High Side Sense
General Purpose Measurements for Any Battery
Chemistry and Capacity
I2C/SMBus Interface
Configurable Alert Output/Charge Complete Input
Quiescent Current Less Than 120µA
Small 8-Lead 3mm × 3mm DFN Package
Applications
The LTC®2943-1 measures battery charge state, battery
voltage, battery current and its own temperature in portable
product applications. The wide input voltage range allows
use with multicell batteries up to 20V. A precision coulomb
counter integrates current through a sense resistor between
the battery’s positive terminal and the load or charger.
Voltage, current and temperature are measured with an
internal 14-bit No Latency ΔΣ™ ADC. The measurements
are stored in internal registers accessible via the onboard
I2C/SMBus Interface.
The LTC2943-1 features programmable high and low
thresholds for all four measured quantities. If a programmed threshold is exceeded, the device communicates
an alert using either the SMBus alert protocol or by setting
a flag in the internal status register.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency ∆Σ and PowerPath are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patent, 8390363.
Power Tools
Portable Medical Equipment
n Video Cameras
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Typical Application
Total Charge Error vs Current Sense
2.0
1A
LOAD
CHARGER
3.3V
2k
2k
2k
VDD
ALCC
µP
SDA
SENSE+
SENSE–
SCL
GND
+
MULTICELL
LI-ION
CHARGE ERROR (%)
1µF
LTC2943-1
VSENSE+ = 10V
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
29431 TA01a
–2.0
1
10
100
|ISENSE| (mA)
1k
29431 TA01b
29431f
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1
LTC2943-1
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
Supply Voltage (SENSE+)............................ –0.3V to 24V
SCL, SDA, ALCC Voltage............................... –0.3V to 6V
Sense Current (into SENSE–).....................................±2A
Operating Ambient Temperature Range
LTC2943C-1............................................. 0°C to 70°C
LTC2943I-1..........................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
TOP VIEW
SENSE+
1
GND
2
GND
3
SCL
4
8 SENSE–
9
7 GND
6 ALCC
5 SDA
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 53.4°C/W
EXPOSED PAD (PIN 9) PCB GND CONNECTION OPTIONAL
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2943CDD-1#PBF
LTC2943CDD-1#TRPBF
LGQN
8-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC2943IDD-1#PBF
LTC2943IDD-1#TRPBF
LGQN
8-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
20
V
80
650
15
120
750
25
µA
µA
µA
3.3
3.6
V
Power Requirements
VSENSE+
Supply Voltage
ISUPPLY
Supply Current (Note 3)
Battery Gas Gauge On, ADC Sleep
Battery Gas Gauge On, ADC On
Shutdown
l
l
l
3.6
VUVLO
Undervoltage Lockout Threshold
VSENSE+ Falling
l
3.0
Coulomb Counter
ISENSE
Sense Current
RSENSE
Internal Sense Resistance
RFP
Pin-to-Pin Resistance from SENSE+ (Note 8)
to SENSE–
qLSB
Charge LSB (Note 4)
Prescaler M = 4096(Default)
TCE
Total Charge Error (Note 5)
0.2A ≤ |ISENSE–| ≤ 1A DC
0.2A ≤ |ISENSE–| ≤ 1A DC, 0°C to 70°C
0.02A ≤ |ISENSE–| ≤ 1A DC (Note 8)
l
l
ISENSE ≥ 10mA, VSENSE+ = 10V
l
VOSE
Effective Differential Offset Current
(Note 9)
±1
l
50
50
74
100
0.4
100
A
mΩ
mΩ
mAh
±1
±1.5
±3.5
%
%
%
200
µA
29431f
2
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LTC2943-1
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage Measurement ADC
Resolution (No Missing Codes)
VFS(V)
Full-Scale Voltage Conversion
ΔVLSB
Quantization Step of 14-Bit Voltage
ADC
TUEV
Voltage Total Unadjusted Error
GainV
INLV
TCONV(V)
(Note 8)
14
(Note 6)
Voltage Gain Accuracy
Integral Nonlinearity
l
Bits
23.6
V
1.44
mV
l
1
1.3
%
%
l
1.3
%
VSENSE+ > 5V
l
±4
LSB
3.6V ≤ VSENSE+ ≤ 5V
l
±8
LSB
l
48
ms
Voltage Conversion Time
±1
Current Measurement ADC
Resolution (No Missing Codes)
(Note 8)
VFS(I)
Full-Scale Current Conversion
VSENSE
Sense Voltage Differential Input
Range
VSENSE+ – VSENSE–
ΔILSB
Quantization Step of 12-Bit Current
ADC
(Note 6)
GainI
Current Gain Accuracy
l
12
0°C to 70°C
–40°C to 85°C
Bits
±1.3
l
A
±1
l
317.4
Offset
INLI
Integral Nonlinearity
l
TCONV(I)
Current Conversion Time
l
µA
1
1.3
3
%
%
%
±1
±10
LSB
±1
±4
LSB
8
ms
l
l
VOS(I)
A
Temperature Measurement ADC
Resolution (No Missing Codes)
TFS
Full-Scale Temperature
ΔTLSB
Quantization Step of 11-Bit
Temperature ADC
TUET
Temperature Total Unadjusted Error
TCONV(T)
Temperature Conversion Time
(Note 8)
l
11
(Note 6)
Bits
510
K
0.25
K
±3
K
8
l
ms
Digital Inputs and Digital Outputs
VITH(HV)
Logic Input Threshold
VSENSE+ ≥ 5V
l
3.6V < VSENSE+ < 5V
VITH(LV)
0.8
2.2
V
0.45
1.8
V
VOL
Low Level Output Voltage, ALCC,
SDA
I = 3mA, VSENSE+ ≥ 5V
l
0.4
V
IIN
Input Leakage, ALCC, SCL, SDA
VIN = 5V
l
±1
µA
CIN
Input Capacitance, ALCC, SCL, SDA (Note 8)
l
10
pF
tPCC
Minimum Charge Complete (CC)
Pulse Width
1
µs
29431f
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LTC2943-1
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
400
900
MAX
UNITS
I2C Timing Characteristics
fSCL(MAX)
Maximum SCL Clock Frequency
l
tBUF(MAX)
Bus Free Time Between Stop/Start
l
1.3
µs
tSU(STA(MIN)) Minimum Repeated Start Set-Up
Time
l
600
ns
tHD(STA(MIN)) Minimum Hold Time (Repeated)
Start Condition
l
600
ns
tSU(STO(MIN)) Minimum Set-Up Time for Stop
Condition
l
600
ns
tSU(DAT(MIN)) Minimum Data Setup Time Input
l
100
ns
THD(DAT(MIN)) Minimum Data Hold Time Input
l
50
ns
THDDATO
Data Hold Time Input Output
TOF
Data Output Fall Time
(Notes 7, 8)
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 3. ISUPPLY = ISENSE+ + ISENSE–. In most operating modes, ISUPPLY is
flowing in SENSE+ pin. Only during ADC conversions, current is flowing in
SENSE– pin as well. Typically, ISENSE– = VSENSE–/150k during ADC voltage
conversion and ISENSE– = 20µA during ADC current conversion.
Note 4. The equivalent charge of an LSB in the accumulated charge
register depends on the value of RSENSE and the setting of the internal
prescaling factor M:
qLSB = 0.4mAh • (M/4096)
kHz
l
0.3
0.9
µs
l
20 + 0.1 • CB
300
ns
See Choosing Coulomb Counter Prescaler M section for more information.
1mAh = 3.6C (Coulombs)
Note 5. Deviation of qLSB from its nominal value.
Note 6. The quantization step of the 14-bit ADC in voltage mode,12-bit
ADC in current mode and 11-bit ADC in temperature mode is not the
same as the LSB of the respective combined 16-bit registers. See Voltage,
Current and Temperature Registers section for more information.
Note 7. CB = Capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).
Note 8. Guaranteed by design, not subject to test.
Note 9. See Effect of Differential Offset Voltage on Total Charge Error
section.
29431f
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LTC2943-1
Timing Diagram
tOF
SDA
tSU(DAT)
tBUF
tSU(STA)
tHD(DAT0)
tHD(DAT1)
tHD(STA)
tSU(STO)
29431 TD01
SCL
tHD(STA)
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 1. Definition of Timing on I2C Bus
Typical Performance Characteristics
Total Charge Error vs Sense
Current
VSENSE+ = 10V
1.0
CHARGE ERROR (%)
0.5
0
–0.5
–1.0
–1.5
–2.0
1.00
1.00
0.75
0.75
0.50
0.25
0
–0.25
1
10
100
|ISENSE| (mA)
1k
–1.00
0
5
29431 G01
10
15
VSENSE+ (V)
20
ISUPPLY (µA)
–40°C
–25
0
25
50
TEMPERATURE (°C)
75
100
29431 G03
Voltage Measurement ADC
Gain Error vs Temperature
0.75
0.50
85°C
25°C
15
–40°C
10
70
ISENSE = 1mA
–0.50
1.00
20
25°C
80
–0.25
29431 G02
25
100
90
0
Shutdown Supply Current vs
Supply Voltage
85°C
ISENSE = 200mA
0.25
–1.00
–50
25
30
110
0.50
–0.75
–0.75
120
ISUPPLY (µA)
ISENSE = 1A
–0.50
Supply Current vs Supply Voltage
0.25
0
–0.25
–0.50
5
60
50
ISENSE = 200mA
GAIN ERROR (%)
CHARGE ERROR (%)
1.5
Total Charge Error vs
Temperature
CHARGE ERROR (%)
2.0
Total Charge Error vs Supply
Voltage
0
5
10
15
VSENSE+ (V)
20
25
29431 G04
0
–0.75
0
5
10
15
VSENSE+ (V)
20
25
29431 G05
–1.00
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
29431 G06
29431f
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LTC2943-1
Typical Performance Characteristics
Voltage Measurement ADC
Integral Nonlinearity
1.00
4
3
0.75
3
0.50
2
0.25
1
GAIN ERROR (%)
TA = 85°C
1
0
–1
TA = 25°C
–2
TA = –40°C
–3
–4
0
5
10
15
VSENSE– (V)
20
INL (LSB)
4
2
INL (LSB)
Current Measurement ADC
Integral Nonlinearity
Current Measurement ADC
Gain Error vs Temperature
0
–0.25
–0.75
–3
–25
0
25
50
TEMPERATURE (°C)
75
900
1.5
800
VSENSE+ = 20V
0.5
NUMBER OF READINGS
TEMPERATURE ERROR (°C)
Temperature Error vs Temperature
VSENSE+ = 10V
0
–0.5
VSENSE+ = 5V
–1.0
–1.5
TA = –40°C
–4
–1000 –750 –500 –250 0 250 500 750 1000
ISENSE (mA)
100
29431 G08
29431 G07
TA = 85°C
–1
–2
2.0
1.0
0
–0.50
–1.00
–50
25
TA = 25°C
29431 G09
Voltage Measurement Noise
N = 800
700
600
500
400
300
200
100
–2.0
–50
–25
0
25
50
TEMPERATURE (°C)
75
0
100
–2
–1
0
LSB
1
2
29431 G11
29431 G10
Sense Resistor Stability
Current Measurement Noise
450
N = 800
400
–0.5
350
300
–1.0
250
–1.5
200
150
–2.0
100
–2.5
50
0
ACCELERATED LOAD LIFE TEST
DATA SCALED TO TAMB = 85°C,
ISENSE = 1A CONDITIONS
∆R/RO (%)
NUMBER OF READINGS
0
–3
–2
–1
0
LSB
1
2
3
–3.0
0
10
20
30
kHOURS
40
50
29431 G12
29431 G13
29431f
6
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LTC2943-1
Pin Functions
SENSE+ (Pin 1): Positive Current Sense Input and Power
Supply. Connect to the load and battery charger output.
VSENSE+ operating range is 3.6V to 20V. SENSE+ is also
an input to the ADC during current measurement. Bypass
to GND with a 1µF capacitor located as close to pin 1 and
pin 2 as possible.
GND (Pin 2, Pin 3, Pin 7): Device Ground. Connect directly
to the negative battery terminal.
SCL (Pin 4): Serial Bus Clock Input. SCL is internally pulled
up with 50µA (Typ) above its logic input high threshold
to about 2V (Typ).
SDA (Pin 5): Serial Bus Data Input and Output. SDA is
internally pulled up with 50µA (Typ) above its logic input
high threshold to about 2V (Typ).
ALCC (Pin 6): Alert Output or Charge Complete Input.
Configured either as an SMBus alert output or charge
complete input by control register bits B[2:1]. At power-up,
the pin defaults to alert mode conforming to the SMBus
alert response protocol. It behaves as an open-drain logic
output that pulls to GND when any threshold register value
is exceeded. When configured as a charge complete input,
connect to the charge complete output from the battery
charger circuit. A low level at CC sets the value of the
accumulated charge (registers C, D) to FFFFh.
SENSE– (Pin 8): Negative Current Sense Input. Connect
SENSE– to the positive battery terminal. Current from/
into this pin must not exceed 1A in normal operation.
SENSE– is also an input to the ADC during voltage and
current measurement.
Exposed Pad (Pin 9): Exposed pad may be left open or
connected to device ground (GND).
29431f
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7
LTC2943-1
Block Diagram
1
SENSE+
LTC2943-1
VSUPPLY
RBOND
12mΩ
CC
COULOMB COUNTER
REF
RSENSE
50mΩ
TEMPERATURE
SENSOR
ACCUMULATED
CHARGE
REGISTER
CLK
REFERENCE
GENERATOR
AL
I2C/
SMBUS
OSCILLATOR
F = 10kHz
ALCC
SCL
4
SDA
REF+
8
7
2
3
SENSE
RBOND
– 12mΩ
MUX
IN
6
5
CLK
ADC
DATA AND
CONTROL
REGISTERS
REF–
GND
GND
GND
29431 BD
Operation
Overview
Coulomb Counter
The LTC2943-1 is a battery gas gauge designed for use
with multicell batteries with terminal voltages from 3.6V
to 20V. It measures battery charge and discharge, battery
voltage, current and its own temperature.
Charge is the time integral of current. The LTC2943-1
measures charge by monitoring the voltage developed
across an internal sense resistor. The differential voltage
is applied to an auto-zeroed differential analog integrator
to infer charge.
A precision analog coulomb counter integrates current
through a sense resistor between the battery’s positive
terminal and the load or charger. Battery voltage, battery
current and silicon temperature are measured with an
internal ADC.
The integrated, temperature compensated sense resistor
offers board space savings and superior change measurement accuracy in applications with currents up to 1A.
When the integrator output ramps to REFHI or REFLO
levels, switches S1, S2, S3 and S4 toggle to reverse the
ramp direction (Figure 2). By observing the condition of
the switches and the ramp direction, polarity is determined.
This approach also significantly lowers the impact on offset
of the analog integrator as described in the Differential
Offset Voltage section.
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LTC2943-1
Operation
A programmable prescaler effectively increases integration
time by a factor M programmable from 1 to 4096. At each
underflow or overflow of the prescaler, the accumulated
charge register (ACR) value is incremented or decremented
one count. The value of accumulated charge is read via
the I2C interface.
Voltage, Current and Temperature ADC
The LTC2943-1 includes a 14-bit No Latency ΔΣ analogto-digital converter, with internal clock and voltage reference circuits.
The ADC can be used to monitor the battery voltage at
SENSE– or the battery current flowing through the sense
resistor or to convert the output of the on-chip temperature sensor.
Conversion of voltage, current and temperature are triggered by programming the control register via the I2C
interface. The LTC2943-1 includes a scan mode where
CHARGER
LOAD
1
SENSE+
6
S1
RBOND
IBAT
BATTERY
+
2
SENSE–
RBOND
GND
The temperature sensor generates a voltage proportional
to temperature with a slope of 2mV/K resulting in a voltage of 600mV at 27°C.
Power-Up Sequence
When SENSE+ rises above a threshold of approximately
3.3V, the LTC2943-1 generates an internal power-on reset
(POR) signal and sets all registers to their default state. In
the default state, the coulomb counter is active while the
voltage, current and temperature ADC is switched off. The
accumulated charge register is set to mid-scale (7FFFh),
all low threshold registers are set to 0000h and all high
threshold registers are set to FFFFh. The alert mode is
enabled and the coulomb counter prescaling factor M is
set to 4096.
REFHI
VCC
RSENSE
voltage, current and temperature conversion measurements are executed every 10 seconds. At the end of each
conversion the corresponding registers are updated and
the converter goes to sleep to minimize quiescent current.
–
+
CONTROL
LOGIC
–
S2
S3
M
PRESCALER
+
ACR
+
S4
REFLO
–
POLARITY
DETECTION
29431 F02
Figure 2. Coulomb Counter Section of the LTC2943-1
29431f
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9
LTC2943-1
Applications Information
Internal Registers
The LTC2943-1 register map is shown in Table 1. The
LTC2943-1 integrates current through a sense resistor,
measures battery voltage, current and temperature and
stores the results in internal 16-bit registers accessible
via I2C. High and low limits can be programmed for each
measured quantity. The LTC2943-1 continuously monitors
these limits and sets a flag in the status register when a
limit is exceeded. If the alert mode is enabled, the ALCC
pin pulls low.
Table 1. Register Map
ADDRESS NAME REGISTER DESCRIPTION
R/W
00h
A
Status
R
01h
B
Control
R/W
DEFAULT
See Table 2
3Ch
02h
C
Accumulated Charge MSB
R/W
7Fh
03h
D
Accumulated Charge LSB
R/W
FFh
04h
E
Charge Threshold High MSB
R/W
FFh
05h
F
Charge Threshold High LSB
R/W
FFh
06h
G
Charge Threshold Low MSB
R/W
00h
07h
H
Charge Threshold Low LSB
R/W
00h
08h
I
Voltage MSB
R
00h
09h
J
Voltage LSB
R
00h
0Ah
K
Voltage Threshold High MSB
R/W
FFh
0Bh
L
Voltage Threshold High LSB
R/W
FFh
0Ch
M
Voltage Threshold Low MSB
R/W
00h
0Dh
N
Voltage Threshold Low LSB
R/W
00h
0Eh
O
Current MSB
R
00h
0Fh
P
Current LSB
R
00h
10h
Q
Current Threshold High MSB
R/W
FFh
11h
R
Current Threshold High LSB
R/W
FFh
12h
S
Current Threshold Low MSB
R/W
00h
13h
T
Current Threshold Low LSB
R/W
00h
14h
U
Temperature MSB
R
00h
15h
V
Temperature LSB
R
00h
16h
W
Temperature Threshold High
R/W
FFh
17h
X
Temperature Threshold Low
R/W
00h
R = Read, W = Write
The status of the charge, voltage, current and temperature
alerts is reported in the status register shown in Table 2.
Table 2. Status Register (A)
BIT
NAME
OPERATION
A[7]
Reserved
A[6]
Current Alert
A[5]
Accumulated
Charge
Overflow/
Underflow
A[4]
Temperature
Alert
Indicates one of the
temperature limits was
exceeded
0
A[3]
Charge Alert
High
Indicates that the ACR value
exceeded the charge threshold
high limit
0
A[2]
Charge Alert
Low
Indicates that the ACR value
exceeded the charge threshold
low limit
0
A[1]
Voltage Alert
Indicates one of the voltage
limits was exceeded
0
A[0]
Undervoltage
Lockout Alert
Indicates recovery from
undervoltage. If set to 1, a
UVLO has occurred and the
contents of the registers are
uncertain
1
Indicates one of the current
limits was exceeded
Indicates that the value of the
ACR hit either top or bottom
DEFAULT
0
0
After each voltage, current or temperature conversion, the
conversion result is compared to the respective threshold
registers. If a value in the threshold registers is exceeded,
the corresponding bit A[6], A[4] or A[1] is set.
The accumulated charge register (ACR) is compared to
the charge thresholds every time the analog integrator
increments or decrements the prescaler. If the ACR value
exceeds the threshold register values, the corresponding
bit A[3] or A[2] are set. Bit A[5] is set if the accumulated
charge registers (ACR) overflows or underflows. At each
overflow or underflow, the ACR rolls over and resumes
integration.
The undervoltage lockout (UVLO) bit of the status register
A[0] is set if, during operation, the voltage on the SENSE+
pin drops below 3.5V without reaching the POR level. The
analog parts of the coulomb counter are switched off while
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LTC2943-1
Applications Information
the digital register values are retained. After recovery of the
supply voltage the coulomb counter resumes integrating
with the stored value in the accumulated charge registers
but it has missed any charge flowing while SENSE+ < 3.5V.
BIT
NAME
OPERATION
B[2:1]
ALCC
Configure
Configures the ALCC pin
[01] Charge Complete Mode. Pin
becomes logic input and accepts
charge complete inverted signal
(e.g., from a charger) to set
accumulated charge register (C,D)
to FFFFh
Control Register (B)
[00] ALCC pin disabled
[11] Not allowed
The operation of the LTC2943-1 is controlled by programming the control register. Table 3 shows the organization
of the 8-bit control register B[7:0].
B[0]
Table 3. Control Register B
Power Down B[0]
BIT
NAME
OPERATION
B[7:6]
ADC Mode
[11] Automatic Mode:
continuously performing
voltage, current and temperature
conversions
DEFAULT
[00]
[10] Scan Mode: performing
voltage, current and temperature
conversion every 10s
[01] Manual Mode: performing
single conversions of voltage,
current and temperature then
sleep
Sets coulomb counter prescaling
factor M between 1 and 4096.
Default is 4096.
Maximum value is limited to 4096
B[5:3]
M
000
1
001
4
010
16
011
64
100
256
101
1024
110
4096
111
4096
Shutdown
Shut down analog section to
reduce ISUPPLY
[0]
Setting B[0] to 1 shuts down the analog parts of the
LTC2943-1, reducing the current consumption to less than
15μA (typical). The circuitry managing I2C communication remains operating and the values in the registers are
retained. Note that any charge flowing while B[0] is 1 is
not measured and any charge information below 1LSB of
the accumulated charge register is lost.
Alert/Charge Complete Configuration B[2:1]
[00] Sleep
Prescaler M
[10]
[10] Alert Mode.
Alert functionality enabled. Pin
becomes logic output
All status register bits are cleared after being read by the
host, but might be reasserted after the next temperature,
voltage or current conversion or charge integration, if the
corresponding alert condition is still fulfilled.
B[5:3]
DEFAULT
[111]
The ALCC pin is a dual function pin configured by the
control register. By setting bits B[2:1] to [10] (default),
the ALCC pin is configured as an alert pin following the
SMBus protocol. In this configuration, the ALCC is pulled
low if one of the four measured quantities (charge, voltage,
current, temperature) exceeds its high or low threshold or
if the value of the accumulated charge register overflows
or underflows. An alert response procedure started by the
master resets the alert at the ALCC pin. If the configuration of the ALCC pin is changed while it is pulled low due
to an alert condition, the part will continue to pull ALCC
low until a successful alert response procedure (ARA) has
been issued by the master. For further information see the
Alert Response Protocol section.
Setting the control bits B[2:1] to [01] configures the
ALCC pin as a digital input. In this mode, a low input on
the ALCC pin indicates to the LTC2943-1 that the battery
is full and the accumulated charge register is set to its
maximum, value FFFFh.
29431f
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11
LTC2943-1
Applications Information
If neither the alert nor the charge complete functionality
is desired, bits B[2:1] should be set to [00]. The ALCC
pin is then disabled and should be tied to the supply of
the I2C bus with a 10k resistor.
Avoid setting B[2:1] to [11] as it enables the alert and the
charge complete modes simultaneously.
Choosing Coulomb Prescaler M B[5:3]
If the battery capacity (QBAT) is small compared to the
maximum current (IMAX) the prescaler value M should
be changed from its default value (4096).
In these applications with a small battery but a high
maximum current, qLSB can get quite large with respect
to the battery capacity. For example, if the battery capacity
is 100mAh and the maximum current is 1A, the default
value M = 4096 leads to:
qLSB = 0.4mAh
The battery capacity then corresponds to only 250 qLSB
and less than 0.5% of the accumulated charge register
is utilized.
To preserve digital resolution in this case, the LTC2943-1
includes a programmable prescaler. Lowering the prescaler
factor M reduces qLSB to better match the accumulated
charge register to the capacity of the battery. The prescaling
factor M can be chosen between 1 and its default value
of 4096. The charge LSB then becomes:
qLSB = 0.4mAh •
M
4096
To use as much of the range of the accumulated charge
register as possible the prescaler factor M should be
chosen for a given battery capacity QBAT and a sense
resistor RSENSE as:
M≥ 4096 •
16
QBAT
2 • 0.4mAh
M can be set to 1, 4, 16, ... 4096 by programming B[5:3]
of the control register as M = 22•(4 • B[5] + 2 • B[4] + B[3]) .
The default value is 4096.
In the above example of a 100mAh battery, the prescaler
should be programmed to M = 64. The qLSB is then 6.25μAh
and the battery capacity corresponds to 16000 qLSBs.
ADC Mode B[7:6]
The LTC2943-1 features an ADC which measures either
voltage on SENSE– (battery voltage), current through
SENSE+ and SENSE– (battery current) or temperature via
an internal temperature sensor. The reference voltage and
clock for the ADC are generated internally.
The ADC has four different modes of operation as shown
in Table 3. These modes are controlled by bits B[7:6] of
the control register. At power-up, bits B[7:6] are set to
[00] and the ADC is in sleep mode.
A single conversion of the three measured quantities
is initiated by setting the bit B[7:6] to [01]. After three
conversions (voltage, current and temperature), the ADC
resets B[7:6] to [00] and goes back to sleep.
The LTC2943-1 is set to scan mode by setting B[7:6] to
[10]. In scan mode the ADC converts voltage, current,
then temperature, then sleeps for approximately 10 seconds. It then reawakens automatically and repeats the
three conversions. The chip remains in scan mode until
reprogrammed by the host.
Programming B[7:6] to [11] sets the chip into automatic
mode where the ADC continuously performs voltage,
current and temperature conversions. The chip stays in
automatic mode until reprogrammed by the host.
Programming B[7:6] to [00] puts the ADC to sleep. If
control bits B[7:6] change within a conversion, the ADC
will complete the running cycle of conversions before
entering the newly selected mode.
A conversion of voltage requires 33ms (typical), and current and temperature conversions are completed in 4.5ms
(typical). At the end of each conversion, the corresponding
registers are updated. If the converted quantity exceeds
the values programmed in the threshold registers, a flag
is set in the status register and the ALCC pin is pulled low
(if alert mode is enabled).
29431f
12
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LTC2943-1
Applications Information
Alert Thresholds Registers (E,F,G,H,K,L,M,N,Q,R,S,
T,W,X)
For each of the measured quantities (battery charge, voltage, current and temperature) the LTC2943-1 features
high and low threshold registers. At power-up, the high
thresholds are set to FFFFh while the low thresholds are set
to 0000h, with the effect of disabling them. All thresholds
can be programmed to a desired value via I2C. As soon as
a measured quantity exceeds the high threshold or falls
below the low threshold, the LTC2943-1 sets the corresponding flag in the status register and pulls the ALCC
pin low if alert mode is enabled via bits B[2:1].
Accumulated Charge Register (C,D)
Example 1: a register value I[7:0] = B0h and J[7:0] = 1Ch
corresponds to a voltage on SENSE– of:
VSENSE– = 23.6V •
B01Ch
45084DEC
= 23.6V •
≈ 16.235V
FFFFh
65535
Example 2: To set a low level threshold for the battery
voltage of 7.2V, register M should be programmed to 4Eh
and register N to 1Ah.
Current Registers (O,P) and Current Threshold
Registers (Q,R,S,T)
The result of the current conversion is stored in the current registers (O,P).
As the ADC resolution is 12 bits in current mode, the
lowest four bits of the combined current registers (O, P)
are always zero.
The coulomb counting circuitry in the LTC2943-1 integrates
current through the sense resistor. The result of this charge
integration is stored in the 16-bit accumulated charge register (registers C, D). As the LTC2943-1 does not know the
actual battery status at power-up, the accumulated charge
register (ACR) is set to mid-scale (7FFFh). If the host knows
the status of the battery, the accumulated charge (C[7:0]
D[7:0]) can be either programmed to the correct value via
I2C or it can be set after charging to FFFFh (full) by pulling
the ALCC pin low if charge complete mode is enabled via
bits B[2:1]. Note that before writing to the accumulated
charge registers, the analog section should be temporarily
shut down by setting B[0] to 1. In order to avoid a change
in the accumulated charge registers between reading MSBs
C[7:0] and LSBs D[7:0], it is recommended to read them
sequentially as shown in Figure 9.
The ADC measures battery current by converting the voltage, VSENSE, across the sense resistor RSENSE. Depending
on whether the battery is being charged or discharged, the
measured voltage drop on RSENSE is positive or negative.
The result is stored in registers O and P in excess –32767
representation. O[7:0] = FFh, P[7:0] = FFh corresponds to
the full-scale positive current 1.3A. While O[7:0] = 00h,
P[7:0] = 00h corresponds to the full-scale negative current
–1.3A. The battery current can be obtained from the two
byte register O[7:0]P[7:0] and the value of the chosen
sense resistor RSENSE:
Voltage Registers (I,J) and Voltage Threshold
Registers (K,L,M,N)
RESULTDEC – 32767
1.3A •
32767
The result of the 14-bit ADC conversion of the voltage at
SENSE– is stored in the voltage registers (I, J).
From the result of the 16-bit voltage registers I[7:0]J[7:0]
the measured voltage can be calculated as:
VSENSE– = 23.6V •
RESULTh – 7FFF h
IBAT =1.3A •
=
7FFF h
Positive current is measured when the battery is charging and negative current is measured when the battery is
discharging.
RESULTh
RESULTDEC
= 23.6V •
FFFFh
65535
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13
LTC2943-1
Applications Information
Example 1: a register value of O[7:0] = A8h P[7:0] = 40h
together with a sense resistor RSENSE = 50mΩ corresponds
to a battery current:
A840 h – 7FFF h
IBAT =1.3A •
=
7FFF h
The actual temperature can be obtained from the two byte
register U[7:0]V[7:0] by:
T = 510K •
RESULTDEC
RESULTh
= 510K •
FFFFh
65535
Example: a register value of U[7:0] = 96h, V[7:0] = 96h
corresponds to ~300K or ~27°C
43072 – 32767
1.3A •
≈ 314.5mA
32767
The positive current result indicates that the battery is
being charged.
The values in the threshold register for the current mode
Q,R,S,T are also expressed in excess –32767 representation in the same manner as the current conversion result.
The alert after a current measurement is set if the result
is higher than the value stored in the high threshold registers Q,R or lower than the value stored in the low value
registers S,T.
Example 2: In an application, the user wants to get an alert
if the absolute current through the sense resistor, exceeds
1A. This is achieved by setting the upper threshold IHIGH
in register [Q,R] to 1A and the lower threshold ILOW in
register [S,T] to –1A. The formula for IBAT leads to:
1A
IHIGH (DEC) =
• 32767 + 32767= 57972
1.3A
–1A
• 32767 + 32767= 7562
ILOW (DEC) =
1.3A
Leading the user to set Q[7:0] = E2h, R[7:0] = 74h for the
high threshold and S[7:0] = 1Dh and T[7:0] = 8Ah for the
low threshold.
Temperature Registers (U,V) and Temperature
Threshold Registers (W,X)
As the ADC resolution is 11 bits in temperature mode, the
lowest five bits of the combined temperature registers
(U, V) are always zero.
A high temperature limit of 60°C is programmed by setting
register W to A7h. Note that the temperature threshold
register is a single byte register and only the eight MSBs
of the 11 bits temperature result are checked.
Effect of Differential Offset Voltage on Total Charge
Error
In battery gas gauges, an important parameter is the
differential offset (IOS) of the circuitry monitoring the battery charge. Many coulomb counter devices perform an
analog to digital conversion of ISENSE and accumulate the
conversion results to infer charge. In such an architecture,
the differential offset IOS causes relative charge error of
IOS/ISENSE. For small ISENSE values IOS can be the main
source of error.
The LTC2943-1 performs the tracking of the charge with
an analog integrator. This approach allows to continuously
monitor the battery charge and significantly lowers the
error due to differential offset. The relative charge error
due to offset (CEOV) can be expressed by:
CE OV
IOS 2
=
ISENSE
As an example, at a 20mA input signal, a differential voltage offset VOS = 20µV results in a 2% error using digital
integration, whereas the error is only 0.04% (a factor of
50 times smaller!) using the analog integration approach
of LTC2943-1.
29431f
14
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LTC2943-1
Applications Information
The reduction of the impact of the offset in LTC2943-1 can
be explained by its integration scheme depicted in Figure 2.
While positive offset accelerates the up ramping of the
integrator output from REFLO to REFHI, it slows the down
ramping from REFHI to REFLO thus the effect is largely
canceled as depicted below.
INTEGRATOR
OUTPUT
REFHI
WITHOUT OFFSET
WITH OFFSET
REFLO
FASTER
UP RAMPING
SLOWER
DOWN RAMPING
TIME
29431 F0B
For input signals with an absolute value smaller than the
offset of the internal op amp, the LTC2943-1 stops integrating and does not integrate its own offset.
I2C/SMBus Interface
The LTC2943-1 communicates with a bus master using a
2-wire interface compatible with I2C and SMBus. The 7-bit
hard coded I2C address of the LTC2943-1 is 1100100.
The LTC2943-1 is a slave only device. The serial clock
line (SCL) is input only while the serial data line (SDA) is
bidirectional. The device supports I2C standard and fast
mode. For more details refer to the I2C Protocol section.
SDA
a6 - a0
SCL
1-7
8
9
ADDRESS
R/W
ACK
I2C Protocol
The LTC2943-1 uses an I2C/SMBus-compatible 2-wire
interface supporting multiple devices on a single bus.
Connected devices can only pull the bus lines low and
must never drive the bus high. The bus wires are externally
connected to a positive supply voltage via current sources
or pull-up resistors. When the bus is idle, all bus lines are
high. Data on the I2C bus can be transferred at rates of
up to 100kbit/s in standard mode and up to 400kbit/s in
fast mode.
Each device on the I2C/SMbus is recognized by a unique
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be classified as masters or slaves when performing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. At the same time any device addressed is considered a slave. The LTC2943-1 always
acts as a slave.
Figure 3 shows an overview of the data transmission on
the I2C bus.
Start and Stop Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with
a START condition by transitioning SDA from high to low
while SCL is high. When the master has finished com-
b7 - b0
1-7
b7 - b0
8
9
1-7
8
9
S
START
CONDITION
P
DATA
ACK
DATA
ACK
STOP
CONDITION
29431 F03
Figure 3. Data Transfer Over I2C or SMBus
29431f
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15
LTC2943-1
Applications Information
municating with the slave, it issues a STOP condition by
transitioning SDA from low to high while SCL is high. The
bus is then free for another transmission. When the bus
is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START
(Sr) conditions are functionally identical to the START (S).
master continues by sending a second data byte instead
of a stop, the LTC2943-1 acknowledges again, increments
its address pointer and latches the second data byte in the
following register, as shown in Figure 5.
S
ADDRESS
W
A
REGISTER
A
DATA
A
DATA
A
1100100
0
0
02h
0
F0h
0
01h
0
Write Protocol
29431 F05
Figure 5. Writing F001h to the LTC2943-1 Accumulated
Charge Register (C, D)
The master begins a write operation with a START condition followed by the seven bit slave address 1100100
and the R/W bit set to zero, as shown in Figure 4. The
LTC2943-1 acknowledges this by pulling SDA low and
the master sends a command byte which indicates which
internal register the master is to write. The LTC2943-1
acknowledges and latches the command byte into its
internal register address pointer. The master delivers the
data byte, the LTC2943-1 acknowledges once more and
latches the data into the desired register. The transmission
is ended when the master sends a STOP condition. If the
S
P
ADDRESS
W
A
REGISTER
A
DATA
A
1100100
0
0
01h
0
FCh
0
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address 1100100 and the
R/W bit set to zero, as shown in Figure 6. The LTC29431 acknowledges and the master sends a command byte
which indicates which internal register the master is to
read. The LTC2943-1 acknowledges and then latches the
command byte into its internal register address pointer.
The master then sends a repeated START condition followed by the same seven bit address with the R/W bit
now set to one. The LTC2943-1 acknowledges and sends
the contents of the requested register. The transmission
is ended when the master sends a STOP condition. If
the master acknowledges the transmitted data byte, the
LTC2943-1 increments its address pointer and sends the
contents of the following register as depicted in Figure 7.
P
29431 F04
FROM MASTER TO SLAVE
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
FROM SLAVE TO MASTER
S: START CONDITION
P: STOP CONDITION
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
Figure 4. Writing FCh to the LTC2943-1 Control Register (B)
S
ADDRESS
W
A
REGISTER
A
1100100
0
0
00h
0
Sr
ADDRESS
R
A
DATA
A
1100100
1
0
01h
1
P
29431 F06
Figure 6. Reading the LTC2943-1 Status Register (A)
S
ADDRESS
W
A
REGISTER
A
1100100
0
0
08h
0
Sr
ADDRESS
R
A
DATA
A
DATA
A
1100100
1
0
F1h
0
24h
1
P
29431 F07
Figure 7. Reading the LTC2943-1 Voltage Register (I, J)
29431f
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LTC2943-1
Applications Information
Alert Response Protocol
In a system where several slaves share a common interrupt
line, the master can use the alert response address (ARA)
to determine which device initiated the interrupt (Figure 8).
S
ALERT RESPONSE ADDRESS
R
A
DEVICE ADDRESS
A
0001100
1
0
1100100
1
P
29431 F08
Figure 8. LTC2943-1 Serial Bus SDA Alert Response Protocol
S ADDRESS W A REGISTER A S ADDRESS R A DATA A DATA A P
1100100 0 0
02h
1100100 1 0 80h 0 01h 1
0
2943 F09
Figure 9. Reading the LTC2943-1 Accumulated Charge
Registers (C, D)
S ADDRESS W A REGISTER A DATA P
1100100 0 0
01h
0
4C
40ms
S ADDRESS W A REGISTER A S ADDRESS R A DATA A DATA A P
1100100 0 0
08h
0
1100100 1 0 F1h 0 80h 1
2943 F10
Figure 10. ADC Single Conversion Sequence and Reading
of Voltage Registers (I,J)
The master initiates the ARA procedure with a START
condition and the special 7-bit ARA bus address (0001100)
followed by the read bit (R) = 1. If the LTC2943-1 is asserting the ALCC pin in alert mode, it acknowledges and
responds by sending its 7-bit bus address (1100100) and
a 1. While it is sending its address, it monitors the SDA pin
to see if another device is sending an address at the same
time using standard I2C bus arbitration. If the LTC2943-1
is sending a 1 and reads a 0 on the SDA pin on the rising
edge of SCL, it assumes another device with a lower address is sending and the LTC2943-1 immediately aborts
its transfer and waits for the next ARA cycle to try again.
If transfer is successfully completed, the LTC2943-1 will
stop pulling down the ALCC pin and will not respond to
further ARA requests until a new Alert event occurs.
Internal Sense Resistor
The internal sense resistor uses proprietary temperature
compensation techniques to reduce the effective temperature coefficient to less than ±50 ppm/K typically.
The effective sense resistance as seen by the coulomb
counter is factory trimmed to 50mΩ. Both measures,
and the lack of thermocouple effects in the sense resistor connections, contribute to the LTC2943-1’s superior
charge measurement accuracy compared to competing
solutions employing a common 1% tolerance, 50ppm/K
tempco discrete current sense resistor.
Like all sense resistors, the integrated sense resistor in
the LTC2943-1 will exhibit minor long-term resistance
shift. The resistance typically drops less than –0.1% per
1000h at 1A current and 85°C ambient temperature; this
outperforms most types of discrete sense resistors except
those of the very high and ultrahigh stability variety. See
the Typical Performance Characteristics for expected
resistor drift performance under worst-case conditions.
Drift will be much slower at lower temperatures. Contact
LTC applications for more information.
For most coulomb counter applications this aging behavior
of the integrated sense resistor is insignificant compared
to the change of battery capacity due to battery aging.
The LTC2943-1 is factory trimmed to optimum accuracy
when new; for applications which require the best possible
coulomb count accuracy over the full product lifetime, the
coulomb counter gain can be adjusted in software. For
instance, if the error contribution of sense resistor drift
must be limited to ±1%, coulomb counts may be biased
high by 1% (use factor 1.01), and maximum operational
temperature and current then must be derated such that
sense resistor drift over product lifetime or calibration
intervals is less than –2%.
Applications employing the standard external resistor
LTC2943 with an external 50mΩ sense resistor may be
upgraded to the pin-compatible LTC2943-1 by removing
the external sense resistor.
29431f
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17
LTC2943-1
Applications Information
Voltage Drop Between SENSE+ and SENSE–
Power Dissipation
The LTC2943-1 is trimmed for an effective internal resistance of 50mΩ , but the total pin-to-pin resistance (RPP),
consisting of the sense resistor in series with pin and bond
wire resistances, is somewhat higher. Assuming a sense
resistor temperature coefficient of about 3900ppm/K,
the total resistance between SENSE+ and SENSE– at a
temperature T is typically:
Power dissipation in the RPP resistance when operated
at high currents can increase the die temperature several degrees over ambient. Soldering the exposed pad
of the DFN package to a large copper region on the PCB
is recommended for applications operating close to the
specified maximum current and ambient temperature. Die
temperature at a given ISENSE can be estimated by:
RPP(T) = RPP(TNOM) [1 + 0.0039(T – TNOM)]
TDIE = TAMB + 1.22 • θJA • RPP(MAX) • ISENSE2
where TNOM = 27°C (or 300K) and RPP(TNOM) is from
the Electrical Characteristics table. This means that the
resistance between SENSE+ and SENSE– may drop by
26% if die temperature changes from 27°C to –40°C
or increase by 23% for a 27°C to 85°C die temperature
change. Ensure that total voltage drop between SENSE+
and SENSE–, caused by maximum peak current flowing
in/out of SENSE–:
where the factor 1.22 approximates the effect of sense
resistor self-heating, RPP(MAX) is the maximum pad-topad resistance at nominal temperature (27°C) and θJA is
the thermal resistance from junction to ambient. The θJA
data given for the DFN package is valid for typical PCB
layouts; more precise θJA data for a particular PCB layout
may be obtained by measuring the voltage VP-P between
SENSE+ and SENSE–, the ambient temperature TAMB, and
the die temperature TDIE, and calculating:
VDROP = IPEAK • RPP(TDIE(MAX))
does not exceed the application’s requirements.
Limiting Inrush Current
Inrush currents during events like battery insertion or
closure of a mechanical power switch may be substantially higher than peak currents during normal operation.
Extremely large inrush currents may require additional
circuitry to keep currents through the LTC2943-1 sense
resistor below the absolute maximum ratings.
Note that external Schottky clamp diodes between SENSE+
and SENSE– can leak significantly, especially at high tem-
perature, which can cause significant coulomb counter
errors. Preferred solutions to limit inrush current include
active Hot Swap current limiting or connector designs that
include current limiting resistance and staggered pins to
ensure a low impedance connection when the connector
is fully mated.
θJA =
TDIE – TAMB
VP-P • ISENSE
Both TAMB and TDIE temperature may be measured using
the internal temperature sensor included in the LTC2943-1.
ISENSE should be set to zero to measure TAMB, and high
enough during TDIE measurement to achieve a significant
temperature increase over TAMB.
PC Board Layout Suggestions
Keep all traces as short as possible to minimize noise and
inaccuracy. Use wider traces from the resistor to the battery, load and/or charger (see Figure 11). Put the bypass
capacitor close to SENSE+.
TO
CHARGER/LOAD
C
2
TO BATTERY
8
1
LTC2943-1
7
3
6
4
5
29431 F11
Figure 11. Recommended Layout
29431f
18
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LTC2943-1
Package Description
Please refer to http://www.linear.com/product/LTC2943-1#packaging for the most recent package drawings.
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
0.70 ±0.05
3.5 ±0.05
1.65 ±0.05
2.10 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.00 ±0.10
(4 SIDES)
R = 0.125
TYP
5
0.40 ± 0.10
8
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
4
0.25 ± 0.05
1
(DD8) DFN 0509 REV C
0.50 BSC
2.38 ±0.10
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
29431f
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19
LTC2943-1
Typical Application
2-Cell 8.4V Linear Charger and Battery Gas Gauge
VIN = 10V
MBRM120T3
R1
1k
R2
1k
3
2
8
SEL
VCC
SENSE
DRV
CHRG
9
Q1
Si7135DP
7
LTC1732-8.4
10
4
ACPR
BAT
TIMER
CTIMER
0.1µF
PROG
IBAT = 500mA
1
6
GND
C1
1µF
RSENSE
0.25Ω
RPROG*
19.6k
C2
10µF
0.5A
LOAD
3.3V
R3
2k
R4
2k
R5
2k
C3
1µF
LTC2943-1
VDD
ALCC
µP
SDA
SCL
SENSE+
SENSE–
GND
+
8.4V
Li-Ion
BATTERY
2943 TA02
Related Parts
PART
NUMBER
DESCRIPTION
COMMENTS
Battery Gas Gauges
LTC2941
Battery Gas Gauge with I2C Interface
2.7V to 5.5V Operation, 6-Lead (2mm × 3mm) DFN Package
LTC2941-1
1A I2C Battery Gas Gauge with Internal Sense
2.7V to 5.5V Operation, 6-Lead (2mm × 3mm) DFN Package
LTC2942
I2C Battery Gas Gauge with Temperature/Voltage
Measurement
2.7V to 5.5V Operation, 14-Bit Δ∑-ADC, 6-Lead (2mm × 3mm) DFN Package
LTC2942-1
1A I2C Battery Gas Gauge with Internal Sense
Resistor and Temperature/Voltage Measurement
2.7V to 5.5V Operation, 14-Bit Δ∑-ADC, 6-Lead (2mm × 3mm) DFN Package
LTC2943
Battery Gas Gauge with I2C Interface and Voltage,
Current and Temperature ADC
3.6V to 20V Operation, 14-Bit ∆∑-ADC, Pin Compatible with LTC2944, LTC2943-1, or
LTC2943, 8-Lead (3mm × 3mm) DFN Package
LTC4150
Coulomb Counter/Battery Gas Gauge
2.7V to 8.5V Operation, 10-Pin MSOP Package
Resistor
Battery Chargers
LTC4000
High Voltage High Current Controller for Battery
Charging and Power Management
3V to 60V Operation, 28-Lead (4mm × 5mm) QFN or SSOP Packages
LTC4009
High Efficiency, Multi-Chemistry Battery Charger
6V to 28V Operation, 20-Lead (4mm × 4mm) QFN Package
LTC4012
High Efficiency, Multi-Chemistry Battery Charger
with PowerPath™ Control
6V to 28V Operation, 20-Lead (4mm × 4mm) QFN Package
LT3652HV
Power Tracking 2A Battery Charger
Input Supply Voltage Regulation Loop for Peak Power Tracking, 5V to 34V Operation,
1MHz, 2A Charge Current, 3mm × 3mm DFN-12 and MSOP-12 Packages
LTC1732
Li-Ion Battery Charger
4.5V to 12V Operation, MSOP-10 Package
29431f
20 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2943-1
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2943-1
LT 1215 • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2015