LTC3305
Lead-Acid Battery Balancer
FEATURES
DESCRIPTION
Single IC Balances Up to Four 12V Lead-Acid
Batteries in Series
n All NFET Design
n Stackable to Balance Larger Series Battery Packs
n Standalone Balancing Operation: Requires No
External μP or Additional Control Circuitry
n Balancing Current Limited by External PTC Thermistor
n Continuous Mode and Timer Mode
n Programmable UV and OV Fault Thresholds
n Programmable Termination Time and Termination
Voltage
n Thermally Enhanced 38-Lead TSSOP Package
The LTC®3305 balances up to 4 lead-acid batteries
connected in series. It is intended to be used in conjunction
with a separate pre-existing battery charger as part of a
high performance battery system. All voltage monitoring,
gate drive, and fault detection circuitry is integrated.
n
APPLICATIONS
n
n
n
n
n
Telecom Backup Systems
Home Battery Powered Backup Systems
Industrial Electric Vehicles
Energy Storage Systems (ESS)
Medical Equipment
The LTC3305 employs an auxiliary battery or an alternative
storage cell to transfer charge to or from each individual
battery in the stack. A mode pin provides two operating
modes, timer mode and continuous mode. In timer mode,
once the balancing operation is completed, the LTC3305
goes into a low power state for a programmed time and then
periodically rebalances the batteries. In continuous mode,
the balancing operation continues even after the batteries
are balanced to their programmed termination voltage.
The LTC3305 is available in a thermally enhanced 38-lead
TSSOP package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
4-Battery Balancer with Programmed High and Low Battery Voltage Faults
10µF
25V
1µF
6V
100k EACH
10nF
100nF
10nF
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
CTON
CP
BOOST
NGATE4
6.04k
NGATE3
10µF
25V
CTOFF
3.01k
V2
NGATE2
10µF
25V
V1
6.04k
NGATE6
10µF
25V
CTBAT
NGATE1-9
6.04k
42.2k
AUXN
ISET
NGATE1
6.04k
+
+
+
BAT3
BAT2
BAT1
NGATE7
6.04k
PTC
VH
16
BAT4
9
27.4k
AUXP
+
Battery Voltages Converge
Over Time
BATTERY
STACK
CHARGER
14
V3
LTC3305
ICHARGE
6.04k
10µF
25V
VL
12.1k
NGATE5
10µF
25V
V4
CHARGER
SUPPLY
1.33k
249Ω
10µF
25V
+
BATTERY VOLTAGE (V)
VREG CM
EN1
EN2
MODE
TERM1
TERM2
12
10
8
6
4
BATTERY 1
BATTERY 2
BATTERY 3
BATTERY 4
2
0
TIME
3305 TA01a
AUX
6.04k
NGATE8
GND
3305 TA01
6.04k
NGATE9
3305fb
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1
LTC3305
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
Stack Voltage, V4 to GND..........................................68V
Battery Voltages, V4 to V3, V3 to V2, V2 to V1,
V1 to GND................................................... –0.3V to 20V
Auxiliary Cell Voltage, AUXP to AUXN......... –0.3V to 20V
VREG Voltage................................................. –0.3V to 6V
VH, VL Voltage...... –0.3V to Lesser of 6V or (VREG+0.3V)
UVFLT, OVFLT, PTCFLT, BAL, DONE, BATX,
BATY Voltage................................................ –0.3V to 6V
EN1, EN2, MODE, TERM1, TERM2
Voltage................. –0.3V to Lesser of 6V or (VREG+0.3V)
NGATE1, NGATE2, NGATE3, NGATE4, NGATE8, NGATE9
Voltage............... –0.3V to Lesser of 68V or (V4+0.3V)
NGATE5, NGATE6, NGATE7
Voltage............... (Greater of –0.3V or BOOST–68V) to
(BOOST+0.3V)*
UVFLT, OVFLT, PTCFLT, BAL, DONE, BATX,
BATY Current..........................................................10mA
ISET Current...............................................................1mA
CP, CM Current.......................................................50mA
Operating Junction Temperature Range
(Notes 2, 3)............................................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
TOP VIEW
BOOST
1
38 CM
V4
2
37 CP
V3
3
36 NC
AUXP
4
35 MODE
AUXN
5
34 EN1
V2
6
33 EN2
V1
7
32 TERM1
NGATE1
8
31 TERM2
NGATE2
9
30 VREG
NGATE3 10
NGATE4 11
39
GND
29 ISET
28 VH
NGATE5 12
27 VL
NGATE6 13
26 CTBAT
NGATE7 14
25 CTON
NGATE8 15
24 CTOFF
NGATE9 16
23 PTCFLT
BATX 17
22 DONE
BATY 18
21 BAL
OVFLT 19
20 UVFLT
FE PACKAGE
38-LEAD PLASTIC TSSOP
θJA = 28°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
NC = No Connect
*The BOOST voltage is generated by the LTC3305 and is typically 8.45V higher than V4.
ORDER INFORMATION
(http://www.linear.com/product/LTC3305#orderinfo)
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3305EFE#PBF
LTC3305EFE#TRPBF
LTC3305 FE
38-Lead Plastic TSSOP
–40ºC to 125°C
LTC3305IFE#PBF
LTC3305IFE#TRPBF
LTC3305 FE
38-Lead Plastic TSSOP
–40ºC to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
3305fb
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LTC3305
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) V1 = 13.2V, V2 = 26.4V, V3 = 39.6V, V4 = 52.8V,
AUXP - AUXN = 13.2V, RISET = 12.1kΩ
SYMBOL
PARAMETER
VBAT
Individual Battery Voltage
CONDITIONS
MIN
l
TYP
4
MAX
UNITS
16
V
64
V
2.6
V
V4
Voltage at the Top of the Battery Stack
l
12
VREG
Regulator Output Voltage
IVREG = 200µA
l
2.4
2.5
VREG,UV
Regulator Undervoltage Threshold
Regulator Voltage Falling
l
1.7
2.1
V
125
mV
Maximum Guaranteed Load Current
VREG > VREG,UV
l
3
Regulator Short Circuit Current Limit
VREG = 0V
Shutdown Current
Measured at V4, BOOST-V4 = 0V
Measured at V3, V2, V1, AUXP, BOOST
Hysteresis
mA
8
15
22
mA
16
33
0
50
1
µA
µA
l
Supply Current While Balancing Battery 1
(Notes 4, 5)
Measured at V4
Measured at V3
Measured at V2
Measured at V1
900
0
0
150
1350
1
1
225
µA
µA
µA
µA
Supply Current While Balancing Battery 2
(Notes 4, 5)
Measured at V4
Measured at V3
Measured at V2
Measured at V1
900
0
150
–45
1350
1
225
µA
µA
µA
µA
900
150
–45
0
1350
225
µA
µA
µA
µA
1050
–45
0
0
1575
165
–130
245
µA
µA
100
0
150
1
µA
µA
220
330
µA
Supply Current While Balancing Battery 3
(Notes 4, 5)
–70
Measured at V4
Measured at V3
Measured at V2
Measured at V1
Supply Current While Balancing Battery 4
(Notes 4, 5)
Measured at V4
Measured at V3
Measured at V2
Measured at V1
Supply Current While Balancing any Battery
Measured at AUXP
Measured at AUXN
Supply Current in OFF State (MODE = 0)
Measured at V4, BOOST-V4 = 0V
Measured at V3, V2, V1, AUXP, BOOST
–70
–70
–195
Boost Pin Current While Balancing any Battery
(Notes 4, 5)
1
1
1
µA
µA
µA
µA
VISET
ISET Servo Voltage
50µA< IISET< 150µA
l
1.18
1.2
1.22
V
IVH, IVL
Current Out of VH and VL Pins
IISET = 100µA
l
31.3
33.3
35.3
µA
INGATE
Current For External NMOS Turn On (Note 5)
NGATE3 Current, IISET = 100µA
All Other NGATE Currents, IISET = 100µA
EN1 = EN2 = 0
l
l
l
2.0
1.0
–2
2.2
1.1
2.4
1.2
2
mA
mA
µA
NGATE3 Current
All Other NGATE Currents
l
l
1
0.5
3
1.5
mA
mA
l
l
3.9
15.6
4.1
16.4
V
V
Leakage Current in Shutdown
Current Programmable Range
VBAT,UV
Undervoltage Falling Battery Threshold (Note 6) VL = 0.4V
VL = 1.6V
Undervoltage Hysteresis
120
Undervoltage Falling Programmable Range
VBAT,OV
4
16
Overvoltage Rising Battery Threshold (Note 6)
VH = 0.4V
VH = 1.6V
l
4
l
l
3.9
15.6
Overvoltage Hysteresis
4
16
mV
16
V
4.1
16.4
V
V
150
Overvoltage Rising Programmable Range
l
4
mV
16
V
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3
LTC3305
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) V1 = 13.2V, V2 = 26.4V, V3 = 39.6V, V4 = 52.8V,
AUXP - AUXN = 13.2V, RISET = 12.1kΩ
SYMBOL
PARAMETER
CONDITIONS
MIN
PTC Fault Threshold
|BAT-AUXP| Falling
0.8
Hysteresis
VTERMINATE
TYP
MAX
1
1.2
100
l
l
l
l
5.0
17.5
40
85
12.5
25
50
100
20.0
32.5
60
115
Minimum (BOOST-V4) Voltage for Operation
l
6.7
6.95
7.2
180
Maximum (BOOST-V4) Voltage Regulated
8.45
l
Hysteresis
V
mV
|BAT-AUXP| for Which Balancing Is Terminated TERM2 = 0, TERM1 = 0
TERM2 = 0, TERM1 = 1
TERM2 = 1, TERM1 = 0
TERM2 = 1, TERM1 = 1
Hysteresis
UNITS
mV
mV
mV
mV
V
mV
8.75
V
200
mV
RNMOS
Charge Pump NMOS Switch ON Resistance
Measured at 10mA
20
Ω
RPMOS
Charge Pump PMOS Switch ON Resistance
Measured at 10mA
55
Ω
tBAT
Maximum Time a Single Battery Stays
Connected to the Auxiliary Battery
CTBAT = 10nF
4.5
5
5.5
sec
tON
Maximum Stack Balancing Termination Time
MODE = 0, CTON = 10nF
0.43
0.48
0.53
hrs
tOFF
Off Time After Stack Balance Termination
MODE = 0, DONE = 0, CTOFF = 10nF
0.43
0.48
0.53
hrs
VIH
Digital Input High Voltage
EN1, EN2, MODE, TERM1, TERM2 Pins
l
VIL
Digital Input Low Voltage
EN1, EN2, MODE, TERM1, TERM2 Pins
l
IIH, IIL
Leakage Current
EN1, EN2, MODE, TERM1, TERM2 Pins;
2.5V at Pin
l
VOL
Output Low Voltage
BATX, BATY, BAL, DONE,
UVFLT, OVFLT, PTCFLT Pins; 3mA Into Pin
l
IOH
Output High Leakage Current
BATX, BATY, BAL, DONE,
UVFLT, OVFLT, PTCFLT Pins; 6V at Pin
Thermal Shutdown Threshold (Note 7)
Rising Temperature
Thermal Shutdown Hysteresis
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. The LTC3305 is tested under pulsed load conditions such that TJ
≈ TA. The LTC3305E is guaranteed to meet specifications from 0ºC to 85ºC
junction temperature. Specifications over the –40ºC to 125ºC operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3305I is guaranteed
over the –40°C to 125°C operating junction temperature range. Note that
the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance, and other environmental
factors. The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according
to the formula: TJ = TA + (PD • θJA), where θJA (in °C/W) is the package
thermal impedance.
4
1.2
V
–1
27.5
0.4
V
1
µA
150
mV
1
µA
155
°C
10
°C
Note 3. Continuous operation above the specified maximum operating
junction temperature may result in device degradation or failure.
Note 4. The NGATE pin currents are not included in this number.
Note 5. The NGATE5, NGATE6, NGATE7 pin currents are drawn from the
BOOST pin. All other NGATE pin currents are drawn from the V4 pin. The
NGATE pin currents add to the currents drawn by V4 and BOOST.
Note 6. The voltage programmed at the VH and VL pins are gained up to
set the undervoltage and overvoltage thresholds of each battery.
Note 7: This IC includes overtemperature protection intended to protect
the device during momentary overload conditions. The maximum junction
temperature may be exceeded when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may result in device degradation or failure.
3305fb
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LTC3305
VREG Line and Load Regulation
2.55
2.5
2.2
VREG,UV (V)
2.35
2.30
2.25
2.20
2.10
0
3
6
9
CURRENT (mA)
2.05
12
2.00
–55 –35 –15
15
1.6
1.5
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
125
1.220
120
1.215
110
30
V4 = 12V
105
V4 = 52.8V
100
95
V4 = 12V
90
25
75
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
INGATE vs IISET
3305 G07
1.195
1.180
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1.20
UV Threshold vs Temperature
INGATE vs Temperature
5.25
RISET = 12.1k
5.20 RVL = 15k
INGATE (mA)
ALL NGATE PIN CURRENTS
1.18 AND NGATE3 CURRENT
2
1.16
V4 = 52.8V, VNGATE = 0V, RISET = 12kΩ
1.14
5.15
1.12
1.10
1.08
1.06
5.10
5.00
4.95
1.02
4.80
3305 G08
FALLING
4.90
4.85
5 25 45 65 85 105 125
TEMPERATURE (°C)
RISING
5.05
1.04
1.00
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
3305 G06
3305 G05
3305 G04
1.8
1.7 ALL NGATE PIN CURRENTS
1.6 AND NGATE3 CURRENT
2
1.5
1.4 V4 = 52.8V, VNGATE = 0V
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
50 60 70 80 90 100 110 120 130 140 150
IISET (µA)
1.200
1.185
80
15
–55 –35 –15
1.205
1.190
85
20
VISET vs Temperature
1.210
V4 = 64V
VISET (V)
IV4 (µA)
40
5 25 45 65 85 105 125
TEMPERATURE (°C)
3305 G03
OFF State Current vs Temperature
V4 = 64V
V4 = 52.8V
1.9
1.7
IVREG = 0.2mA, V4 = 52.8V
IVREG = 1mA, V4 = 52.8V
IVREG = 3mA, V4 = 12V
115
35
FALLING
2.0
3305 G02
3305 G01
50
45
2.1
1.8
2.15
V4 = 52.8V
RISING
2.3
2.40
V4 = 12V
VREG,UV vs Temperature
2.4
2.45
Shutdown Current vs Temperature
IV4 (µA)
VREG vs Temperature
2.50
55
INGATE (mA)
TA = 25°C, unless otherwise noted.
BATTERY VOLTAGE (V)
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VREG (V)
VREG (V)
TYPICAL PERFORMANCE CHARACTERISTICS
4.75
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
3305 G09
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5
LTC3305
TYPICAL PERFORMANCE CHARACTERISTICS
UV Threshold vs Temperature
7.70
15.4
10.3
7.60
15.2
RISING
10.0
FALLING
9.9
9.8
7.55
BATTERY VOLTAGE (V)
BATTERY VOLTAGE (V)
RISING
7.50
7.45
7.40
FALLING
7.35
15.1
14.9
14.7
14.6
9.6
7.25
14.5
9.5
–55 –35 –15
7.20
–55 –35 –15
1200
10.4
1175
1125
525
V1 = 13.2V, AUXN = GND
UV GAIN
10.0
OV GAIN
1100
505
RISING
495
1075
1050
1025
1000
FALLING
485
475
465
455
975
9.7
445
950
9.6
925
9.5
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
VL OR VH (V)
900
–55 –35 –15
435
3305 G13
425
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
25mV Termination Threshold
vs Temperature
50mV Termination Threshold
vs Temperature
35
60
20.5
33
58
18.5
31
56
16.5
29
54
VTERMINATE (mV)
22.5
12.5
10.5
8.5
27
25
23
21
52
50
48
46
6.5
19
44
4.5
17
42
2.5
–55 –35 –15
15
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
3305 G16
6
5 25 45 65 85 105 125
TEMPERATURE (°C)
3305 G15
3305 G14
12.5mV Termination Threshold
vs Temperature
14.5
V1 = 13.2V, AUXN = AUXP = GND
515
IV1 (µA)
|V1-AUXP| (mV)
10.2
9.8
Maximum Battery Current During
PTC Fault Condition
1150
10.3
5 25 45 65 85 105 125
TEMPERATURE (°C)
3305 G12
PTC Fault Threshold
vs Temperature
10.5
9.9
14.4
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
3305 G11
UV and OV Programming Gain
10.1
FALLING
14.8
7.30
5 25 45 65 85 105 125
TEMPERATURE (°C)
RISING
15.0
9.7
VTERMINATE (mV)
BATTERY VOLTAGE (V)
10.2
10.1
RISET = 12.1k
15.3 RVH = 45.3k
RISET = 12.1k
7.65 RVH = 22.6k
3305 G10
VBAT,UV/VL or VBAT,OV/VH (V/V)
OV Threshold vs Temperature
OV Threshold vs Temperature
10.5
RISET = 12.1k
10.4 RVL = 30.1k
VTERMINATE (mV)
TA = 25°C, unless otherwise noted.
5 25 45 65 85 105 125
TEMPERATURE (°C)
3305 G17
40
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
3305 G18
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LTC3305
TYPICAL PERFORMANCE CHARACTERISTICS
100mV Termination Threshold
vs Temperature
Minimum Boost Voltage
vs Temperature
0.510
7.2
110
tON, tOFF vs Temperature
V4 = 52.8V
CTON = CTOFF = 10nF (COG)
0.505
108
7.1
0.500
7.0
VBOOST-V4 (V)
104
102
100
98
6.9
6.8
FALLING
6.7
96
94
0.495
RISING
TIME (HOURS)
106
92
90
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
0.480
0.475
0.470
0.455
6.5
–55 –35 –15
0.450
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
45.0
CTBAT = 10nF (COG)
42.5
5 25 45 65 85 105 125
TEMPERATURE (°C)
3305 G21
3305 G20
tBAT vs Temperature
5.4
0.485
0.460
3305 G19
5.5
0.490
0.465
6.6
VOL vs Temperature
I = 3mA
40.0
5.3
37.5
5.2
35.0
5.1
VOL (mV)
TIME (SECONDS)
VTERMINATE (mV)
TA = 25°C, unless otherwise noted.
5.0
4.9
32.5
30.0
27.5
25.0
4.8
22.5
4.7
20.0
4.6
17.5
4.5
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
15.0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
3305 G23
3305 G22
Boost Charge Pump Start-Up
VREG Start-Up
CVREG = 2.2µF
CH2, 0V
5V/DIV
500mV/
DIV
VOLTAGE ACROSS CBOOST
VOLTAGE ACROSS CFLY
0V
100µs/DIV
3305 G24
CH1, 0V
2V/DIV
5ms/DIV
3305 G25
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7
LTC3305
PIN FUNCTIONS
BOOST (Pin 1): Charge Pump Output. Decouple with a
10µF capacitor to V4.
V4 (Pin 2): Positive terminal of Battery 4 connects to this
pin. Battery 4 is connected between V4 and V3. Decouple
with at least a 10µF capacitor to V3.
V3 (Pin 3): Positive terminal of Battery 3 connects to this
pin. Battery 3 is connected between V3 and V2. Decouple
with at least a 10µF capacitor to V2.
AUXP (Pin 4): Positive terminal of the auxiliary cell connects to this pin. Decouple with at least a 10µF capacitor
to AUXN.
AUXN (Pin 5): Negative Terminal of the auxiliary cell connects to this pin.
V2 (Pin 6): Positive terminal of Battery 2 connects to this
pin. Battery 2 is connected between V2 and V1. Decouple
with at least a 10µF capacitor to V1.
V1 (Pin 7): Positive terminal of Battery 1 connects to this
pin. Battery 1 is connected between V1 and GND. Decouple
with at least a 10µF capacitor to GND.
NGATE1 (Pin 8): NMOS1 Gate. Connect to the gate terminal
of external NMOS switch.
NGATE2 (Pin 9): NMOS2 Gate. Connect to the gate terminal
of external NMOS switch.
NGATE3 (Pin 10): NMOS3 Gate. Connect to the gate terminal of external NMOS switch.
NGATE4 (Pin 11): NMOS4 Gate. Connect to the gate terminal of external NMOS switch.
NGATE5 (Pin 12): NMOS5 Gate. Connect to the gate terminal of external NMOS switch.
NGATE6 (Pin 13): NMOS6 Gate. Connect to the gate terminal of external NMOS switch.
NGATE7 (Pin 14): NMOS7 Gate. Connect to the gate terminal of external NMOS switch.
NGATE8 (Pin 15): NMOS8 Gate. Connect to the gate terminal of external NMOS switch.
NGATE9 (Pin 16): NMOS9 Gate. Connect to the gate terminal of external NMOS switch.
8
BATX (Pin 17): This pin along with BATY indicates which
battery in the stack is currently being balanced and to
which the fault outputs apply. Open Drain Output.
BATY (Pin 18): This pin along with BATX indicates which
battery in the stack is currently being balanced and to
which the fault outputs apply. Open Drain Output.
OVFLT (Pin 19): Overvoltage Fault. This pin is pulled low
when an overvoltage fault condition is detected on a battery. Open Drain Output.
UVFLT (Pin 20): Undervoltage Fault. This pin is pulled
low when an undervoltage fault condition is detected on
a battery. Open Drain Output.
BAL (Pin 21): Balancing Indicator. This pin is pulled low
while the balancing operation is being performed and is
in its high impedance state when the part is disabled or
the part is in the sleep state. Open Drain Output.
DONE (Pin 22): Done Indicator. This pin is pulled low when
all the batteries in the stack are balanced. This pin is in its
high impedance state in shutdown. Open Drain Output.
PTCFLT (Pin 23): PTC Fault. This pin is pulled low when the
voltage across the PTC thermistor exceeds 1V. It is in its
high impedance state at all other times. Open Drain Output.
CTOFF (Pin 24): A capacitor from this pin to GND programs
the retry time in timer mode. Connect to GND if MODE = 1.
CTON (Pin 25): A capacitor from this pin to GND programs
the maximum time for the balancing operation in timer
mode. Connect to GND if MODE = 1.
CTBAT (Pin 26): A capacitor from this pin to GND programs
the maximum time an individual battery in the stack is connected to the auxiliary cell during the balancing operation.
VL (Pin 27): Low Voltage Fault Threshold. A resistor from
this pin to GND programs the low voltage fault threshold
for each battery in the series stack. Works in conjunction
with the ISET pin.
VH (Pin 28): High Voltage Fault Threshold. A resistor from
this pin to GND programs the high voltage fault threshold
for each battery in the series stack. Works in conjunction
with the ISET pin.
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LTC3305
PIN FUNCTIONS
ISET (Pin 29): Reference Current Pin that Servos to 1.2V.
A resistor from this pin to GND programs the gate charge
current for the external NMOS switches. The reference
current is also used to program the undervoltage and
overvoltage thresholds.
VREG (Pin 30): Low Voltage Regulated Output. An internally generated voltage of 2.5V is always present at this
pin. The voltage at this pin may be overdriven by a higher
external voltage up to 5.5V. This pin has limited current
sink capability and will not pull down a higher externally
applied voltage. All logic input pins must be referenced to
this pin. Decouple with a 1µF capacitor to GND.
TERM2 (Pin 31): Termination Threshold Select. This pin
along with TERM1 is used to set the voltage difference
between the battery and auxiliary cell at which a battery is
deemed balanced. High input impedance pin, do not float.
TERM1 (Pin 32): Termination Threshold Select. This pin
along with TERM2 is used to set the voltage difference
between the battery and auxiliary cell at which a battery is
deemed balanced. High input impedance pin, do not float.
EN1 (Pin 34): Enable Input. The state of the EN1 and EN2
pins is used to indicate the number of batteries in the stack.
With both pins at GND, the part is in shutdown. High input
impedance pin, do not float.
MODE (Pin 35): Mode Select. When held high, continuous
mode is selected. When held low, timer mode is selected.
High input impedance pin, do not float.
No Connect (Pin 36): This pin is not connected internally.
Solder this pin to a pad electrically isolated from all other
circuit nodes.
CP (Pin 37): Positive Terminal of Charge Pump Flying
Capacitor. Connect a 10µF capacitor from this pin to CM
for charge pump operation.
CM (Pin 38): Negative Terminal of Charge Pump Flying
Capacitor. Connect a 10µF capacitor from this pin to CP
for charge pump operation.
GND (Pin 39): The exposed pad is ground and must be
soldered to PCB ground for electrical connectivity and
rated thermal performance.
EN2 (Pin 33): Enable Input. The state of the EN1 and EN2
pins is used to indicate the number of batteries in the stack.
With both pins at GND, the part is in shutdown. High input
impedance pin, do not float.
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9
LTC3305
BLOCK DIAGRAM
BOOST
1
NO CONNECT 36
GATE DRIVE
CHARGE
PUMP
CP
CM
NGATE1
NGATE2
2
3
6
7
V4
NGATE3
MUX
NGATE4
V3
NGATE5
NGATE6
V2
NGATE7
V1
NGATE8
NGATE9
MIRROR
BANDGAP
1.2V
REFERENCE
29
VREG
EN1
27
31
32
4
5
24
25
26
8
9
10
11
12
13
14
15
16
30
ISET
EN2
28
38
V4
LOW
VOLTAGE
REGULATOR
+
–
37
VH
VL
MODE
UV/OV
BATX
TERM2
BATY
TERMINATION
SENSE
COMPARATOR
TERM1
AUXP
CONTROL
LOGIC
UVFLT
AUXN
BAL
CTOFF
CTON
OVFLT
DONE
TIMERS
CTBAT
PTCFLT
THERMAL
SHUTDOWN
33
34
35
17
18
19
20
21
22
23
OT
39
GND
10
3305 BD
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LTC3305
OPERATION
The LTC3305 balancer is intended to be used in conjunction with a separate pre-existing battery stack charger as
part of a high performance battery system. The balancing
operation itself is stand-alone and can operate independent
of whether the battery stack is being charged, discharged,
or both. That being said, because the LTC3305 balances
voltages, it works best if the voltage readings are stable,
which is more true when the battery stack is not being
charged or discharged. Nevertheless, it will properly balance the battery voltages when the stack is being concurrently charged and/or discharged, since the voltage across
the batteries will average out over time as the LTC3305
repeatedly cycles through them. Like all balancers, the
LTC3305 will slightly net-discharge the stack in the absence
of a separate charger.
The LTC3305 balances batteries using an auxiliary cell or an
alternate storage cell as a charge reservoir. External NMOS
switches are controlled in a preprogrammed sequence
to connect each battery in the stack to an auxiliary cell.
Charge is transferred to or from the auxiliary cell when it
is connected to a battery.
The LTC3305 can operate in one of two modes programmable via the MODE pin.
Timer Mode (MODE = 0)
The balancing operation begins once the CBOOST capacitor
is charged to at least 6.95V. The BAL pin is pulled low,
indicating that the part is enabled and balancing the battery stack.
The termination voltage, VTERMINATE, is the difference in
voltage between the auxiliary cell and the battery connected
to the auxiliary cell for which a battery is considered to
be balanced. VTERMINATE is programmed via the TERM1
and TERM2 pins to one of four preset voltages as shown
in Table 1.
Table 1. Termination Voltages
TERM1
TERM2
VTERMINATE
0
0
±12.5mV
1
0
±25mV
0
1
±50mV
1
1
±100mV
NGATE5
NGATE1-9
9
N5
NGATE4
+
NGATE6
N4
LTC3305
NGATE7
N3A
AUXP
NGATE3
N6
PTC
N7
+
AUX
N8
AUXN
N3B
NGATE2
+
+
BAT4
BAT3
BAT2
N2
NGATE8
NGATE1
N9
NGATE9
+
BAT1
N1
3305 F01
Figure 1. External Switch Arrangement
for a 4- Battery Balancing Application
The balancing operation begins with the negative terminal
of the auxiliary cell connected to the negative terminal of
BAT1, the lowest battery in the stack. Referring to Figure 1,
the bottom switches N1 and N9 that connect the negative
terminal of BAT1 to the auxiliary cell’s negative terminal are
first turned on. To turn on an external NMOS switch, the
current source at the NGATE pin connected to the gate of
the external NMOS is turned on and a gate source voltage
is developed across an external resistor.
After an internally set delay of 35ms, the voltages across
the auxiliary cell and BAT1 are compared by the termination sense comparator.
If the voltage difference between the auxiliary cell and BAT1
is less than the selected termination voltage, the battery
is deemed to be balanced with respect to the auxiliary cell
and the bottom switches are turned off by turning off the
corresponding NGATE pin currents. The next battery in
the stack is then connected to the auxiliary cell.
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11
LTC3305
OPERATION
If the voltage difference between the auxiliary cell and
BAT1 is greater than the selected termination voltage, the
top NMOS switches N2 and N7 that connect the positive
terminal of BAT1 to the auxiliary cell’s positive terminal
through the PTC thermistor are turned on. After a second
internally set delay of 35ms, the termination sense comparator starts monitoring the voltages across the auxiliary
cell and the battery. The battery stays connected to the
auxiliary cell until the voltage difference decreases to
VTERMINATE or a tBAT timeout occurs (tBAT is the maximum
time that a battery remains connected to the auxiliary cell
and is programmed by a capacitor on the CTBAT pin). This
timer is reset each time the auxiliary cell is connected to
a different battery.
At this point, all switches are turned off and the next battery in the stack is connected to the auxiliary cell. After
the switches have been turned off, an internal 40ms delay
provides a break-before-make time after which the negative terminal of the next battery in the stack is connected
to the negative terminal of the auxiliary cell via its bottom
switches. Table 2 shows the top and bottom switches
used to connect each battery for different battery stack
configurations. When only the bottom switches are on,
there is a conduction path between the auxiliary cell and
the battery through the body diodes of the top switches.
Current will flow through this conduction path if the auxiliary cell and the battery are more than two diode drops
apart. The current is limited by the PTC resistor.
Table 2. Top and Bottom Switch Arrangement
EN1, EN2
1,1
(4 Bat App)
1,0
(3 Bat App)
0,1
(2 Bat App)
12
BATTERY BEING
BALANCED
TOP
SWITCHES
BOTTOM
SWITCHES
Battery 1
N2, N7
N1, N9
Battery 2
N3, N6
N2, N8
Battery 3
N4, N7
N3, N9
Battery 4
N5, N6
N4, N8
Battery 1
N2, N7
N1, N8
Battery 2
N4, N6
N2, N9
Battery 3
N5, N7
N4, N8
Battery 1
N7
N9
Battery 2
N5
N8
In this fashion each battery in the stack is connected to the
auxiliary cell and the batteries in the stack will be balanced.
An internal clamp circuit protects the LTC3305 when the
voltage difference between the battery being balanced
and the auxiliary cell is greater than 1V. With a 13.2V
difference, the clamp draws 475µA of current. In the worst
case scenario, a 16V difference may appear between the
auxiliary cell and a battery. The internal clamp draws 600µA
of current in this scenario.
In the state when both the top and bottom side switches
are turned on, the PTCFLT pin will be pulled low if the
voltage difference between the battery being balanced and
the auxiliary cell is greater than 1V. If during the balancing
operation the voltage difference becomes less than 1V, the
PTCFLT pin returns to its high impedance state.
The BATX and BATY pins indicate which battery in the
stack is currently connected to the auxiliary cell as shown
in Table 3. In shutdown, the BATX and BATY pins are in
a High Z state and the BAL pin is also in a High Z state.
Table 3. State of BATX and BATY Pins
STATE OF OPERATION
BATX
BATY
Battery 1 Connected
High Z
High Z
Battery 2 Connected
High Z
0
Battery 3 Connected
0
0
Battery 4 Connected
0
High Z
Once all batteries in the stack are balanced the DONE pin
is pulled low, the BAL pin is in its high impedance state
and the part is put in a low power OFF state.
A four-battery stack is deemed balanced when the termination sense comparator detects VTERMINATE on five
consecutive cycles that connect each of the batteries to
the auxiliary cell using the bottom switches only.
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LTC3305
OPERATION
In timer mode, a capacitor at the CTON pin programs the
maximum time, tON, that the balancing operation can run
for. The balancing operation is terminated either when the
batteries in the stack are deemed to be balanced or a tON
time out occurs. After the balancing operation has been
terminated, the LTC3305 is put in a low power OFF state
for a fixed time, tOFF. The tOFF time is programmed by a
capacitor at the CTOFF pin. In the OFF state, the BAL pin
is put in its high impedance state. Once tOFF times out,
the LTC3305 is put back in its ON state and the balancing
operation begins again. The tON timer may be defeated by
tying the CTON pin to GND. In this scenario, the LTC3305
will enter the OFF state only when all the batteries in the
stack are deemed to be balanced.
Continuous Mode (MODE = 1)
In the continuous mode of operation the part functions in
much the same way as in timer mode with the following
differences.
1. There is no ON or OFF state. The CTON and CTOFF pins
must be tied to GND in continuous mode. The balancing operation continues even if the stack is in balance.
The balancing operation is terminated only if the part
is put in shutdown. The BAL pin is always pulled low
in continuous mode.
2. In timer mode, if the termination comparator senses
that a battery is balanced to the auxiliary cell with only
the bottom plates connected, the balancing operation
on that battery is terminated. This is not the case in
continuous mode. In continuous mode the top switches
are turned on and the balancing operation on a battery
is terminated only by a tBAT time out. Since the auxiliary
cell remains connected to the battery until a tBAT time
out occurs, its voltage can change before it connects
to the next battery in the stack. As a result, when the
stack is balanced and the DONE pin is pulled low, the
voltages across the individual batteries in the stack
may differ by more than the programmed VTERMINATE.
In the worst case when the capacity of the auxiliary cell
is much smaller than the battery, the individual battery
voltages could differ by up to twice the programmed
VTERMINATE when balanced.
Charge Pump Operation
The LTC3305 uses external NMOS devices as switches to
connect a battery to the auxiliary cell. The LTC3305 has a
charge pump that generates the higher voltage required
to turn on some of the external NMOS switches.
Two external capacitors CFLY and CBOOST, two diodes D1
and D2, and resistors R1 and R2 are required for charge
pump operation as shown in Figure 2. When the LTC3305
is enabled, the charge pump is turned on. CFLY initially
charges with a current ICHG through external diode D1,
resistor R1, and the internal NMOS switch N1 to GND. When
CFLY is charged to 10.5V, an internal comparator switches
the internal NMOS switch off and turns on switch P1. CFLY
connects to CBOOST through diode D2, resistor R2 and the
internal PMOS switch P1. Charge is transferred from CFLY
to CBOOST with a current IDISCHG. When CFLY is discharged
to 9.5V, it is disconnected from CBOOST, recharged back up
to 10.5V, and then reconnected to CBOOST. In this fashion
the voltage across CBOOST is built up.
ICHG
D1
R1
IDISCHG
CFLY
CM
CP
P1
D2
BOOST
R2
N1
CBOOST
V4
LTC3305
3305 F02
Figure 2. Charge Pump Operation
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13
LTC3305
OPERATION
Once the CBOOST capacitor has 6.95V across it, balancing
begins. When CBOOST is charged to 8.45V, the charge
pump operation is disabled and CFLY remains connected
to CBOOST. Charge pump operation resumes when CBOOST
discharges to 8.25V.
Undervoltage and Overvoltage Fault Detection
The undervoltage and overvoltage thresholds can be
programmed using the resistor at the ISET pin in conjunction with resistors at the VL and VH pins. The voltage
present at the VL or VH pin programs the corresponding
fault threshold to 10× that voltage for each battery in the
stack. An internal amplifier accurately gains up the voltage
at the VL and VH pins and shifts the threshold voltage to
the appropriate battery common mode level. The VL and
VH pins have a programming range from 0.4V to 1.6V.
The internal undervoltage and overvoltage comparators
may not trip correctly for a program voltage outside this
range. An internal clamp prevents the thresholds from
being programmed to greater than 20V.
When an undervoltage or overvoltage fault condition is
detected, the corresponding UVFLT or OVFLT pin is pulled
to GND. The balancing operation is not interrupted during
this time. If an undervoltage or overvoltage fault condition
goes away during the balancing operation, the corresponding fault pin returns to its high impedance state.
If the undervoltage and overvoltage fault detection is not
needed, the VL and VH pins must be tied to GND. The UVFLT
and OVFLT pins may either be tied to GND or left floating.
Low Voltage Regulator
The LTC3305 has an always on regulator that provides
2.5V at the VREG pin. The VREG pin may be driven externally
up to 5.5V. The VREG pin cannot sink current and will not
pull down an externally applied voltage. The regulator can
source up to 3mA of current. If more than 3mA of current
14
is drawn from the regulator, the VREG voltage will drop
below its undervoltage threshold, disabling the LTC3305
and terminating the balancing operation. The balancing
operation restarts when the regulator recovers from its
undervoltage state. In short circuit, the VREG current is
limited to 15mA. The VREG pin should be decoupled with
at least a 1µF capacitor to GND.
Thermal Shutdown
The LTC3305 has an overtemperature detect circuit that
shuts down the balancing operation when the internal
silicon junction temperature exceeds 155°C. The LTC3305
resumes balancing when the temperature drops to 145°C.
In thermal shutdown, the low voltage regulator remains
powered.
Balancing Battery Stacks with Two or Three Batteries
The LTC3305 can also be configured to balance battery
stacks of two or three batteries. The state of the enable pins
tells the LTC3305 to select the correct switch sequencing.
For a two battery stack, the LTC3305 must be enabled
with EN1 = 0 and EN2 = 1. For a three battery stack, the
LTC3305 must be enabled with EN1 = 1 and EN2 = 0. The
external NMOS switch arrangements for a two-battery
and three-battery application are shown in Figures 3 and
4 respectively. If pin NGATE6 is unused, it must be connected to the BOOST pin. All other unused NGATE pins
must be connected to V4 as shown in Figures 3 and 4.
A two battery stack is deemed balanced if the termination
sense comparator senses the voltage difference between
the auxiliary cell and the battery is less than VTERMINATE
on three successive cycles when the auxiliary cell and a
battery are connected using only the bottom switches.
In the case of a three battery stack, four successive cycles
are required to deem the stack balanced.
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LTC3305
OPERATION
10µF
25V
ALL NMOS DEVICES = SiR882DP
D1, D2 = CMMSH1-100
D2
CM
VREG
EN1
1µF
6V
249Ω
CP
BOOST
D1
NGATE6
EN2
MODE
100k EACH
10nF
100nF
22nF
TERM1
TERM2
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
CTON
22µF
25V
V4
NGATE1-4
NGATE5
6.04k
V3
LTC3305
V2
NGATE5, 7, 8, 9
10µF
25V
4
+
BAT2
BAT1
NGATE7
6.04k
PTC
VL
AUXP
10µF
25V
VH
AUXN
42.2k
ISET
+
10µF
25V
V1
27.4k
12.1k
4
CTOFF
CTBAT
1.33k
+
AUX
6.04k
NGATE8
GND
3305 F03
NGATE9
6.04k
Figure 3. Two-Battery Application Showing External Switch Arrangement
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15
LTC3305
OPERATION
10µF
25V
D2
CM
VREG
EN1
EN2
1µF
6V
MODE
100k EACH
10nF
100nF
22nF
TERM1
TERM2
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
CTON
249Ω
CP
BOOST
ALL NMOS SWITCHES = SiR882DP
D1, D2 = CMMSH1-100
1.33k
D1
10µF
25V
V4
NGATE5
6.04k
NGATE3
V3
NGATE4
10µF
25V
LTC3305
6.04k
V2
NGATE2
10µF
25V
6.04k
V1
CTOFF
NGATE6
10µF
25V
6.04k
CTBAT
VL
8
BAT2
NGATE1
+
BAT1
6.04k
6.04k
PTC
VH
ISET
12.1k
+
BAT3
NGATE7
NGATE1, 2, 4-9
27.4k
42.2k
+
AUXP
GND
AUXN
10µF
25V
+
AUX
6.04k
3305 F04
NGATE8
6.04k
NGATE9
Figure 4. Three-Battery Application Showing External Switch Arrangement
16
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LTC3305
APPLICATIONS INFORMATION
Selecting the PTC Thermistor
PTC Current Voltage Characteristics
As seen in the PTC Current Voltage Characteristics in Figure
5a, when the PTC has a small voltage or a high voltage
across it, the current flowing through it is small. For small
voltages, this is OK since the battery and the auxiliary cell
are close to balance. For high voltages, this slows down
balancing. To increase balance currents at high voltages
a power resistor can be placed in parallel with the PTC
device, as shown in Figure 5b. Additionally, multiple PTC
resistors may be connected in parallel to increase current
flow at all voltages.
PTC devices are manufactured in two styles: ceramic and
poly fuse. Only a ceramic style PTC device should be used
in this application. Poly fuse devices have a very limited
number of lifetime trip cycles and are not suitable in a
balancing application.
The PTC must be selected such that power dissipation
through the external NMOS switches never exceeds their
rated SOA power dissipation value. Refer to Table 4 for a
list of recommended PTC thermistors.
CURRENT →
CURIE POINT
VOLTAGE →
3305 F05a
(a)
Increasing Current at Large Voltage
PTC RESISTOR IN PARALLEL
WITH A RESISTOR
CURRENT →
A PTC thermistor is a type of resistor with a Positive Temperature Coefficient that serves as a protection device by
limiting its current above a certain threshold. The PTC device
limits the peak current that transfers charge between the
auxiliary cell and the battery. When the voltage across the
PTC is small, the power dissipated in the PTC is small and
the PTC resistance remains constant. As the voltage across
the PTC increases, power dissipation in the PTC increases
which causes the PTC temperature to rise. When the temperature reaches the Curie Temperature, further increases
in voltage will cause the PTC resistance to increase rapidly,
which limits the current through the device and thus limits
the power dissipation in the PTC. This behavior is shown
in the PTC Current Voltage Characteristics in Figure 5a. In
this fashion the PTC serves to protect the external NMOS
switches from operating outside of their SOA region.
SINGLE PTC RESISTOR
RESISTOR ONLY
VOLTAGE →
3305 F05b
(b)
Figure 5. PTC Behavior
Table 4. Recommended Ceramic PTC Thermistors
MANUFACTURER
VOLTAGE
RESISTANCE
(Ω)
PTGL7SARR47M1B51B0
Murata
16V
0.47
PTGLASARR27M1B51B0
Murata
16V
0.27
PTGLESARR15M1B51B0
Murata
16V
0.15
PTGL12AR1R2H2B51B0
Murata
30V
1.2
2381 663 51121
Vishay
30V
0.7
2381 663 51321
Vishay
30V
0.5
2381 664 52021
Vishay
30V
0.3
PART NUMBER
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17
LTC3305
APPLICATIONS INFORMATION
Selecting the Auxiliary Cell
The auxiliary cell must be capable of sourcing and sinking current and withstand the maximum voltage of any
individual battery in the stack. The ESR of the auxiliary
cell must be small compared to the PTC thermistor. Any
voltage dropped across the auxiliary cell ESR appears as
an offset voltage at the input of the termination comparator.
The auxiliary cell used may be a lead-acid battery, a stacked
supercapacitor, or a low leakage, high voltage capacitor.
When using a supercapacitor stack, the voltage across
each individual supercapacitor must not exceed its rated
operating voltage.
Figure 6a shows a battery stack made of 4 batteries,
each with a nominal capacity of 50Ah, but with a 10%
capacity mismatch. With no balancing, the stack capacity
is determined by the weakest battery in the stack and is
limited to 45Ah.
In Figure 6b, a small capacity auxiliary cell, such as a
supercapacitor stack, is used to balance the battery stack.
When balanced the stack capacity can be made to approach
the nominal capacity of 50Ah despite the 10% mismatch.
In Figure 6c, the auxiliary cell has the same capacity as
the batteries in the stack. Each of the batteries in Figure 6c
has a nominal capacity of only 40Ah but the stack capacity approaches 50Ah since the auxiliary cell supplements
55Ah
(+10%)
55Ah
(+10%)
50Ah
50Ah
50Ah
50Ah
45Ah
(–10%)
45Ah
(–10%)
STACK CAPACITY
=45Ah
(a)
the capacity of the battery stack. Using a large capacity
auxiliary cell supplements stack capacity. Smaller capacity batteries may be used in the stack which helps reduce
system costs.
Precharging the Auxiliary Cell
When using stacked supercapacitors or a single high voltage capacitor as the auxiliary cell, the auxiliary cell may
be initially discharged with a voltage of 0V. At startup, a
large voltage exists across the PTC resistor, which will
cause the PTC resistance to increase. This limits the current and hence the charge transfer between the auxiliary
cell and the battery it is connected to. The auxiliary cell
will be charged very slowly with an indeterminate time,
as it sequentially connects to each battery in the stack.
Once the auxiliary cell has been charged to a point where
the PTC device operates as a low resistance device, the
balancing process is sped up.
A more time efficient solution is to precharge the auxiliary
cell to the average voltage of the batteries in the stack. Figure
7a shows a circuit using a high voltage buck regulator to
precharge the auxiliary cell to V4/4 volts. NMOS devices
N2A and N2B eliminate a parasitic charging path from
BATTERY1 to the auxiliary cell when AUXN is connected
to GND through N10. Figures 7b and 7c are scope photos
showing a complete precharging and balancing operation.
44Ah
(+10%)
40Ah
PTC
PTC
40Ah
4Ah
(AUX)
40Ah
(AUX)
36Ah
(–10%)
STACK CAPACITY
≈50Ah
(b)
STACK CAPACITY
≈50Ah
(c)
Figure 6. Increasing Stack Capacity with an Auxiliary Cell
18
3305fb
For more information www.linear.com/LTC3305
LTC3305
APPLICATIONS INFORMATION
D1, D2 = CMMSH1-100
D3 = CMMSH2-80
D2
10µF
25V
VREG
TERM1
TERM2
MODE
1µF
6V
CP
CM
BOOST
10µF
25V
NGATE5
D1
6.04k
N5
V4
NGATE4
10µF
25V
6.04k
3.01k
10µF
25V
N3A
V2
N2A
10µF
25V
CTOFF
CTBAT
10nF
NGATE2
NGATE1-9
NGATE7
6.04k
174k
LTC3630A
GND
VPROG1
VPROG2
+
BAT1
N1
N7
PTC
VH
42.2k
D3
AUXP
10µF
25V
ISET
12.1k
GND
+
AUX
N8
5.11M
6.04k
AUXN
N9
NGATE8
365k
6.04k
NGATE9
100µH
D4, D5, D6 = 1N914
D6
S
N11
Q
LTC1440
2.21M
D5
V+
IN–
D4
N12
N10
START
RUN
ISET
VL
27.4k
D
+
BAT2
FB
NGATE1
6.04k
N6
9
VIN
SS
FBO
SW
N2B
6.04k
NGATE6
2.2µF
100V
+
BAT3
N3B
10µF
25V
V1
100nF
NGATE3
6.04k
LTC3305
+
BAT4
N4
V3
CTON
10nF
1.33k
249Ω
EN1
EN2
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
N1A, N1B, N2, N3A, N3B, N4, N5, N6, N7, N8, N9, N10 - SiR882DP
IN+
2.21M
365k
OUT
REF
40.2k
HYST
V–
GND
2.43M
681k
CLK
R
Q
N11, N12 = FDV301N
3305 F07
(a)
BAT1, BAT2, BAT3, BAT4, AUXP-AUXN = 2V/DIV
AUXN = 10V/DIV; START, EN_3305 = 5V/DIV
TIME = 20s/DIV
(b)
AUXP-AUXN = 2V/DIV
AUXN = 10V/DIV; START, EN_3305 = 5V/DIV
TIME = 5s/DIV
(c)
Figure 7. Precharging the Auxiliary Cell Using the LTC3630A and LTC1440
3305fb
For more information www.linear.com/LTC3305
19
LTC3305
APPLICATIONS INFORMATION
Selection of External NMOS Switches
The external NMOS switches must be capable of withstanding a reverse voltage equal to the battery stack voltage. They should also be capable of carrying DC current
up to the PTC thermistor trip point. The maximum power
dissipated in the NMOS should not cause it to operate
outside of its Safe Operating Area. Refer to Table 5 for a
list of recommended NMOS switches.
Table 5. Recommended NMOS Switches
PART NUMBER
MANUFACTURER
IDS(MAX)
VDC(MAX)
Vishay
60A
100V
SiS892DN
Vishay
25A
100V
IPD70N10S3-12
Infineon
70A
100V
IPB35N10S3L-26
Infineon
35A
100V
RJK1051DPB
Renesas
60A
100V
RJK1054DPB
Renesas
92A
100V
SiR882DP
the NMOS device. Programming a higher current reduces
the NMOS device turn on time. Programming a large gate
source voltage reduces the on resistance of the NMOS
device. During turn off, the gate capacitor discharges
through the gate source resistor.
Programming Undervoltage and Overvoltage
Thresholds
Referring to the Block Diagram, the voltage at the ISET pin
is servoed to 1.2V. An external resistor, RISET, from this
pin to GND programs a current which is divided down and
mirrored to the VL and VH pins. The ISET pin current has
a programmed range from 50µA to 150µA.
The ISET pin current is given by:
1.2V
I ISET =
RISET
The current out of the VL and VH pins is given by:
Programming NMOS Turn On
The NMOS switches are turned on by developing a voltage
across an external resistor from the gate to the source.
The current through the resistor is delivered from the
NGATE pins and is programmed by the current at the
ISET pin. The internal current sources that provide the
NGATE pin currents operate from the V4 and BOOST
supplies as shown in the Block Diagram. The BOOST
pin voltage is regulated at 8.45V greater than V4. It is
recommended that the gate turn on voltage be set to no
more than 7.5V. The current flowing through the gate
turn on resistor connected to the NGATE3 pin is given by:
26.4V
I NGATE3 =
RISET
The current flowing through the other NGATE pins is
given by:
13.2V
I NGATE =
RISET
The NGATE3 current has a programmed range from 1mA
to 3mA. All other NGATE currents have a programmed
range from 500µA to 1.5mA.
The NGATE current initially charges the gate capacitor of
the NMOS device to turn it on. The external gate source
resistor maintains a constant gate to source voltage on
20
I ISET
3
External resistors RVL from the VL pin to GND and RVH
from the VH pin to GND program the undervoltage and
overvoltage thresholds for each battery. The undervoltage threshold for a battery is given by:
R
VBAT,UV = 4V • VL
RISET
The overvoltage threshold for a battery is given by:
R
VBAT,OV = 4V • VH
RISET
Programming the tBAT Parameter
IVL = IVH =
The tBAT parameter is programmed using a capacitor
from the CTBAT pin to GND. tBAT is given by:
C
tBAT = 5sec• TBAT
10nF
A C0G type capacitor is recommended due to its superior
temperature characteristics.
Programming the tON and tOFF Parameters
The tON parameter is programmed by a capacitor from
the CTON pin to GND. tON is given by:
tON = 0.48hrs•
For more information www.linear.com/LTC3305
CTON
10nF
3305fb
LTC3305
APPLICATIONS INFORMATION
The tOFF parameter is programmed by a capacitor from
the CTOFF pin to GND. tOFF is given by:
C
tOFF = 0.48hrs• TOFF
10nF
C0G type capacitors are recommended due to their superior
temperature characteristics.
In the continuous operation mode (MODE = 1), the CTON
and CTOFF pins are unused and should be connected to
GND.
Selecting Charge Pump Components
Referring to Figure 2, recommended values for R1, R2
and CFLY are 249Ω, 1.33k & 10µF respectively for all applications. For applications in which V4 is no lower than
32V a 10µF capacitor is recommended for CBOOST. For
applications which may have lower voltages at V4, the
recommended value for CBOOST is 22µF. Schottky diodes
with a breakdown voltage larger than the maximum V4
voltage are recommended for diodes D1 and D2.
Selecting Decoupling Capacitors
Decoupling capacitors of at least 10µF must be placed
across each battery, from the BOOST pin to V4 and from
the AUXP pin to the AUXN pin. These capacitors must be
placed as close as possible to the LTC3305. The capacitors
must be capable of withstanding the maximum voltage
across each battery. Capacitors with an X5R or X7R type
dielectric should be used.
Thermal Considerations and Limiting On-Chip Power
Dissipation
Excessive on-chip power dissipation will cause the
LTC3305 to enter thermal shutdown. It is important to
understand the source of the power dissipation and how
power dissipation can be reduced. The two contributions
of on-chip power dissipation on the LTC3305 that may be
controlled by the user are the loading on the low voltage
regulator and the power dissipated through the current
sources that provide the NGATE pin currents.
The low voltage linear regulator provides a 2.5V output.
Any current provided by the regulator will cause power
dissipation in the internal switch connected from V4 to
VREG, which causes die temperature to increase. In Figure 8,
an external switching regulator generates a 3.3V rail that
back drives the VREG pin and provides power to the external
microprocessor and other low voltage circuits. There is
no on-chip loading on the VREG pin and thus no on chip
power dissipation in the low voltage regulator.
In Figure 8, external resistors R1, R2, R3, R4, and R5 are in
series with the on-chip current sources that provide NGATE
pin current. These resistors reduce the voltage across the
on-chip current sources and thus reduce on-chip power
dissipation. As an example, the current source at NGATE1
delivers current from the V4 pin. When this current source
is turned on, the voltage across it is V4-VNGATE1. For a
typical application with V4 = 52.8V, programmed INGATE =
506µA and VNGATE1 = 6.12V, the on-chip power dissipated
in the current source is 23mW. In Figure 8, resistor R1
operates with approximately 30.5V across it. The on-chip
power dissipated in the current source is reduced to approximately 8mW. In similar fashion resistors R2, R3,
R4, and R5 reduce the on-chip power dissipation on the
respective current sources. When choosing these resistors
it is recommended to have the internal current sources
biased with at least 6V across them under all operating
conditions. Power dissipation through the on-chip current
sources may be further reduced by programming a lower
gate current through the NGATE pins.
Balancing Battery Stacks with more than Four Batteries
To balance battery stacks that have more than four batteries, multiple LTC3305 devices may be stacked together. In
this scenario, it is recommended that each LTC3305 be
run in continuous mode and at least one battery in each
sub-stack of four is common to two LTC3305s. Each
LTC3305 needs an auxiliary cell for the balancing operation. Figure 9 shows an eight battery stack being balanced
using three LTC3305 devices connected together. Figure
10 shows a stack of six batteries being balanced using
two LTC3305 devices. To balance a battery stack with
n batteries, the minimum number of LTC3305 devices
required is [(n-1)/3] rounded up to the nearest integer.
In this calculation, each LTC3305 is assumed to be used
in a four-battery configuration and at least one battery
interleaves two LTC3305 devices.
3305fb
For more information www.linear.com/LTC3305
21
LTC3305
APPLICATIONS INFORMATION
When multiple LTC3305 devices are stacked, the logic output pins may need to be level shifted and ground referred.
In Figure 9, optical isolators are used for level shifting.
The no-connect pin on the LTC3305 must be soldered to
a pad on the PCB and must be electrically isolated from
any other circuit node.
Figure 11 shows an application in which an eight battery
stack is balanced using two LTC3305 devices and two
auxiliary cells. BAT1, BAT2, BAT3, and BAT4 are balanced
to each other using the lower LTC3305 whereas BAT5,
BAT6, BAT7, and BAT8 are balanced to each other by the
upper LTC3305.
The trace that connects the AUXP pin to the positive
terminal of the auxiliary source must be as close to the
auxiliary source positive terminal as possible. Otherwise
the trace impedance adds to the ESR of the auxiliary cell
which manifests itself as an offset at the internal termination comparator.
PCB Considerations
The V1, V2, V3 and V4 traces must be Kelvin connected
directly to the battery terminal and must not share a common trace through which high balance current will flow.
Any voltage drop in these traces also manifests itself as
an offset voltage at the termination comparator input.
In operation the LTC3305 can dissipate large amounts
of power which can increase die temperature and cause
the part to enter thermal shutdown. The exposed pad of
LTC3305 must be well soldered to the PCB to provide
adequate heat sinking. The exposed pad also provides an
electrical GND to the LTC3305.
10µF
25V
ALL NMOS SWITCHES = SiR882DP
D1, D2 = CMMSH1-100
D2
249Ω
LTC3630A
BUCK REGULATOR
3.3V
VREG
EN1
EN2
MODE
TERM1
TERM2
100k EACH
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
MICROPROCESSOR
10nF
100nF
10nF
CP
CM
1.33k
BOOST
10µF
25V
V4
D1
10µF
25V
NGATE4
BAT4
12.1k
V3
6.04k
V2
12.1k
LTC3305
10µF
25V
CTON
V1
CTOFF
CTBAT
NGATE1-9
37.4k
R2
10µF
25V NGATE6
12.1k
12.1k
12.1k
60.4k
R1
9
VL
10k
R3
10µF
25V
NGATE7
59k
NGATE5
12.1k
NGATE3
BAT3
NGATE2
BAT2
NGATE1
BAT1
+
+
+
+
12.1k
R4
PTC = PTGL13AROR8H2B71B0
93.1k
VH
ISET
23.7k
AUXP
GND
AUXN
10µF
25V
+
AUX
12.1k
NGATE8
12.1k
20k
NGATE9
3305 F08
R5
Figure 8. 4-Battery Application with External Resistors to Limit Power Dissipation
22
3305fb
For more information www.linear.com/LTC3305
LTC3305
APPLICATIONS INFORMATION
100k
100k
100k
100k
100k
100k
100k
10µF
25V
TO
µP
ALL NMOS DEVICES = SiR882DP
D1, D2, D3, D4, D5, D6 = CMMSH1-100
D6
2.43k
2.43k
2.43k
2.43k
2.43k
2.43k
2.43k
VREG
CM
CP
EN1
EN2
MODE
TERM1
TERM2
1µF
6V
CPC1301G
1.33k
249Ω
BOOST
V4
NGATE5C
10µF
25V
5.49k
D5
+
NGATE4C
10µF
25V
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
BAT8
5.49k
V3
2.74k
10µF
25V
+
NGATE3C
BAT7
V2
LTC3305
+
NGATE2C
5.49k
10µF
25V
CTON
BAT6
V1
CTOFF
10µF
25V
10nF
CTBAT
20k
NGATE1C
5.49k
NGATE6C
5.49k
9 NGATE1C-9C
NGATE1-9
NGATE7C
5.49k
VL
PTC
32.4k
8.06k
100k
100k
100k
100k
100k
100k
AUXP
VH
10µF
25V
+
AUX3
NGATE8C
GND
100k
+
5.49k
AUXN
ISET
BAT5
5.49k
NGATE9C
10µF
25V
TO
µP
2.43k
2.43k
2.43k
2.43k
2.43k
2.43k
D4
2.43k
VREG
CM
CP
EN1
EN2
MODE
TERM1
TERM2
1µF
6V
CPC1301G
1.33k
249Ω
BOOST
10µF
25V
NGATE5B
5.49k
D3
V4
NGATE4B
10µF
25V
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
5.49k
V3
2.74k
10µF
25V
NGATE3B
V2
LTC3305
NGATE2B
5.49k
10µF
25V
CTON
V1
CTOFF
10µF
25V
10nF
CTBAT
20k
NGATE1B
5.49k
NGATE6B
9
NGATE1-9
5.49k
NGATE1B-9B
+
BAT4
NGATE7B
5.49k
VL
PTC
32.4k
8.06k
AUXP
VH
10µF
25V
+
AUX2
5.49k
NGATE8B
AUXN
ISET
GND
+
5.49k
BAT3
NGATE9B
10µF
25V
D2
VREG
3.3V
100k
100k
100k
100k
100k
100k
100k
CM
CP
EN1
EN2
MODE
TERM1
TERM2
1µF
6V
TO
µP
V4
V3
NGATE5A
5.49k
D1
10µF
25V
5.49k
2.74k
V2
LTC3305
+
NGATE2A
5.49k
10µF
25V
+
10µF
25V
NGATE6A
5.49k
CTBAT
NGATE1-9
9
BAT2
NGATE1A
5.49k
BAT1
NGATE1A-9A
NGATE7A
5.49k
VL
20k
PTC
AUXP
VH
10µF
25V
32.4k
+
AUX1
5.49k
NGATE8A
AUXN
ISET
8.06k
NGATE3A
10µF
25V
V1
CTOFF
10nF
10µF
25V
NGATE4A
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
CTON
1.33k
249Ω
BOOST
GND
5.49k
NGATE9A
3305 F07
Figure 9. Three LTC3305 Devices Connected to Balance Eight Lead-Acid Batteries
For more information www.linear.com/LTC3305
3305fb
23
LTC3305
APPLICATIONS INFORMATION
10µF
25V
ALL NMOS DEVICES = SiR882DP
D1, D2, D3, D4 = CMMSH1-100
D4
VREG
EN1
EN2
MODE
TERM1
TERM2
1µF
6V
475Ω
475k
CP
CM
BOOST
NGATE5B
6.04k
10µF
25V
V4
D3
NGATE4B
10µF
25V
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
CTON
1.33k
249Ω
+
BAT6
6.04k
V3
3.01k
NGATE3B
10µF
25V
V2
LTC3305
CTOFF
+
BAT5
NGATE2B
10µF
25V
6.04k
V1
CTBAT
10nF
NGATE1-9
10µF
25V
9
NGATE1B-9B
VL
NGATE6B
NGATE7B
27.4k
VH
6.04k
6.04k
PTC
42.2k
+
BAT4
AUXP
10µF
25V
ISET
12.1k
+
AUX2
6.04k
NGATE1B
NGATE8B
AUXN
GND
6.04k
6.04k
NGATE9B
10µF
25V
D2
VREG
EN1
EN2
MODE
TERM1
TERM2
1µF
6V
475k
CP
CM
BOOST
NGATE5A
+
BAT3
6.04k
10µF
25V
V4
D1
NGATE4A
10µF
25V
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
CTON
1.33k
249Ω
6.04k
V3
3.01k
NGATE3A
10µF
25V
V2
LTC3305
CTOFF
+
BAT2
NGATE2A
10µF
25V
6.04k
V1
CTBAT
10nF
NGATE1-9
VL
10µF
25V
9
NGATE1A-9A
27.4k
VH
NGATE6A
NGATE7A
6.04k
+
BAT1
6.04k
PTC
42.2k
AUXP
10µF
25V
ISET
12.1k
GND
+
AUX1
6.04k
NGATE1A
NGATE8A
AUXN
6.04k
6.04k
NGATE9A
3305 F08
Figure 10. Two LTC3305 Devices Connected to Balance Six Lead-Acid Batteries with AND’d DONE Indicator
24
3305fb
For more information www.linear.com/LTC3305
LTC3305
APPLICATIONS INFORMATION
1µF
6V
100k
VREG
EN1
EN2
MODE
TERM1
TERM2
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
CM
CP
249Ω
1.33k
BOOST
10µF
25V
NGATE5B
6.04k
D3
V4
6.04k
NGATE4B
10µF
25V
V3
3.01k
10µF
25V
10µF
25V
+
BAT7
NGATE2B
+
BAT6
NGATE1B
+
BAT5
6.04k
V1
CTOFF
CTBAT
NGATE1-9
NGATE6B
10µF
25V
9
NGATE7B
NGATE1B-9B
VL
+
BAT8
NGATE3B
V2
LTC3305
CTON
10nF
ALL NMOS
DEVICES = SiR892DP
D1, D2, D3, D4 = CMMSH1-100
D4
10µF
25V
6.04k
6.04k
6.04k
PTC
AUXP
10µF
25V
VH
+
AUX2
6.04k
AUXN
12.1k I
SET
NGATE8B
GND
6.04k
NGATE9B
D2
10µF
25V
1µF
6V
100k
VREG
EN1
EN2
MODE
TERM1
TERM2
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
CTON
CM
CP
10µF
25V
NGATE5A
6.04k
D1
6.04k
NGATE4A
10µF
25V
V3
3.01k
10µF
25V
+
BAT4
NGATE3A
+
BAT3
NGATE2A
+
BAT2
NGATE1A
+
BAT1
V2
LTC3305
10µF
25V
6.04k
V1
CTBAT
NGATE1-9
NGATE6A
10µF
25V
9
6.04k
6.04k
NGATE7A
NGATE1A-9A
VL
6.04k
PTC
AUXP
10µF
25V
VH
12.1k I
SET
1.33k
V4
CTOFF
10nF
249Ω
BOOST
AUXN
GND
+
AUX1
6.04k
NGATE8A
6.04k
3305 F11
NGATE9A
Figure 11. Eight Battery Balancer Using Two LTC3305 Devices
For more information www.linear.com/LTC3305
3305fb
25
LTC3305
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3305#packaging for the most recent package drawings.
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev C)
Exposed Pad Variation AA
4.75 REF
38
9.60 – 9.80*
(.378 – .386)
4.75 REF
(.187)
20
6.60 ±0.10
4.50 REF
2.74 REF
SEE NOTE 4
6.40
2.74
REF (.252)
(.108)
BSC
0.315 ±0.05
1.05 ±0.10
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
26
1
0.25
REF
19
1.20
(.047)
MAX
0° – 8°
0.50
(.0196)
BSC
0.17 – 0.27
(.0067 – .0106)
TYP
0.05 – 0.15
(.002 – .006)
FE38 (AA) TSSOP REV C 0910
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3305fb
For more information www.linear.com/LTC3305
LTC3305
REVISION HISTORY
REV
DATE
DESCRIPTION
A
09/15
Added timer mode section.
13
Modified Figure 6 schematic.
16
Modified Figure 8 schematic.
22
Modified Figure 9 schematic.
23
Updated Feature bulleted items and description
1
B
03/16
PAGE NUMBER
Updated Application schematic
1
Enhanced Operation section
11
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTC3305
tion that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
27
LTC3305
TYPICAL APPLICATION
A Minimum Component Application in Which an LED is Used to Display Status
10µF
25V
D1, D2 = CMMSH1-100
D1
1µF
6V
100Ω
VREG
EN1
EN2
MODE
TERM1
TERM2
CP
CM
10µF
25V
V4
NGATE5
6.04k
D2
NGATE4
10µF
25V
UVFLT
OVFLT
DONE
BAL
PTCFLT
BATX
BATY
+
6.04k
V3
3.01k
NGATE3
BAT4
+
BAT3
10µF
25V
V2
LTC3305
V1
CTOFF
CTBAT
NGATE2
10µF
25V
CTON
10nF
1.33k
249Ω
BOOST
NGATE1-9
10µF
25V
+
6.04k
NGATE6
6.04k
NGATE1
+
6.04k
9
6.04k
NGATE7
VL
BAT2
BAT1
ALL NMOS
DEVICES = SiR882DP
PTC
AUXP
VH
10µF
25V
ISET
12.1k
GND
+
AUX
6.04k
NGATE8
AUXN
6.04k
NGATE9
3305 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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High Voltage High Current Controller for Battery Charging
and Power Management
Complete High Performance Battery Charger When Paired with a DC/DC
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LTC3630A
High Efficiency, 65V 500mA Synchronous Step Down
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Efficiently Generates a Low Voltage Rail. Synchronous Operation for high
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Measures Current, Voltage, Power, Charge and Energy in a Battery Stack
up to 100V
28 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC3305
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3305
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LT 0316 REV B • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2015
