LTC3307A
5V, 3A Synchronous Step-Down Silent Switcher in
2mm x 2mm LQFN and 1.6mm x 1.6mm WLCSP
FEATURES
DESCRIPTION
Pin Compatible with LTC3308(4A) and LTC3309(6A)
n High Efficiency: 8mΩ NMOS, 31mΩ PMOS
n Programmable Frequency 1MHz to 3MHz
n Tiny Inductor and Capacitors
n Peak Current Mode Control
n 22ns Minimum On-Time
n Wide Bandwidth, Fast Transient Response
n Silent Switcher® Architecture
n Ultralow EMI Emissions
n Low Ripple Burst Mode® Operation with I of 40µA
Q
n Safely Tolerates Inductor Saturation in Overload
n V Range: 2.25V to 5.5V
IN
n V
OUT Range: 0.5V to VIN
n V
OUT Accuracy: ±1% Over Temperature Range
n Precision 400mV Enable Threshold, 1μA in Shutdown
n Power Good, Internal Compensation and Soft-Start
n Thermally Enhanced 12-Lead 2mm × 2mm LQFN and
16-Pin 1.64mm × 1.64mm WLCSP Packages
n AEC-Q100 Qualified for Automotive Applications
The LTC®3307A is a very small, high efficiency, low noise,
monolithic synchronous 3A step-down DC/DC converter
operating from a 2.25V to 5.5V input supply. Using constant frequency, peak current mode control at switching
frequencies 1MHz to 3MHz and minimum on-time as low
as 22ns, this regulator achieves fast transient response
with small external components. Silent Switcher architecture minimizes EMI emissions.
APPLICATIONS
All registered trademarks and trademarks are the property of their respective owners.
n
The LTC3307A operates in forced continuous or pulseskipping mode for low noise, or low-ripple Burst Mode
operation for high efficiency at light loads, ideal for battery-powered systems. The IC regulates output voltages
as low as 500mV. Other features include output overvoltage protection, short-circuit protection, thermal shutdown, clock synchronization, and up to 100% duty cycle
operation for low dropout. The device is available in a low
profile 12-lead 2mm × 2mm × 0.74mm LQFN package
with exposed pad for low thermal resistance, and a 16-pin
1.64mm × 1.64mm × 0.5mm WLCSP package.
Optical Networking, Servers, Telecom
Automotive, Industrial, Communications
n Distributed DC Power Systems (POL)
n FPGA, ASIC, µP Core Supplies
n Battery Operated Systems
n
n
TYPICAL APPLICATION
Efficiency and Power Loss
in Burst Mode Operation
High Efficiency, 2MHz, 1.2V, 3A Step-Down Converter
10
100
VIN = 2.25V TO 5.5V
90
1µF
0201
1µF
0201
VIN
VIN
SW
SW
10pF
LTC3307A
VOUT
1.2V
3A
140k
FB
VIN
100k
15µF
×2
10nF
MODE/SYNC
RT
PGND
PGOOD
fOSC = 2MHz
Document Feedback
50
40
30
10
3307A TA01a
0.1
60
20
AGND
1
70
0
0.001
0.01
POWER LOSS
VIN = 3.3V
VOUT = 1.2V
fSW = 2 MHz
0.001
MURATA DFE201210S-R47M
0.01
0.1
LOAD CURRENT (A)
1
3
3307A TA01b
For more information www.analog.com
POWER LOSS (W)
EN
470nH
EFFICIENCY
80
4.7µF
EFFICIENCY (%)
4.7µF
0.0001
Rev. C
1
LTC3307A
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN ............................................................... –0.3V to 6V
EN......................... –0.3V to Lesser of (VIN + 0.3V) or 6V
FB ......................... –0.3V to Lesser of (VIN + 0.3V) or 6V
MODE/SYNC......... –0.3V to Lesser of (VIN + 0.3V) or 6V
RT......................... –0.3V to Lesser of (VIN + 0.3V) or 6V
AGND to PGND........................................ –0.3V to +0.3V
PGOOD.......................................................... –0.3V to 6V
IPGOOD.......................................................................5mA
Operating Junction Temperature Range (Note 2):
LTC3307AE........................................ –40˚C to +125°C
LTC3307AI......................................... –40˚C to +125°C
LTC3307AA........................................ –40˚C to +125°C
LTC3307AJ........................................ –40˚C to +150°C
LTC3307AH........................................ –40˚C to +150°C
LTC3307AMP..................................... –55˚C to +150°C
Storage Temperature Range.................. –65˚C to +150°C
Maximum Reflow (Package Body) Temperature.... 260°C
PIN CONFIGURATION
2
VIN
3
PGND
4
PGOOD
EN
12
11
13
PGND
5
6
TOP VIEW
1
2
3
4
FB
AGND
PGOOD
RT
VIN
EN
MODE/
SYNC
VIN
PGND
SW
SW
PGND
PGND
SW
SW
PGND
A
10 RT
9
MODE/SYNC
8
VIN
7
PGND
B
C
D
SW
1
SW
AGND
FB
TOP VIEW
LQFN PACKAGE
12-LEAD (2mm × 2mm × 0.74mm)
WLCSP PACKAGE
CB-16-11
16-PIN (1.64mm × 1.64mm × 0.5mm)
TJMAX = 150°C, θJA = 51°C/W, θJB = 12°C/W,
θJCBOTTOM = 8.6°C/W, θJCTOP = 73°C/W, ΨJT = 0.6°C/W
θ AND Ψ VALUES DETERMINED PER JESD51-7 ON A JEDEC 2S2P PCB,
EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 58°C/W, θJCTOP = 2.7°C/W,
θJB = 14.8°C/W, ΨJT = 2.1°C/W, ΨJB = 15°C/W
θ AND Ψ VALUES DETERMINED PER JESD51-7 ON A JEDEC 2S2P PCB
Rev. C
2
For more information www.analog.com
LTC3307A
ORDER INFORMATION
TAPE AND REEL
TAPE AND REEL MINI
PART MARKING*
PACKAGE TYPE
TEMPERATURE RANGE
LTC3307AEV#TRPBF
LTC3307AEV#TRMPBF
LHFR
LQFN (Laminate Package with QFN Footprint)
–40°C to 125°C
LTC3307AIV#TRPBF
LTC3307AIV#TRMPBF
LHFR
LQFN (Laminate Package with QFN Footprint)
–40°C to 125°C
LTC3307AJV#TRPBF
LTC3307AJV#TRMPBF
LHFR
LQFN (Laminate Package with QFN Footprint)
–40°C to 150°C
LTC3307AHV#TRPBF
LTC3307AHV#TRMPBF
LHFR
LQFN (Laminate Package with QFN Footprint)
–40°C to 150°C
LTC3307AMPV#TRPBF
LTC3307AMPV#TRMPBF
LHFR
LQFN (Laminate Package with QFN Footprint)
–55°C to 150°C
LTC3307AACBZ-R7
N/A
3307A
LTC3307AEV#WTRPBF
LTC3307AEV#WTRMPBF
LHFR
LQFN (Laminate Package with QFN Footprint)
–40°C to 125°C
LTC3307AIV#WTRPBF
LTC3307AIV#WTRMPBF
LHFR
LQFN (Laminate Package with QFN Footprint)
–40°C to 125°C
LTC3307AJV#WTRPBF
LTC3307AJV#WTRMPBF
LHFR
LQFN (Laminate Package with QFN Footprint)
–40°C to 150°C
LTC3307AHV#WTRPBF
LTC3307AHV#WTRMPBF
LHFR
LQFN (Laminate Package with QFN Footprint)
–40°C to 150°C
WLCSP (16-Pin Wafer Level Chip Scale Package) –40°C to 125°C
AUTOMOTIVE PRODUCTS**
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500-unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range (Note 2), otherwise specifications are at TA = 25°C; VIN = 3.3V, VEN = VIN, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply
Operating Supply Voltage (VIN)
VIN Undervoltage Lockout
VIN Undervoltage Lockout Hysteresis
VIN Rising
VIN Quiescent Current in Shutdown
VEN = 0.1V
VIN Quiescent Current
Burst Mode Operation, Sleeping
All Modes, Not Sleeping (Note 3)
Enable Threshold
Enable Threshold Hysteresis
VEN Rising
EN Pin Leakage
VEN =0.5V
l
2.25
l
2.0
l
0.375
2.1
150
5.5
V
2.2
V
mV
1
2
µA
40
1.2
60
2
µA
mA
0.4
50
0.425
V
mV
±20
nA
0.5
0.505
V
0.015
0.05
%/V
±20
nA
42
ns
Voltage Regulation
Regulated Feedback Voltage (VFB)
l
Feedback Voltage Line Regulation
VIN = 2.25V to 5.5V
FB Pin Input Current
VFB = 0.5V
Minimum On Time (tON,MIN)
VIN = 5.5V
Maximum Duty Cycle
0.495
22
l
l
100
Top Switch ON-Resistance
31
Bottom Switch ON-Resistance
Top Switch Current Limit (IPEAKMAX)
%
mΩ
8
VOUT/VIN ≤ 0.2
4.5
4.8
mΩ
5.1
A
Rev. C
For more information www.analog.com
3
LTC3307A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range (Note 2), otherwise specifications are at TA = 25°C; VIN = 3.3V, VEN = VIN, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Bottom Switch Current Limit (IVALLEYMAX)
TYP
MAX
3.9
Bottom Switch Reverse Current Limit (IREVMAX)
Forced Continuous Mode, LQFN
Forced Continuous Mode, WLCSP
SW Leakage Current
VEN = 0.1V
–0.75
–0.75
–1.5
–1.5
UNITS
A
–2.25
–2.55
±100
A
A
nA
Power Good and Soft-Start
PGOOD Rising Threshold
PGOOD Hysteresis
As a Percentage of the Regulated VOUT
l
l
97
0.7
98
1.2
99
1.7
%
%
Overvoltage Rising Threshold
Overvoltage Hysteresis
As a Percentage of the Regulated VOUT
l
l
107
1
110
2.2
114
3.5
%
%
PGOOD Delay
120
PGOOD Pull Down Resistance
VPGOOD = 0.1V
10
PGOOD Leakage Current
VPGOOD = 5.5V
Soft-Start Duration
VOUT rising from 0V to PGOOD Threshold
µs
20
Ω
20
nA
l
0.25
1
3
ms
Default Oscillator Frequency
l
1.9
2
2.1
MHz
Oscillator Frequency with RT = 34.8kΩ
l
1.9
2
2.1
MHz
3
MHz
Oscillator and MODE/SYNC
Frequency Range
RT Programming and Synchronization
Minimum SYNC High or Low Pulse Width
SYNC Pulse Voltage Levels
Level High
Level Low
l
1
l
40
l
l
1.2
MODE/SYNC No Clock Detect Time
MODE/SYNC Pin Threshold
ns
0.4
10
For Programming Pulse-Skipping Mode
For Programming Forced Continuous Mode
For Programming Burst Mode Operation
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3307A is tested under pulsed load conditions such
that TJ ≈ TA. The LTC3307AEV is guaranteed to meet specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization, and correlation with statistical process controls. The
LTC3307AIV is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTC3307AJV and LTC3307AHV are guaranteed
over the –40°C to 150°C operating junction temperature range. The
LTC3307AMPV is guaranteed over the –55°C to 150°C operating junction
temperature range. The LTC3307AACBZ specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization, and correlation with statistical process controls. High
junction temperatures degrade operating lifetimes; operating lifetime is
l
l
l
1.0
VIN – 0.1
Float
V
V
µs
0.1
VIN – 1.0
V
V
V
derated for junction temperatures above 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance, and other environmental factors. The junction
temperature (TJ in °C) is calculated from ambient temperature (TA in °C)
and power dissipation (PD in Watts) according to the formula:
TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal
impedance. See High Temperature Considerations section for more
details.
The LTC3307A includes overtemperature protection that protects the
device during momentary overload conditions. Junction temperatures will
exceed 150°C when overtemperature protection is engaged. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 3: Supply current specification does not include switching currents.
Actual supply currents will be higher.
Rev. C
4
For more information www.analog.com
LTC3307A
TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Voltage
VIN = 3.3V, TA = 25°C, unless otherwise noted.
Minimum On-Time
505
Minimum On-Time
60
60
50
50
502
501
500
499
498
497
MINIMUM ON–TIME (ns)
503
MINIMUM ON–TIME (ns)
40
30
20
150°C
25°C
–50°C
10
496
495
–50 –25
0
0
25 50 75 100 125 150
TEMPERATURE (ºC)
2
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
3307A G01
40
PMOS
NMOS
RDS(ON) (mΩ)
RDS(ON) (mΩ)
28
24
20
16
VIN = 3.3V
2.16
25
PMOS
NMOS
20
2.12
2.08
2.04
2.00
1.96
1.92
1.88
1.84
5
–50 –25
5.5
0
1.80
25 50 75 100 125 150
TEMPERATURE (°C)
3307A G04
2.20
2.16
3.0
2.16
2.8
2.12
2.4
2.2
2.0
1.8
1.6
1.4
1.88
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
1.84
1.80
–50 –25
FREQUENCY (MHz)
FREQUENCY (MHz)
1.92
0
25 50 75 100 125 150
TEMPERATURE (°C)
3307A G07
5.5
RT = 34.8kΩ
2.08
2.04
2.00
1.96
1.92
1.88
1.2
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
1.84
1.0
0.8
5
2.12
2.6
1.96
3
3.5
4
4.5
INPUT VOLTAGE (V)
RT Switching Frequency
3.2
2.00
2.5
3307A G06
Switching Frequency
Default Switching Frequency
2.04
2
3307A G05
2.20
2.08
25 50 75 100 125 150
TEMPERATURE (°C)
3307A G03
10
8
5
0
Default Switching Frequency
15
12
3
3.5
4
4.5
INPUT VOLTAGE (V)
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
2.20
30
32
DEFAULT FREQUENCY (MHz)
0
–50 –25
5.5
35
36
2.5
20
Switch On Resistance
40
2
30
3307A G02
Switch On Resistance
44
4
5
40
10
DEFAULT FREQUENCY (MHz)
FEEDBACK VOLTAGE (mV)
504
20 25 30 35 40 45 50 55 60 65 70 75
RT (kΩ)
3307A G08
1.80
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3307A G09
Rev. C
For more information www.analog.com
5
LTC3307A
TYPICAL PERFORMANCE CHARACTERISTICS
Switch Current Limits
PMOS Current Limit
5.5
DUTY CYCLE = 20%
DUTY CYCLE = 20%
5.0
PMOS CURRENT (A)
5.0
SWITCH CURRENT (A)
PMOS
PMOS Current
Current Limit
Limit
5.5
4.5
4.0
3.5
3.0
0
4.5
4.0
3.5
150°C
25°C
–60°C
3.0
NMOS IVALLEYMAX
PMOS IPEAKMAX
2.5
–50 –25
5.0
PMOS CURRENT (A)
5.5
VIN = 3.3V, TA = 25°C, unless otherwise noted.
2.5
25 50 75 100 125 150
TEMPERATURE (°C)
2
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
5
2.5
VIN = 2.5V
VIN = 3.3V
VIN = 5V
3.0
2.5
5.5
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3307A G12
VIN Quiescent Current All Modes,
Not Sleeping
70
1.30
65
2.0
1.25
1.5
1.0
VIN CURRENT (mA)
60
VIN CURRENT (µA)
VIN CURRENT (µA)
3.5
VIN Quiescent Current, Burst
Mode Operation, Sleeping
VIN Shutdown Current
55
50
45
1.20
1.15
1.10
40
0.5
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
35
0
–50 –25
0
30
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
25 50 75 100 125 150
TEMPERATURE (°C)
3307A G13
0
–50 –25
2.3
390
VIN UVLO (V)
EN THRESHOLD (mV)
0
VIN UVLO Threshold
EN RISING
380
370
360
EN FALLING
350
PMOS
NMOS
25 50 75 100 125 150
TEMPERATURE (°C)
25 50 75 100 125 150
TEMPERATURE (°C)
2.4
400
4
2
0
3307A G15
EN Threshold
VIN = 5.5V
1
1.00
–50 –25
410
3
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
1.05
3307A G14
Switch Leakage
SWITCH LEAKAGE CURRENT (µA)
4.0
3307A G11
3307A G10
5
4.5
340
–50 –25
0
2.2
2.1
2.0
1.9
25 50 75 100 125 150
TEMPERATURE (°C)
3307A G17
3307A G16
RISING
FALLING
1.8
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3307A G18
Rev. C
6
For more information www.analog.com
LTC3307A
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT Load Regulation in
112
1.210
110
1.208
VOUT = 1.2V
= 1.2V Application
UV,
UV,
OV,
OV,
102
100
VOUT RISING
VOUT FALLING
VOUT RISING
VOUT FALLING
98
96
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1.204
1.202
1.202
1.200
1.198
1.194
1.194
1.192
1.192
0.5
1
100
2.5
3
1.190
100
95
90
85
85
VOUT = 0.5V
VOUT = 0.75V
VOUT = 1V
VOUT = 1.2V
VOUT = 1.8V
55
50
0.001
93
0.01
0.1
ILOAD (A)
1
VOUT = 0.5V
VOUT = 0.75V
VOUT = 1V
VOUT = 1.2V
VOUT = 1.8V
65
50
0.001
3
0.01
3307A G22
95
MURATA DFE201612E SERIES
EFFICIENCY (%)
90
330nH
470nH
680nH
1.4
1.8
2.2
2.6
SWITCHING FREQUENCY (MHz)
3.0
3307A G25
0.1
ILOAD (A)
1
75
70
50
0.001
3
100
90
80
70
87
85
83
81
2.5
3
3.5
4
VIN (V)
5
5.5
3307A G26
1
3
3307A G24
fSW = 2MHz, MURATA DFE201612E-R47M
60
50
40
30
BURST
FC
PULSE-SKIPPING
10
4.5
0.1
ILOAD (A)
Efficiency vs Load, 3.3V to 1.2V,
fSW = 2MHz
20
0.01A (BURSTING)
3A (CONTINUOUS)
2
0.01
3307A G23
89
75
VOUT = 1V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
65
91
77
5.5
80
55
fSW = 2MHz MURATA DFE201612E-R47M
79
5
fSW = 2MHz MURATA DFE201210S-R47M
60
Efficiency vs VIN, VOUT = 1.2V,
fSW = 2MHz, Burst Mode Operation
93
91
1
70
55
92
88
75
60
Efficiency vs fSW,
3.3VIN to 1.2VOUT, ILOAD = 1.5A
89
80
EFFICIENCY (%)
65
EFFICIENCY (%)
90
70
3
3.5
4
4.5
INPUT VOLTAGE (V)
Efficiency, VIN = 5.0V
Burst Mode Operation
85
75
2.5
3307A G21
90
80
2
3307A G20
fSW = 2MHz MURATA DFE201210S-R47M
95
EFFICIENCY (%)
EFFICIENCY (%)
2
Efficiency, VIN = 3.3V
Burst Mode Operation
fSW = 2MHz MURATA DFE201210S-R47M
60
EFFICIENCY (%)
1.5
ILOAD (A)
Efficiency, VIN = 2.5V
Burst Mode Operation
95
1.198
1.196
3307A G19
100
1.200
1.196
0
ILOAD = 0A
ILOAD = 1A
ILOAD = 2A
ILOAD = 3A
1.206
1.204
1.190
VOUT Line Regulation in
VOUT = 1.2V Application
1.208
VOUT (V)
106
1.210
VIN = 2.5V
VIN = 3.3V
VIN = 5V
1.206
108
VOUT (V)
PERCENTAGE OF THE REGULATED VOUT (%)
UV, OV PGOOD Thresholds
104
VIN = 3.3V, TA = 25°C, unless otherwise noted.
0
0.001
0.01
0.1
ILOAD (A)
1
3
3307A G27
Rev. C
For more information www.analog.com
7
LTC3307A
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up Waveforms
Forced Continuous Mode
VIN = 3.3V, TA = 25°C, unless otherwise noted.
Start-Up Waveforms
Pulse-Skipping Mode
Start-Up Waveforms
Burst Mode
EN
2V/DIV
EN
2V/DIV
EN
2V/DIV
VOUT
500mV/DIV
IL
500mA/DIV
VOUT
500mV/DIV
VOUT
500mV/DIV
IL
250mA/DIV
IL
250mA/DIV
PGOOD
2V/DIV
200µs/DIV
3307A G28
PGOOD
2V/DIV
200µs/DIV
3307A G29
PGOOD
2V/DIV
200µs/DIV
3307A G30
3.3VIN TO 1.2VOUT, 2MHz TYPICAL APPLICATION
RLOAD = 120Ω
3.3VIN TO 1.2VOUT, 2MHz TYPICAL APPLICATION
RLOAD = 120Ω
3.3VIN TO 1.2VOUT, 2MHz TYPICAL APPLICATION
RLOAD = 120Ω
Switching Waveforms,
Forced Continuous Mode
Switching Waveforms,
Pulse-Skipping Mode
Switching Waveforms,
Burst Mode Operation
SW
2V/DIV
SW
2V/DIV
IL
500mA/DIV
IL
200mA/DIV
VOUT
5mV/DIV
VOUT
5mV/DIV
3307A G31
SW
2V/DIV
IL
500mA/DIV
VOUT
10mV/DIV
3307A G33
3307A G32
200ns/DIV
3.3VIN TO 1.2VOUT, 2MHz TYPICAL APPLICATION
ILOAD = 500mA
3.3VIN TO 1.2VOUT, 2MHz TYPICAL APPLICATION
ILOAD = 40mA
800ns/DIV
3.3VIN TO 1.2V OUT, 2MHz TYPICAL APPLICATION
ILOAD = 50mA
Load Transient Response,
Forced Continuous Mode
Load Transient Response,
Pulse-Skipping Mode
Load Transient Response,
Burst Mode Operation
150ns/DIV
ILOAD
2A/DIV
ILOAD
2A/DIV
ILOAD
2A/DIV
IL
2A/DIV
IL
2A/DIV
IL
2A/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
10µs/DIV
3307A G34
3.3VIN TO 1.2VOUT, 2MHz TYPICAL APPLICATION
COUT = 30µF, L = 470nH
LOAD STEP: 50mA TO 2.25A (10A/μs)
10µs/DIV
3307A G35
3.3VIN TO 1.2VOUT, 2MHz TYPICAL APPLICATION
COUT = 30µF, L = 470nH
LOAD STEP: 50mA TO 2.25A (10A/μs)
10µs/DIV
3307A G36
3.3VIN TO 1.2VOUT, 2MHz TYPICAL APPLICATION
COUT = 30µF, L = 470nH
LOAD STEP: 50mA TO 2.25A (10A/μs)
Rev. C
8
For more information www.analog.com
LTC3307A
PIN FUNCTIONS
(LQFN/WLCSP)
AGND (Pin 1/Pin A2): The AGND pin is the output voltage
remote ground sense. Connect the AGND pin directly to
the negative terminal of the output capacitor at the load.
The AGND pin is also the ground reference for the internal
analog circuitry. Place a small analog bypass 0201 or
0402 ceramic capacitor as close as possible to the VIN
(Pin 3/Pin B1) and AGND pins. Connect RT and FB returns
to AGND as well.
EN (Pin 2/Pin B2): The EN pin has a precision IC enable
threshold with hysteresis. An external resistor divider,
from VIN or from another supply, can be used to program
the threshold below which the LTC3307A will shut down.
If the precision threshold is not required, tie EN directly
to VIN. When the EN pin is low the LTC3307A enters a
low current shutdown mode where all internal circuitry
is disabled. Do not float this pin.
VIN (Pins 3, 8/Pins B1, B4): The VIN pins supply current
to internal circuitry and topside power switch. Connect
both VIN pins together with short wide traces and bypass
to PGND and AGND with low ESR capacitors located as
close as possible to the pins.
PGND (Pins 4, 7, Exposed Pad Pin 13/Pins C1, C4, D1,
D4): The PGND pins are the return path of the internal
bottom side power switch. Connect the negative terminal of the input capacitors as close to the PGND pins as
possible. For low parasitic inductance and good thermal
performance, connect Pin 4 and Pin 7 (Pins C1, C4, D1,
D4) to a large continuous ground plane on the printed
circuit board directly under the LTC3307A. On the LQFN
package, the PGND exposed pad is the main electrical and
thermal highway and should be connected to large PCB
ground plane(s) with many vias.
SW (Pins 5, 6/Pins C2, C3, D2, D3): The SW pins are the
switching outputs of the internal power switches. Connect
these pins together and to the inductor with a short, wide
trace.
MODE/SYNC (Pin 9/Pin B3): The MODE/SYNC pin is a
mode selection and external clock synchronization input.
Ground this pin to enable pulse-skipping mode at light
loads. For higher efficiency at light loads, tie this pin to
VIN to enable the low-ripple Burst Mode operation. For
faster transient response, lower noise and full frequency
operation over a wide load range, float this pin to enable
forced continuous mode. Drive MODE/SYNC with an
external clock to synchronize the switcher to the applied
frequency. While synchronizing, the part operates in the
forced continuous mode. The slope compensation is automatically adapted to the external clock frequency. In the
absence of an external clock the switching frequency is
determined by the RT pin.
RT (Pin 10/Pin A4): The RT pin sets the switching frequency with an external resistor to AGND. If this pin is
tied to VIN, the buck will switch at the default oscillator
frequency. If the external clock is driving the MODE/SYNC
pin, the RT pin is ignored.
PGOOD (Pin 11/Pin A3): The PGOOD pin is the open drain
output of an internal power good comparator. When the
regulated output voltage falls below the PGOOD threshold or rises above the overvoltage threshold, this pin is
pulled low. When VIN is above VIN UVLO and the part is
in shutdown, this pin is also pulled low.
FB (Pin 12/Pin A1): Program the output voltage and close
the control loop by connecting this pin to the middle node
of a resistor divider between the VOUT and AGND. The
LTC3307A regulates FB to 500mV (typical). A phase lead
capacitor connected between FB and VOUT may be used
to optimize transient response.
Rev. C
For more information www.analog.com
9
LTC3307A
BLOCK DIAGRAM
VIN
R1
EN
2, B2
R2
(OPT)
0.4V
MODE/SYNC
9, B3
RT
10, A4
+
–
MODE
DETECT
0.55V
0.5V
0.49V
INTERNAL
REFERENCE
VIN
3, 8, B1, B4
BURST
FORCED CONTINUOUS
PULSE-SKIPPING
SWITCH LOGIC
AND
ANTI-SHOOT
THROUGH
S Q
OSCILLATOR
RT
R
+
–
L
VOUT
COUT
4, 7,
13 (EXPOSED PAD),
C1, C4, D1, D4
BURST
DETECT
GM
VC
CPAR
SW 5, 6, C2,
C3, D2, D3
PGND
SLOPE
COMP
AGND
1, A2
VIN
CIN
0.5V 0.49V
RC
CC
0.55V
+
–
+
–
FB
12, A1
RA
PGOOD
11, A3
RB
CFF
FAULT
ISS
SS
FAULT
CSS
3307A BD
Rev. C
10
For more information www.analog.com
LTC3307A
OPERATION
Voltage Regulation
Mode Selection
The LTC3307A is a 5V, 3A monolithic, constant frequency,
peak current mode control, step-down DC/DC converter.
The synchronous buck switching regulators are internally
compensated and require only external feedback resistors
to set the output voltage. An internal oscillator, with the
frequency set using a resistor on the RT pin or synchronized to an external clock, turns on the internal top power
switch at the beginning of each clock cycle. Current in the
inductor ramps up until the top switch current comparator
trips and turns off the top power switch. The peak inductor current at which the top switch turns off is controlled
by an internal VC voltage. The error amplifier regulates VC
by comparing the voltage on the FB pin with an internal
500mV reference. An increase in the load current causes a
reduction in the feedback voltage relative to the reference,
causing the error amplifier to raise the VC voltage until the
average inductor current matches the new load current.
When the top power switch turns off, the synchronous
power switch turns on and ramps down the inductor current for the remainder of the clock cycle or, if in pulseskipping or Burst mode, until the inductor current falls to
zero. If an overload condition results in excessive current
flowing through the bottom switch, the next clock cycle
will be skipped until switch current returns to a safe level.
The LTC3307A operates in three different modes set by
the MODE/SYNC pin: pulse-skipping mode (when the
MODE/SYNC pin is set low), forced continuous mode
(when the MODE/SYNC pin is floating) and Burst Mode
operation (when the MODE/SYNC pin is set high).
The enable pin has a precision 400mV threshold to provide event-based power-up sequencing by connecting the
EN pin to the output of another buck through a resistor
divider. If the EN pin is low, the device is shut down and
in a low quiescent current state. When the EN pin is above
its threshold, the switching regulator will be enabled.
The LTC3307A has forward and reverse inductor current
limiting, short-circuit protection, output over-voltage protection, and soft-start to limit inrush current during startup or recovery from a short-circuit.
In pulse-skipping mode, the oscillator operates continuously and positive SW transitions are aligned to the
clock. Negative inductor current is disallowed and, during light loads, switch pulses are skipped to regulate the
output voltage.
In forced continuous mode, the oscillator operates continuously. The top switch turns on every cycle and regulation is maintained by allowing the inductor current to
reverse at light load. This mode allows the buck to run
at a fixed frequency with minimal output ripple. In forced
continuous mode, if the inductor current reaches IREVMAX
(into the SW pin), the bottom switch will turn off for the
remainder of the cycle to limit the current.
In Burst Mode operation at light loads, the output capacitor is charged to a voltage slightly higher than its regulation point. The regulator then goes into a sleep state,
during which time the output capacitor provides the
load current. In sleep, most of the regulator’s circuitry is
powered down, helping conserve input power. When the
output voltage drops below its programmed value, the
circuitry is powered on and another burst cycle begins.
The sleep time decreases as load current increases. In
Burst Mode operation, the regulator will burst at light
loads whereas at higher loads it will operate in constant
frequency PWM mode.
Rev. C
For more information www.analog.com
11
LTC3307A
OPERATION
Synchronizing the Oscillator to an External Clock
Output Overvoltage Protection
The LTC3307A’s internal oscillator can be synchronized
through an internal PLL circuit to an external frequency
by applying a square wave clock signal to the MODE/
SYNC pin.
During an output overvoltage event, when the FB pin voltage is greater than 110% of nominal, the LTC3307A top
power switch will be turned off. If the output remains out
of regulation for more than 120µs, the PGOOD pin will
be pulled low.
During synchronization, the top power switch turn-on is
locked to the rising edge of the external frequency source.
While synchronizing, the switcher operates in forced continuous mode. The slope compensation is automatically
adapted to the external clock frequency. The synchronization frequency range is 1MHz to 3MHz.
After detecting an external clock on the first rising edge
of the MODE/SYNC pin, the internal PLL gradually adjusts
its operating frequency to match the frequency and phase
of the signal on the MODE/SYNC pin. When the external
clock is removed, the LTC3307A will detect the absence
of the external clock within approximately 10μs. During
this time, the PLL will continue to provide clock cycles.
Once the external clock removal has been detected, the
oscillator will gradually adjust its operating frequency to
the one programmed by the RT pin.
Output Power Good
When the LTC3307A’s output voltage is within the
–2%/+10% window of the nominal regulation voltage the
output is considered good and the open-drain PGOOD pin
goes high impedance and is typically pulled high with an
external resistor. Otherwise, the internal pull-down device
will pull the PGOOD pin low. The PGOOD pin is also pulled
low during the following fault conditions: EN pin is low,
VIN is too low or thermal shutdown. To filter noise and
short duration output voltage transients, the lower threshold has a hysteresis of 1.2%, the upper threshold has a
hysteresis of 2.2%, and both have a built-in time delay to
report PGOOD, typically 120µs.
An output overvoltage event should not happen under
normal operating conditions.
Overtemperature Protection
To prevent thermal damage to the LTC3307A and its surrounding components, the device incorporates an overtemperature (OT) function. When the die temperature
reaches 165°C (typical, not tested) the switcher is shut
down and remains in shutdown until the die temperature
falls to 160°C (typical, not tested).
Output Voltage Soft-Start
Soft starting the output prevents current surge on the
input supply and/or output voltage overshoot. During the
soft-start, the output voltage will proportionally track the
internal node voltage ramp. An active pull-down circuit
discharges that internal node in the case of fault conditions. The ramp will restart when the fault is cleared. Fault
conditions that initiate the soft-start ramp are the EN pin
transitioning low, VIN voltage falling too low, or thermal
shutdown.
Dropout Operation
As the input supply voltage approaches the output voltage, the duty cycle increases toward 100%. Further reduction of the supply voltage forces the main switch to remain
on for more than one cycle, eventually reaching 100%
duty cycle. The output voltage will then be determined by
the input voltage minus the DC voltage drop across the
internal P-channel MOSFET and the inductor.
Rev. C
12
For more information www.analog.com
LTC3307A
Low Supply Operation
The LTC3307A is designed to operate down to an input
supply voltage of 2.25V. One important consideration at
low input supply voltages is that the RDS(ON) of the internal power switches increases. Calculate the worst case
LTC3307A power dissipation and die junction temperature
at the lowest input voltages.
Output Short-Circuit Protection and Recovery
The peak inductor current level, at which the current comparator shuts off the top power switch, is controlled by the
internal VC voltage. When the output current increases,
the error amplifier raises VC until the average inductor
current matches the load current. The LTC3307A clamps
the maximum VC voltage, thereby limiting the peak inductor current.
When the output is shorted to ground, the inductor current decays very slowly when the bottom power switch
is on because the voltage across the inductor is low. To
keep the inductor current in control, a secondary limit is
imposed on the valley of the inductor current. If the inductor current measured through the bottom power switch
remains greater than IVALLEYMAX at the end of the cycle,
the top power switch will be held off. Subsequent switching cycles will be skipped until the inductor current falls
below IVALLEYMAX.
Recovery from an output short circuit may involve a softstart cycle if VFB falls more than approximately 100mV
below regulation. During such a recovery, VFB will quickly
charge up by that ~100mV and then follow the soft-start
ramp until regulation is reached.
APPLICATIONS INFORMATION
Refer to the Block Diagram for reference.
Output Voltage and Feedback Network
The output voltage is programmed by a resistor divider
between the output and the FB pin. Choose the resistor
values according Equation 1.
⎛ V
⎞
RA = RB ⎜ OUT – 1⎟
⎝ 500mV ⎠
(1)
as shown in Figure 1:
Reference designators refer to the Block Diagram. Typical
values for RB range from 40kΩ to 400kΩ. 0.1% resistors
are recommended to maintain output voltage accuracy.
The buck regulator transient response may improve with
an optional phase lead capacitor CFF that helps cancel
the pole created by the feedback resistors and the input
capacitance of the FB pin. Experimentation with capacitor values between 2pF and 22pF may improve transient
response. The values used in the typical application circuits are a good starting point.
Operating Frequency Selection and Trade-Offs
VOUT
BUCK
SWITCHING FB
REGULATOR
RA
RB
CFF
+
(OPTIONAL)
3307A F01
Figure 1. Feedback Resistor Network
COUT
Selection of the operating frequency is a trade-off between
efficiency, component size, transient response and input
voltage range.
The advantage of high frequency operation is that smaller
inductor and capacitor values may be used. Higher
switching frequencies allow for higher control loop
bandwidth and, therefore, faster transient response. The
disadvantages of higher switching frequencies are lower
efficiency, because of increased switching losses, and a
smaller input voltage range, because of minimum switch
on-time limitations.
Rev. C
For more information www.analog.com
13
LTC3307A
APPLICATIONS INFORMATION
The minimum on-time of the buck regulator imposes a
minimum operating duty cycle. The highest switching
frequency (fSW(MAX)) for a given application can be calculated with Equation 2.
fSW (MAX ) =
VOUT
tON(MIN) • VIN(MAX )
Table 1. RT Value vs Switching Frequency
fSW (MHz)
RT (kΩ)
1.0
71.5
1.2
59.0
1.4
49.9
1.6
43.2
1.8
38.3
2.0
34.8
2.2
30.9
2.4
28.7
2.6
26.1
2.8
24.3
3.0
22.6
(2)
where VIN(MAX) is the maximum input voltage, VOUT
is the output voltage and tON(MIN) is the minimum top
switch on-time. This equation shows that a slower
switching frequency is necessary to accommodate a high
VIN(MAX)/VOUT ratio.
The LTC3307A is capable of a maximum duty cycle of
100%, therefore, the VIN-to-VOUT dropout is limited by
the RDS(ON) of the top switch, the inductor DCR and the
load current.
Setting the Switching Frequency
Inductor Selection and Maximum Output Current
Considerations in choosing an inductor are inductance,
RMS current rating, saturation current rating, DCR and
core loss.
The LTC3307A uses a constant frequency peak current
mode control architecture. There are three methods to
set the switching frequency.
Select the inductor value based on Equation 4 and
Equation 5.
The first method, connecting the RT pin to VIN, sets the
switching frequency to the internal default with a nominal
value of 2MHz.
L≈
The second method is with a resistor (RT) tied from the
RT pin to ground. The frequency can be programmed
from 1MHz to 3MHz. Table 1 and the Equation 3 show
the necessary RT value for a desired switching frequency.
RT =
73.4
– 1.9
fsw
(3)
where RT is in kΩ and fSW is the desired switching frequency in MHz, ranging from 1MHz to 3MHz.
The third method to set the switching frequency is by synchronizing the internal PLL circuit to an external square
wave clock applied to the MODE/SYNC pin. The synchronization frequency range is 1MHz to 3MHz. The square
wave amplitude should have valleys that are below 0.4V
and peaks above 1.2V. High and low pulse widths should
both be at least 40ns.
L≈
⎛
⎞
VOUT
V
VOUT
• ⎜ 1− OUT ⎟ for
≤ 0.5 (4)
0.9A • fSW ⎝ VIN(MAX ) ⎠
VIN(MAX )
0.25 • VIN(MAX )
0.9A • fSW
for
VOUT
VIN(MAX )
> 0.5
(5)
where fSW is the switching frequency, VIN(MAX) is the
maximum input voltage.
To avoid overheating of the inductor choose an inductor with an RMS current rating that is greater than the
maximum expected output load of the application.
Overload and short-circuit conditions need to be taken
into consideration.
In addition, ensure that the saturation current rating
(typically labeled ISAT) of the inductor is higher than the
maximum expected load current plus half the inductor
ripple current use Equation 6.
1
ISAT > ILOAD(MAX ) + ∆IL
2
(6)
Rev. C
14
For more information www.analog.com
LTC3307A
APPLICATIONS INFORMATION
where ILOAD(MAX) is the maximum output load current for
a given application and ΔIL is the inductor ripple current
calculated with Equation 7.
⎛ V ⎞
V
∆IL = OUT • ⎜ 1– OUT ⎟
L • fSW ⎝
VIN ⎠
(7)
A more conservative choice would be to use an inductor
with an ISAT rating higher than the maximum current limit
of the LTC3307A.
To keep the efficiency high, choose an inductor with
the lowest series resistance (DCR). The core material
should be intended for high frequency applications.
Table 2 shows recommended inductors from several
manufacturers.
Input Capacitors
Bypass the input of the LTC3307A with at least two
ceramic capacitors close to the part, one on each side
from VIN to PGND, for best performance. These capacitors should be 0603 or 0805 in size. Smaller, optional
0201 capacitors can also be placed as close as possible
to the LTC3307A directly on the traces leading from VIN
(Pin 3, Pin B1) and PGND (Pin 4, Pins C1, D1) and on the
traces leading from VIN (Pin 8, Pin B4) and PGND (Pin 7,
Pins C4, D4) for better performance with minimal (if at all)
Table 2. Recommended Inductors with Typical Specifications
MANUFACTURER
INDUCTOR
FAMILY
INDUCTANCE (nH)
ITEMP (A)*
ISAT (A)
DCR (mΩ)
W × L × H (mm)
Murata
DFE18SAN-E0
240
3.2
4.2
36
1.6 × 0.8 × 0.8
Murata
DFE18SAN-G0
240
3.5
4.9
30
1.6 × 0.8 × 1.0
Murata
DFE201210S
110, 470
6.3, 4.0
11, 5.3
8, 27
2.0 × 1.2 × 1.0
Murata
DFE201210U
240 to 470
3.8 to 3.0
6.5 to 4.4
20 to 34
2.0 × 1.2 × 1.0
Murata
DFE201610E
240 to 680
5.5 to 3.7
7.0 to 4.8
16 to 36
2.0 × 1.6 × 1.0
Murata
DFE201612E
240 to 680
6.0 to 4.1
7.8 to 4.8
13 to 27
2.0 × 1.6 × 1.2
Murata
DFE201612PD
150
5.2
6.2
12
2.0 × 1.6 × 1.2
Murata
DFE252010F
330 to 680
5.6 to 4.1
7.6 to 5.5
16 to 31
2.5 × 2.0 × 1.0
Murata
DFE252012F
330 to 680
6.0 to 4.6
8.5 to 6.0
14 to 25
2.5 × 2.0 × 1.2
Vishay
IHHP-0806AB-01
220 to 470
5.3 to 4.2
5.8 to 4.4
13 to 29
2.0 × 1.6 × 1.2
Vishay
IHHP-1008AB-01
220 to 680
7.4 to 3.8
7.1 to 4.1
8.4 to 28
2.5 × 2.0 × 1.2
XFRMS
XFHCL43LT
220 to 470
8.0 to 4.5
7.0 to 3.8
13 to 25 (Max)
2.5 × 2.0 × 1.2
NIC
NPMH0805B
240, 470
4.2, 3.0
4.8, 3.2
25, 48 (Max)
2.0 × 1.2 × 0.8
NIC
NPMH0805C
240 to 470
3.7 to 3.0
4.5 to 3.3
28 to 42 (Max)
2.0 × 1.2 × 1.0
NIC
NPMH0806C
240 to 470
4.7 to 3.5
5.6 to 3.9
23 to 42 (Max)
2.0 × 1.6 × 1.0
NIC
NPIM26LP
240 to 680
6.5 to 4.2
7.5 to 5.1
15 to 36
2.0 × 1.6 × 1.0
NIC
NPIM20LP
240 to 680
6.0 to 4.4
9.5 to 5.5
18 to 32
2.5 × 2.0 × 1.0
Sumida
201610CDMCC/DS
240, 470
5.2, 3.8
6.5, 4.2
19, 34
2.2 × 1.8 × 1.0
Sumida
252010CDMCC/DS
330 to 1000
5.2 to 3.2
6.8 to 3.8
16 to 46
2.7 × 2.2 × 1.0
Wurth Electronik
WE-PMMI-0805LP
110
3
6
24
2.0 × 1.2 × 0.6
Wurth Electronik
WE-PMMI-0806
240 to 470
3.5 to 3.0
4.0 to 3.4
15 to 20
2.0 × 1.6 × 0.6
Wurth Electronik
WE-PMCI-0806
240, 470
3.6, 2.9
5.4, 4.2
19, 34
2.0 × 1.6 × 1.0
Wurth Electronik
WE-PMCI-1008
470
3.3
5
25
2.5 × 2.0 × 1.0
Wurth Electronik
WE-LQS-2512
160
3.7
6.4
16
2.5 × 2.0 × 1.2
TDK
TFM201208BLD
110
6.8
8.8
10
2.0 × 1.2 × 0.8
*Strongly depends on the PCB thermal properties
Rev. C
For more information www.analog.com
15
LTC3307A
APPLICATIONS INFORMATION
increase in application footprint. See the layout section for
more detail. X7R or X5R capacitors are recommended for
best performance across temperature and input voltage
variations (see Table 3). Note that larger input capacitance
is required when a lower switching frequency is used. If
the input power source has high impedance, or there is
significant inductance due to long wires or cables, additional bulk capacitance may be necessary. This can be
provided with an electrolytic capacitor.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (under damped) tank
circuit. If the LTC3307A circuit is plugged into a live supply, the input voltage can ring to twice its nominal value,
possibly exceeding the LTC3307A’s voltage rating. This
situation is easily avoided (see Application Note AN88).
Table 3. Ceramic Capacitor Manufacturers
VENDOR
URL
AVX
www.avxcorp.com
Murata
www.murata.com
TDK
www.tdk.com
Taiyo Yuden
www.t-yuden.com
Samsung
www.samsungsem.com
Wurth Elektronik
www.we-online.com
where COUT is the recommended output capacitor value
in µF, fSW is the switching frequency in MHz, IMAX = 3A
is the rated output current in Amps, and VOUT is in Volts.
A lower value output capacitor saves space and cost but
transient performance will suffer and loop stability must
be verified.
Ceramic capacitors have very low equivalent series
resistance (ESR) and provide the best output ripple and
transient performance. Use X5R or X7R ceramic capacitors (see Table 3). Even better output ripple and transient
performance can be achieved by using low-ESL reverse
geometry or three-terminal ceramic capacitors.
During a load step, the output capacitor must instantaneously supply the current to support the load until the
feedback loop increases the switch current enough to support the load. The time required for the feedback loop to
respond is dependent on the compensation components
and the output capacitor size. Typically, 3 to 4 cycles are
required to respond to a load step, but only in the first cycle
does the output drop linearly. Although affected by VOUT,
VIN, fSW, tON(MIN), the equivalent series inductance (ESL)
of the output capacitor, and other factors, the output droop,
VDROOP, is usually about 3 times the linear drop of the first
cycle given by Equation 9.
Output Capacitor, Output Ripple and Transient Response
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LTC3307A at the SW pin to produce the DC output.
In this role, it determines the output ripple; thus, low
impedance at the switching frequency is important. The
second function is to store energy in order to satisfy transient loads and stabilize the LTC3307A’s control loop.
The LTC3307A is internally compensated and has been
designed to operate at a high bandwidth for fast transient response capability. The selection of COUT affects
the bandwidth of the system, but the transient response is
also affected by VOUT, VIN, fSW and other factors. A good
place to start is with the output capacitance approximately
value given by Equation 8.
COUT = 20 •
IMAX
fSW
0.5
VOUT
(8)
VDROOP =
3 • ∆IOUT
COUT • fSW
(9)
where ∆IOUT is the load step.
Transient performance and control loop stability can be
improved with a higher COUT and/or the addition of a
feedforward capacitor CFF placed between VOUT and FB.
Capacitor CFF provides phase lead compensation by creating a high frequency zero which improves the phase
margin and the high-frequency response. The values used
in the typical application circuits are a good starting point.
LTpowerCAD® is a useful tool to help optimize CFF and
COUT for a desired transient performance.
Applying a load transient and monitoring the response of
the system or using a network analyzer to measure the
actual loop response are two ways to experimentally verify
Rev. C
16
For more information www.analog.com
LTC3307A
APPLICATIONS INFORMATION
transient performance and control loop stability, and to
optimize CFF and COUT.
When using the load transient response method to stabilize the control loop apply an output current pulse of
20% to 100% of full load current having a very fast rise
time. This will produce a transient on the output voltage.
Monitor VOUT for overshoot or ringing that might indicate
a stability problem (see Application Note AN149).
the regulator from operating at source voltages where
problems may occur. This threshold can be adjusted
by setting the values R1 and R2 such that they satisfy
Equation 10.
⎛ R1 ⎞
VIN(EN) = ⎜ + 1⎟ • 400mV
⎝ R2 ⎠
(10)
as shown in Figure 2:
Output Voltage Sensing
VIN
The LTC3307A’s AGND pin is the ground reference for the
internal analog circuitry, including the bandgap voltage
reference. To achieve good load regulation connect the
AGND pin to the negative terminal of the output capacitor
(COUT) at the load. Any drop in the high current power
ground return path will be compensated. The AGND node
carries very little current and, therefore, can be a minimal
size trace. Place a small analog bypass 0201 or 0402
ceramic capacitor as close as possible to the LTC3307A
directly on the traces leading from VIN (Pin 3, B1) and
AGND pin. All of the signal components, such as the FB
resistor dividers and the RT resistor, should be referenced to the AGND node. See the example PCB Layout
for more information.
Enable Threshold Programming
The LTC3307A has a precision threshold enable pin to
enable or disable the switching. When forced low, the
device enters a low current shutdown mode.
The rising threshold of the EN comparator is 400mV,
with 50mV of hysteresis. The EN pin can be tied to VIN
if the shutdown feature is not used. Adding a resistor
divider from VIN to EN programs the LTC3307A to regulate the output only when VIN is above a desired voltage
(see Figure 2). Typically, this threshold, VIN(EN), is used
in situations where the input supply is current limited, or
has a relatively high source resistance. A switching regulator draws near constant power from its input source,
so source current increases as source voltage drops. This
looks like a negative resistance load to the source and can
cause the source to current limit or latch low under low
source voltage conditions. The VIN(EN) threshold prevents
BUCK
SWITCHING EN
REGULATOR
R1
R2
3307A F02
Figure 2. EN Divider
The LTC3307A will remain off until VIN is above VIN(EN).
The buck regulator will remain enabled until VIN falls to
0.875 • VIN(EN) and EN is 350mV typical.
Alternatively, a resistor divider from an output of an
upstream regulator to the EN pin of the LTC3307A provides event-based power-up sequencing, enabling the
LTC3307A when the output of the upstream regulator
reaches a predetermined level (e.g. 90% of the regulated output). Replace VIN(EN) in Equation 10 with that
predetermined level.
Low EMI PCB Layout
The LTC3307A is specifically designed to minimize
EMI/EMC emissions and also to maximize efficiency
and improve transient response when switching at
high frequencies.
Reference the layout design files for the demo board for
both the LQFN and WLCSP packages on the LTC3307A
product page on the ADI website to see the optimal PCB
layout. See Figure 3 for a recommended PCB layout.
For optimal performance the LTC3307A requires that both
input supply VIN pins (Pins 3, 8/Pins B1, B4) each have
a local decoupling capacitor with their ground terminals
soldered directly to the ground plane on the top layer
near PGND pins (Pins 4, 7/Pins C1, C4, D1, D4). These
Rev. C
For more information www.analog.com
17
LTC3307A
APPLICATIONS INFORMATION
capacitors provide the AC current to the internal power
MOSFETs and their drivers. Large, switched currents flow
in the VIN and PGND pins and the input capacitors. The
loops formed by the input capacitors should be as small
as possible by placing the capacitors adjacent to the VIN
and PGND pins. Capacitors with small case size such
as 0603 are optimal due to lowest parasitic inductance.
Even smaller 0201 capacitors can additionally be placed
right next to the respective VIN and PGND pins for better
performance with minimal (if at all) increase in application footprint. In addition, place a local, unbroken ground
plane under the application circuit on the layer closest to
the surface layer.
Decoupling AGND is also very important. Place a small
analog bypass 0201 or 0402 capacitor as close as possible to the LTC3307A directly on the traces leading from
VIN (Pin 3/Pin B1) and AGND (Pin 1/Pin A2).
VIN
PGND
GROUND PLANE ON LAYER 2
COUT1
CIN1
VOUT
Place the inductor on the same side of the circuit board.
The trace connecting SW pins (Pins 5, 6/Pins C2, C3,
D2, D3) to the inductor should be as short as possible to
reduce radiated EMI and parasitic coupling.
Keep the FB and RT nodes small and far away or shielded
from the noisy SW node.
On the LQFN package, five 5mil vias are used to provide the best conductivity to the GND plane within the
EPAD. For layouts where 5mil vias are not allowed, it is
recommended to use either four 8mil vias or a single
(filled or tented) 12mil diameter via. Refer to the Thermal
Via Design section of the Analog Devices Application
Note, Application Notes for Thermally Enhanced Leaded
Plastic Packages for more information on thermal via
recommendations.
VIN
RT
7
CIN3
10
L
13
CFF
1
4
RA
CBYP
COUT3
CIN3
1
CIN2
COUT1
L
VOUT
4
CIN4
RB
COUT2
AGND
VIN
7
13
CFF
CIN4
RB
CIN1
RT
10
RA
PGND
GROUND PLANE ON LAYER 2
CBYP
COUT4
COUT2
CIN2
AGND
PGND
VOUT
VIN
3307A F03
(a) Small Solution Size. On the LQFN Package, Five 5mil Vias
Are Used within the EPAD. For Layouts Where 5mil Vias Are Not
Allowed, It Is Recommended to Use Either Four 8mil Vias or a
Single (Filled or Tented) 12mil Diameter Via.
PGND
3307A F03b
(b) With Capacitors COUT1 and COUT2 Rotated by 90°, Which
Reduces High Frequency Output Ripple. Optional 0201
Capacitors COUT3 and COUT4 Further Improve the High Frequency
Output Ripple. On the LQFN Package, Five 5mil Vias Are Used
within the EPAD. For Layouts Where 5mil Vias Are Not Allowed,
It Is Recommended to Use Either Four 8mil Vias or a Single
(Filled or Tented) 12mil Diameter Via.
Figure 3. Recommended PCB Layout for the LTC3307A LQFN Package
Rev. C
18
For more information www.analog.com
LTC3307A
APPLICATIONS INFORMATION
High Temperature Considerations
Care should be taken in the layout of the PCB to ensure
good heat sinking of the LTC3307A. On the LQFN package, connect the exposed pad on the bottom of the package (Pin 13) to a large, unbroken ground plane under the
application circuit on the layer closest to the surface layer.
Place many vias to minimize thermal and electrical impedance. Solder the PGND pins (Pins 4, 7/Pins C1, C4, D1,
D4) directly to a ground plane on the top layer. Connect
the top layer ground plane to ground plane(s) on lower
levels with many thermal vias. These layers will spread
heat dissipated by the LTC3307A. Figure 4 is a simplified thermal representation of a thermally enhanced LQFN
package with exposed pad, with the silicon die and thermal metrics identified. A simplified thermal representation
of a WLCSP package is very similar, with θJCBOTTOM representing the thermal conductivity of the Pins and redistribution layer instead of the LQFN substrate. The current
source represents power loss PD on the die; node voltages
represent temperatures; electrical impedances represent
conductive thermal impedances θJCBOTTOM, θJCTOP, θVIA,
θCB, and convective thermal impedances θBA and θCA. The
junction temperature, TJ, is calculated from the ambient
temperature, TA, as:
does not have good thermal vias, i.e., θVIA is relatively
high. Assuming, somewhat arbitrarily but not unreasonably, that θVIA ~ (θCB + θBA)/2, we back calculate
(θCB + θBA)/2 = θVIA ≈ 60°C/W for such a board. The
importance of thermal vias becomes clear once we
observe that if the test PCB had low-thermal-resistance
vias, the θJA would have been reduced by up to 10°C/W,
which is an improvement of up to 20%. Similarly, having
more ground planes that are larger, uninterrupted and
higher-copper-weight improves θCB + θBA, which has a
dominant effect on θJA, given the low value of θJCBOTTOM
of the package. See the Application Note, Application
Notes for Thermally Enhanced Leaded Plastic Packages,
for the proper size and layout of the thermal vias and solder stencils. The maximum load current should be derated
as the ambient temperature approaches the maximum
junction rating. Power dissipation within the LTC3307A
is estimated by calculating the total power loss from an
efficiency measurement and subtracting the inductor loss.
TA
DIE
TCTOP
TJ = TA + PD • θJA (11)
LQFN
θJCTOP
TA
θBA
θJCBOTTOM
θCB
θCB
PCB
⎛θCB + θBA⎞ ⎛θCB + θBA
⎞
θJA ≈ θJCBOTTOM + ⎜
+ θ VIA⎟ (12)
!⎜
⎟
⎝
⎠
2 ⎠ ⎝
2
PACKAGE
SUBSTRATE
TJ
θBA
where, neglecting the θJCTOP + θCA path:
where θJCBOTTOM = 8.6°C/W. The value of θJA =
51°C/W reported in the Pin Configuration section corresponds to JEDEC standard 2S2P test PCB, which
PD
TA
θCA
θVIA
θCB
θCB
PCB
3307A F04
θBA
TA
θBA
TA
Figure 4. Multi-Layer PCB with Thermal Vias Acts as a Heat Sink
Rev. C
For more information www.analog.com
19
LTC3307A
TYPICAL APPLICATIONS
VIN UVLO 3.0V, 1MHz, 1.8V, 3A, Pulse-Skipping Mode
VIN = 3.0V TO 5.5V
1µF
0201
4.7µF
1µF
0201
1.3M
EN
200k
15pF
VFB
LTC3307A
VIN
33µF
×2
10nF
AGND
RT
PGND
261k
100k
MODE/SYNC
71.5k
VOUT
1.8V
3A
SW
SW
VIN
VIN
4.7µF
1μH
1M
PGOOD
3307A TA02
VIN
fOSC = 1MHz
Small Solution Size, 3MHz, 1.2V, 3A, Forced Continuous Mode
VIN = 2.25V TO 5.5V
4.7µF
1µF
0201
1µF
0201
EN
10pF
LTC3307A
FLOAT
VFB
VIN
PGND
PGOOD
10µF
×2
10nF
AGND
RT
140k
100k
MODE/SYNC
22.6k
VOUT
1.2V
3A
SW
SW
VIN
VIN
4.7µF
330nH
1M
3307A TA03
VIN
fOSC = 3MHz
VIN UVLO 3.0V, 2.5V, 3A, Syncing to 1MHz, Forced Continuous Mode
VIN = 3.0V TO 5.5V
4.7µF
1µF
0201
1µF
0201
1.3M
EN
VIN
VIN
200k
SW
SW
6.8pF
LTC3307A
VFB
VIN
MODE/SYNC
fSYNC = 1MHz
VIN
RT
PGOOD
VOUT
2.5V
3A
402k
100k
22µF
×2
10nF
AGND
PGND
4.7µF
1.2μH
511k
VOUT
3307A TA04
Rev. C
20
For more information www.analog.com
LTC3307A
TYPICAL APPLICATIONS
High Efficiency, 2MHz, 3A, 5V to 3.3V, Burst Mode Operation
VIN = 4.5V TO 5.5V
4.7µF
1µF
0201
1µF
0201 680nH
EN
VIN
4.7µF
VOUT
3.3V
3A
SW
SW
VIN
6.8pF
FB
LTC3307A
MODE/SYNC
RT
VIN
562k
10µF
×2
100k
10nF
AGND
PGND
PGOOD
511k
3307A TA05
VOUT
fOSC = 2MHz
High Efficiency, 2MHz, 3A, 2.5V, Burst Mode Operation
VIN = 2.7V TO 5.5V
4.7µF
1µF
0201
1µF
0201
EN
4.7µF
VOUT
2.5V
3A
SW
SW
VIN
VIN
680nH
6.8pF
FB
LTC3307A
MODE/SYNC
RT
VIN
402k
100k
10µF
×2
10nF
AGND
PGND
PGOOD
511k
3307A TA06
VOUT
fOSC = 2MHz
High Efficiency, 2MHz, 3A, 1.8V, Burst Mode Operation
VIN = 2.25V TO 5.5V
4.7µF
1µF
0201 470nH
1µF
0201
EN
VIN
VIN
SW
SW
15pF
LTC3307A
MODE/SYNC
RT
4.7µF
FB
VIN
VOUT
1.8V
3A
261k
100k
15µF
×2
10nF
AGND
PGND
PGOOD
511k
VOUT
3307A TA07
fOSC = 2MHz
Rev. C
For more information www.analog.com
21
LTC3307A
TYPICAL APPLICATIONS
High Efficiency, 2MHz, 3A, 1.0V, Burst Mode Operation
VIN = 2.25V TO 5.5V
4.7µF
1µF
0201
1µF
0201
EN
VIN
VIN
SW
SW
10pF
LTC3307A
MODE/SYNC
RT
4.7µF
330nH
FB
VIN
200k
VOUT
1.0V
3A
15µF
×2
200k
10nF
AGND
PGOOD
PGND
511k
3307A TA08
VOUT
fOSC = 2MHz
High Efficiency, 2MHz, 3A, 0.75V, Burst Mode Operation
VIN = 2.25 TO 5.5V
4.7µF
1µF
0201 330nH
1µF
0201
EN
VIN
VIN
SW
SW
10pF
LTC3307A
MODE/SYNC
RT
4.7µF
FB
VIN
VOUT
0.75V
3A
100k
200k
22µF
×2
10nF
AGND
PGND
PGOOD
511k
VOUT
3307A TA09
fOSC = 2MHz
Rev. C
22
For more information www.analog.com
For more information www.analog.com
0.70 ±0.05
2.50 ±0.05
0.25 ±0.05
5
0.70
SUGGESTED PCB LAYOUT
TOP VIEW
2.50 ±0.05
0.70
0.0000
aaa Z
2×
D
PACKAGE TOP VIEW
0.2500
PIN 1
CORNER
0.2500
X
aaa Z
// bbb Z
0.7500
0.2500
0.0000
0.2500
0.7500
PACKAGE
OUTLINE
Y
E
2×
Z
H1
0.30
0.22
MIN
0.65
DETAIL C
SUBSTRATE
SYMBOL
A
A1
L
b
D
E
D1
E1
e
H1
H2
aaa
bbb
ccc
ddd
eee
fff
DETAIL B
H2
MOLD
CAP
ddd Z
Z
0.40
0.25
2.00
2.00
0.70
0.70
0.50
0.24 REF
0.50 REF
NOM
0.74
DIMENSIONS
12b
eee M Z X Y
fff M Z
DETAIL C
A1
12×
0.10
0.10
0.10
0.10
0.15
0.08
MAX
0.83
0.03
0.50
0.28
e/2
e
L
SUBSTRATE THK
MOLD CAP HT
NOTES
DETAIL A
DETAIL B
A
(Reference LTC DWG # 05-08-1530 Rev C)
e
7
6
D1
e
0.250
b
12
5
DETAIL A
PACKAGE BOTTOM VIEW
6
11
4
1
PIN 1 NOTCH
0.14 × 45°
4
SEE NOTES
DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER
MAY BE EITHER A MOLD OR MARKED FEATURE
THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII
5
6
LQFN 12 0721 REV C
METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN
SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES
4
3. PRIMARY DATUM -Z- IS SEATING PLANE
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
E1
b 10
ccc M Z X Y
ccc M Z X Y
LQFN Package
12-Lead (2mm × 2mm × 0.74mm)
LTC3307A
PACKAGE DESCRIPTION
Rev. C
23
LTC3307A
PACKAGE DESCRIPTION
WLCSP PACKAGE
CB-16-11
16-Pin (1.64mm × 1.64mm × 0.5mm)
1.680
1.640 SQ
1.600
4
3
2
1
A
BALL A1
IDENTIFIER
1.20
REF
B
C
0.40
REF
TOP VIEW
(BALL SIDE DOWN)
PKG-006559
SEATING
PLANE
END VIEW
BOTTOM VIEW
(BALL SIDE UP)
0.330
0.300
0.270
COPLANARITY
0.05
0.300
0.260
0.220
0.230
0.200
0.170
09-12-2019-B
0.560
0.500
0.440
D
Rev. C
24
For more information www.analog.com
LTC3307A
REVISION HISTORY
REV
DATE
DESCRIPTION
A
11/19
Added AEC-Q100 Qualified.
Added J-Grade and #W Parts.
Note 2: Added J-Grade.
Table 2: Added Thermal Properties Note.
Modified Figure 3 into 3a and 3b.
Capacitor App Circuit Changes.
B
01/21
Updated Features List.
Added “Battery Powered Systems” to Applications List.
Corrected Default Conditions for Electrical Characteristics Table.
Updated Load and Line Regulation Typical Curves.
Corrected PGOOD Upper Threshold Hysteresis Typical Value.
Changed Inductor Value Equation to Approximate Value.
Updated Recommended Inductor Table.
Added Description of Allowable Modifications to Epad Vias.
Added Mode of Operation Descriptors to All Typical Applications.
Expanded Allowed Input Voltages in Typical Applications.
Updated Related Parts Table.
C
11/22
Added WLCSP Package Option.
Updated Typical Switching Waveform In Pulse-Skipping Mode.
PAGE NUMBER
1
2
4
15
18
20-26
1
1
3
7
12
14
15
18
21, 22, 23, 26
22, 23
26
1-24
8
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
25
LTC3307A
TYPICAL APPLICATION
High Efficiency, 2MHz, 0.5V, 3A, Burst Mode Operation
VIN = 2.25V TO 5.5V
4.7µF
1µF
0201
EN
VIN
VIN
LTC3307A
1µF
0201
220nH
SW
SW
FB
MODE/SYNC
33µF
×2
VIN
4.7µF
1M
(OPT)
VOUT
0.5V
3A
10nF
RT
AGND
PGND
PGOOD
511k
VOUT
3307A TA08
fOSC = 2MHz
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC3307B
5V, 3A Synchronous Step-Down Silent
Switcher in 2mm × 2mm LQFN
Monolithic Synchronous Step-Down DC/DC Capable of Supplying 3A at Switching Frequencies
Up to 10MHz; Silent Switcher Architecture for Ultralow EMI Emissions; 2.25V to 5.5V Input
Operating Range; 0.5V to VIN Output Voltage Range with ±1% Accuracy; PGOOD Indication,
RT Programming, SYNC Input; 2mm × 2mm LQFN
LTC3308A/
LTC3308B
5V, 4A Synchronous Step-Down
Silent Switcher in 2mm × 2mm LQFN
Monolithic Synchronous Step-Down DC/DC Capable of Supplying 4A at Switching Frequencies
Up to 3MHz/10MHz; Silent Switcher Architecture for Ultralow EMI Emissions; 2.25V to
5.5V Input Operating Range; 0.5V to VIN Output Voltage Range with ±1% Accuracy; PGOOD
Indication, RT Programming, SYNC Input; 2mm × 2mm LQFN
LTC3309A/
LTC3309B
5V, 6A Synchronous Step-Down
Silent Switcher in 2mm × 2mm LQFN
Monolithic Synchronous Step-Down DC/DC Capable of Supplying 6A at Switching Frequencies
Up to 3MHz/10MHz; Silent Switcher Architecture for Ultralow EMI Emissions; 2.25V to
5.5V Input Operating Range; 0.5V to VIN Output Voltage Range with ±1% Accuracy; PGOOD
Indication, RT Programming, SYNC Input; 2mm × 2mm LQFN
LTC3315A/
LTC3315B
Dual 5V, 2A Synchronous Step-Down
DC/DCs in 2mm × 2mm LQFN
Dual Monolithic Synchronous Step-Down Voltage Regulators each Capable of Supplying 2A at
Switching Frequencies Up to 3MHz/10MHz; 2.25V to 5.5V Input Operating Range; 0.5V to VIN
Output Voltage Range with ±1% Accuracy; PGOOD Indication, SYNC Input; 2mm × 2mm LQFN
LTC3310/
LTC3310S
LTC3311/
LTC3311S
5V, 10A/12.5A Synchronous Step-Down Monolithic Synchronous Step-Down DC/DC Capable of Supplying 10A/12.5A at Switching
Silent Switcher/Silent Switcher 2 in
Frequencies Up to 5MHz; Silent Switcher Architecture for Ultralow EMI Emissions; 2.25V to
3mm × 3mm LQFN
5.5V Input Operating Range; 0.5V to VIN Output Voltage Range with ±1% Accuracy; PGOOD
Indication, RT Programming, SYNC Input; Configurable for Paralleling Power Stages; 3mm ×
3mm LQFN
LTC3370/
LTC3371
4-Channel 8A Configurable 1A Buck
DC/DCs
LTC3374A
8-Channel Parallelable 1A Buck DC/DCs Eight 1A Synchronous Buck Regulators; Can Connect Up to Four Power Stages in Parallel to
Make a High Current Output (4A Maximum) with a Single Inductor, 15 Output Configurations
Possible; Precision Enable inputs and PGOOD_ALL reporting; 38-Lead 5mm × 7mm QFN and
TSSOP
LTC3375
8-Channel Parallelable 1A Buck DC/DCs Eight 1A Synchronous Buck Regulators; Can Connect Up to Four Power Stages in Parallel to
Make a High Current Output (4A Maximum) with a Single Inductor, 15 Output Configurations
Possible; Precision Enable Inputs and PGOOD_ALL Reporting; I2C Programming with a
Watchdog Timer and Pushbutton; 48-Lead 7mm × 7mm QFN
LTC3616
5.5V, 6A, 4MHz, Synchronous
Step-Down DC/DC Converter
95% Efficiency, VIN: 2.25 to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD
