LTC3309B
5V, 6A Synchronous Step-Down
Silent Switcher in 2mm × 2mm LQFN
FEATURES
DESCRIPTION
Pin Compatible with LTC3307(3A) and LTC3308(4A)
n High Efficiency: 8mΩ NMOS, 31mΩ PMOS
n Programmable Frequency 3MHz-10MHz
n Tiny Inductor and Capacitors
n Peak Current Mode Control
n 22ns Minimum On-Time
n Wide Bandwidth, Fast Transient Response
n Silent Switcher™ Architecture
n Ultralow EMI Emissions
n Low Ripple Burst Mode® Operation with I of 40µA
Q
n Safely Tolerates Inductor Saturation in Overload
n V Range: 2.25V to 5.5V
IN
n V
OUT Range: 0.5V to VIN
n V
OUT Accuracy: ±1% Over Temperature Range
n Precision 400mV Enable Threshold, 1µA in Shutdown
n Power Good, Internal Compensation and Soft Start
n Thermally Enhanced 2mm × 2mm LQFN Package
n AEC-Q100 Qualified for Automotive Applications
The LTC®3309B is a very small, high efficiency, low noise,
monolithic synchronous 6A step-down DC/DC converter
operating from a 2.25V to 5.5V input supply. Using constant frequency, peak current mode control at switching
frequencies 3MHz-10MHz and minimum on-time as low
as 22ns, this regulator achieves fast transient response
with small external components. Silent Switcher architecture minimizes EMI emissions.
APPLICATIONS
All registered trademarks and trademarks are the property of their respective owners.
n
The LTC3309B operates in forced continuous or pulse
skip mode for low noise, or the low-ripple Burst Mode
operation for high efficiency at light loads, ideal for battery-powered systems. The IC regulates output voltages
as low as 500mV. Other features include output overvoltage protection, short-circuit protection, thermal shutdown, clock synchronization, and up to 100% duty cycle
operation for low dropout. The device is available in a low
profile 12-lead 2mm × 2mm × 0.74mm LQFN package
with exposed pad for low thermal resistance.
Optical Networking, Servers, Telecom
Automotive, Industrial, Communications
n Distributed DC Power Systems (POL)
n FPGA, ASIC, µP Core Supplies
n
n
TYPICAL APPLICATION
Efficiency and Power Loss
in Burst Mode Operation
Small Solution Size, 6.6MHz, 1.8V 6A Step-Down Converter
10
100
VIN = 2.5V TO 5.5V
90
1µF
0201
1µF
0201
VIN
VOUT
1.8V
6A
SW
SW
VIN
10pF
47.5k
FB
LTC3309B
VIN
18.2k
10µF
×2
10nF
MODE/SYNC
RT
PGOOD
0.1
60
50
40
POWER LOSS
0.01
30
VIN = 3.3V
VOUT = 1.8V
fSW = 6.6 MHz
20
AGND
PGND
70
10
3309B TA01a
fOSC = 6.6MHz
1
EFFICIENCY
0
0.001
POWER LOSS (W)
EN
80
4.7µF
110nH
EFFICIENCY (%)
4.7µF
0.001
MURATA DFE201210S–R11M
0.01
0.1
ILOAD (A)
1
6
0.0001
3309B TA01b
Rev. 0
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1
LTC3309B
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
EN
2
VIN
3
PGND
4
PGOOD
1
12
11
13
PGND
5
6
SW
AGND
FB
TOP VIEW
SW
VIN ............................................................... –0.3V to 6V
EN......................... –0.3V to Lesser of (VIN + 0.3V) or 6V
FB ......................... –0.3V to Lesser of (VIN + 0.3V) or 6V
MODE/SYNC......... –0.3V to Lesser of (VIN + 0.3V) or 6V
RT......................... –0.3V to Lesser of (VIN + 0.3V) or 6V
AGND to PGND........................................ –0.3V to +0.3V
PGOOD.......................................................... –0.3V to 6V
IPGOOD.......................................................................5mA
Operating Junction Temperature Range (Note 2):
LTC3309BE........................................ –40˚C to +125°C
LTC3309BI..........................................–40˚C to +125˚C
LTC3309BJ.........................................–40˚C to +150˚C
LTC3309BH........................................–40˚C to +150˚C
LTC3309BMP......................................–55˚C to +150˚C
Storage Temperature Range.................. –65˚C to +150°C
Maximum Reflow (Package Body) Temperature.... 260°C
10 RT
9
MODE/SYNC
8
VIN
7
PGND
LQFN PACKAGE
12-LEAD (2mm × 2mm × 0.74mm)
TJMAX = 150°C, θJA = 51°C/W, θJB = 12°C/W,
θJCBOTTOM = 8.6°C/W, θJCTOP = 73°C/W, ΨJT = 0.6°C/W
θ AND Ψ VALUES DETERMINED PER JESD51-7 ON A JEDEC 2S2P PCB,
EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
TAPE AND REEL
TAPE AND REEL MINI
PART MARKING*
PACKAGE TYPE
TEMPERATURE RANGE
LTC3309BEV#TRPBF
LTC3309BEV#TRMPBF
LHFQ
LTC3309BIV#TRPBF
LTC3309BIV#TRMPBF
LHFQ
LTC3309BJV#TRPBF
LTC3309BJV#TRMPBF
LHFQ
LTC3309BHV#TRPBF
LTC3309BHV#TRMPBF
LHFQ
LTC3309BMPV#TRPBF
LTC3309BMPV#TRMPBF
LHFQ
–55°C to 150°C
LTC3309BEV#WTRPBF
LTC3309BEV#WTRMPBF
LHFQ
–40°C to 125°C
LTC3309BIV#WTRPBF
LTC3309BIV#WTRMPBF
LHFQ
LTC3309BJV#WTRPBF
LTC3309BJV#WTRMPBF
LHFQ
LTC3309BHV#WTRPBF
LTC3309BHV#WTRMPBF
LHFQ
–40°C to 125°C
LQFN
(Laminate Package with QFN Footprint)
–40°C to 125°C
–40°C to 150°C
–40°C to 150°C
AUTOMOTIVE PRODUCTS**
LQFN
(Laminate Package with QFN Footprint)
–40°C to 125°C
–40°C to 150°C
–40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
2
Rev. 0
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LTC3309B
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range (Note 2), otherwise specifications are at TA = 25°C; VIN = 3.3V, VEN = VIN, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply
Operating Supply Voltage (VIN)
VIN Undervoltage Lockout
VIN Undervoltage Lockout Hysteresis
VIN Rising
VIN Quiescent Current in Shutdown
VEN = 0.1V
VIN Quiescent Current (Note 3)
Burst Mode Operation, Sleeping
All Modes, Not Sleeping
Enable Threshold
Enable Threshold Hysteresis
VEN Rising
EN Pin Leakage
VEN =0.5V
l
2.25
l
2.0
l
0.375
2.1
150
5.5
V
2.2
V
mV
1
2
µA
40
1.2
60
2
µA
mA
0.4
50
0.425
V
mV
±20
nA
0.5
0.505
V
0.015
0.05
%/V
±20
nA
42
ns
Voltage Regulation
Regulated Feedback Voltage (VFB)
l
Feedback Voltage Line Regulation
VIN = 2.25V to 5.5V
FB Pin Input Current
VFB = 0.5V
Minimum On Time (tON,min)
VIN = 5.5V
Maximum Duty Cycle
0.495
22
l
l
100
Top Switch ON-Resistance
31
Bottom Switch ON-Resistance
Top Switch Current Limit (IPEAKMAX)
%
mΩ
8
VOUT/VIN ≤ 0.2
9.1
9.6
Bottom Switch Reverse Current Limit (IREVMAX)
Forced Continuous Mode
–1.5
–3.0
SW Leakage Current
VEN = 0.1V
Bottom Switch Current Limit (IVALLEYMAX)
mΩ
10.1
7.8
A
A
–4.5
±100
A
nA
Power Good and Soft-Start
PGOOD Rising Threshold
PGOOD Hysteresis
As a Percentage of the Regulated VOUT
l
l
97
0.7
98
1.2
99
1.7
%
%
Overvoltage Rising Threshold
Overvoltage Hysteresis
As a Percentage of the Regulated VOUT
l
l
107
1
110
2.2
114
3.5
%
%
PGOOD Delay
PGOOD Pull Down Resistance
120
VPGOOD = 0.1V
PGOOD Leakage Current
VPGOOD = 5.5V
Soft-Start Duration
VOUT rising from 0V to PGOOD Threshold
10
µs
20
Ω
20
nA
l
0.25
1
3
ms
Default Oscillator Frequency
l
6.3
6.6
6.9
MHz
Oscillator Frequency with RT = 38.3kΩ
l
5.7
6.0
6.3
MHz
10
MHz
Oscillator and MODE/SYNC
Frequency Range
RT Programming and Synchronization
Minimum SYNC High or Low Pulse Width
SYNC Pulse Voltage Levels
Level High
Level Low
l
3
l
40
l
l
1.2
MODE/SYNC No Clock Detect Time
MODE/SYNC Pin Threshold
ns
0.4
10
For Programming Pulse Skip Mode
For Programming Forced Continuous Mode
For Programming Burst Mode Operation
l
l
l
1.0
VIN – 0.1
Float
V
V
µs
0.1
VIN – 1.0
V
V
V
Rev. 0
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3
LTC3309B
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3309B is tested under pulsed load conditions such
that TJ ≈ TA. The LTC3309BE is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization, and correlation with statistical process controls. The
LTC3309BI is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTC3309BJ and LTC3309BH are guaranteed
over the –40°C to 150°C operating junction temperature range. The
LTC3309BMP is guaranteed over the –55°C to 150°C operating junction
temperature range. High junction temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures above
125°C. Note that the maximum ambient temperature consistent with
4
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance,
and other environmental factors. The junction temperature (TJ in °C) is
calculated from ambient temperature (TA in °C) and power dissipation (PD
in Watts) according to the formula:
TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal
impedance. See High Temperature Considerations section for more
details.
The LTC3309B includes overtemperature protection that protects the
device during momentary overload conditions. Junction temperatures will
exceed 150°C when overtemperature protection is engaged. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 3: Supply current specification does not include switching currents.
Actual supply currents will be higher.
Rev. 0
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LTC3309B
TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Voltage
VIN = 3.3V, TA = 25°C, unless otherwise noted.
Minimum On-Time
505
Minimum On-Time
60
60
50
50
502
501
500
499
498
497
MINIMUM ON–TIME (ns)
503
MINIMUM ON–TIME (ns)
40
30
20
150°C
25°C
–50°C
10
496
495
–50 –25
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
2
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
3309B G01
40
PMOS
NMOS
RDS(ON) (mΩ)
RDS(ON) (mΩ)
28
24
20
16
12
VIN = 3.3V
7.3
25
PMOS
NMOS
20
0
Default Switching Frequency
6.3
6.1
5.9
Switching Frequency
7.0
6.8
9
FREQUENCY (MHz)
6.7
6.5
6.3
6.1
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
25 50 75 100 125 150
TEMPERATURE (°C)
3309B G07
2
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
7
6
5
5.5
RT Switching Frequency
RT = 38.3 kΩ
6.4
6.2
6.0
5.8
5.6
5.4
4
3
5
6.6
8
FREQUENCY (MHz)
7.1
0
6.5
3309B G06
10
7.3
5.5
–50 –25
6.7
3309B G05
7.5
5.7
6.9
5.5
25 50 75 100 125 150
TEMPERATURE (°C)
3309B G04
5.9
7.1
5.7
5
–50 –25
5.5
6.9
25 50 75 100 125 150
TEMPERATURE (°C)
3309B G03
10
8
5
0
Default Switching Frequency
15
3
3.5
4
4.5
INPUT VOLTAGE (V)
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
7.5
30
32
DEFAULT FREQUENCY (MHz)
0
–50 –25
5.5
35
36
2.5
20
Switch On Resistance
40
2
30
3309B G02
Switch On Resistance
44
4
5
40
10
DEFAULT FREQUENCY (MHz)
FEEDBACK VOLTAGE (mV)
504
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
5.2
20
30
40
50
60
RT (kΩ)
70
80
90
3309B G08
5.0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3309B G09
Rev. 0
For more information www.analog.com
5
LTC3309B
TYPICAL PERFORMANCE CHARACTERISTICS
PMOS Current Limit
Switch Current Limits
VOUT/VIN = 0.2
9.5
9.5
9.0
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.0
–50 –25
0
8.0
7.5
7.0
6.5
6.0
5.0
2
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
3309B G10
2.5
6.5
5
VIN = 5V
VIN = 2.5V
VIN = 3.3V
5.5
5.0
5.5
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3309B G12
VIN Quiescent Current All Modes,
Not Sleeping
70
1.30
1.25
1.0
VIN CURRENT (mA)
60
VIN CURRENT (µA)
VIN CURRENT (µA)
7.0
VIN Quiescent Current, Burst
Mode Operation, Sleeping
VIN Shutdown Current
1.5
55
50
45
1.20
1.15
1.10
40
0.5
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
35
0
–50 –25
0
30
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
25 50 75 100 125 150
TEMPERATURE (°C)
3309B G13
0
–50 –25
2.4
EN RISING
400
0
390
380
370
360
EN FALLING
350
PMOS
NMOS
25 50 75 100 125 150
TEMPERATURE (°C)
25 50 75 100 125 150
TEMPERATURE (°C)
340
–50 –25
0
RISING
FALLING
2.2
2.1
2.0
1.9
25 50 75 100 125 150
TEMPERATURE (°C)
3309B G16
VIN UVLO Threshold
2.3
VIN UVLO (V)
EN THRESHOLD (mV)
4
2
0
3309B G15
EN Threshold
VIN = 5.5V
1
1.00
–50 –25
410
3
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
1.05
3309B G14
Switch Leakage
SWITCH LEAKAGE CURRENT (µA)
7.5
6.0
65
6
8.0
3309B G11
2.0
5
8.5
150°C
25°C
–60°C
5.5
25 50 75 100 125 150
TEMPERATURE (°C)
9.5
9.0
8.5
PMOS IPEAKMAX
NMOS IVALLEYMAX
5.5
PMOS Current Limit
10.0
VOUT/VIN = 0.2
10.0
PMOS CURRENT (A)
SWITCH CURRENT (A)
10.0
10.5
PMOS CURRENT (A)
10.5
VIN = 3.3V, TA = 25°C, unless otherwise noted.
3309B G17
1.8
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3309B G18
Rev. 0
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LTC3309B
TYPICAL PERFORMANCE CHARACTERISTICS
112
1.810
110
1.808
VOUT Load Regulation in
VOUT = 1.8V Application
VIN = 2.5V
VIN = 3.3V
VIN = 5V
1.806
108
1.804
106
UV,
UV,
OV,
OV,
104
102
100
VOUT (V)
PERCENTAGE OF THE REGULATED VOUT (%)
UV, OV PGOOD Thresholds
VIN = 3.3V, TA = 25°C, unless otherwise noted.
VOUT RISING
VOUT FALLING
VOUT RISING
VOUT FALLING
1.802
1.800
1.798
1.796
1.794
98
1.792
96
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1.790
0
1
2
3309B G19
1.810
VOUT Line Regulation in
VOUT = 1.8V Application
1.806
100
95
90
EFFICIENCY (%)
VOUT (V)
1.804
1.802
1.800
1.798
1.796
6
3309B G20
75
70
65
1.792
55
1.790
50
0.001
3
3.5
4
4.5
INPUT VOLTAGE (V)
5
5.5
VIN = 2.5V
VIN = 3.3V
VIN = 5V
80
60
2.5
5
85
1.794
2
4
Efficiency in Burst Mode
Operation
ILOAD = 0A
ILOAD = 3A
ILOAD = 6A
1.808
3
ILOAD (A)
3309B G21
VOUT = 1.8V
fSW = 6.6 MHz
MURATA DFE201210S–R11M
0.01
0.1
ILOAD (A)
1
6
3309B G22
Rev. 0
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7
LTC3309B
PIN FUNCTIONS
AGND (Pin 1): The AGND pin is the output voltage remote
ground sense. Connect the AGND pin directly to the negative terminal of the output capacitor at the load. The AGND
pin is also the ground reference for the internal analog circuitry. Place a small analog bypass 0201 or 0402 ceramic
capacitor as close as possible to the VIN (Pin 3) and AGND
pins. Connect RT and FB returns to AGND as well.
EN (Pin 2): The EN pin has a precision IC enable threshold with hysteresis. An external resistor divider, from
VIN or from another supply, can be used to program the
threshold below which the LTC3309B will shut down. If
the precision threshold is not required, tie EN directly
to VIN. When the EN pin is low the LTC3309B enters a
low current shutdown mode where all internal circuitry
is disabled. Do not float this pin.
VIN (Pins 3, 8): The VIN pins supply current to internal
circuitry and topside power switch. Connect both VIN pins
together with short wide traces and bypass to PGND and
AGND with low ESR capacitors located as close as possible to the pins.
PGND (Pins 4, 7, Exposed Pad Pin 13): The PGND pins
are the return path of the internal bottom side power
switch. Connect the negative terminal of the input capacitors as close to the PGND pins as possible. For low parasitic inductance and good thermal performance, connect
Pin 4 and Pin 7 to a large continuous ground plane on
the printed circuit board directly under the LTC3309B.
The PGND exposed pad is the main electrical and thermal
highway and should be connected to large PCB ground
plane(s) with many vias.
8
SW (Pins 5, 6): The SW pins are the switching outputs of
the internal power switches. Connect these pins together
and to the inductor with a short, wide trace.
MODE/SYNC (Pin 9): The MODE/SYNC pin is a mode
selection and external clock synchronization input. Ground
this pin to enable Pulse Skip mode at light loads. For
higher efficiency at light loads, tie this pin to VIN to enable
the low-ripple Burst Mode operation. For faster transient
response, lower noise and full frequency operation over
a wide load range, float this pin to enable forced continuous mode. Drive MODE/SYNC with an external clock to
synchronize the switcher to the applied frequency. While
synchronizing, the part operates in the forced continuous
mode. The slope compensation is automatically adapted
to the external clock frequency. In the absence of an
external clock the switching frequency is determined by
the RT pin.
RT (Pin 10): The RT pin sets the switching frequency with
an external resistor to AGND. If this pin is tied to VIN, the
buck will switch at the default oscillator frequency. If the
external clock is driving the MODE/SYNC pin, the RT pin
is ignored.
PGOOD (Pin 11): The PGOOD pin is the open drain output
of an internal power good comparator. When the regulated
output voltage falls below the PGOOD threshold or rises
above the overvoltage threshold, this pin is pulled low.
When VIN is above VIN UVLO and the part is in shutdown,
this pin is also pulled low.
FB (Pin 12): Program the output voltage and close the
control loop by connecting this pin to the middle node
of a resistor divider between the VOUT and AGND. The
LTC3309B regulates FB to 500mV (typical). A phase lead
capacitor connected between FB and VOUT may be used
to optimize transient response.
Rev. 0
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LTC3309B
BLOCK DIAGRAM
VIN
R1
R2
(OPT)
2
EN
0.4V
+
–
MODE
DETECT
9
10
0.55V
0.5V
0.49V
INTERNAL
REFERENCE
BURST
FORCED CONTINUOUS
PULSE SKIP
MODE/SYNC
RT
VIN
SWITCH LOGIC
AND
ANTI-SHOOT
THROUGH
S Q
OSCILLATOR
RT
R
+
–
L
SW
5, 6
VOUT
COUT
4, 7, AND
13 (EXPOSED PAD)
BURST
DETECT
FB
GM
VC
CPAR
CIN
PGND
SLOPE
COMP
1 AGND
VIN
3, 8
0.5V 0.49V
RC
CC
0.55V
+
–
+
–
PGOOD
RA
CFF
12
11
RB
FAULT
ISS
SS
FAULT
CSS
3309B BD
Rev. 0
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9
LTC3309B
OPERATION
Voltage Regulation
Mode Selection
The LTC3309B is a 5V, 6A monolithic, constant frequency,
peak current mode control, step-down DC/DC converter.
The synchronous buck switching regulators are internally
compensated and require only external feedback resistors
to set the output voltage. An internal oscillator, with the
frequency set using a resistor on the RT pin or synchronized to an external clock, turns on the internal top power
switch at the beginning of each clock cycle. Current in the
inductor ramps up until the top switch current comparator
trips and turns off the top power switch. The peak inductor current at which the top switch turns off is controlled
by an internal VC voltage. The error amplifier regulates VC
by comparing the voltage on the FB pin with an internal
500mV reference. An increase in the load current causes a
reduction in the feedback voltage relative to the reference,
causing the error amplifier to raise the VC voltage until the
average inductor current matches the new load current.
When the top power switch turns off, the synchronous
power switch turns on and ramps down the inductor current for the remainder of the clock cycle or, if in pulse skip
or Burst mode, until the inductor current falls to zero. If
an overload condition results in excessive current flowing
through the bottom switch, the next clock cycle will be
skipped until switch current returns to a safe level.
The LTC3309B operates in three different modes set by
the MODE/SYNC pin: pulse skip mode (when the MODE/
SYNC pin is set low), forced continuous mode (when the
MODE/SYNC pin is floating) and Burst Mode operation
(when the MODE/SYNC pin is set high).
The enable pin has a precision 400mV threshold to provide event-based power-up sequencing by connecting the
EN pin to the output of another buck through a resistor
divider. If the EN pin is low, the device is shut down and
in a low quiescent current state. When the EN pin is above
its threshold, the switching regulator will be enabled.
The LTC3309B has forward and reverse inductor current
limiting, short-circuit protection, output over-voltage protection, and soft-start to limit inrush current during startup or recovery from a short-circuit.
10
In pulse skip mode, the oscillator operates continuously
and positive SW transitions are aligned to the clock.
Negative inductor current is disallowed and, during light
loads, switch pulses are skipped to regulate the output
voltage.
In forced continuous mode, the oscillator operates continuously. The top switch turns on every cycle and regulation is maintained by allowing the inductor current to
reverse at light load. This mode allows the buck to run
at a fixed frequency with minimal output ripple. In forced
continuous mode, if the inductor current reaches IREVMAX
(into the SW pin), the bottom switch will turn off for the
remainder of the cycle to limit the current.
In Burst Mode operation at light loads, the output capacitor is charged to a voltage slightly higher than its regulation point. The regulator then goes into a sleep state,
during which time the output capacitor provides the
load current. In sleep, most of the regulator’s circuitry is
powered down, helping conserve input power. When the
output voltage drops below its programmed value, the
circuitry is powered on and another burst cycle begins.
The sleep time decreases as load current increases. In
Burst Mode operation, the regulator will burst at light
loads whereas at higher loads it will operate in constant
frequency PWM mode.
Rev. 0
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LTC3309B
OPERATION
Synchronizing the Oscillator to an External Clock
Output Overvoltage Protection
The LTC3309B’s internal oscillator can be synchronized
through an internal PLL circuit to an external frequency
by applying a square wave clock signal to the MODE/
SYNC pin.
During an output overvoltage event, when the FB pin voltage is greater than 110% of nominal, the LTC3309B top
power switch will be turned off. If the output remains out
of regulation for more than 120µs, the PGOOD pin will
be pulled low.
During synchronization, the top power switch turn-on is
locked to the rising edge of the external frequency source.
While synchronizing, the switcher operates in forced continuous mode. The slope compensation is automatically
adapted to the external clock frequency. The synchronization frequency range is 3MHz to 10MHz.
After detecting an external clock on the first rising edge
of the MODE/SYNC pin, the internal PLL gradually adjusts
its operating frequency to match the frequency and phase
of the signal on the MODE/SYNC pin. When the external
clock is removed, the LTC3309B will detect the absence
of the external clock within approximately 10μs. During
this time, the PLL will continue to provide clock cycles.
Once the external clock removal has been detected, the
oscillator will gradually adjust its operating frequency to
the one programmed by the RT pin.
Output Power Good
When the LTC3309B’s output voltage is within the
–2%/+10% window of the nominal regulation voltage the
output is considered good and the open-drain PGOOD pin
goes high impedance and is typically pulled high with an
external resistor. Otherwise, the internal pull-down device
will pull the PGOOD pin low. The PGOOD pin is also pulled
low during the following fault conditions: EN pin is low,
VIN is too low or thermal shutdown. To filter noise and
short duration output voltage transients, the lower threshold has a hysteresis of 1.2%, the upper threshold has a
hysteresis of 2.2%, and both have a built-in time delay to
report PGOOD, typically 120µs.
An output overvoltage event should not happen under
normal operating conditions.
Overtemperature Protection
To prevent thermal damage to the LTC3309B and its surrounding components, the device incorporates an overtemperature (OT) function. When the die temperature
reaches 165°C (typical, not tested) the switcher is shut
down and remains in shutdown until the die temperature
falls to 160°C (typical, not tested).
Output Voltage Soft-Start
Soft starting the output prevents current surge on the
input supply and/or output voltage overshoot. During the
soft-start, the output voltage will proportionally track the
internal node voltage ramp. An active pull-down circuit
discharges that internal node in the case of fault conditions. The ramp will restart when the fault is cleared. Fault
conditions that initiate the soft-start ramp are the EN pin
transitioning low, VIN voltage falling too low, or thermal
shutdown.
Dropout Operation
As the input supply voltage approaches the output voltage, the duty cycle increases toward 100%. Further reduction of the supply voltage forces the main switch to remain
on for more than one cycle, eventually reaching 100%
duty cycle. The output voltage will then be determined by
the input voltage minus the DC voltage drop across the
internal P-channel MOSFET and the inductor.
Rev. 0
For more information www.analog.com
11
LTC3309B
OPERATION
Low Supply Operation
The LTC3309B is designed to operate down to an input
supply voltage of 2.25V. One important consideration at
low input supply voltages is that the RDS(ON) of the internal power switches increases. Calculate the worst case
LTC3309B power dissipation and die junction temperature
at the lowest input voltages.
Output Short-Circuit Protection and Recovery
The peak inductor current level, at which the current comparator shuts off the top power switch, is controlled by the
internal VC voltage. When the output current increases,
the error amplifier raises VC until the average inductor
current matches the load current. The LTC3309B clamps
the maximum VC voltage, thereby limiting the peak inductor current.
When the output is shorted to ground, the inductor current decays very slowly when the bottom power switch
is on because the voltage across the inductor is low. To
keep the inductor current in control, a secondary limit is
imposed on the valley of the inductor current. If the inductor current measured through the bottom power switch
remains greater than IVALLEYMAX at the end of the cycle,
the top power switch will be held off. Subsequent switching cycles will be skipped until the inductor current falls
below IVALLEYMAX.
Recovery from an output short circuit may involve a softstart cycle if VFB falls more than approximately 100mV
below regulation. During such a recovery, VFB will quickly
charge up by that ~100mV and then follow the soft-start
ramp until regulation is reached.
APPLICATIONS INFORMATION
Refer to the Block Diagram for reference.
Output Voltage and Feedback Network
The output voltage is programmed by a resistor divider
between the output and the FB pin. Choose the resistor
values according to:
⎛ V
⎞
RA = RB ⎜ OUT – 1⎟ (1)
⎝ 500mV ⎠
as shown in Figure 1:
Operating Frequency Selection and Trade-Offs
VOUT
BUCK
SWITCHING FB
REGULATOR
RA
RB
CFF
+
(OPTIONAL)
3309B F01
Figure 1. Feedback Resistor Network
12
Reference designators refer to the Block Diagram. Typical
values for RB range from 10kΩ to 100kΩ. 0.1% resistors
are recommended to maintain output voltage accuracy.
The buck regulator transient response may improve with
an optional phase lead capacitor CFF that helps cancel
the pole created by the feedback resistors and the input
capacitance of the FB pin. Experimentation with capacitor values between 2pF and 22pF may improve transient
response. The values used in the typical application circuits are a good starting point.
COUT
Selection of the operating frequency is a trade-off between
efficiency, component size, transient response and input
voltage range.
The advantage of high frequency operation is that smaller
inductor and capacitor values may be used. Higher
switching frequencies allow for higher control loop
bandwidth and, therefore, faster transient response. The
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LTC3309B
APPLICATIONS INFORMATION
disadvantages of higher switching frequencies are lower
efficiency, because of increased switching losses, and a
smaller input voltage range, because of minimum switch
on-time limitations.
The minimum on-time of the buck regulator imposes a
minimum operating duty cycle. The highest switching
frequency (fSW(MAX)) for a given application can be calculated as follows:
VOUT
(2)
fSW(MAX ) =
tON(MIN) • VIN(MAX )
where VIN(MAX) is the maximum input voltage, VOUT
is the output voltage and tON(MIN) is the minimum top
switch on-time. This equation shows that a slower
switching frequency is necessary to accommodate a high
VIN(MAX)/VOUT ratio.
The LTC3309B is capable of a maximum duty cycle of
100%, therefore, the VIN-to-VOUT dropout is limited by
the RDS(ON) of the top switch, the inductor DCR and the
load current.
Setting the Switching Frequency
The LTC3309B uses a constant frequency peak current
mode control architecture. There are three methods to
set the switching frequency.
The first method, connecting the RT pin to VIN, sets the
switching frequency to the internal default with a nominal
value of 6.6MHz.
The second method is with a resistor (RT) tied from the
RT pin to ground. The frequency can be programmed
from 3MHz to 10MHz. Table 1 and the Equation 3 show
the necessary RT value for a desired switching frequency:
RT =
263
– 5.4 (3)
fsw
where RT is in kΩ and fSW is the desired switching frequency in MHz, ranging from 3MHz to 10MHz.
Table 1. RT Value vs Switching Frequency
fSW (MHz)
RT (kΩ)
3.0
82.5
4.0
60.4
5.0
47.5
6.0
38.3
7.0
32.4
8.0
27.4
9.0
23.7
10.0
21.0
The third method to set the switching frequency is by synchronizing the internal PLL circuit to an external square
wave clock applied to the MODE/SYNC pin. The synchronization frequency range is 3MHz to 10MHz. The square
wave amplitude should have valleys that are below 0.4V
and peaks above 1.2V. High and low pulse widths should
both be at least 40ns.
Inductor Selection and Maximum Output Current
Considerations in choosing an inductor are inductance,
RMS current rating, saturation current rating, DCR and
core loss.
Select the inductor value based on the following equation:
L≈
L≈
⎛
⎞
VOUT
V
VOUT
• ⎜ 1− OUT ⎟ for
≤ 0.5 (4)
1.8A • fSW ⎝ VIN(MAX ) ⎠
VIN(MAX )
0.25 • VIN(MAX )
1.8A • fSW
for
VOUT
VIN(MAX )
> 0.5 (5)
where fSW is the switching frequency, VIN(MAX) is the
maximum input voltage.
To avoid overheating of the inductor choose an inductor with an RMS current rating that is greater than the
maximum expected output load of the application.
Overload and short-circuit conditions need to be taken
into consideration.
Rev. 0
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13
LTC3309B
APPLICATIONS INFORMATION
In addition, ensure that the saturation current rating
(typically labeled ISAT) of the inductor is higher than the
maximum expected load current plus half the inductor
ripple current:
ISAT
1
> ILOAD(MAX ) + ∆IL (6)
2
where ILOAD(MAX) is the maximum output load current for
a given application and ΔIL is the inductor ripple current
calculated as:
∆IL =
A more conservative choice would be to use an inductor
with an ISAT rating higher than the maximum current limit
of the LTC3309B.
To keep the efficiency high, choose an inductor with
the lowest series resistance (DCR). The core material
should be intended for high frequency applications.
Table 2 shows recommended inductors from several
manufacturers.
VOUT ⎛ VOUT ⎞
(7)
• 1–
L • fSW ⎜⎝
VIN ⎟⎠
Table 2. Recommended Inductors with Typical Specifications
Inductance (nH)
ITEMP (A)*
ISAT (A)
DCR (mΩ)
W×L×H (mm)
Manufacturer
Manufacturer's Part Number
240
6
9.5
18
2.5×2.0×1.0
NIC
NPIM20LP
240
6.5
7.5
15
2.0×1.6×1.0
NIC
NPIM26LP
240
6.3
7.2
16
2.2×1.8×1.0
Sumida
201610CDMCDDS-R24MC
220
5.9
7.0
9.4
2.5×2.0×1.0
Cyntec
HMLB25201T-R22MSR-01
220
7.4
7.1
8.4
2.5×2.0×1.2
Vishay
IHHP1008ABERR22M01
220
8
7
13 (Max)
2.5×2.0×1.2
XFRMS
XFHCL43LT-R22M
150
5.2
6.2
18 (Max)
2.0×1.6×1.2
Murata
DFE201612PD-R15M
110
6.8
8.8
10
2.0×1.2×0.8
TDK
TFM201208BLD-R11MTCA
110
5.5
8.8
8
2.0×1.2×1.0
Murata
DFE201210S-R11M
100
7.7
12.8
9
2.5×2.0×1.2
Cyntec
VCTA25201B-R10MSG-87
100
11.5
12.9
7.35
3.3×3.3×1.0
Vishay
IHLP1212AZEER10M5A
100
6
11
6
2.5×2.0×2.0
XFRMS
XF2520A-R10M
50
7
11
9
2.0×1.6×0.8
Wurth Electronik
74479978105
40
6
8
13
2.0×1.6×0.6
Wurth Electronik
74479977104
*Strongly depends on the PCB thermal properties
14
Rev. 0
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LTC3309B
APPLICATIONS INFORMATION
Input Capacitors
Bypass the input of the LTC3309B with at least two
ceramic capacitors close to the part, one on each side
from VIN to PGND, for best performance. These capacitors should be 0603 or 0402 in size. Smaller, optional
0201 capacitors can also be placed as close as possible
to the LTC3309B directly on the traces leading from VIN
(Pin 3) and PGND (Pin 4) and on the traces leading from
VIN (Pin 8) and PGND (Pin 7) for better performance with
minimal (if at all) increase in application footprint. See the
layout section for more detail. X7R or X5R capacitors are
recommended for best performance across temperature
and input voltage variations (see Table 3). Note that larger
input capacitance is required when a lower switching frequency is used. If the input power source has high impedance, or there is significant inductance due to long wires
or cables, additional bulk capacitance may be necessary.
This can be provided with an electrolytic capacitor.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (under damped) tank
circuit. If the LTC3309B circuit is plugged into a live supply, the input voltage can ring to twice its nominal value,
possibly exceeding the LTC3309B’s voltage rating. This
situation is easily avoided (see Application Note AN88).
Table 3. Ceramic Capacitor Manufacturers
VENDOR
URL
AVX
www.avxcorp.com
Murata
www.murata.com
TDK
www.tdk.com
Taiyo Yuden
www.t-yuden.com
Samsung
www.samsungsem.com
Wurth Elektronik
www.we-online.com
Output Capacitor, Output Ripple and Transient
Response
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LTC3309B at the SW pin to produce the DC output.
In this role, it determines the output ripple; thus, low
impedance at the switching frequency is important. The
second function is to store energy in order to satisfy transient loads and stabilize the LTC3309B’s control loop.
The LTC3309B is internally compensated and has been
designed to operate at a high bandwidth for fast transient response capability. The selection of COUT affects
the bandwidth of the system, but the transient response
is also affected by VOUT, VIN, fSW and other factors. A
good place to start is with the output capacitance value
of approximately:
COUT = 20 •
IMAX
fSW
0.5
VOUT
(8)
where COUT is the recommended output capacitor value
in µF, fSW is the switching frequency in MHz, IMAX = 6A
is the rated output current in Amps, and VOUT is in Volts.
A lower value output capacitor saves space and cost but
transient performance will suffer and loop stability must
be verified.
Ceramic capacitors have very low equivalent series
resistance (ESR) and provide the best output ripple and
transient performance. Use X5R or X7R ceramic capacitors (see Table 3). Even better output ripple and transient
performance can be achieved by using low-ESL reverse
geometry or three-terminal ceramic capacitors.
During a load step, the output capacitor must instantaneously supply the current to support the load until the
feedback loop increases the switch current enough to
support the load. The time required for the feedback loop
to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4 cycles
are required to respond to a load step, but only in the first
cycle does the output drop linearly. Although affected by
VOUT, VIN, fSW, tON(MIN), the equivalent series inductance
(ESL) of the output capacitor, and other factors, the output
droop, VDROOP, is usually about 4 times the linear drop
of the first cycle:
VDROOP =
4 • ∆IOUT
(9)
COUT • fSW
where ∆IOUT is the load step.
Rev. 0
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15
LTC3309B
APPLICATIONS INFORMATION
Transient performance and control loop stability can be
improved with a higher COUT and/or the addition of a
feedforward capacitor CFF placed between VOUT and FB.
Capacitor CFF provides phase lead compensation by creating a high frequency zero which improves the phase
margin and the high-frequency response. The values used
in the typical application circuits are a good starting point.
LTpowerCAD® is a useful tool to help optimize CFF and
COUT for a desired transient performance.
Applying a load transient and monitoring the response of
the system or using a network analyzer to measure the
actual loop response are two ways to experimentally verify
transient performance and control loop stability, and to
optimize CFF and COUT.
When using the load transient response method to stabilize the control loop apply an output current pulse of
20% to 100% of full load current having a very fast rise
time. This will produce a transient on the output voltage.
Monitor VOUT for overshoot or ringing that might indicate
a stability problem (see Application Note AN149).
The rising threshold of the EN comparator is 400mV,
with 50mV of hysteresis. The EN pin can be tied to VIN
if the shutdown feature is not used. Adding a resistor
divider from VIN to EN programs the LTC3309B to regulate the output only when VIN is above a desired voltage
(see Figure 2). Typically, this threshold, VIN(EN), is used
in situations where the input supply is current limited, or
has a relatively high source resistance. A switching regulator draws near constant power from its input source,
so source current increases as source voltage drops. This
looks like a negative resistance load to the source and can
cause the source to current limit or latch low under low
source voltage conditions. The VIN(EN) threshold prevents
the regulator from operating at source voltages where
problems may occur. This threshold can be adjusted by
setting the values R1 and R2 such that they satisfy the
following equation:
⎛ R1 ⎞
VIN(EN) = ⎜ + 1⎟ • 400mV (10)
⎝ R2 ⎠
as shown in Figure 2:
Output Voltage Sensing
The LTC3309B’s AGND pin is the ground reference for the
internal analog circuitry, including the bandgap voltage
reference. To achieve good load regulation connect the
AGND pin to the negative terminal of the output capacitor
(COUT) at the load. Any drop in the high current power
ground return path will be compensated. The AGND
node carries very little current and, therefore, can be a
minimal size trace. Place a small analog bypass 0201
or 0402 ceramic capacitor as close as possible to the
LTC3309B directly on the traces leading from VIN (Pin 3)
and AGND pin. All of the signal components, such as the
FB resistor dividers and the RT resistor, should be referenced to the AGND node. See the example PCB Layout
for more information.
Enable Threshold Programming
The LTC3309B has a precision threshold enable pin to
enable or disable the switching. When forced low, the
device enters a low current shutdown mode.
16
VIN
BUCK
SWITCHING EN
REGULATOR
R1
R2
3309B F02
Figure 2. EN Divider
The LTC3309B will remain off until VIN is above VIN(EN).
The buck regulator will remain enabled until VIN falls to
0.875 • VIN(EN) and EN is 350mV typical.
Alternatively, a resistor divider from an output of an
upstream regulator to the EN pin of the LTC3309B provides event-based power-up sequencing, enabling the
LTC3309B when the output of the upstream regulator
reaches a predetermined level (e.g. 90% of the regulated output). Replace VIN(EN) in Equation 10 with that
predetermined level.
Rev. 0
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LTC3309B
APPLICATIONS INFORMATION
Low EMI PCB Layout
The LTC3309B is specifically designed to minimize
EMI/EMC emissions and also to maximize efficiency
and improve transient response when switching at
high frequencies.
See Figure 3 for a recommended PCB layout.
For optimal performance the LTC3309B requires that
both input supply VIN pins (Pins 3, 8) each have a local
decoupling capacitor with their ground terminals soldered
directly to the ground plane on the top layer near PGND
pins (Pins 4, 7). These capacitors provide the AC current
to the internal power MOSFETs and their drivers. Large,
switched currents flow in the VIN and PGND pins and the
input capacitors. The loops formed by the input capacitors
should be as small as possible by placing the capacitors
adjacent to the VIN and PGND pins. Capacitors with small
case size such as 0603 or 0402 are optimal due to lowest
parasitic inductance. Even smaller 0201 capacitors can
additionally be placed right next to the respective VIN and
PGND pins for better performance with minimal (if at all)
increase in application footprint. In addition, place a local,
VIN
PGND
GROUND PLANE ON LAYER 2
COUT1
CIN1
unbroken ground plane under the application circuit on
the layer closest to the surface layer.
Decoupling AGND is also very important. Place a small
analog bypass, 0201 or 0402 capacitor as close as possible to the LTC3309B directly on the traces leading from
VIN (Pin 3) and AGND (Pin 1).
Place the inductor on the same side of the circuit board.
The trace connecting SW pins (Pins 5, 6) to the inductor
should be as short as possible to reduce radiated EMI and
parasitic coupling.
Keep the FB and RT nodes small and far away or shielded
from the noisy SW node.
In the recommended layout, five 5mil vias are used to
provide the best conductivity to the GND plane within
the EPAD. For layouts where 5mil vias are not allowed, it
is recommended to use either four 8mil vias or a single
(filled or tented) 12mil diameter via. Refer to the Thermal
Via Design section of the Analog Devices Application
Note, Application Notes for Thermally Enhanced Leaded
Plastic Packages for more information on thermal via
recommendations.
VOUT
VIN
RT
7
CIN3
10
L
13
CFF
1
RA
4
CBYP
COUT3
CIN3
1
CIN2
COUT1
L
VOUT
4
CIN4
RB
COUT2
AGND
VIN
7
13
CFF
CIN4
RB
CIN1
RT
10
RA
PGND
GROUND PLANE ON LAYER 2
CBYP
COUT4
COUT2
CIN2
AGND
PGND
VOUT
VIN
3309B F03a
(3a) Recommended PCB Layout for the LTC3309B
Small Solution Size. Five 5mil Vias Are Used within the
EPAD. For Layouts where 5mil Vias Are Not Allowed,
It Is Recommended to Use Either Four 8mil Vias or a
Single (Filled or Tented) 12mil Diameter Via
PGND
3309B F03b
(3b) Recommended PCB Layout for the LTC3309B with
Capacitors COUT1 and COUT2 Rotated by 90°, which Reduces
High-Frequency Output Ripple. Optional 0201 Capacitors COUT3
and COUT4 Further Improve The High-Frequency Output Ripple.
Five 5mil Vias Are Used within the EPAD. For Layouts where
5mil Vias Are Not Allowed, It Is Recommended to Use Either
Four 8mil Vias or a Single (Filled or Tented) 12mil Diameter Via
Figure 3.
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17
LTC3309B
APPLICATIONS INFORMATION
High Temperature Considerations
Care should be taken in the layout of the PCB to ensure
good heat sinking of the LTC3309B. Connect the exposed
pad on the bottom of the package (Pin 13) to a large,
unbroken ground plane under the application circuit on
the layer closest to the surface layer. Place many vias to
minimize thermal and electrical impedance. Solder the
PGND pins (Pins 4, 7) directly to a ground plane on the
top layer. Connect the top layer ground plane to ground
plane(s) on lower levels with many thermal vias. These
layers will spread heat dissipated by the LTC3309B.
Figure 4 is a simplified thermal representation of a thermally enhanced LQFN package with exposed pad, with
the silicon die and thermal metrics identified. The current
source represents power loss PD on the die; node voltages
represent temperatures; electrical impedances represent
conductive thermal impedances θJCBOTTOM, θJCTOP, θVIA,
θCB, and convective thermal impedances θBA and θCA. The
junction temperature, TJ, is calculated from the ambient
temperature, TA, as:
high. Assuming, somewhat arbitrarily but not unreasonably, that θVIA ~ (θCB + θBA)/2, we back calculate
(θCB + θBA)/2 = θVIA ≈ 60°C/W for such a board. The
importance of thermal vias becomes clear once we
observe that if the test PCB had low-thermal-resistance
vias, the θJA would have been reduced by up to 10°C/W,
which is an improvement of up to 20%. Similarly, having
more ground planes that are larger, uninterrupted and
higher-copper-weight improves θCB + θBA, which has a
dominant effect on θJA, given the low value of θJCBOTTOM
of the package. See the Application Note, Application
Notes for Thermally Enhanced Leaded Plastic Packages,
for the proper size and layout of the thermal vias and solder stencils. The maximum load current should be derated
as the ambient temperature approaches the maximum
junction rating. Power dissipation within the LTC3309B
is estimated by calculating the total power loss from an
efficiency measurement and subtracting the inductor loss.
TA
DIE
TJ = TA + PD • θJA (11)
PD
TA
where, neglecting the θJCTOP + θCA path:
⎛θCB + θBA⎞ ⎛θCB + θBA
⎞
θJA ≈ θJCBOTTOM + ⎜
+ θ VIA⎟ (12)
!⎜
⎟
⎝
⎠
2 ⎠ ⎝
2
θCA
PACKAGE
SUBSTRATE
LQFN
θJCTOP
TJ
θBA
TA
θBA
θJCBOTTOM
θCB
θCB
PCB
where θJCBOTTOM = 8.6°C/W. The value of θJA =
51°C/W reported in the Pin Configuration section corresponds to JEDEC standard 2S2P test PCB, which
does not have good thermal vias, i.e., θVIA is relatively
TCTOP
θVIA
θCB
θCB
PCB
3309B F04
θBA
TA
θBA
TA
Figure 4. Multi-Layer PCB with Thermal Vias Acts as a Heat Sink
18
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LTC3309B
TYPICAL APPLICATIONS
VIN UVLO 3.0V, 3MHz, 0.75V, 6A, Pulse Skip Mode
VIN = 3.0V TO 5.5V
1µF
0201
4.7µF
1µF
0201
1.3M
EN
200k
15pF
VFB
LTC3309B
VIN
22µF
×2
10nF
AGND
RT
PGND
24.3k
48.7k
MODE/SYNC
82.5k
VOUT
0.75V
6A
SW
SW
VIN
VIN
4.7µF
110nH
1M
PGOOD
3309B TA02
VIN
fOSC = 3MHz
Small Solution Size, 1.0V, 6A, Syncing to 3MHz , Forced Continuous Mode
VIN = 2.5V TO 5.5V
4.7µF
1µF
0201
1µF
0201
EN
15pF
LTC3309B
VFB
VIN
RT
PGND
PGOOD
22µF
×2
10nF
AGND
VIN
28k
28k
MODE/SYNC
fSYNC = 3MHz
VOUT
1.0V
6A
SW
SW
VIN
VIN
4.7µF
150nH
1M
3309B TA03
VIN
Ultra-Low Profile, VIN UVLO 3.0V, 10MHz, 2.5V, 6A, Forced Continuous Mode
VIN = 3.0V TO 5.5V
4.7µF
1µF
0201
1µF
0201
1.3M
EN
VIN
VIN
200k
SW
SW
6.8pF
LTC3309B
FLOAT
VFB
VIN
MODE/SYNC
PGND
PGOOD
VOUT
2.5V
6A
40.2k
10k
4.7µF
×2
10nF
AGND
RT
21k
4.7µF
50nH
200k
VOUT
3309B TA04
fOSC = 10MHz
Rev. 0
For more information www.analog.com
19
LTC3309B
TYPICAL APPLICATIONS
Small Solution Size, 6.6MHz, 6A, 5V to 3.3V, Burst Mode Operation
VIN = 4.5V TO 5.5V
4.7µF
1µF
0201
1µF
0201 110nH
EN
VIN
4.7µF
VOUT
3.3V
6A
SW
SW
VIN
6.8pF
FB
LTC3309B
MODE/SYNC
RT
VIN
56.2k
4.7µF
×2
10k
10nF
AGND
PGND
PGOOD
300k
3309B TA08
VOUT
fOSC = 6.6MHz
Small Solution Size, 6.6MHz, 2.5V, 6A, Burst Mode Operation
VIN = 3V TO 5.5V
4.7µF
1µF
0201
1µF
0201 110nH
EN
VIN
4.7µF
SW
SW
VIN
6.8pF
FB
LTC3309B
MODE/SYNC
RT
VIN
VOUT
2.5V
6A
48.7k
4.7µF
×2
12.1k
10nF
AGND
PGND
PGOOD
200k
3309B TA05
VOUT
fOSC = 6.6MHz
Small Solution Size, 6.6MHz, 1.2V, 6A, Burst Mode Operation
VIN = 2.5V TO 4.5V
4.7µF
1µF
0201
1µF
0201
EN
VIN
VIN
SW
SW
15pF
LTC3309B
MODE/SYNC
RT
4.7µF
70nH
FB
VIN
VOUT
1.2V
6A
21k
15k
10µF
×2
10nF
AGND
PGND
PGOOD
200k
3309B TA06
VOUT
fOSC = 6.6MHz
20
Rev. 0
For more information www.analog.com
0.70 ±0.05
2.50 ±0.05
PACKAGE TOP VIEW
0.70
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
SUGGESTED PCB LAYOUT
TOP VIEW
2.50 ±0.05
0.70
X
aaa Z
// bbb Z
0.7500
0.2500
0.0000
0.2500
0.7500
PACKAGE
OUTLINE
Y
E
2×
Z
H1
MIN
0.65
0.01
0.30
0.22
DETAIL C
SUBSTRATE
SYMBOL
A
A1
L
b
D
E
D1
E1
e
H1
H2
aaa
bbb
ccc
ddd
eee
fff
DETAIL B
H2
MOLD
CAP
ddd Z
Z
NOM
0.74
0.02
0.40
0.25
2.00
2.00
0.70
0.70
0.50
0.24 REF
0.50 REF
DIMENSIONS
12b
eee M Z X Y
fff M Z
DETAIL C
A1
0.10
0.10
0.10
0.10
0.15
0.08
MAX
0.83
0.03
0.50
0.28
e/2
e
L
SUBSTRATE THK
MOLD CAP HT
NOTES
DETAIL A
DETAIL B
A
e
7
6
D1
e
0.250
b
12
5
DETAIL A
PACKAGE BOTTOM VIEW
6
11
4
1
PIN 1 NOTCH
0.14 × 45°
4
SEE NOTES
DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER
MAY BE EITHER A MOLD OR MARKED FEATURE
THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII
5
6
LQFN 12 0618 REV B
METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN
SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES
4
3. PRIMARY DATUM -Z- IS SEATING PLANE
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
E1
b 10
ccc M Z X Y
PACKAGE DESCRIPTION
0.25 ±0.05
aaa Z
2×
D
0.0000
5
0.2500
PIN 1
CORNER
0.2500
12×
(Reference LTC DWG # 05-08-1530 Rev B)
ccc M Z X Y
LQFN Package
12-Lead (2mm × 2mm × 0.74mm)
LTC3309B
Rev. 0
21
LTC3309B
TYPICAL APPLICATION
Ultra-Low Profile, 10MHz, 1.8V, 6A, Burst Mode Operation
VIN = 2.5V TO 4.5V
4.7µF
1µF
0201 50nH
1µF
0201
EN
VIN
VIN
SW
SW
10pF
LTC3309B
MODE/SYNC
RT
21k
4.7µF
FB
VIN
VOUT
1.8V
6A
31.2k
12k
4.7µF
×2
10nF
AGND
PGND
PGOOD
200k
VOUT
3309B TA07
fOSC = 10MHz
RELATED PARTS
PART NUMBER DESCRIPTION
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3mm × 3mm LQFN
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LTC3374A
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