LTC3315A
Dual 5V, 2A Synchronous Step-Down
DC/DCs in Tiny LQFN and WLCSP
FEATURES
DESCRIPTION
Dual Outputs Each with 2A Output Current
n High Efficiency: 19mΩ NMOS and 75mΩ PMOS
n Wide Bandwidth, Fast Transient Response
n Switching Frequency Synchronizable Up to 3MHz
n V Range: 2.25V to 5.5V
IN
n V
OUT Range: 0.5V to VIN
n V
OUT Accuracy: ±1%
n Low Ripple Burst Mode® Operation
n Peak Current Mode Control
n Minimum On-Time: 25ns
n Safely Tolerates Inductor Saturation in Overload
n Shutdown Current: 1.2µA
n Precision 400mV Enable Thresholds
n Internal Soft-Start and Compensation
n Power Good Output
n Low Profile, Thermally Enhanced 12-Lead
2mm × 2mm × 0.74mm LQFN and 16-Ball 1.64mm ×
1.64mm × 0.5mm WLCSP Packages
n AEC-Q100 Qualified for Automotive Applications
The LTC®3315A features dual 2A monolithic synchronous
step-down converters operating from a 2.25V to 5.5V
input supply in one package for space-constrained applications with demanding performance requirements. Using
constant frequency, peak current mode control at switching frequencies up to 3MHz with a minimum on-time as
low as 25ns, both bucks achieve high efficiency and fast
transient response in a very small application footprint.
n
APPLICATIONS
The LTC3315A operates in forced continuous or pulseskipping mode for low noise or in Burst Mode® operation for high efficiency at light loads. The common buck
switching frequency is 2MHz and can be synchronized to
an external oscillator via the MODE/SYNC pin.
The LTC3315A can regulate outputs as low as 500mV.
Other features include precision enable thresholds, a
PGOOD signal, output overvoltage protection, thermal
shutdown, output short-circuit protection, and up to 100%
duty cycle operation for low dropout. The LTC3315A is
available in a compact 2mm × 2mm LQFN package and a
1.64mm × 1.64mm WLCSP package.
All registered trademarks and trademarks are the property of their respective owners.
Servers, Telecom Supplies, Optical Networking
n Distributed DC Power Systems (POL)
n FPGA, ASIC, µP Core Supplies
n Industrial/Automotive/Communications
n
TYPICAL APPLICATION
Efficiency vs Load Current
Dual 2MHz 2A Buck Regulators
VIN
SW1
10µF
140k
6.8pF
VOUT1
1.2V, 2A
FB1
EN1
VIN
100k
LTC3315A
1µH
SW2
10µF
261k
EN2
22µF
MODE/SYNC
GND
fSW = 2MHz
4.7pF
VOUT2
1.8V, 2A
FB2
PGOOD
100k
3315A TA01a
1.0
90
0.9
80
0.8
70
0.7
60
0.6
50
40
30
20
0.5
Burst Mode OPERATION
VIN = 3.3V, VOUT = 1.2V
L = 880nH, L DCR = 19mΩ
fSW = 2MHz
10
0
1m
0.4
0.3
0.2
EFFICIENCY
POWER LOSS
10m
100m
LOAD CURRENT (A)
POWER LOSS (W)
33µF
EFFICIENCY (%)
VIN
2.25V TO 5.5V
880nH
100
0.1
1
2
0
3315A TA01b
Rev. B
Document Feedback
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1
LTC3315A
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN................................................................ –0.3V to 6V
EN1, EN2............... –0.3V to Lesser of (VIN + 0.3V) or 6V
FB1, FB2................ –0.3V to Lesser of (VIN + 0.3V) or 6V
MODE/SYNC......... –0.3V to Lesser of (VIN + 0.3V) or 6V
PGOOD.......................................................... –0.3V to 6V
IPGOOD.......................................................................5mA
Operating Junction Temperature (Notes 2, 3):
LTC3315AA......................................... –40°C to 125°C
LTC3315AE......................................... –40°C to 125°C
LTC3315AI.......................................... –40°C to 125°C
LTC3315AJ......................................... –40°C to 150°C
LTC3315AH......................................... –40°C to 150°C
LTC3315AMP...................................... –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Maximum Reflow (Package Body) Temperature.... 260°C
PIN CONFIGURATION
1
FB1
2
11
3
4
1
A
10 VIN
9
13
GND
8
5
6
SW2
EN2
12
TOP VIEW
PGOOD
FB2
SW1
EN1
MODE/SYNC
TOP VIEW
7
B
GND
C
GND
D
VIN
PGOOD FB2
VIN
EN2
3
4
MODE/SYNC
FB1
EN1 GND
SW2 SW2 SW1 SW1
VIN
GND GND
VIN
WLCSP PACKAGE
CB-16-11
16-BALL (1.64mm × 1.64mm × 0.5mm)
LQFN PACKAGE
12-LEAD (2mm × 2mm × 0.74mm)
TJMAX = 150°C, θJA = 51°C/W, θJCBOTTOM = 8.6°C/W,
θJCTOP = 80°C/W, θJB = 12°C/W, ΨJT = 0.8°C/W,
θ AND Ψ VALUES DETERMINED PER JESD51-7 ON A JEDEC 2S2P PC
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
2
2
TJMAX = 125°C, θJA = 58°C/W, θJCTOP = 2.7°C/W,
θJB = 14.8°C/W, ΨJT = 2.1°C/W, ΨJB = 15°C/W
θ AND Ψ VALUES DETERMINED PER JESD51-7 ON A JEDEC 2S2P PC
Rev. B
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LTC3315A
ORDER INFORMATION
PART MARKING*
TAPE AND REEL (MINI)
LTC3315AEV#TRMPBF
TAPE AND REEL
LTC3315AEV#TRPBF
LTC3315AIV#TRMPBF
LTC3315AIV#TRPBF
LTC3315AJV#TRMPBF
LTC3315AJV#TRPBF
LTC3315AHV#TRMPBF
LTC3315AHV#TRPBF
LTC3315AMPV#TRMPBF
LTC3315AMPV#TRPBF
LTC3315AACBZ-R7
LHFY
e4
MSL TEMPERATURE
RATING RANGE (SEE NOTE 2)
–40°C to 125°C
PACKAGE
TYPE
DEVICE FINISH CODE
–40°C to 125°C
LQFN (Laminate Package with QFN
Footprint)
MSL 3 –40°C to 150°C
–40°C to 150°C
–55°C to 150°C
3315A
e1
WLCSP (16-Ball Wafer Level Chip Scale
Package)
MSL1 –40°C to 125°C
AUTOMOTIVE PRODUCTS**
LTC3315AEV#WTRMPBF
LTC3315AIV#WTRMPBF
LTC3315AEV#WTRPBF
LTC3315AIV#WTRPBF
LTC3315AJV#WTRMPBF
LTC3315AJV#WTRPBF
LHFY
e4
LQFN (Laminate Package with QFN
Footprint)
MSL 3
LTC3315AHV#WTRMPBF LTC3315AHV#WTRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 150°C
• Contact the factory for parts specified with wider operating
temperature ranges. *Pad or ball finish code is per IPC/JEDEC
J-STD-609.
• Device temperature grade is indicated by a label on the shipping
container.
• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures
• LGA and BGA Package and Tray Drawings
• Tape and reel specifications. Some packages are available in 500 unit reels
through designated sales channels with #TRMPBF suffix.
• TRM = 500 pieces.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Notes 2, 3). VIN = 3.3V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
2.15
150
2.25
V
mV
1.2
2
µA
Input Supply
Operating Supply Voltage (VIN)
VIN Undervoltage Lockout
VIN Undervoltage Lockout Hysteresis
VIN Rising
l
2.25
l
2.05
VIN Quiescent Current in Shutdown
VIN Quiescent Current with One Buck Enabled
Burst Mode, Buck in Regulation, Sleeping
All Modes, Not Sleeping (Note 4)
45
1.5
70
2.3
µA
mA
VIN Quiescent Current with Both Bucks Enabled
Burst Mode, Bucks in Regulation, Sleeping
All Modes, Not Sleeping (Note 4)
70
2.8
110
4.2
µA
mA
Enable Threshold
Enable Threshold Hysteresis
VEN Rising
400
50
425
mV
mV
EN Pin Leakage
VEN = 5.5V
±20
nA
l
375
Voltage Regulation, Buck 1 and Buck 2
Regulated Feedback Voltage (VFB)
Feedback Voltage Line Regulation
l
495
2.25V ≤ VIN ≤ 5.5V
Feedback Pin Input Current
VFB = 500mV
PMOS Current Limit (ILIM)
Current out of SW, VOUT/VIN ≤ 0.2
2.9
500
505
mV
0.015
0.05
%/V
±20
nA
3.5
A
3.2
Rev. B
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3
LTC3315A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Notes 2, 3). VIN = 3.3V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
NMOS Current Limit (IVALLEY)
Current out of SW
2.4
2.7
3.0
A
NMOS Reverse Current Limit
Current into SW, Forced Continuous, LQFN
0.5
1
1.5
A
Current into SW, Forced Continuous, WLCSP
0.5
1
1.7
PMOS ON-Resistance
75
NMOS ON-Resistance
Shutdown, VIN = 5.5V
Minimum On Time
VIN = 5.5V
Overtemperature Shutdown (OT)
Overtemperature Shutdown Hysteresis
25
l
Maximum Duty Cycle
l
mΩ
±200
nA
45
ns
100
Temperature Rising (Note 5)
A
mΩ
19
SW Leakage Current
UNITS
%
165
5
°C
°C
Power Good/Soft-Start
PGOOD Rising Threshold
PGOOD Hysteresis
As a Percentage of the Regulated VOUT
l
l
97
0.6
98
1.1
99
1.6
%
%
Overvoltage Rising Threshold
Overvoltage Hysteresis
As a Percentage of the Regulated VOUT
l
l
107
1
110
2.2
114
3.5
%
%
PGOOD Delay
120
PGOOD Leakage Current
VPGOOD = 5.5V
PGOOD Pull-Down Resistance
VPGOOD = 0.1V
Soft-Start Time
(Note 6)
µs
20
nA
10
20
Ω
l
0.25
1
3
ms
Internal Oscillator Frequency (fSW)
l
1.85
2
2.15
MHz
Synchronization Frequency Range
l
1
3
MHz
Minimum SYNC High or Low Pulse Width
l
40
SYNC Level High on MODE/SYNC
SYNC Level Low on MODE/SYNC
l
l
1.2
Oscillator and MODE/SYNC
MODE/SYNC No Clock Detect Time
MODE/SYNC Pin Threshold
0.4
10
For Programming Pulse Skipping Mode
For Programming Burst Mode
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3315A is tested under pulsed load conditions such
that TJ ≈ TA. The LTC3315AE is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization, and correlation with statistical process controls. The
LTC3315AI is guaranteed over the –40°C to 125°C operating junction
temperature range, the LTC3315AJV and the LTC3315AH are guaranteed
over the –40°C to 150°C operating junction temperature range, and the
LTC3315AMP is guaranteed over the –55°C to 150°C operating junction
temperature range. The LTC3315AA specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization, and correlation with statistical process controls. High
junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications is
4
ns
l
l
VIN – 0.1
V
V
µs
0.1
V
V
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance, and other environmental
factors. The junction temperature (TJ in °C) is calculated from ambient
temperature (TA in °C) and power dissipation (PD in Watts) according to
the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance. See High
Temperature Considerations section for more details.
Note 3: The LTC3315A includes overtemperature protection which
protects the device during momentary overload conditions. Junction
temperatures will exceed 150°C when overtemperature protection is
active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 4: Static current, switches not switching. Actual current will be
higher due to gate charge losses at the switching frequency.
Note 5: Overtemperature shutdown is not tested in production.
Note 6: The soft-start time is the time from the start of switching until the
FB pin reaches 475mV.
Rev. B
For more information www.analog.com
LTC3315A
TYPICAL PERFORMANCE CHARACTERISTICS
510
VFB vs Temperature
150
PMOS RDS(ON) vs Temperature
125
502
500
498
496
494
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
40
35
100
75
50
30
25
20
15
10
25
492
5
490
–50 –25
0
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
2.20
NMOS, VIN = 5.5V, SW = 5.5V
NMOS, VIN = 3.3V, SW = 3.3V
PMOS, VIN = 5.5V, SW = 0V
PMOS, VIN = 3.3V, SW = 0V
2.16
2.12
2.0
1.6
1.2
0.8
0.4
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3315ab G04
2.20
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
2.12
2.08
2.04
2.00
1.96
1.92
2.08
2.04
2.00
1.96
1.92
1.88
1.88
1.84
1.84
1.80
–50 –25
0
Oscillator Frequency vs VIN
2.16
FREQUENCY (MHz)
2.4
25 50 75 100 125 150
TEMPERATURE (°C)
3315ab G03
Oscillator Frequency vs
Temperature
FREQUENCY (MHz)
2.8
0
3315ab G02
NMOS, PMOS Leakage vs
Temperature
3.2
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3315 G01
LEAKAGE (µA)
NMOS RDS(ON) vs Temperature
45
RDS(ON) (mΩ)
RDS(ON) (mΩ)
VFB (mV)
504
50
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
508
506
TA = 25°C, VIN = 3.3V, unless otherwise noted.
25 50 75 100 125 150
TEMPERATURE (°C)
3315aba G05
1.80
2
2.5
3
3.5
4
VIN (V)
4.5
5
5.5
3315ab G06
Rev. B
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5
LTC3315A
TYPICAL PERFORMANCE CHARACTERISTICS
VIN Quiescent Current vs
Temperature, All Modes, Not
Sleeping
VIN Shutdown Quiescent Current
vs Temperature
10.0
BOTH BUCKS ENABLED
2.4
4.0
2.0
1.8
ONE BUCK ENABLED
1.6
3.0
1.2
1.0
1.0
0
0.8
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
0
150°C
25°C
–50°C
20
50
2.2
40
30
3
3.5
4
VIN (V)
4.5
5
1.9
0
–50 –25
5.5
410
3.3
CURRENT OUT OF SW PIN (A)
380
370
360
350
340
330
0
25 50 75 100 125 150
TEMPERATURE (°C)
3315ab G13
0
25 50 75 100 125 150
TEMPERATURE (°C)
3315 G12
Efficiency vs ILOAD Syncing,
Forced Continuous
Current Limit vs Temperature
3.4
390
1.8
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3315ab G11
EN RISING
EN FALLING
400
320
–50 –25
0
3315ab G10
EN Threshold vs Temperature
420
2.1
2.0
20
100
PMOS
NMOS
90
3.1
3.0
2.9
2.8
70
60
50
40
30
2.7
20
2.6
10
2.5
–50 –25
VIN = 3.3V
VOUT = 1.2V
80
3.2
EFFICIENCY (%)
2.5
UVLO RISING
UVLO FALLING
2.3
10
2
25 50 75 100 125 150
TEMPERATURE (°C)
UVLO Threshold vs Temperature
2.4
VIN (V)
30
0
3315ab G09
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
60
MINIMUM ON TIME (ns)
MINIMUM ON TIME (ns)
70
10
VEN (mV)
30.0
–50 –25
Minimum On Time vs
Temperature
40
ONE BUCK ENABLED
3315ab G08
Minimum On Time vs VIN
50
BOTH BUCKS ENABLED
60.0
40.0
25 50 75 100 125 150
TEMPERATURE (°C)
3315ab G7
60
70.0
50.0
1.4
2.0
0
–50 –25
6
IVIN (µA)
IVIN (mA)
5.0
0
80.0
2.2
6.0
VIN = 5.5V
VIN = 3.3V
VIN = 2.25V
90.0
2.6
7.0
IVIN (µA)
100.0
2.8
8.0
70
VIN Quiescent Current vs
Temperature, Burst Mode,
Sleeping
3.0
VIN = 5.5V
VIN = 3.3V
9.0
TA = 25°C, VIN = 3.3V, unless otherwise noted.
0
25 50 75 100 125 150
TEMPERATURE (°C)
3315ab G14
0
1m
10m
100m
LOAD CURRENT (A)
1MHz, L = 1.5µH, DCR = 33mΩ
2MHz, L = 880nH, DCR = 19mΩ
3MHz, L = 560nH, DCR = 16mΩ
1
2
3315ab G15
Rev. B
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LTC3315A
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT Load Regulation
1.212
VOUT Line Regulation
1.208
1.206
106
OV RISING
OV FALLING
PGOOD RISING
PGOOD FALLING
102
100
98
96
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1.204
1.202
1.200
1.198
1.198
1.196
1.194
1.194
1.192
1.192
1.190
1.190
10m
100m
LOAD CURRENT (A)
1
2
1.188
100
Efficiency vs ILOAD,
VOUT = 0.8V, VIN = 3.3V
100
90
90
80
80
80
70
70
70
50
fSW = 2MHz
L = 680nH
L DCR = 17mΩ
40
30
10
0
1m
10m
100m
LOAD CURRENT (A)
1
60
50
fSW = 2MHz
L = 680nH
L DCR = 17mΩ
40
30
20
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
10
0
1m
2
10m
100m
LOAD CURRENT (A)
1
50
30
0
1m
100
Efficiency vs ILOAD,
VOUT = 1.2V, VIN = 3.3V
100
80
70
70
70
30
20
10
0
1m
fSW = 2MHz
L = 880nH
L DCR = 19mΩ
10m
100m
LOAD CURRENT (A)
1
50
40
30
20
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
10
2
3315ab G22
EFFICIENCY (%)
90
80
EFFICIENCY (%)
90
60
0
1m
fSW = 2MHz
L = 880nH
L DCR = 19mΩ
10m
100m
LOAD CURRENT (A)
1
3315ab G18
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
10m
100m
LOAD CURRENT (A)
3315ab G23
1
2
60
50
40
30
10
2
5.5
Efficiency vs ILOAD,
VOUT = 1.2V, VIN = 5.5V
20
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
5
3315ab G21
80
40
4.5
fSW = 2MHz
L = 680nH
L DCR = 17mΩ
40
90
50
3.5
4
VIN (V)
3315ab G20
Efficiency vs ILOAD,
VOUT = 1.2V, VIN = 2.25V
60
3
60
10
2
2.5
Efficiency vs ILOAD,
VOUT = 0.8V, VIN = 5.5V
20
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
3315ab G19
100
EFFICIENCY (%)
90
60
2
3315ab G17
EFFICIENCY (%)
EFFICIENCY (%)
1.200
1.196
Efficiency vs ILOAD,
VOUT = 0.8V, VIN = 2.25V
20
EFFICIENCY (%)
1.206
1.202
3315ab G16
100
1.208
1.204
1.188
1m
ILOAD = 0A
ILOAD = 2A
VOUT = 1.2V
1.210
VOUT (V)
108
1.212
VIN = 5.5V
VIN = 5.0V
VIN = 3.3V
VIN = 2.25V
VOUT = 1.2V
1.210
110
VOUT (V)
PERCENTAGE OF THE REGULATED VOUT (%)
PGOOD, OV vs Temperature
112
104
TA = 25°C, VIN = 3.3V, unless otherwise noted.
0
1m
fSW = 2MHz
L = 880nH
L DCR = 19mΩ
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
10m
100m
LOAD CURRENT (A)
1
2
3315ab G24
Rev. B
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7
LTC3315A
TYPICAL PERFORMANCE CHARACTERISTICS
100
Efficiency vs ILOAD,
VOUT = 1.8V, VIN = 3.3V
100
90
90
80
80
80
70
70
70
60
50
fSW = 2MHz
L = 1µH
L DCR = 20mΩ
40
30
20
10
0
1m
10m
100m
LOAD CURRENT (A)
1
60
50
fSW = 2MHz
L = 1µH
L DCR = 20mΩ
40
30
20
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
0
1m
10m
100m
LOAD CURRENT (A)
1
3315ab G25
Efficiency vs ILOAD,
VOUT = 2.5V, VIN = 3.3V
100
90
90
80
80
70
70
60
50
fSW = 2MHz
L = 1.2µH
L DCR = 23mΩ
40
30
20
10
0
1m
60
50
fSW = 2MHz
L = 1µH
L DCR = 20mΩ
40
30
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
10
2
0
1m
10m
100m
LOAD CURRENT (A)
3315ab G26
EFFICIENCY (%)
EFFICIENCY (%)
100
Efficiency vs ILOAD,
VOUT = 1.8V, VIN = 5.5V
20
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
10
2
EFFICIENCY (%)
90
EFFICIENCY (%)
EFFICIENCY (%)
100
Efficiency vs ILOAD,
VOUT = 1.8V, VIN = 2.25V
TA = 25°C, VIN = 3.3V, unless otherwise noted.
10m
100m
LOAD CURRENT (A)
1
3315ab G27
60
50
fSW = 2MHz
L = 1.2µH
L DCR = 23mΩ
40
30
10
0
1m
2
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
10m
100m
LOAD CURRENT (A)
3315ab G28
Efficiency vs ILOAD,
VOUT = 3.3V, VIN = 4.2V
100
90
90
80
80
70
70
60
50
40
30
20
10
0
1m
fSW = 2MHz
L = 1.2µH
L DCR = 23mΩ
10m
100m
LOAD CURRENT (A)
1
60
50
40
30
10
2
0
1m
3315ab G30
8
2
Efficiency vs ILOAD,
VOUT = 3.3V, VIN = 5.5V
20
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
1
3315ab G29
EFFICIENCY (%)
EFFICIENCY (%)
100
2
Efficiency vs ILOAD,
VOUT = 2.5V, VIN = 5.5V
20
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
1
fSW = 2MHz
L = 1.2µH
L DCR = 23mΩ
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
10m
100m
LOAD CURRENT (A)
1
2
3315ab G31
Rev. B
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LTC3315A
TYPICAL PERFORMANCE CHARACTERISTICS
Transient Response, Pulse Skip
Mode
TA = 25°C, VIN = 3.3V, unless otherwise noted.
Transient Response, Burst Mode
Operation
Transient Response, FC Mode
ILOAD
1A/DIV
ILOAD
1A/DIV
ILOAD
1A/DIV
IL
1A/DIV
IL
1A/DIV
IL
1A/DIV
VOUT
50mV/DIV
LOAD STEP: 0.1A TO 1.5A, 5A/µs
10µs/DIV
VOUT
50mV/DIV
LOAD STEP: 0.1A TO 1.5A, 5A/µs
3315ab G32
10µs/DIV
VOUT
50mV/DIV
10µs/DIV
3315ab G34
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
Startup Transient, Pulse Skip
Mode
Startup Transient, FC Mode
Startup Transient, Burst Mode
EN
2V/DIV
EN
2V/DIV
EN
2V/DIV
VOUT
500mV/DIV
VOUT
500mV/DIV
VOUT
500mV/DIV
IL
500mA/DIV
PGOOD
5V/DIV
LOAD STEP: 0.1A TO 1.5A, 5A/µs
3315ab G33
IL
500mA/DIV
IL
500mA/DIV
RLOAD = 120Ω
200µs/DIV
3315ab G35
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
PGOOD
5V/DIV
RLOAD = 120Ω
200µs/DIV
3315ab G36
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
PGOOD
5V/DIV
RLOAD = 120Ω
200µs/DIV
3315ab G37
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
Rev. B
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9
LTC3315A
PIN FUNCTIONS
(LQFN/WLCSP)
EN1 (Pin 1/Ball B3): Enable Input for Buck Regulator 1.
Active high. The EN1 pin has a precision threshold and
an optional external resistor divider from VIN or another
supply programs when Buck Regulator 1 is enabled. If
the precision threshold is not required, drive EN1 to VIN
to enable. Do not float.
FB1 (Pin 2/Ball A3): Feedback Input for Buck Regulator
1. Program the output voltage and close the control loop
by connecting this pin to the middle node of a resistor
divider between the output and ground. The LTC3315A
regulates FB1 to 500mV (typical). A phase lead capacitor connected between VOUT1 and FB1 may be used to
optimize transient response.
FB2 (Pin 3/Ball A2): Feedback Input for Buck Regulator
2. Program the output voltage and close the control loop
by connecting this pin to the middle node of a resistor
divider between the output and ground. The LTC3315A
regulates FB2 to 500mV (typical). A phase lead capacitor connected between VOUT2 and FB2 may be used to
optimize transient response.
EN2 (Pin 4/Ball B2): Enable Input for Buck Regulator 2.
Active high. The EN2 pin has a precision threshold and
an optional external resistor divider from VIN or another
supply programs when Buck Regulator 2 is enabled. If
the precision threshold is not required, drive EN2 to VIN
to enable. Do not float.
PGOOD (Pin 5/Ball A1): Power Good Output. Open
drain output. When the regulated output voltage of
either enabled switching regulator falls below its PGOOD
threshold or rises above its overvoltage threshold, this
pin is driven low. When both buck regulators are disabled
PGOOD is driven low.
10
SW2 (Pin 6/Balls C1, C2): Switch Node for Buck Regulator
2. Connect an inductor to this pin with a short, wide trace.
VIN (Pin 7, Pin 10/Balls B1, D1, D4): Input Supply Pins.
The VIN pins supply current to internal circuitry and to
each buck’s PMOS power switch. Connect both VIN pins
together with a short, wide trace and bypass to GND
with low ESR capacitors located as close as possible
to the pins. On the WLCSP package, an optional 0.1µF
bypass capacitor can be added to Ball B1 to reduce noise
at high VIN.
GND (Pin 8, Pin 9, Exposed Pad Pin 13/Balls B4, D2,
D3): Ground. Connect the exposed pad to a continuous
ground plane on the printed circuit board directly under
the LTC3315A for electrical contact and rated thermal performance. Additionally, Pin 8 and Pin 9 should be shorted
to the exposed pad with a wide trace. On the WLCSP
package, Balls D2 and D3 can connect on the top of the
PCB board to bypass capacitors on VIN and then via to a
ground plane on the next layer. Ball B4 can via directly to
the ground plane on the next layer.
SW1 (Pin 11/Balls C3, C4): Switch Node for Buck
Regulator 1. Connect an inductor to this pin with a short,
wide trace.
MODE/SYNC (Pin 12/Ball A4): Mode Selection and
External Clock Synchronization Input. Ground this pin
to enable pulse-skipping mode. For higher efficiency at
light loads, tie this pin to VIN to enable Burst Mode. For
fast transient response and constant frequency operation
over a wide load range, float this pin to enable forced
continuous mode. Drive MODE/SYNC with an external
clock to synchronize both buck converters to the applied
frequency. When syncing, the operating mode is forced
continuous. The slope compensation is automatically
adapted to the external clock frequency. In the absence
of an external clock both buck converters will switch at
the default switching frequency.
Rev. B
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LTC3315A
BLOCK DIAGRAM
VIN
10, B1, D4
BUCK1
EN1
1, B3
0.4V
+
–
ENBUCK1
BUCK
CONTROL
OT
MODE/SYNC
12, A4
0°
SWITCH
LOGIC
AND
ANTISHOOT
THROUGH
OSCILLATOR
VC1
PULSE SKIP
MODE
DETECTION
FC
0.49V
180°
0.4V
0.4V
0.55V
OVER
TEMPERATURE
DETECT
ENBUCK2
OT
BUCK
CONTROL
VC2
+
–
SWITCH
LOGIC
AND
ANTISHOOT
THROUGH
0.55V
+
–
+
–
+
–
GM
FB1
0.49V
FB1
2, A3
VIN
7, D1
BUCK2
0.5V
INTERNAL
REFERENCE
+
–
0.5V
BURST
0.55V
EN2
4, B2
+
–
GM
SW1
11, C3, C4
SW2
6, C1, C2
0.5V
FB2
3, A2
PGOOD
5, A1
ENBUCK1
ENBUCK2
FB2
0.49V
+
–
GND: PINS 8, 9, 13 (EXPOSED PAD); BALLS B4, D2, D3
3315ab BD
Rev. B
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11
LTC3315A
OPERATION
Buck Switching Regulators
The LTC3315A is a 5V dual 2A monolithic, constant frequency, peak current mode step-down DC/DC converter.
The synchronous buck switching regulators are internally
compensated and require only external feedback resistors
to set the output voltage.
An internal oscillator, which can be externally synchronized, turns on the internal PMOS power switch at the
beginning of each clock cycle. Current in the inductor
ramps up until the PMOS current comparator trips and
turns off the PMOS. The peak inductor current, IPEAK, at
which the PMOS turns off is controlled by an internal VC
voltage which the error amplifier regulates by comparing the voltage on the feedback (FB) pin with an internal
500mV reference. An increase in the load current causes
a reduction in the feedback voltage relative to the reference, causing the error amplifier to raise the VC voltage
(and IPEAK) until the average inductor current matches the
new load current. When the PMOS turns off, the NMOS
turns on and ramps down the inductor current for the
remainder of the clock cycle or, if in pulse skipping mode
or Burst Mode, until the inductor current falls to zero. If
an overload condition results in excessive current flowing
through the NMOS, the next clock cycle will be skipped
until the current returns to a safe level.
Each buck switching regulator has its own SW, FB, and
EN pins. The buck input supplies are internally connected,
but each VIN pin should have its own input bypass capacitor (see Applications Information). The enable pins have
precision 400mV thresholds which may be used to provide event-based power-up sequencing by connecting
the enable pin to the output of another buck through a
resistor divider. If the EN pin of a buck is low, that buck is
in shutdown and in a low quiescent current state. If both
EN pins are low, both bucks are in shutdown, the SW
pins are high impedance, and the quiescent current of the
LTC3315A is 1µA (typical). If either EN pin is above the
enable threshold of 400mV its respective buck is enabled.
Both buck regulators have forward and reverse inductor
current limiting, soft-start to limit inrush current during
start-up, and short-circuit protection. When both bucks
are disabled and either buck is subsequently enabled,
12
there is a 400µs (typical) delay while internal circuitry
powers up followed by a 100µs (typical) no start time
before switching commences and the soft-start ramp
begins. If a second buck is then enabled, it will also have
a 100µs (typical) no start time. If the second buck is
enabled within 400µs of the first buck, it will wait until
the expiry of the 400µs to begin its no start time.
The buck switching regulators are switched 180° out of
phase with respect to each other. The phase determines
the fixed edge of the switching sequence, which is when
the PMOS turns on. The PMOS off (NMOS on) phase is
subject to the regulated duty cycle of each buck.
Mode Selection
The buck switching regulators operate in three different
modes set by the MODE/SYNC pin: pulse skipping mode
(when the MODE/SYNC pin is set low), forced continuous
PWM mode (when the MODE/SYNC pin is floating), and
Burst Mode (when the MODE/SYNC pin is set high). The
MODE/SYNC pin sets the operating mode for both buck
switching regulators.
In pulse skipping mode, the oscillator operates continuously and positive SW transitions are aligned to the clock.
Negative inductor current is disallowed and during light
loads switch pulses are skipped to regulate the output.
In forced continuous mode, the oscillator runs continuously, no pulses are skipped, and switching occurs in
every cycle. To maintain regulation, the inductor current
is allowed to reverse under light load conditions. This
mode allows the buck to run at a fixed frequency with
minimal output ripple. In forced continuous mode if the
inductor current reaches –1A (typical, 1A into the SW pin)
the NMOS will turn off for the remainder of the cycle to
limit the current.
In Burst Mode operation, at light loads, the output capacitor is charged to a voltage slightly higher than its regulation point. The regulator then goes into a sleep state,
during which time the output capacitor provides the load
current. In sleep most of the regulator’s circuitry is powered down, helping to conserve input power. When the
output voltage drops below its programmed value, the circuitry is powered back on and another burst cycle begins.
Rev. B
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LTC3315A
OPERATION
The sleep time decreases as load current increases. In
Burst Mode operation, the regulator will burst at light
loads whereas at higher loads it will operate in constant
frequency PWM mode.
Synchronizing the Oscillator to an External Clock
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values
and improves transient response. Operation at lower
frequencies improves efficiency by reducing switching
losses but requires larger inductance and/or capacitance values to maintain low output voltage ripple. The
LTC3315A operates at a default frequency of 2MHz.
The LTC3315A’s internal oscillator is synchronized
through an internal PLL circuit to an external frequency by
applying a square wave clock signal to the MODE/SYNC
pin. During synchronization, the Buck 1 PMOS turn-on is
locked to the rising edge of the external frequency source.
Buck 2 will be 180° out of phase with respect to Buck 1.
While syncing, the buck switching regulators operate in
forced continuous mode. The synchronization frequency
range is 1MHz to 3MHz.
After detecting an external clock on the SYNC pin, the
internal PLL starts up at the default frequency. The internal PLL then gradually adjusts its operating frequency to
match the frequency and phase of the SYNC signal.
When the external clock is removed the LTC3315A will
detect the absence of the external clock within approximately 10µs. During this time it will continue to provide
clock cycles. Once the external clock removal has been
detected, the oscillator will gradually adjust its operating
frequency back to the default.
Power Failure Reporting Via PGOOD Pin
Power failure faults are reported via the PGOOD pin.
Both buck switching regulators have an internal power
good (PGOOD) signal and if a buck is enabled its internal
PGOOD signal must be high for the PGOOD pin to be high.
When the regulated output voltage of an enabled buck
rises above 98% of its programmed value, the PGOOD
signal transitions high. If the regulated output voltage
subsequently falls below 97% of its programmed value,
the PGOOD signal is pulled low. If either enabled buck’s
internal PGOOD signal stays low for greater than 120μs,
then the PGOOD pin is pulled low, indicating to a microprocessor that a power fault has occurred. The 120μs
filter time prevents the pin from being pulled low during a
transient event. In addition, whenever PGOOD transitions
high there will be a 120μs assertion delay.
The LTC3315A also reports overvoltage conditions at
the PGOOD pin. If either enabled buck regulator’s output voltage rises above 110% of its programmed value,
the PGOOD pin is pulled low after 120μs. Similarly, if all
enabled outputs that are overvoltage subsequently fall
below 107.8% of their programmed value, the PGOOD
pin transitions high again after 120μs.
An error condition that pulls the PGOOD pin low is not
latched. When the error condition goes away, the PGOOD
pin is released and is pulled high if no other error condition exists. PGOOD is also pulled low in the following
scenarios: if neither buck switching regulator is enabled,
if VIN is below the UVLO threshold, or if the LTC3315A is
over temperature (see below).
Output Overvoltage Protection
During an output overvoltage event, when the FB pin
voltage is greater than 110% of its regulated value, the
LTC3315A PMOS will be turned off immediately.
An output overvoltage event should not happen under
normal operating conditions.
Overtemperature Protection
To prevent thermal damage, the LTC3315A incorporates
an overtemperature (OT) function. When the LTC3315A
die temperature reaches 165°C (typical, not tested) all
enabled buck switching regulators are shut down and
remain in shutdown until the die temperature falls to
160°C (typical, not tested).
Rev. B
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13
LTC3315A
OPERATION
Output Voltage Soft-Start
Low Supply Operation
Soft starting the output prevents current surge on the input
supply and/or output voltage overshoot. During soft-start,
the output voltage will proportionally track an internal
voltage ramp. An active pull-down circuit discharges that
internal voltage in the case of fault conditions. The ramp
will restart when the fault is cleared. Fault conditions that
initiate the soft-start ramp are the VIN voltage falling too
low or thermal shutdown.
The LTC3315A is designed to operate down to an input
supply voltage of 2.25V. An important thermal design
consideration is that the RDS(ON) of the power switches
increases at low input. Consider the worst case LTC3315A
power dissipation and die junction temperature at the lowest input voltage.
Recovery from an output short-circuit (see below) may
involve another soft-start cycle if the FB voltage falls more
than 120mV (typical) below regulation. During such a
recovery, the FB voltage will quickly charge up to 120mV
(typical) and then follow the soft-start ramp until regulation is reached.
The peak inductor current level at which the current comparator shuts off the PMOS is controlled by the error
amplifier. When the output current increases, the error
amplifier raises the internal VC voltage until the average
inductor current matches the load current. The LTC3315A
clamps the maximum internal VC voltage, thereby limiting
the peak inductor current.
Dropout Operation
As the input supply voltage approaches the output voltage, the duty cycle increases toward 100%. Further reduction of the supply voltage forces the PMOS to remain on
for more than one cycle, eventually reaching 100% duty
cycle. The output voltage will then be determined by the
input voltage minus the DC voltage drop across the internal PMOS and the inductor.
Output Short-Circuit Protection and Recovery
When the output is shorted to ground, the inductor current decays very slowly during the downslope because
the voltage across the inductor is low. To keep the inductor current in control a secondary limit is imposed on
the valley of the inductor current. If the inductor current measured through the NMOS remains greater than
IVALLEY at the end of the cycle, the PMOS will be held
off. Subsequent switching cycles will be skipped until the
inductor current falls below IVALLEY.
APPLICATIONS INFORMATION
Buck Switching Regulator Output Voltage and
Feedback Network
VOUT
BUCK
SWITCHING FB
REGULATOR
The output voltage of the buck switching regulators is
programmed by a resistor divider connected from the
switching regulator’s output to ground and is given by:
VOUT
⎛ R2 ⎞
= VFB ⎜ 1+ ⎟
⎝ R1⎠
R1
CFF
+
COUT
(OPTIONAL)
3315ab F01
(1)
as shown in Figure 1 where VFB = 500mV. Typical values for R1 range from 40kΩ to 1MΩ. 1% resistors are
recommended to maintain output voltage accuracy. The
buck regulator transient response may improve with
an optional phase lead capacitor CFF that helps cancel
14
R2
Figure 1. Feedback Components
the pole created by the feedback resistors and the input
capacitance of the FB pin. Experimentation with capacitor values between 2pF and 22pF may improve transient
response. The values used in the typical application circuits are a good starting point.
Rev. B
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LTC3315A
APPLICATIONS INFORMATION
Operating Frequency Selection and Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, transient response, and input
voltage range. The LTC3315A can operate at frequencies
between 1MHz and 3MHz.
The advantage of high frequency operation is that smaller
inductor and capacitor values may be used. Higher
switching frequencies allow for higher control loop
bandwidth and, therefore, faster transient response. The
disadvantages of higher switching frequencies are lower
efficiency, because of increased switching losses, and a
smaller input voltage range, because of minimum switch
on-time limitations.
The minimum on-time of the buck regulator imposes a
minimum operating duty cycle. The highest switching
frequency (fSW(MAX)) for a given application can be calculated as follows:
VOUT
fSW(MAX) =
tON(MIN) • VIN(MAX)
(2)
where VIN(MAX) is the maximum input voltage, VOUT is the
output voltage and tON(MIN) is the minimum top switch
on-time. This equation shows that a slower switching
frequency might be necessary to accommodate a high
VIN/VOUT ratio.
The LTC3315A is capable of a maximum duty cycle of
100%, therefore, the VIN-to-VOUT dropout is limited by
the RDS(ON) of the PMOS, the inductor DCR, and the load
current.
Inductor Selection and Maximum Output Current
Considerations in choosing an inductor are inductance,
RMS current rating, saturation current rating, DCR, and
core loss.
Select the inductor value based on the following equations:
L≈
L≈
VOUT
0.6A • fSW
VIN(MAX)
2.4A • fSW
⎞
⎛
V
V
• ⎜ 1− OUT ⎟ for OUT ≤ 0.5 (3)
VIN(MAX)
⎝ VIN(MAX) ⎠
for
VOUT
VIN(MAX)
(4)
> 0.5
where fSW is the switching frequency and VIN(MAX) is the
maximum applied input voltage.
To avoid overheating of the inductor, choose an inductor
with an RMS current rating that is greater than the maximum expected output load of the application. Overload and
short-circuit conditions need to be taken into consideration.
In addition ensure that the saturation current rating (typically labeled ISAT) is either higher than 3.5A, the maximum
current limit of the LTC3315A, or higher than the maximum
expected load plus half the inductor ripple:
1
ISAT > ILOAD(MAX) + ΔIL
2
(5)
where ILOAD(MAX) is the maximum output load current
for the application and ΔIL is the inductor ripple current
calculated as:
ΔIL =
VOUT
L • fSW
⎛ V ⎞
• ⎜ 1− OUT ⎟
VIN ⎠
⎝
(6)
To keep the efficiency high, choose an inductor with
the lowest series resistance (DCR) and a core material
intended for high frequency applications. Table 1 shows
recommended inductors from several manufacturers.
Input Capacitors
Bypass the input of the LTC3315A with at least two ceramic
capacitors, one near each VIN pin for best performance.
Connect the ground of each capacitor to a wide PCB trace
on the top layer of the PCB that connects pins 8 and 9
with the exposed pad. These capacitors should be 0603
or 0805 in size. Smaller 0201 capacitors can also be
placed as close as possible to the LTC3315A directly on
the traces leading from VIN (Pin 7) and GND (Pin 8) and
on the traces leading from VIN (Pin 10) and GND (Pin 9)
to reduce input noise with minimal (if at all) increase in
application footprint. See the layout section for more
detail. On the WLCSP package, an optional 0.1µF bypass
capacitor can be added to Ball B1 to reduce noise at high
VIN. X7R or X5R capacitors are recommended for best
performance across temperature and input voltage variations (see Table 2). Note that larger input capacitance is
Rev. B
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15
LTC3315A
APPLICATIONS INFORMATION
Table 1. Recommended Inductors
MANUFACTURER
FAMILY
L (nH)
MAX IDC (A)
MAX DCR (mΩ)
SIZE IN mm (L × W × H)
Murata
DFE18SAN_G0
240 - 470
3.6 - 4.9
30 - 54
1.6 × 0.8 × 1.0
Murata
DFE252010F
330 - 680
3.5 - 4.8
21 - 37
2.5 × 2.0 × 1.0
Vishay
IHLP-1212BZ-11
220 - 1500
4.0 - 7.5
11.4 - 32
3.0 × 3.0 × 2.0
Vishay
IHHP-0806AB-01
220 - 470
3.6 - 5.0
16 - 35
2.0 × 1.6 × 1.2
Wurth Elektronik
WE-MAPI
330 - 1500
3.7 - 5.5
17 - 39
3.0 × 3.0 × 2.0
Wurth Elektronik
WE-PMCI
250 - 470
3.6 - 4
12.5 - 31
3.2 × 2.5 × 1.2
Coilcraft
XEL3515
72 - 560
3.2 - 23.7
6.5 - 16
3.5 × 3.2 × 1.5
required when a lower switching frequency is used. If
the input power source has high impedance, or if there
is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. This can be
provided with an electrolytic capacitor. A ceramic input
capacitor combined with trace or cable inductance forms
a high quality (underdamped) tank circuit. If the LTC3315A
circuit is plugged in to a live supply, the input voltage can
ring to twice its nominal value, possibly exceeding the
voltage rating. This situation is easily avoided (see Analog
Devices Application Note 88).
Table 2. Ceramic Capacitor Manufacturers
MANUFACTURER
URL
AVX
www.avxcorp.com
Murata
www.murata.com
TDK
www.tdk.com
Taiyo Yuden
www.t-yuden.com
Samsung
www.samsungsem.com
Wurth Elektronik
www.we-online.com
Output Capacitor, Output Ripple, and Loop Response
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LTC3315A at the SW pin to produce the DC output. In
this role it determines the output ripple; thus, low impedance at the switching frequency is important. The second
function is to store energy in order to satisfy transient
loads and to stabilize the LTC3315A’s control loop.
The LTC3315A is internally compensated and designed to
operate at a high bandwidth for fast transient response
capability. The selection of COUT affects the bandwidth of
16
the system, but the transient response is also affected by
VOUT, VIN, fSW and other factors. A good place to start is
with an output capacitance value of approximately:
COUT =
80µF • MHz 500mV
VOUT
fSW
(7)
where COUT is the recommended output capacitor value
and fSW is the switching frequency. A lower value of output
capacitor saves space and cost, but transient performance
will suffer and loop stability must be verified. Ceramic capacitors have very low equivalent series resistance (ESR)
and provide the best output ripple and transient performance. Use X5R or X7R ceramic capacitors. (see Table 2).
Even better output ripple and transient performance can
be achieved by using low-ESL reverse geometry or three
terminal ceramic capacitors.
During a load step, the output capacitor must instantaneously
supply the current to support the load until the feedback
loop increases the switch current enough to support the
load. The time required for the feedback loop to respond
is dependent on the compensation components and the
output capacitor size. Typically, 3 to 4 cycles are required
to respond to a load step, but only in the first cycle does the
output drop linearly. Although affected by VOUT, VIN, fSW,
tON(MIN), the equivalent series inductance (ESL) of the output
capacitor, and other factors, the output droop, VDROOP, is
usually about 3 times the linear drop of the first cycle:
VDROOP =
3 • ΔIOUT
COUT • fSW
(8)
where ΔIOUT is the load step.
Rev. B
For more information www.analog.com
LTC3315A
APPLICATIONS INFORMATION
Transient performance and control loop stability can
be improved with a higher COUT and/or the addition of
a feedforward capacitor, CFF, placed between VOUT and
FB. Capacitor CFF provides phase lead compensation by
creating a high frequency zero which improves the phase
margin and the high-frequency response. The values used
in the typical application circuits are a good starting point.
LTpowerCAD® is a useful tool to help optimize CFF and
COUT for the desired transient performance.
Applying a load transient and monitoring the response of
the system or using a network analyzer to measure the
actual loop response are two ways to experimentally verify
transient performance and control loop stability, and to
optimize CFF and COUT.
When using the load transient response method to stabilize
the control loop, apply an output current pulse going from
20% to 100% of full load current having a very fast rise
time. This will produce a transient on the output voltage.
Monitor VOUT for overshoot or ringing that might indicate
a stability problem (see Application Note 149).
Using the Precision Enable Threshold
The LTC3315A has precision threshold enable pins for
each buck regulator to enable or disable each buck. When
both are forced low, the device enters into a low current
shutdown mode.
VIN
BUCK
SWITCHING EN
REGULATOR
R4
R3
3315ab F02
Figure 2. EN Divider
be adjusted by setting the values of R3 and R4 such that
they satisfy the following equation:
⎛ R4 ⎞
VIN(EN) = 400mV • ⎜ 1+ ⎟
⎝ R3 ⎠
(9)
The buck regulator will remain off until VIN is above
VIN(EN). The buck regulator will remain enabled until VIN
falls to 0.875 • VIN(EN) and EN is 350mV.
Alternatively a resistor divider from the output of one buck
to the EN pin of the second buck to ground provides event
based power-up sequencing as the first buck reaching
regulation enables the second buck. Replace VIN(EN) in
Equation 9 with the desired output voltage of the first buck
(e.g. 90% of the regulated value) at which the second
buck is enabled.
PCB Considerations
The rising threshold of both EN comparators is 400mV,
with 50mV of hysteresis. The EN pins can be tied to VIN
if the shutdown feature is not used. Adding a resistor
divider from VIN to an EN pin to ground programs the
LTC3315A to regulate that output only when VIN is above
a desired voltage.
The LTC3315A is a high performance IC designed for high
efficiency and fast transient response. For optimal results
carefully consider the layout of the PCB board and follow
the below list to ensure proper operation. Reference the
layout design files for the demo board for both the LQFN
and WLCSP packages on the LTC3315A product page on
the ADI website to see the optimal PCB layout. See Figure 3
for a recommended PCB layout.
Typically, this threshold, VIN(EN), is used in situations
where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws
near constant power from its input source, so source current increases as source voltage drops. This looks like
a negative resistance load to the source and can cause
the source to current limit or latch low under low source
voltage conditions. The VIN(EN) threshold prevents the
regulator from operating at source voltages where problems may occur. Referring to Figure 2, this threshold can
1. Connect the exposed pad of the LQFN package (Pin 13)
directly to a large, unbroken ground plane under the
application circuit on the layer closest to the surface
layer to minimize thermal and electrical impedance.
Additionally, short the exposed pad to ground pins
8 and 9 on the top layer. See the Application Note,
Application Notes for Thermally Enhanced Leaded
Plastic Packages document for the proper size and
layout of the thermal vias and solder stencils. On the
WLCSP package, Balls D2 and D3 can connect on the
Rev. B
For more information www.analog.com
17
LTC3315A
APPLICATIONS INFORMATION
VOUT2
VIN
COUT2
L2
CFF2
CIN2
R4
7
4
13
7
R1
1
10
R3
R2
R1, R3 KELVIN
TO GND ON
LAYER 4 TO VIAS
ON EXPOSED
PAD, PIN 13
CIN1
CFF1
L1
GND
COUT1
VOUT1
GROUND
PLANE ON
LAYER 2
3315ab F03
Figure 3. Recommended LTC3315A LQFN PCB Layout
top of the PCB board to bypass capacitors on VIN and
then via to a ground plane on the next layer. Ball B4
can via directly to the ground plane on the next layer.
input impedance sensitive nodes, such as the feedback
nodes, should be kept far away or shielded from the
switching nodes or poor performance could result.
2. Both of the input supply pins should have local decoupling capacitors with their grounded pins connecting
on the top layer to the ground plane around pin 8,
pin 9, and the exposed pad. These capacitors provide
the AC current to the internal power MOSFETs and
their drivers. Large, switched currents flow in these
capacitors and it is important to minimize inductance
from these capacitors by choosing a small case size
such as 0603 and placing them close to the VIN pins
of the LTC3315A. To further minimize inductance and
input noise, smaller 0201 capacitors can be placed
as close as possible to the LTC3315A directly on the
traces leading from VIN (Pin 7) and GND (Pin 8) and on
the traces leading from VIN (Pin 10) and GND (Pin 9)
minimal (if at all) increase in application footprint. On
the WLCSP package, an optional 0.1µF bypass capacitor can be added to Ball B1 to reduce noise at high VIN.
4. The GND side of the switching regulator output capacitors connects directly to the thermal ground plane
of the IC. Minimize the trace length from the output
capacitor to the inductor(s)/pin(s).
3. The switching power traces connecting SW1 and SW2
to their respective inductors should be minimized to
reduce radiated EMI and parasitic coupling. Due to
the large voltage swing on the switching nodes, high
18
High Temperature Considerations
A thermal representation of the LTC3315A thermally
enhanced LQFN package is shown in Figure 4 with the
silicon die and thermal metrics identified. The current
source represents power loss PD on the die; node voltages
represent temperatures; electrical impedances represent
conductive thermal impedances θJCBOTTOM, θJCTOP, θVIA,
θCB, and convective thermal impedances θCA and θBA. The
junction temperature, TJ, is calculated from the ambient
temperature, TA, as:
TJ = TA + PD • θJA (10)
where, neglecting the θJCTOP + θCA path:
θ JA ≈ θ JCB +
⎛θCB + θBA⎞ ⎛θCB + θBA
⎞
!
+ θ VIA (11)
⎝
⎠ ⎝
⎠
2
2
Rev. B
For more information www.analog.com
LTC3315A
APPLICATIONS INFORMATION
where θJCB = θJCBOTTOM = 10°C/W. The value of
θJA = 51°C/W reported in the Pin Configuration section
corresponds to JEDEC standard 2S2P test PCB, which
does not have good thermal vias, i.e., θVIA is relatively
high. Assuming, somewhat arbitrarily but not unreasonably, that θVIA ~ (θCB + θBA)/2, and back calculating it is
seen that (θCB + θBA)/2 = θVIA ≈ 60°C/W for such a board.
The importance of thermal vias becomes clear observing
that if the test PCB had low-thermal-resistance vias, the
θJA would have been reduced by up to 10°C/W, which is
an improvement of up to 20%. Similarly, having more
ground planes that are larger, uninterrupted and highercopper-weight improves θCB + θBA, which has a dominant
effect on θJA, given the low value of θJCBOTTOM of the
package. The maximum load current should be derated
as the ambient temperature approaches the maximum
junction rating. Power dissipation within the LTC3315A
is estimated by calculating the total power loss from an
efficiency measurement and subtracting the inductor loss.
TA
DIE
PD
TA
θCA
PACKAGE
SUBSTRATE
LQFN
θJCTOP
TJ
θBA
θBA
θJCBOTTOM
θCB
θCB
PCB
TA
θVIA
θCB
θCB
PCB
3315ab F04
θBA
TA
θBA
TA
Figure 4. Multi-Layer PCB with Thermal Vias Acts as a Heat Sink
Rev. B
For more information www.analog.com
19
LTC3315A
TYPICAL APPLICATIONS
Dual 1.5V and 1.8V 2MHz, 2A Buck Regulators, VIN = 2.5V
VIN
2.5V
470nH
10µF
1µF
0201
VIN
200k
EN1
10µF
1µF
0201
SW1
LTC3315A
3.3pF
100k
SW2
261k
EN2
22µF
FB1
470nH
VIN
VOUT1
1.5V, 2A
3.3pF
VOUT2
1.8V, 2A
22µF
FB2
100k
MODE/SYNC
GND
fSW = 2MHz
20
PGOOD
1M
VOUT2
3315A TA02
Rev. B
For more information www.analog.com
LTC3315A
TYPICAL APPLICATIONS
Dual 1.2V and 0.8V 2MHz, 2A Buck Regulators, VIN = 3.3V
680nH
VIN
3.3V
VIN
SW1
140k
10µF
6.8pF
VOUT1
1.2V, 2A
33µF
FB1
EN1
VIN
100k
LTC3315A
560nH
SW2
10µF
60.4k
EN2
10pF
VOUT2
0.8V, 2A
33µF
FB2
100k
MODE/SYNC
PGOOD
1M
GND
VOUT1
3315A TA03
fSW = 2MHz
Dual 3.3V and 2.5V 2MHz, 2A Buck Regulators, VIN = 5V
1.2µH
VIN
5V
VIN
10µF
SW1
1µF
0201
562k
2.7pF
VOUT1
3.3V, 2A
22µF
FB1
EN1
VIN
10µF
100k
LTC3315A
SW2
1µF
0201
1.2µH
402k
EN2
3.3pF
VOUT2
2.5V, 2A
22µF
FB2
100k
MODE/SYNC
PGOOD
1M
GND
fSW = 2MHz
VIN
3315A TA04
Rev. B
For more information www.analog.com
21
LTC3315A
TYPICAL APPLICATIONS
Dual 1.2V and 0.8V 1MHz, 2A Buck Regulators, VIN = 3.3V
1.2µH
VIN
3.3V
VIN
SW1
140k
22µF
6.8pF
VOUT1
1.2V, 2A
47µF
FB1
EN1
VIN
100k
LTC3315A
1.0µH
SW2
22µF
60.4k
EN2
20pF
VOUT2
0.8V, 2A
68µF
FB2
100k
1MHz
MODE/SYNC
PGOOD
1M
GND
VIN
3315A TA05
fSW = 1MHz
Dual 1.2V and 0.8V 3MHz, 2A Buck Regulators, VIN = 3.3V
470nH
VIN
3.3V
VIN
SW1
140k
4.7µF
4.7pF
VOUT1
1.2V, 2A
22µF
FB1
EN1
VIN
100k
LTC3315A
330nH
SW2
4.7µF
60.4k
EN2
6.8pF
VOUT2
0.8V, 2A
22µF
FB2
100k
3MHz
MODE/SYNC
PGOOD
GND
fSW = 3MHz
22
1M
VIN
3315A TA06
Rev. B
For more information www.analog.com
For more information www.analog.com
0.70 ±0.05
2.50 ±0.05
0.25 ±0.05
5
0.70
SUGGESTED PCB LAYOUT
TOP VIEW
2.50 ±0.05
0.70
0.0000
aaa Z
2×
D
PACKAGE TOP VIEW
0.2500
PIN 1
CORNER
0.2500
X
aaa Z
// bbb Z
0.7500
0.2500
0.0000
0.2500
0.7500
PACKAGE
OUTLINE
Y
E
2×
Z
H1
MIN
0.65
0.01
0.30
0.22
DETAIL C
SUBSTRATE
SYMBOL
A
A1
L
b
D
E
D1
E1
e
H1
H2
aaa
bbb
ccc
ddd
eee
fff
DETAIL B
H2
MOLD
CAP
ddd Z
Z
NOM
0.74
0.02
0.40
0.25
2.00
2.00
0.70
0.70
0.50
0.24 REF
0.50 REF
DIMENSIONS
12b
eee M Z X Y
fff M Z
DETAIL C
A1
12×
0.10
0.10
0.10
0.10
0.15
0.08
MAX
0.83
0.03
0.50
0.28
e/2
e
L
SUBSTRATE THK
MOLD CAP HT
NOTES
DETAIL A
DETAIL B
A
(Reference LTC DWG # 05-08-1530 Rev B)
e
7
6
D1
e
0.250
b
12
5
DETAIL A
PACKAGE BOTTOM VIEW
6
11
4
1
PIN 1 NOTCH
0.14 × 45°
4
SEE NOTES
DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER
MAY BE EITHER A MOLD OR MARKED FEATURE
THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII
5
6
LQFN 12 0618 REV B
METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN
SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES
4
3. PRIMARY DATUM -Z- IS SEATING PLANE
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
E1
b 10
ccc M Z X Y
ccc M Z X Y
LQFN Package
12-Lead (2mm × 2mm × 0.74mm)
LTC3315A
PACKAGE DESCRIPTION
Rev. B
23
LTC3315A
PACKAGE DESCRIPTION
WLCSP PACKAGE
CB-16-11
16-BALL (1.64mm × 1.64mm × 0.5mm)
Dimensions shown in millimeters
1.680
1.640 SQ
1.600
4
3
2
1
A
BALL A1
IDENTIFIER
1.20
REF
B
C
0.40
REF
TOP VIEW
(BALL SIDE DOWN)
PKG-006559
SEATING
PLANE
24
END VIEW
BOTTOM VIEW
(BALL SIDE UP)
0.330
0.300
0.270
COPLANARITY
0.05
0.300
0.260
0.220
0.230
0.200
0.170
09-12-2019-B
0.560
0.500
0.440
D
Rev. B
For more information www.analog.com
LTC3315A
REVISION HISTORY
REV
DATE
DESCRIPTION
A
11/19
Added AEC-Q100 Qualified.
B
09/21
Added #W Flow Part Numbers.
Added WLCSP package and references.
Revised NMOS Reverse Current Limit spec.
PAGE NUMBER
1
2
1-24
3
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
25
LTC3315A
TYPICAL APPLICATION
Dual Buck Regulators with Supply Sequencing
VIN
2.25V TO 5.5V
880nH
10µF
1µF
0201
VIN
140k
EN1
10µF
169k
1µF
0201
SW1
LTC3315A
VIN
VOUT1
1.2V, 2A
33µF
FB1
100k
1.0µH
SW2
261k
EN2
100k
6.8pF
4.7pF
VOUT2
1.8V, 2A
22µF
FB2
0.1µF
100k
MODE/SYNC
GND
fSW = 2MHz
PGOOD
1M
VOUT1
3315A TA07
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3307A/B,
LTC3308A/B,
LTC3309A/B
3A, 4A and 6A 5V Synchronous Step-Down
Silent Switcher DC/DC in 2mm × 2mm
LQFN-12
Monolithic Synchronous Step-Down DC/DC Capable of Supplying up to 6A at Switching
Frequencies Up to 3MHz(A) and 10MHz(B). Silent Switcher Architecture for Ultralow EMI
Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with
±1% Accuracy. PGOOD Indication, RT Programming, SYNC Input. 2mm × 2mm LQFN-12
LTC3310/
LTC3310S
5V, 10A Synchronous Step-Down
Silent Switcher/Silent Switcher 2 in
3mm × 3mm LQFN
Switching Frequencies Up to 5MHz. Silent Switcher/Silent Switcher 2 Architecture for
Ultralow EMI Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output
Voltage Range with ±1% Accuracy. PGOOD Indication, RT Programming, SYNC Input.
Configurable for Paralleling Power Stages. 150°C Operation (LTC3310). Pin Compatible
with LTC3311/LTC3311S. 3mm × 3mm LQFN-18 Package.
LTC3370/
LTC3371
4-Channel 8A Configurable 1A Buck DC/DCs
Four Synchronous Buck Regulators with 8 × 1A Power Stages. Can Connect Up to Four
Power Stages in Parallel to Make a High Current Output (4A Maximum) with a Single
Inductor. 8 Output Configurations Possible. Precision PGOOD Indication. LTC3371
Has a Watchdog Timer. LTC3370: 32-Lead 5mm × 5mm QFN. LTC3371: 38-Lead
5mm × 7mm QFN and TSSOP
LTC3374/
LTC3374A
8-Channel Parallelable 1A Buck DC/DCs
Eight 1A Synchronous Buck Regulators. Can Connect Up to Four Power Stages in
Parallel to Make a High Current Output (4A Maximum) with a Single Inductor. 15 Output
Configurations Possible. Precision Enable Inputs and PGOOD_ALL Reporting. 38-Lead
5mm × 7mm QFN and TSSOP
LTC3375
8-Channel Parallelable 1A Buck DC/DCs
Eight 1A Synchronous Buck Regulators. Can Connect Up to Four Power Stages in
Parallel to Make a High Current Output (4A Maximum) with a Single Inductor. 15 Output
Configurations Possible. Precision Enable Inputs and PGOOD_ALL Reporting. I2C
Programming with a Watchdog Timer and Pushbutton. 48-Lead 7mm × 7mm QFN
LT8614
42V, 4A Synchronous Step-Down Silent
Switcher® with 2.5μA Quiescent Current
Synchronous Micropower Step-Down DC/DC Converter with Silent Switcher
Architecture. Up to 96% Efficiency at 1MHz, 12VIN to 5VOUT. Up to 94% Efficiency
at 2MHz, 12VIN to 5VOUT. VIN: 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 2.5μA, ISD
