LTC3409A
600mA Low VIN Buck
Regulator in 3mm × 3mm DFN
FEATURES
DESCRIPTION
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The LTC®3409A is a high efficiency, monolithic synchronous
buck regulator using a constant frequency, current mode
architecture. The LTC3409A improves upon the LTC3409’s
light load regulation in Burst Mode operation. The output
voltage is adjusted via an external resistor divider.
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1.6V to 5.5V Input Voltage Range
0.62V to 5.5V Output Voltage Range
Internal Soft-Start
Selectable 1.7MHz or 2.6MHz Constant Frequency
Operation
Internal Oscillator Can Be Synchronized to an
External Clock, 1MHz to 3MHz Range
High Efficiency: Up to 95%
65μA Quiescent Current, Burst Mode® Operation
600mA Output Current (VIN = 1.8V, VOUT = 1.2V)
750mA Peak Inductor Current
No Schottky Diode Required
Low Dropout Operation: 100% Duty Cycle
0.612V Reference Voltage
Stable with Ceramic Capacitors
Shutdown Mode Draws 1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately
(25 • CLOAD). Thus, a 10μF capacitor charging to 3.3V
would require a 250μs rise time, limiting the charging
current to about 130mA.
4. The SW trace should be kept as small as possible. Keep
sensitive components away from the SW pins. The input
capacitor CIN and the resistors R1 and R2 should be
routed away from the SW traces and the inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point. They should not share the high current path of
CIN or COUT.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to VIN or GND (preferably).
VIN
CIN
VIN
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3409A. These items are also illustrated graphically
in the layout diagram of Figure 3. Check the following in
your layout.
1. Does the capacitor CIN connect to the power VIN
(Pins 3, 4) and GND (Exposed Pad) as close as possible? This capacitor provides the AC current to the
internal power MOSFETs and their drivers.
VIN
LTC3409A
RUN
SYNC
VFB
MODE
L1
VOUT
SW
SGND GND
C1
COUT
R2
R1
3409A F03
Figure 3
3409af
13
LTC3409A
APPLICATIONS INFORMATION
Design Example
As a design example, assume the LTC3409A is used in a
2-alkaline cell battery-powered application. The VIN will be
operating from a maximum of 3.2V down to about 1.8V.
The load current requirement is a maximum of 600mA
but most of the time it will be in standby mode, requiring
only 2mA. Efficiency at both low and high load currents is
important, so the minimum frequency setting of 1.7MHz
is chosen. Output voltage is 1.5V. With this information
we can calculate L using Equation 3:
⎛ V ⎞
1
L=
VOUT ⎜ 1– OUT ⎟
f • ΔIL
VIN ⎠
⎝
For best efficiency choose a 750mA or greater inductor
with less than 0.3Ω series resistance. CIN will require
an RMS current rating of at least 0.3A ≅ ILOAD(MAX) /2 at
temperature.
For the feedback resistors, choose R2 = 137k. R1 is then
calculated to be 200k from Equation 2. Figure 4 shows the
complete circuit along with its efficiency curve.
Table 2 below gives 1% resistor values for selected output
voltages.
(3)
Substituting VOUT = 1.5V, VIN = 3.2V, ΔIL = 240mA and
f = 1.7MHz in Equation 2 gives:
L=
VOUT
R1
R2
0.85V
53.6k
137k
1.2V
137k
143k
1.5V
200k
137k
1.8V
267k
137k
1
⎛ 1.5V ⎞
1.5V ⎜ 1–
≅ 2.2µH
⎝ 3.2V ⎟⎠
1.7MHz • 240mA
Burst Mode Efficiency, 1.5VOUT
100
CIN
4.7μF
R2
137k
90
LTC3409A
VFB
SYNC
GND
RUN
VIN
SW
VIN
R1
200k
1.8VIN
3.2VIN
80
L1
2.2μH
COUT
22μF
s2
MODE
3409A F04
VOUT
1.5V
0.6A
EFFICIENCY (%)
VIN
1.8V TO 3.2V
70
60
2.5VIN
50
40
30
20
L1: SUMIDA CDRH2D18/LD
10
0
0.1
C1
10pF
1
10
100
LOAD CURRENT (mA)
1000
3409A F04b
Figure 4
3409af
14
LTC3409A
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 ±0.05
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
R = 0.115
TYP
5
0.38 ± 0.10
8
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD) DFN 1203
0.200 REF
0.75 ±0.05
0.00 – 0.05
4
0.25 ± 0.05
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
3409af
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3409A
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