LTC3410ESC6#TRMPBF

LTC3410 2.25MHz, 300mA Synchronous Step-Down Regulator in SC70 U FEATURES DESCRIPTIO ■ The LTC ®3410 is a high efficiency monolithic synchronous buck regulator using a constant frequency, current mode architecture. The device is available in adjustable and fixed output voltage versions. Supply current during operation is only 26µA, dropping to 2.5V 10µH or 2x 4.7µF 4.7µF If tantalum capacitors are used, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Output Voltage Programming (LTC3410 Only) Using Ceramic Input and Output Capacitors The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3410’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. The output voltage is set by a resistive divider according to the following formula: ⎛ R2⎞ VOUT = 0.8V ⎜ 1+ ⎟ ( 2) ⎝ R1⎠ The external resistive divider is connected to the output, allowing remote voltage sensing as shown in Figure 2. Efficiency Considerations Efficiency = 100% – (L1 + L2 + L3 + ...) 0.8V ≤ VOUT ≤ 5.5V R2 However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires VFB LTC3410 R1 GND 3410 F02 Figure 2. Setting the LTC3410 Output Voltage 3410fb 9 LTC3410 U W U U APPLICATIO S I FOR ATIO where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3410 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 3. 1. The VIN quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Charateristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations In most applications the LTC3410 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3410 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If 1 VIN = 3.6V POWER LOSS (W) 0.1 0.01 0.001 0.0001 0.00001 0.1 VOUT = 3.3V VOUT = 1.8V VOUT = 1.2V 10 100 1 LOAD CURRENT (mA) 1000 3410 F03 Figure 3. Power Loss vs Load Current 3410fb 10 LTC3410 U W U U APPLICATIO S I FOR ATIO the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3410 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = (PD)(θJA) where PD is the power dissipated by the regulator and θJAis the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: T J = TA + TR where TA is the ambient temperature. As an example, consider the LTC3410 in dropout at an input voltage of 2.7V, a load current of 300mA and an ambient temperature of 70°C. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 70°C is approximately 1.0Ω. Therefore, power dissipated by the part is: PD = ILOAD2 • RDS(ON) = 90mW For the SC70 package, the θJA is 250°C/ W. Thus, the junction temperature of the regulator is: TJ = 70°C + (0.09)(250) = 92.5°C which is well below the maximum junction temperature of 125°C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD • ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steadystate value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a 250µs rise time, limiting the charging current to about 130mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3410. These items are also illustrated graphically in Figures 4 and 5. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 3410fb 11 LTC3410 U W U U APPLICATIO S I FOR ATIO 1 1 RUN 2 – VFB GND + 2 6 COUT VOUT L1 VIN SW 5 6 COUT VOUT R1 4 VOUT GND – R2 3 RUN LTC3410-1.875 LTC3410 3 + L1 CFWD SW VIN 5 CIN 4 CIN VIN VIN 3410 F04b 3410 F04a BOLD LINES INDICATE HIGH CURRENT PATHS BOLD LINES INDICATE HIGH CURRENT PATHS Figure 4a. LTC3410 Layout Diagram Figure 4b. LTC3410-1.875 Layout Diagram VIA TO GND R1 VOUT VOUT VIN VIA TO VIN VIA TO VOUT R2 PIN 1 L1 PIN 1 L1 CFWD LTC3410 VIN VIA TO VIN LTC34101.875 SW SW COUT COUT CIN CIN GND 3410 F05b 3410 F05a Figure 5b. LTC3410 Fixed Output Voltage Suggested Layout Figure 5a. LTC3410 Suggested Layout 2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1/R2 must be connected between the (+) plate of COUT and ground. 3. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 4. Keep the (–) plates of CIN and COUT as close as possible. 5. Keep the switching node, SW, away from the sensitive VFB node. Design Example As a design example, assume the LTC3410 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 0.3A but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 3V. With this information we can calculate L using Equation (1), L= ⎛ V ⎞ 1 VOUT ⎜ 1− OUT ⎟ ( f)(∆IL ) ⎝ VIN ⎠ (3) 3410fb 12 LTC3410 U W U U APPLICATIO S I FOR ATIO Substituting VOUT = 3V, VIN = 4.2V, ∆IL = 100mA and f = 2.25MHz in Equation (3) gives: L= of less than 0.5Ω. In most cases, a ceramic capacitor will satisfy this requirement. From Table 2, Capacitance Selection, COUT = 10µF and CIN = 4.7µF. 3V 3V ⎞ ⎛ ⎜ 1− ⎟ = 3.8µH 2.25MHz(100mA) ⎝ 4.2V ⎠ For the feedback resistors, choose R1 = 301k. R2 can then be calculated from equation (2) to be: A 4.7µH inductor works well for this application. For best efficiency choose a 350mA or greater inductor with less than 0.3Ω series resistance. ⎛V ⎞ R2 = ⎜ OUT − 1⎟ R1= 827.8k ; use 825k ⎝ 0.8 ⎠ Figure 6 shows the complete circuit along with its efficiency curve. CIN will require an RMS current rating of at least 0.125A ≅ ILOAD(MAX)/2 at temperature and COUT will require an ESR VIN 2.7V TO 4.2V 4 CIN†† 4.7µF CER VIN SW 3 VOUT 3V 10pF LTC3410 1 4.7µH* COUT† 10µF CER RUN VFB 6 825k GND 2, 5 301k 3410 F06a † TAIYO YUDEN JMK212BJ106 TAIYO YUDEN JMK212BJ475 *MURATA LQH32CN4R7M23 †† Figure 6a 100 90 VOUT 100mV/DIV AC COUPLED EFFICIENCY (%) 80 70 60 50 IL 200mA/DIV 40 30 20 VIN = 3.6V VIN = 4.2V 10 0 0.1 1 10 ILOAD (mA) 100 1000 3410 F06b Figure 6b ILOAD 200mA/DIV 20µs/DIV VIN = 3.6V VOUT = 3V ILOAD = 100mA TO 300mA 3410 F06c Figure 6c 3410fb 13 LTC3410 U TYPICAL APPLICATIO S Using Low Profile Components,