LTC3421
3A, 3MHz Micropower Synchronous
Boost Converter with Output Disconnect
FEATURES
DESCRIPTION
Synchronous Rectification: Up to 96% Efficiency
nn True Output Disconnect
nn Inrush Current Limiting
nn Very Low Quiescent Current: 12µA
nn Up to 1.5A Continuous Output Current
nn Fixed Frequency Operation Up to 3MHz
nn 0.5V to 4.5V Input Range
nn 2.4V to 5.25V Adjustable Output Voltage
nn Guaranteed 1V Start-Up
nn Programmable Current Limit
nn Programmable Soft-Start
nn Synchronizable Oscillator
nn Manual or Automatic Burst Mode® Operation
nn Low-Battery Comparator
nn 1.4V
MIN
0.1
0.2
1
2
µA
µA
Quiescent Current—Active
(Note 3)
0.6
1.1
mA
NMOS Switch Leakage
0.1
5
µA
PMOS Switch Leakage
0.1
10
µA
NMOS Switch On Resistance
0.1
Ω
0.14
Ω
A
A
PMOS Switch On Resistance
l
l
NMOS Current Limit
1
3
1.5
4.2
Max Duty Cycle
l
84
91
Min Duty Cycle
l
Frequency Accuracy
l
0.85
SYNC Input High
l
2.2
SYNC Input Low
l
SYNC Input Current
l
ENB Input High
l
ENB Input Low
l
ENB Input Current
l
SHDN Input High
ILIM Resistor = 105k
ILIM Resistor = 36.5k
VOUT = 0V (Initial Start-Up), ENB = 0V
VOUT > 2.4V, ENB = 0V
1.15
l
REF Output Voltage
l
REF Output Current Range
0.01
V
1
µA
1.2
1.183
V
0.4
V
1
µA
V
V
0.25
V
0.01
1
µA
1.22
1.257
V
8
µA
–100
Error Amp Transconductance
45
Falling Edge
l
LBI Input Current
0.58
l
MHz
0.8
1.00
0.65
SHDN Input Current
%
V
SHDN Input Low
LBI Threshold
%
0
1
UNITS
µs
0.6
0.62
V
0.01
1
µA
12.0
0.25
50
0.5
mV
V
LBO Low Voltage
VIN = 0V, ISINK = 1mA
VIN = 0V, ISINK = 20mA
LBO Leakage
VLBO = 5.5V
0.01
1
µA
SS Current Source
VSS = 1V
1.2
2.4
5
µA
BURST Threshold Voltage
Falling Edge
0.87
0.97
1.07
V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3421E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the 4 0°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: Current is measured into the VOUTS pin since the supply current is
bootstrapped to the output. The current will reflect to the input supply by
(VOUT/VIN) • Efficiency. The outputs are not switching.
4
Note 4: Once VOUT is greater than 2.4V, the IC is not dependent on the VIN
supply.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 85°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Rev. A
For more information www.analog.com
LTC3421
TYPICAL PERFORMANCE CHARACTERISTICS
Single Cell to 3.3V Efficiency
80
70
VIN = 3V
80
VIN = 1.2V
VIN = 1V
60
50
40
30
20
Li-Ion to 5V Efficiency
100
Burst Mode OPERATION
90
EFFICIENCY (%)
EFFICIENCY (%)
VIN = 1.5V
Burst Mode OPERATION
90
2-Cell to 3.3V Efficiency
100
90
VIN = 2.4V
VIN = 2V
70
60
50
40
30
20
VOUT = 3.3V
fOSC = 1MHz
10
0
0.1
0
0.1
1000
70
60
50
40
30
VOUT = 5V
fOSC = 1MHz
0
1
0.1
10
100
OUTPUT CURRENT (mA)
10
1
10
100
OUTPUT CURRENT (mA)
3421 G01
1000
3421 G02
Burst Mode Operation
1000
3421 G03
Load Transient Response
VOUT
50mV/DIV
AC COUPLED
VIN = 4.2V
VIN = 3.6V
VIN = 2.7V
20
VOUT = 3.3V
fOSC = 1MHz
10
1
10
100
OUTPUT CURRENT (mA)
Burst Mode
OPERATION
80
EFFICIENCY (%)
100
TA = 25°C, unless otherwise noted.
Inrush Current Control
VOUT
100mV/DIV
AC COUPLED
VOUT
1V/DIV
SW
600mA
INDUCTOR
CURRENT
0.5A/DIV
50mA
2.5µs/DIV
VIN = 2.4V
VOUT = 3.3V
COUT = 44µF
3421 G04
Efficiency vs Frequency
100
100
f = 300kHz
90
VIN = 0V TO 2.4V 500µs/DIV
COUT = 44µF
3421 G05
1.20
VOUT = 3.3V
IOUT = 200mA
1.15
f = 3MHz
60
f = 1MHz
50
40
30
20
70
START VOLTAGE (V)
70
60
50
VIN > VOUT
PMOS LDO MODE
40
30
VIN = 2.4V
VOUT = 3.3V
1
10
100
OUTPUT CURRENT (mA)
1000
1.05
1.00
0.95
0.85
10
0
1.10
0.90
20
10
3421 G06
Start-Up Voltage vs Output
Current
80
EFFICIENCY (%)
EFFICIENCY (%)
2.5ms/DIV
Efficiency vs VIN
90
80
0
INDUCTOR
CURRENT
0.5A/DIV
IOUT
1
1.5
2
2.5 3
3.5 4
INPUT VOLTAGE (V)
4.5
3421 G07
5
3421 G08
0.80
0
100
50
150
OUTPUT CURRENT (mA)
200
3421 G09
Rev. A
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5
LTC3421
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Threshold vs RBURST
TA = 25°C, unless otherwise noted.
FB Voltage
180
Frequency Accuracy
1.24
1.03
1.23
1.01
120
100
80
60
OUT OF BURST
40
20
0
70
RBURST (kΩ)
1.22
1.21
INTO BURST
20
FREQUENCY (MHz)
140
VOLTAGE (V)
OUTPUT CURRENT (mA)
160
0.97
1.20
–45 –30 –15
120
0 15 30 45 60
TEMPERATURE (°C)
75
Burst Mode Quiescent Current
1.65
0.20
RLIM = 105k
0.16
1.55
0.14
1.50
1.45
1.40
1.35
5
75
90
90
RDS(ON)
0.12
0.06
0.04
0.02
75
90
3421 G14
3421 G13
NMOS
0.08
1.25
0 15 30 45 60
TEMPERATURE (°C)
PMOS
0.10
1.30
1.20
–45 –30 –15
75
0.18
1.60
RESISTANCE (Ω)
CURRENT (A)
CURRENT (µA)
15
10
0 15 30 45 60
TEMPERATURE (°C)
3421 G12
Current Limit Accuracy
1.70
20
0 15 30 45 60
TEMPERATURE (°C)
0.95
–45 –30 –15
90
3421 G11
3421 G10
0
–45 –30 –15
0.99
0
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
3421 G15
PIN FUNCTIONS
FB (Pin 1): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 2.4V to
5.25V. The feedback reference voltage is typically 1.220V.
SHDN (Pin 2): Shutdown Pin. Less than 0.25V on this
pin shuts down the IC. The IC is enabled when the SHDN
voltage is greater than 1V. Once VOUT is above 2.2V,
hysteresis is applied to the pin (–500nA out of the pin)
allowing it to operate at a logic high while the battery can
drop to 0.5V.
ENB (Pin 4): Reference Output (VREF) Enable. When the
converter is enabled (SHDN = High), forcing ENB = High
enables the VREF output, while forcing ENB = Low disables
the VREF output and lowers the quiescent current by 5µA.
The low-battery comparator is always active when the
converter is enabled. In shutdown, both the VREF output and low-battery comparator are disabled unless both
VOUT ≥ 2.5V and ENB = High. Under these conditions, both
the VREF output and low-battery comparator are enabled.
VREF (Pin 3): Buffered 1.22V Reference Output. This pin
can source up to 100µA and sink up to 8µA. This pin must
be decoupled with a 0.1µF capacitor for stability.
6
Rev. A
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LTC3421
PIN FUNCTIONS
RT (Pin 5): Connect a resistor to ground to program the
oscillator frequency according to the formula:
fOSC =
28,1 00
RT
where fOSC is in kHz and RT is in kΩ.
SS (Pin 6): Soft-Start Pin. Connect a capacitor from this
pin to ground to set the soft-start time according to the
formula:
t(ms) = CSS(µF) • 320
The nominal soft-start charging current is 2.5µA. The
active range of SS is from 0.8V to 1.6V.
SYNC (Pin 7): Oscillator Synchronization Pin. A clock
pulse width of 100ns to 2µs is required to synchronize the
internal oscillator. If not used SYNC should be grounded.
ILIM (Pin 8): Current Limit Adjust Pin. Connect a resistor from this pin to ground to set the peak current limit
threshold for the N-channel MOSFET according to the
formula (note that this is the peak current in the inductor):
ILIM =
15 0
R
where I is in amps and R is in kΩ.
BURST (Pin 9): Burst Mode Threshold Adjust Pin. A resistor/capacitor combination from this pin to ground programs the average load current at which automatic Burst
Mode operation is entered, according to the formula:
R BURST =
2
IBURST
where RBURST is in kΩ and IBURST is in amps.
CBURST ≥
C OUT • VOUT
10,000
where CBURST(MIN) and COUT are in µF.
For manual control of Burst Mode operation, ground the
BURST pin to force Burst Mode operation or connect it to
VOUT to force fixed frequency PWM mode. Note that the
BURST pin must not be pulled higher than VOUT.
GND, Exposed Pad (Pins 10 and 25): Signal Ground Pin.
Connect to ground plane near the RT resistor, error amp
compensation components and feedback divider. The
exposed pad must be soldered to the PCB and is typically connected through the power GND plane.
PGND (Pins 11 to 13): Source Terminal of Power Internal
N-Channel MOSFET.
SW (Pins 14 to 16): Switch Pin for Inductor Connection.
For applications where VOUT > 4.3V, a Schottky diode from
SW to VOUT or to a snubber circuit is required to maintain
absolute maximum rating for SW. (see Application Circuits
for 5V).
VOUT (Pins 17, 19 and 20): The output of the synchronous rectifier and bootstrapped power source for the IC.
A ceramic bypass capacitor is required to be very close
to the VOUT and PGND pins of the IC.
VOUTS (Pin 18): VOUT Sense Pin. Connect VOUTS directly to
an output filter capacitor. The top of the feedback divider
network should also be tied to this point.
VIN (Pin 21): Input Supply Pin. Connect this pin to the
input supply and decouple with at least a 4.7µF ceramic
capacitor.
LBO (Pin 22): Open-Drain Output. This pin pulls low when
the LBI input is below 0.6V. The open-drain output can
sink up to 20mA. During Burst Mode operation LBO is
only active during the time the IC wakes up to service
the output.
LBI (Pin 23): Low-Battery Comparator Input. Typical
threshold voltage is 0.6V with 30mV hysteresis. This
function is always enabled in non-back-fed applications.
To enable this comparator when VOUT is back-fed, the ENB
pin must be high. The low-battery comparator will operate
off VIN or VOUT, whichever is greater.
VC (Pin 24): Error Amp Output. A frequency compensation network is connected from this pin to ground to compensate the loop. See the section Closing the Feedback
Loop for guidelines.
Exposed Pad (Pin 25): Ground. This pin must be soldered
to the PCB and is typically connected through the power
GND plane.
Rev. A
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7
LTC3421
BLOCK DIAGRAM
+
1V TO 4.5V
21
14
SW
VIN
15
SW
16
18
VIN
SW
ANTIRING
VIN
WELL
SWITCH
PMOS
VDD
VOUTS
VOUT
VOUT
VOUT
ANTICROSS
CONDUCTION
NMOS
–
IZERO
AMP
VOUT
2.40V TO 5.25V
17
19
20
+
ISENSE
AMP
R1
+
CURRENT
LIMIT
3
VREF
+
+
PWM
LOGIC
SLEEP
THERMAL
REG/SHDN
5
RT
6
RC1
CSS
1.22V
ERROR
AMP
CURRENT
COMP
1.22V REF
2%
FB
–
1
R2
Σ
+
Burst Mode
CONTROL
OFF
VC
1%
+
UV
OSC
24
I/3000
BURST
COMP
–
4
8
+
VOUT
SS
SHUTDOWN
ENB
–
2
SHDN
ILIM
ILIMIT =
150k/RC1
–
–
CP
RZ
BURST
9
0.97V/1.05V
SLOPE COMP
+
SYNC
IN
7
SYNC
OV
VIN
R1
23
R2
8
–3%
LBI
0.6V/
0.63V
+
–
VOUT
3%
–
LBO
+
ENB
GND
EXPOSED
PAD
PGND
PGND
PGND
10
25
11
12
13
22
3421 BD
Rev. A
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LTC3421
OPERATION
LOW VOLTAGE START-UP
Oscillator
The LTC3421 includes an independent start-up oscillator
designed to start-up at input voltages of 0.85V typical.
The frequency and peak current limit during start-up are
internally controlled. The device can start-up under some
load (see graph of Start-Up Current vs Input Voltage).
Soft-start and inrush current limiting are provided during start-up as well as normal mode. The same soft-start
capacitor is used for each operating mode.
The frequency of operation is set through a resistor
from the RT pin to ground. An internally trimmed timing capacitor resides inside the IC. The oscillator can be
synchronized with an external clock applied to the SYNC
pin. When synchronizing the oscillator, the free running
frequency must be set to an approximately 30% lower
frequency than the desired synchronized frequency.
When either VIN or VOUT exceeds 2.25V, the IC enters normal operating mode. Once the output voltage exceeds the
input by 0.3V, the IC powers itself from VOUT instead of
VIN. At this point the internal circuitry has no dependency
on the VIN input voltage, eliminating the requirement for
a large input capacitor. The input voltage can drop as low
as 0.5V without affecting circuit operation. The limiting
factor for the application becomes the availability of the
power source to supply sufficient energy to the output at
the low voltages and the maximum duty cycle, which is
clamped at 91% typical.
LOW NOISE FIXED FREQUENCY OPERATION
Shutdown
The part is shut down by pulling SHDN below 0.25V, and
activated by pulling the pin initially above 1V and maintaining a high state down to 0.5V. Note that the SHDN pin
can be driven above VIN or VOUT as long as it is limited to
less than the absolute maximum rating.
Soft-Start
The soft-start time is programmed with an external capacitor to ground on the SS pin. An internal current source
charges it with a nominal 2.5µA. The voltage on the SS pin
(in conjunction with the external resistor on the ILIM pin)
is used to control the peak current limit until the voltage
on the capacitor exceeds 1.6V, at which point the external
resistor sets the peak current. In the event of a commanded shutdown or a thermal shutdown, the capacitor is
discharged automatically. Note that Burst Mode operation
is inhibited during the soft-start time.
t(ms) = CSS(µF) • 320
Current Sensing
Lossless current sensing converts the peak current signal
to a voltage to sum in with the internal slope compensation. This summed signal is compared to the error amplifier output to provide a peak current control command for
the PWM. The slope compensation in the IC is adaptive to
the input voltage and output voltage. Therefore, the converter provides the proper amount of slope compensation
to ensure stability, but not an excess to cause a loss of
phase margin in the converter.
Error Amplifier
The error amplifier is a transconductance amplifier, with
its positive input internally connected to the 1.22V reference and its negative input connected to FB. A simple
compensation network is placed from COMP to ground.
Internal clamps limit the minimum and maximum error
amplifier output voltage for improved large-signal transient response. During sleep (in Burst Mode operation),
the compensation pin is high impedance; however, clamps
limit the voltage on the external compensation network,
preventing the compensation capacitor from discharging
to zero during the sleep time.
Current Limit
The programmable current limit circuit sets the maximum peak current. This clamp level is programmed with
a resistor from ILIM to ground. In Burst Mode operation,
the current limit is automatically set to a nominal value
of 0.6A peak for optimal efficiency.
ILIM =
150
R
where I is in amps and R is in kΩ.
Rev. A
For more information www.analog.com
9
LTC3421
OPERATION
Zero Current Amplifier
The zero current amplifier monitors the inductor current
to the output and shuts off the synchronous rectifier once
the current is below 50mA typical, preventing negative
inductor current.
Antiringing Control
The antiringing control places a resistor across the inductor to damp the ringing on the SW pin in discontinuous conduction mode. The LCSW ringing (L = inductor,
CSW = capacitance on SW pin) is low energy, but can
cause EMI radiation.
VREF
The internal 1.22V reference is buffered and brought
out to VREF. It is active when the ENB pin is pulled high
(above 1.2V). For stability, a minimum of a 0.1µF capacitor must be placed on the pin. The output can source up
to 100µA and sink up to 8µA. For the lowest possible
quiescent current in Burst Mode operation, the reference
output should be disabled by grounding the ENB pin.
by increasing the output capacitance. Another method
of reducing Burst Mode ripple is to place a small feedforward capacitor across the upper resistor in the VOUT
feedback divider network.
During Burst Mode operation, the VC pin is disconnected
from the error amplifier in an effort to hold the voltage on
the external compensation network where it was before
entering Burst Mode operation. To minimize the effects of
leakage current and stray resistance, voltage clamps limit
the min and max voltage on VC during Burst Mode operation. This minimizes the transient experienced when a
heavy load is suddenly applied to the converter after being
in Burst Mode operation for an extended period of time.
For automatic operation, an RC network should be connected from BURST to ground. The value of the resistor
will control the average load current (IBURST) at which
Burst Mode operation will be entered and exited (there
is hysteresis to prevent oscillation between modes). The
equation given for the capacitor on BURST is for the minimum value to prevent ripple on BURST from causing the
part to oscillate in and out of Burst Mode operation at the
current where the mode transition occurs.
Burst Mode OPERATION
Burst Mode operation can be automatic or user controlled. In automatic operation, the IC will automatically
enter Burst Mode operation at light load and return to
fixed frequency PWM mode for heavier loads. The user
can program the average load current at which the mode
transition occurs using a single resistor.
The oscillator is shut down in this mode, since the on time
is determined by the time it takes the inductor current to
reach a fixed peak current and the off time is determined
by the time it takes for the inductor current to return to
zero.
In Burst Mode operation, the IC delivers energy to the
output until it is regulated and then goes into a sleep mode
where the outputs are off and the IC is consuming only
12µA of quiescent current. In this mode, the output ripple
has a variable frequency component with load current and
will be typically 2% peak-peak. This maximizes efficiency
at very light loads by minimizing switching and quiescent losses. Burst Mode ripple can be reduced slightly
10
R BURST =
2
IBURST
where RBURST is in kΩ and IBURST is in amps.
CBURST ≥
C OUT • VOUT
10,000
where CBURST(MIN) and COUT are in µF.
In the event that a sudden load transient causes FB to
deviate by more than 4% from the regulation value, an
internal pull-up is applied to BURST, forcing the part
quickly out of Burst Mode operation. For optimum transient response when going between Burst Mode operation and PWM mode, the mode should be controlled
manually by the host. This way PWM mode can be commanded before the load step occurs, minimizing output
voltage droop. For manual control of Burst Mode operation, the RC network can be eliminated. To force fixed
frequency PWM mode, BURST should be connected to
VOUT. To force Burst Mode operation, BURST should be
Rev. A
For more information www.analog.com
LTC3421
OPERATION
Simplified Diagram of Automatic Burst Mode Control Circuit
VCC
1mA
–
VREF
–4%
IOUT/3000
UV
+
SSDONE
SSDONE
–
FB 1
MODE
1 = Burst Mode
OPERATION
0 = PWM MODE
+
0.9V/
1.1V
9 BURST
RB
CB
–
VREF
±1%
ERROR AMP/
SLEEP COMP
TO
MODULATOR
+
SLEEP
3421 TA03
CLAMP
0.5V TO 1V
24 VC
RCOMP
CCOMP
grounded. The circuit connected to BURST should be
able to sink or source up to 2mA. Note that Burst Mode
operation is inhibited during start-up and soft-start.
Note that if VIN is above VOUT – 0.3V, the part will exit
Burst Mode operation and the synchronous rectifier will
be disabled.
Note that if the load applied during forced Burst Mode
operation exceeds the current that can be supplied, the
output voltage will start to droop and the part will automatically come out of Burst Mode operation and enter
fixed frequency mode, raising VOUT. The maximum current that can be supplied in Burst Mode operation is given
by:
IO(M AX ) =
2•
0.55
in amps
1+ ( VOUT – VIN )
VIN
OUTPUT DISCONNECT AND INRUSH LIMITING
The LTC3421 is designed to allow true output disconnect by eliminating body diode conduction of the internal
P‑channel MOSFET rectifier. This allows VOUT to go to
zero volts during shutdown without drawing any current
from the input source. It also allows for inrush current
limiting at turn-on, minimizing surge currents seen by the
input supply. Note that to obtain the advantages of output
Rev. A
For more information www.analog.com
11
LTC3421
OPERATION
disconnect, there must not be any external Schottky
diodes connected between the SW pins and VOUT.
Note: Board layout is extremely critical to minimize voltage overshoot on the SW pins due to stray inductance.
Keep the output filter capacitors as close as possible to
the VOUT pins and use very low ESR/ESL ceramic capacitors, tied to a good ground plane. In VOUT > 4.3V applications, a Schottky diode is required from the switch nodes
to VOUT to limit the peak switch voltage to less than 6V
unless some form of external snubbing is employed. (See
5V Applications section.)
APPLICATIONS INFORMATION
COMPONENT SELECTION
where
f = Operating Frequency in MHz
1 FB
24
VC
23
LBI
22
LBO
21
VIN
20
19
VOUT VOUT
VOUTS 18
2 SHDN
VIN
VOUT
The inductor current ripple is typically set to 20% to 40%
of the maximum inductor current.
VOUT 17
3 VREF
SW 16
4 ENB
SW 15
5 RT
SW 14
PGND 13
6 SS
SYNC ILIM BURST GND PGND PGND
7
8
9
10
11
GND
12
MULTIPLE VIAS
TO GROUND
PLANE
3421 F01
Figure 1. Recommended Component Placement. Traces Carrying
High Current are Direct (PGND, SW, VOUT). Trace Area at FB and
VC are Kept Low. Lead Length to Battery Should be Kept Short.
VIN and VOUT Ceramic Capacitors Should be as Close to the IC
Pins as Possible
The high frequency operation of the LTC3421 allows the
use of small surface mount inductors. The minimum
inductance value is proportional to the operating frequency and is limited by the following constraints:
3
f
12
and L >
For high efficiency, choose an inductor with high frequency core material, such as ferrite, to reduce core
loses. The inductor should have low ESR (equivalent
series resistance) to reduce the I2R losses and must be
able to handle the peak inductor current without saturating. Molded chokes or chip inductors usually do not have
enough core to support peak inductor currents in the 1A
to 4A region. To minimize radiated noise, use a toroidal
or shielded inductor. See Table 1 for suggested inductor
suppliers and Table 2 for a list of capacitor suppliers.
Table 1. Inductor Vendor Information
SUPPLIER PHONE
Coilcraft
Inductor Selection
L>
Ripple = Allowable Inductor Current Ripple (Amps
Peak-Peak)
VIN(MIN) = Minimum Input Voltage
VOUT(MAX) = Maximum Output Voltage
WEB SITE
(847) 639-6400 (847) 639-1469 www.coilcraft.com
Coiltronics (561) 241-7876 (516) 241-9339
Murata
USA:
USA:
www.murata.com
(814) 237-1431 (814) 238-0490
(800) 831-9172
Sumida
USA:
(847) 956-0666
Japan:
81-3-3607-5111
TDK
(847) 803-6100 (847) 803-6296 www.component.tdk.com
TOKO
(847) 297-0070 (847) 669-7864 www.toko.com
VIN(M IN ) • ( VOUT (M AX ) – VIN(M IN ) )
f • Ripple • VOUT (M AX )
FAX
USA:
www.sumida.com
(847) 956-0702
Japan
81-3-3607-5144
Rev. A
For more information www.analog.com
LTC3421
APPLICATIONS INFORMATION
Output Capacitor Selection
Operating Frequency Selection
The output voltage ripple has two components to it. The
bulk value of the capacitor is set to reduce the ripple due
to charge into the capacitor each cycle. The maximum
ripple due to charge is given by:
There are several considerations in selecting the operating frequency of the converter. The first is, which are the
sensitive frequency bands that cannot tolerate any spectral noise? The second consideration is the physical size
of the converter. As the operating frequency goes up, the
inductor and filter capacitors go down in value and size.
The trade off is in efficiency since the switching losses due
to gate charge are going up proportional with frequency.
VRBULK =
IP • VIN
C OUT • VOUT • f
where IP = peak inductor current.
The ESR (equivalent series resistance) is usually the most
dominant factor for ripple in most power converters. The
ripple due to capacitor ESR is simply given by:
VRCESR = IP • CESR
where CESR = capacitor series resistance.
Low ESR capacitors should be used to minimize output
voltage ripple. For surface mount applications, AVX TPS
series tantalum capacitors, Sanyo POSCAP or Taiyo Yuden
ceramic capacitors are recommended. For through-hole
applications, Sanyo OS-CON capacitors offer low ESR in
a small package size.
In some layouts it may be necessary to place a 1µF low
ESR ceramic capacitor as close to the VOUT and GND pins
as possible.
Input Capacitor Selection
The input filter capacitor reduces peak currents drawn
from the input source and reduces input switching noise.
Since the IC can operate at voltages below 0.5V once the
output is regulated, the demand on the input capacitor is
much less. In most applications 1µF per amp of peak input
current is recommended. Taiyo Yuden offers very low ESR
ceramic capacitors, for example the 1µF in a 0603 case
(JMK107BJ105MA).
Table 2. Capacitor Vendor Information
SUPPLIER
PHONE
AVX
(803) 448-9411 (803) 448-1943 www.avxcorp.com
FAX
WEB SITE
Sanyo
(619) 661-6322 (619) 661-1055 www.sanyovideo.com
TDK
(847) 803-6100 (847) 803-6296 www.component.tdk.com
Murata
USA:
USA:
www.murata.com
(814) 237-1431 (814) 238-0490
(800) 831-9172
Taiyo Yuden (408) 573-4150 (408) 573-4159 www.t-yuden.com
Another operating frequency consideration is whether the
application can allow “pulse skipping.” In this mode, the
minimum on time of the converter cannot support the
duty cycle, so the converter ripple will go up and there
will be a low frequency component of the output ripple. In
many applications where physical size is the main criterion, running the converter in this mode is acceptable. In
applications where it is preferred not to enter this mode,
the maximum operating frequency is given by:
fM AX _ NOSKIP =
VOUT – VIN
VOUT • t ON(M IN )
Hz
where tON(MIN) = minimum on time = 120ns.
Thermal Considerations
To deliver the power that the LTC3421 is capable of, it is
imperative that a good thermal path be provided to dissipate the heat generated within the package. This can
be accomplished by taking advantage of the large thermal pad on the underside of the IC. It is recommended
that multiple vias in the printed circuit board be used to
conduct heat away from the IC and into a copper plane
with as much area as possible. In the event that the junction temperature gets too high, the peak current limit will
automatically be decreased. If the junction temperature
continues to rise, the part will go into thermal shutdown,
and all switching will stop until the temperature drops.
VIN > VOUT Operation
The LTC3421 will maintain voltage regulation when the
input voltage is above the output voltage. This is achieved
by terminating the switching on the synchronous PMOS
and applying VIN statically on the gate. This will ensure
Rev. A
For more information www.analog.com
13
LTC3421
APPLICATIONS INFORMATION
the volts • seconds of the inductor will reverse during the
time current is flowing to the output. Since this mode will
dissipate more power in the IC, the maximum output current is limited in order to maintain an acceptable junction
temperature.
IOUT (M AX ) =
125 – TA
40 • ( ( VIN + 1.5 ) – VOUT )
Closing the Feedback Loop
The LTC3421 uses current mode control with internal
adaptive slope compensation. Current mode control eliminates the 2nd order filter due to the inductor and output
capacitor exhibited in voltage mode controllers, and simplifies it to a single pole filter response. The product of the
modulator control to output DC gain and the error amp
open-loop gain gives the DC gain of the system:
where TA = ambient temperature.
GDC = GCONTROL_OUTPUT • GEA •
For example at VIN = 4.5V and VOUT = 3.3V and TA = 85°C,
the maximum output current is 370mA.
GCONTROL =
2 • VIN
IOUT
VREF
VOUT
, GEA ≈ 2000
Short Circuit
The LTC3421 output disconnect feature allows output
short circuit while maintaining a maximum set current
limit. The IC has incorporated internal features such as
current limit and thermal shutdown for protection from
an excessive overload or short circuit. In applications
that require a prolonged short circuit, it is recommended
to limit the power dissipation in the IC to maintain an
acceptable junction temperature. The circuit in Figure 2
will limit the maximum current during a prolonged short
by reducing the current limit value in a short circuit by
disconnecting R2 with the N-channel MOSFET switch. R3
and C1 provide a soft-start function after a short circuit.
Resistor R1 lowers the current limit value as VIN rises,
maintaining a relatively constant power. The current limit
equation for the circuit in Figure 2 is given by:
The output filter pole is given by:
⎛ 0.6 V – 0.6 ⎞
ILIM IT = ⎜
– IN
⎟ • 250
R LIM
R1 ⎠
⎝
R1
1M
VN2222
RLIM
100k
R2
50k
The output filter zero is given by:
fFILTER _ ZERO =
1
2 • π •R ESR • C OUT
where RESR is the capacitor equivalent series resistance.
A troublesome feature of the boost regulator topology is
the right-half plane zero (RHP) and is given by:
fRHPZ =
VIN 2
2 • π • IOUT • L
At heavy loads this gain increase with phase lag can occur
at a relatively low frequency. The loop gain is typically
rolled off before the RHP zero frequency.
R3
10k
fPOLE 1 ≈
TO VOUT
C1
0.1µF
fZERO 1 ≈
3421 F02
Figure 2. Current Limit Foldback Circuit for
Extended Short Conditions
14
π • VOUT • C OUT
The typical error amp compensation is shown in Figure 4.
The equations for the loop dynamics are as follows:
TO VIN
8
IOUT
where COUT is the output filter capacitor.
where ILIMIT is in Amps; RLIM and R1 are in kΩ.
ILIM
fFILTER _ POLE =
fPOLE 2 ≈
1
2 • π • 20e6 • C C 1
which is extremely close to DC
1
2 • π •R Z • C C 1
1
2 • π •R Z • C C 2
Rev. A
For more information www.analog.com
LTC3421
APPLICATIONS INFORMATION
VOUT
+
1.22V
ERROR
AMP
R1
FB
–
1
R2
VC
24
CC1
CC2
RZ
3421 F03
Figure 4.
TYPICAL APPLICATION
5V Applications
When the output voltage is programmed above 4.3V it
is necessary to add a Schottky diode either from SW
to VOUT, or to a snubber network in order to maintain
an acceptable peak voltage on SW. The Schottky to the
L1
3µH
VIN
2.7V TO
4.2V
D1*
Li-Ion to 5V Efficiency
C6*
1µF
M1
+
2
21
SS
6
C2
0.1µF
15
16
SW SW SW
18
VOUTS
17
VOUT
19
VOUT
20
VOUT
LTC3421
1
FB
24
VC
9
BURST
GND PGND PGND PGND
RT
5
10
R2
28k
*LOCATE COMPONENTS CLOSE TO PINS
C1: TAIYO YUDEN JMK212BJ106MM
C5: TAIYO YUDEN JMK325BJ226MM
11
12
VOUT
5V
1A
R5
1.13M
C5*
22µF
×2
C4
470pF
R3
10k
13
C3
0.1µF
100
90
VIN
SHDN
4
ENB
3
VREF
23
LBI
22
LBO
7
SYNC
8
ILIM
R1
60k
14
70
VIN = 4.2V
VIN = 3.6V
VIN = 2.7V
60
50
40
30
20
10
R6
365k
VOUT = 5V
fOSC = 1MHz
0
0.1
R4
100k
D1: MOTOROLA MBR0520L
L1: SUMIDA CDRH6D28-3R0
M1: ZETEX ZXM61P025
Burst Mode
OPERATION
80
EFFICIENCY (%)
C1*
10µF
Li-Ion
output will provide a peak efficiency improvement but will
negate the output disconnect feature. If output disconnect
is required, the Schottky to an active snubber network is
suggested as shown in Figure 3.
1
10
100
OUTPUT CURRENT (mA)
1000
3421 G03
3421 F04
Figure 3. Lithium-Ion to 5V at 1A Application with an Active Snubber Circuit
Rev. A
For more information www.analog.com
15
LTC3421
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
0.70 ±0.05
4.50 ±0.05
2.45 ±0.05
3.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ±0.05
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
2.45 ±0.10
(4-SIDES)
(UF24) QFN 0105 REV B
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
16
Rev. A
For more information www.analog.com
LTC3421
REVISION HISTORY
REV
DATE
DESCRIPTION
A
08/18
Clarified Typical Application
Clarified Order Information
Clarified Note 5
Clarified SHDN Input High and LDO Leakage Conditions
Clarified RDS(ON) vs Temp Graph
Clarified ENB (Pin 4) description
Clarified GND, Exposed Pad (Pin 10, Pin 25) and LBI (Pin 23) description
Clarified Shutdown paragragh
Clarified VREF paragragh
Clarified VIN > VOUT paragraph
PAGE NUMBER
1
2
3
3
5
5
6
8
9
13
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
17
LTC3421
TYPICAL APPLICATION
Single Cell to 3.3V at 500mA with Secondary Cell Backup During Shutdown. LOWBAT and VREF Output are Enabled
L1
4.7µH
VIN
1V TO 1.5V
C1*
4.7µF
2
301k
1 CELL
PRIMARY CELL
4
0.1µF
3
23
+
21
SHDN
ENB
R1
60k
VREF
LBI
SS
RT
6
C2
0.1µF
*LOCATE COMPONENTS CLOSE TO PINS
C1: TAIYO YUDEN JMK212BJ106MM
15
+
16
VIN
LOW BAT 22
LBO
OUTPUT 7
SYNC
8
ILIM
604k
14
D1
SW SW SW
18
VOUTS
17
VOUT
19
VOUT
20
VOUT
LTC3421
1
FB
24
VC
9
BURST
GND PGND PGND PGND
5
R2
28k
10
11
12
13
3V
SECONDARY CELL
VOUT
3.3V
500mA
R5
340k
C5*
22µF
C4
470pF
R3
40k
R6
200k
R4
100k
C3
0.1µF
C5: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A916CY-4R7M
3421 TA05
Single Cell to 3.3V Efficiency
100
90
Burst Mode OPERATION
EFFICIENCY (%)
80
VIN = 1.5V
VIN = 1.2V
70
VIN = 1V
60
50
40
30
20
VOUT = 3.3V
fOSC = 1MHz
0
0.1
1
10
100
OUTPUT CURRENT (mA)
10
1000
3421 G01
RELATED PARTS
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NUMBER
DESCRIPTION
COMMENTS
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LTC3122
2.5A ISW, 3MHz, Synchronous Step-Up DC/DC Converter
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IQ = 25µA, ISD < 1µA, 3mm × 4mm DFN and TSSOP Packages
18
Rev. A
8/18(A)
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