LTC3440
Micropower Synchronous
Buck-Boost DC/DC Converter
Features
Description
Single Inductor
nn Fixed Frequency Operation with Battery Voltages
Above, Below or Equal to the Output
nn Synchronous Rectification: Up to 96% Efficiency
nn 25µA Quiescent Current in Burst Mode® Operation
nn Up to 600mA Continuous Output Current
nn No Schottky Diodes Required (V
OUT < 4.3V)
nn V
Disconnected
from
V
During
Shutdown
OUT
IN
nn 2.5V to 5.5V Input and Output Range
nn Programmable Oscillator Frequency
from 300kHz to 2MHz
nn Synchronizable Oscillator
nn Burst Mode Enable Control
nn 1.5V to
enable the IC and >2.5V to ensure the error amp is not
clamped from soft-start. An RC from the shutdown command signal to this pin will provide a soft-start function
by limiting the rise time of the VC pin.
FB (Pin 9): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 2.5V to
5.5V. The feedback reference voltage is typically 1.22V.
⎛ R1 ⎞
VOUT = 1.22V • ⎜1+ ⎟
⎝ R2 ⎠
VC (Pin 10): Error Amp Output. A frequency compensation network is connected from this pin to the FB pin to
compensate the loop. See the section “Compensating the
Feedback Loop” for guidelines.
Exposed Pad (Pin 11, DFN Package Only): Ground. This
pin must be soldered to the PCB and electrically connected
to ground.
3440fd
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LTC3440
Block Diagram
SW1
3
7
SW D
6
REVERSE
CURRENT
LIMIT
SUPPLY
CURRENT
LIMIT
UVLO
PWM
LOGIC
AND
OUTPUT
PHASING
–
ERROR
AMP
+
1.22V
R1
–
PWM
COMPARATORS
9
+
10
1
FB
CLAMP
–
–
+
2.4V
ISENSE
AMP
+
2.7A
VOUT
2.5V TO 5.5V
VOUT
–0.4A
SW C
–
+
GATE
DRIVERS
AND
ANTICROSS
CONDUCTION
–
SW B
RT
SW2
SW A
+
RT
4
+
VIN
2.5V TO 5.5V
VC
OSC
R2
SYNC
SLEEP
Burst Mode
OPERATION
CONTROL
SHUTDOWN
8
SHDN/SS
RSS
VIN
5µs DELAY
CSS
MODE/SYNC 2
1 = Burst Mode
OPERATION
0 = FIXED FREQUENCY
5
GND
3440 BD
3440fd
For more information www.linear.com/LTC3440
7
LTC3440
Operation
The LTC3440 provides high efficiency, low noise power
for applications such as portable instrumentation. The
LTC proprietary topology allows input voltages above,
below or equal to the output voltage by properly phasing
the output switches. The error amp output voltage on the
VC pin determines the output duty cycle of the switches.
Since the VC pin is a filtered signal, it provides rejection
of frequencies from well below the switching frequency.
The low RDS(ON), low gate charge synchronous switches
provide high frequency pulse width modulation control at
high efficiency. Schottky diodes across the synchronous
switch D and synchronous switch B are not required, but
provide a lower drop during the break-before-make time
(typically 15ns). The addition of the Schottky diodes will
improve peak efficiency by typically 1% to 2% at 600kHz.
High efficiency is achieved at light loads when Burst Mode
operation is entered and when the IC’s quiescent current
is a low 25µA.
Error Amp
Low Noise Fixed Frequency Operation
Output Switch Control
Oscillator
The frequency of operation is user programmable and is
set through a resistor from the RT pin to ground where:
⎛ 6e10 ⎞
f=⎜
⎟Hz
RT ⎠
⎝
An internally trimmed timing capacitor resides inside the
IC. The oscillator can be synchronized with an external
clock applied to the MODE/SYNC pin. A clock frequency
of twice the desired switching frequency and with a pulse
width between 100ns and 2µs is applied. The oscillator
RT component value required is given by:
RT =
8 • 1010
fSW
The error amplifier is a voltage mode amplifier. The loop
compensation components are configured around the
amplifier to provide loop compensation for the converter.
The SHDN/SS pin will clamp the error amp output, VC, to
provide a soft-start function.
Supply Current Limit
The current limit amplifier will shut PMOS switch A off
once the current exceeds 2.7A typical. The current amplifier delay to output is typically 50ns.
Reverse Current Limit
The reverse current limit amplifier monitors the inductor
current from the output through switch D. Once a negative inductor current exceeds – 400mA typical, the IC will
shut off switch D.
Figure 1 shows a simplified diagram of how the four internal
switches are connected to the inductor, VIN, VOUT and GND.
Figure 2 shows the regions of operation for the LTC3440
as a function of the internal control voltage, VCI. The VCI
voltage is a level shifted voltage from the output of the
error amp (VC pin) (see Figure 5). The output switches are
properly phased so the transfer between operation modes
is continuous, filtered and transparent to the user. When
VIN approaches VOUT the Buck/Boost region is reached
where the conduction time of the four switch region is
typically 150ns. Referring to Figures 1 and 2, the various
regions of operation will now be described.
VIN
VOUT
7
6
PMOS A
where fSW = desired synchronized switching frequency.
For example to achieve a 1.2MHz synchronized switching
frequency the applied clock frequency to the MODE/SYNC
pin is set to 2.4MHz and the timing resistor, RT, is set to
66.5k (closest 1% value).
PMOS D
SW1
SW2
3
4
NMOS B
VOUT
NMOS C
3440 F01
Figure 1. Simplified Diagram of Output Switches
8
3440fd
For more information www.linear.com/LTC3440
LTC3440
Operation
75%
DMAX
BOOST
V4 (≈2.05V)
The input voltage, VIN, where the four switch region begins
is given by:
A ON, B OFF
BOOST REGION
PWM CD SWITCHES
DMIN
BOOST
DMAX
BUCK
FOUR SWITCH PWM
VOUT
V
1– (150ns • f)
V3 (≈1.65V)
V2 (≈1.55V)
The point at which the four switch region ends is given by:
BUCK/BOOST REGION
D ON, C OFF
PWM AB SWITCHES BUCK REGION
VIN = VOUT(1 – D) = VOUT(1 – 150ns • f) V
V1 (≈0.9V)
0%
DUTY
CYCLE
VIN =
3440 F02
INTERNAL
CONTROL
VOLTAGE, VCI
Figure 2. Switch Control vs Internal Control Voltage, VCI
Buck Region (VIN > VOUT)
Switch D is always on and switch C is always off during
this mode. When the internal control voltage, VCI, is above
voltage V1, output A begins to switch. During the off time of
switch A, synchronous switch B turns on for the remainder
of the time. Switches A and B will alternate similar to a
typical synchronous buck regulator. As the control voltage increases, the duty cycle of switch A increases until
the maximum duty cycle of the converter in Buck mode
reaches DMAX_BUCK, given by:
DMAX_BUCK = 100 – D4SW %
where D4SW = duty cycle % of the four switch range.
D4SW = (150ns • f) • 100 %
where f = operating frequency, Hz.
Beyond this point the “four switch,” or Buck/Boost region
is reached.
Buck/Boost or Four Switch (VIN ~ VOUT)
When the internal control voltage, VCI, is above voltage V2,
switch pair AD remain on for duty cycle DMAX_BUCK, and
the switch pair AC begins to phase in. As switch pair AC
phases in, switch pair BD phases out accordingly. When
the VCI voltage reaches the edge of the Buck/Boost range,
at voltage V3, the AC switch pair completely phase out the
BD pair, and the boost phase begins at duty cycle D4SW.
Boost Region (VIN < VOUT)
Switch A is always on and switch B is always off during
this mode. When the internal control voltage, VCI, is
above voltage V3, switch pair CD will alternately switch
to provide a boosted output voltage. This operation is
typical to a synchronous boost regulator. The maximum
duty cycle of the converter is limited to 75% typical and
is reached when VCI is above V4.
Burst Mode Operation
Burst Mode operation is when the IC delivers energy to
the output until it is regulated and then goes into a sleep
mode where the outputs are off and the IC is consuming
only 25µA. In this mode the output ripple has a variable
frequency component that depends upon load current.
During the period where the device is delivering energy to
the output, the peak current will be equal to 400mA typical
and the inductor current will terminate at zero current for
each cycle. In this mode the maximum average output
current is given by:
IOUT(MAX)BURST ≈
0.1• VIN
A
VOUT + VIN
Burst Mode operation is user controlled, by driving the
MODE/SYNC pin high to enable and low to disable.
The peak efficiency during Burst Mode operation is less
than the peak efficiency during fixed frequency because
the part enters full-time 4-switch mode (when servicing
the output) with discontinuous inductor current as illustrated in Figures 3 and 4. During Burst Mode operation,
the control loop is nonlinear and cannot utilize the control
voltage from the error amp to determine the control mode,
3440fd
For more information www.linear.com/LTC3440
9
LTC3440
Operation
Burst Mode Operation to Fixed Frequency Transient
Response
therefore full-time 4-switch mode is required to maintain the Buck/Boost function. The efficiency below 1mA
becomes dominated primarily by the quiescent current and
not the peak efficiency. The equation is given by:
Efficiency Burst ≈
When transitioning from Burst Mode operation to fixed
frequency, the system exhibits a transient since the modes
of operation have changed. For most systems this transient
is acceptable, but the application may have stringent input
current and/or output voltage requirements that dictate a
broad-band voltage loop to minimize the transient. Lowering the DC gain of the loop will facilitate the task (10M
FB to VC) at the expense of DC load regulation. Type 3
compensation is also recommended to broad band the
loop and roll off past the two pole response of the LC of
the converter (see Closing the Feedback Loop).
(ηbm) • ILOAD
25µA +ILOAD
where (ηbm) is typically 79% during Burst Mode operation for an ESR of the inductor of 50mΩ. For 200mΩ of
inductor ESR, the peak efficiency (ηbm) drops to 75%.
VIN
VOUT
7
6
3
+
dI ≈ VIN
dT L
D
–
L
SW1
4
IINDUCTOR
A
SW2
B
C
400mA
0mA
3440 F03
T1
5
GND
Figure 3. Inductor Charge Cycle During Burst Mode Operation
VIN
VOUT
7
6
3
SW1
–
dI ≈ – VOUT
L
dT
+
L
B
D
4
SW2
C
IINDUCTOR
A
400mA
0mA
T2
3440 F04
5
GND
Figure 4. Inductor Discharge Cycle During Burst Mode Operation
10
3440fd
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LTC3440
Operation
Soft-Start
The soft-start function is combined with shutdown.
When the SHDN/SS pin is brought above typically 1V,
the IC is enabled but the EA duty cycle is clamped from
the VC pin. A detailed diagram of this function is shown
in Figure 5. The components RSS and CSS provide a
slow ramping voltage on the SHDN/SS pin to provide a
soft-start function.
ERROR AMP
VIN
15µA
+
VOUT
1.22V
R1
FB
–
9
VC
SOFT-START
CLAMP
TO PWM
COMPARATORS
R2
CP1
10
VCI
SHDN/SS
RSS
ENABLE SIGNAL
8
CSS
3440 F05
+
CHIP
ENABLE
–
1V
Figure 5. Soft-Start Circuitry
3440fd
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11
LTC3440
Applications Information
COMPONENT SELECTION
L1
D1
LTC3440
1
RT
2
MODE/SYNC
3
SW1
SW2
4
5
D2
GND
VC 10
FB
9
SHDN/SS
8
VIN
7
VOUT
6
R1
R2
VIN
C1
MULTIPLE
VIAS
Table 1. Inductor Vendor Information
C2
VOUT
GND
3440 F06
Figure 6. Recommended Component Placement. Traces Carrying
High Current are Direct. Trace Area at FB and VC Pins are Kept
Low. Lead Length to Battery Should be Kept Short
Inductor Selection
The high frequency operation of the LTC3440 allows the
use of small surface mount inductors. The inductor current ripple is typically set to 20% to 40% of the maximum
inductor current. For a given ripple the inductance terms
are given as follows:
VIN(MIN) • ( VOUT − VIN(MIN) )
L>
µH
f •IOUT(MAX) • Ripple • VOUT
L>
For high efficiency, choose an inductor with a high frequency core material, such as ferrite, to reduce core loses.
The inductor should have low ESR (equivalent series
resistance) to reduce the I2R losses, and must be able to
handle the peak inductor current without saturating. Molded
chokes or chip inductors usually do not have enough core
to support the peak inductor currents in the 1A to 2A
region. To minimize radiated noise, use a toroid, pot core
or shielded bobbin inductor. See Table 1 for suggested
components and Table 2 for a list of component suppliers.
VOUT • ( VIN(MAX) − VOUT )
f •IOUT(MAX) • Ripple • VIN(MAX)
µH
where f = operating frequency, MHz
Ripple = allowable inductor current ripple
(e.g., 0.2 = 20%)
VIN(MIN) = minimum input voltage, V
VIN(MAX) = maximum input voltage, V
VOUT = output voltage, V
IOUT(MAX) = maximum output load current
12
SUPPLIER
PHONE
FAX
WEB SITE
Coilcraft
(847) 639-6400
(847) 639-1469
www.coilcraft.com
Coiltronics
(561) 241-7876
(561) 241-9339
www.coiltronics.com
Murata
USA:
(814) 237-1431
(800) 831-9172
USA:
(814) 238-0490
www.murata.com
Sumida
www.japanlink.com/
USA:
(847) 956-0666 (847) 956-0702 sumida
Japan:
81(3) 3607-5111 81(3) 3607-5144
Output Capacitor Selection
The bulk value of the capacitor is set to reduce the ripple
due to charge into the capacitor each cycle. The steady
state ripple due to charge is given by:
IOUT(MAX) • ( VOUT – VIN(MIN) ) • 100
%
IOUT(MAX) • ( VIN(MAX) – VOUT ) • 100
%
%Ripple _Boost =
%Ripple _Buck =
COUT • VOUT2 • f
COUT • VIN(MAX) • VOUT • f
where COUT = output filter capacitor, F
The output capacitance is usually many times larger in
order to handle the transient response of the converter. For
a rule of thumb, the ratio of the operating frequency to the
unity-gain bandwidth of the converter is the amount the
output capacitance will have to increase from the above
calculations in order to maintain the desired transient
response.
3440fd
For more information www.linear.com/LTC3440
LTC3440
APPLICATIONS INFORMATION
The other component of ripple is due to the ESR (equivalent series resistance) of the output capacitor. Low ESR
capacitors should be used to minimize output voltage
ripple. For surface mount applications, Taiyo Yuden ceramic
capacitors, AVX TPS series tantalum capacitors or Sanyo
POSCAP are recommended.
Input Capacitor Selection
Since the VIN pin is the supply voltage for the IC it is
recommended to place at least a 4.7µF, low ESR bypass
capacitor.
Table 2. Capacitor Vendor Information
SUPPLIER
PHONE
FAX
WEB SITE
AVX
(803) 448-9411 (803) 448-1943 www.avxcorp.com
Sanyo
(619) 661-6322 (619) 661-1055 www.sanyovideo.com
Taiyo Yuden (408) 573-4150 (408) 573-4159 www.t-yuden.com
Optional Schottky Diodes
Input Voltage > 4.5V
For applications with input voltages above 4.5V which could
exhibit an overload or short-circuit condition, a 2Ω/1nF
series snubber is required between the SW1 pin and GND.
A Schottky diode such as the Phillips PMEG2010EA or
equivalent from SW1 to VIN should also be added as close
to the pins as possible. For the higher input voltages VIN
bypassing becomes more critical, therefore, a ceramic
bypass capacitor as close to the VIN and GND pins as
possible is also required.
Operating Frequency Selection
There are several considerations in selecting the operating frequency of the converter. The first is, what are the
sensitive frequency bands that cannot tolerate any spectral noise? For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz and in
that case a 2MHz converter frequency may be employed.
To achieve a 1%-2% efficiency improvement above
50mW, Schottky diodes can be added across synchronous
switches B (SW1 to GND) and D (SW2 to VOUT). The
Schottky diodes will provide a lower voltage drop during
the break-before-make time (typically 15ns) of the NMOS to
PMOS transition. General purpose diodes such as a 1N914
are not recommended due to the slow recovery times and
will compromise efficiency. If desired a large Schottky
diode, such as an MBRM120T3, can be used from SW2 to
VOUT. A low capacitance Schottky diode is recommended
from GND to SW1 such as a Phillips PMEG2010EA or
equivalent.
Boost: [0.25 • (VIN + VOUT) • f ] mA
Output Voltage > 4.3V
Buck/Boost: f • (0.75 • VIN + 0.25 • VOUT) mA
A Schottky diode from SW to VOUT is required for output
voltages over 4.3V. The diode must be located as close to
the pins as possible in order to reduce the peak voltage
on SW2 due to the parasitic lead and trace inductance.
where f = switching frequency in MHz
Other considerations are the physical size of the converter
and efficiency. As the operating frequency goes up, the
inductor and filter capacitors go down in value and size.
The trade off is in efficiency since the switching losses due
to gate charge are going up proportional with frequency.
Additional quiescent current due to the output switches
GATE charge is given by:
Buck: (0.5 • VIN • f ) mA
3440fd
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13
LTC3440
APPLICATIONS INFORMATION
Closing the Feedback Loop
The LTC3440 incorporates voltage mode PWM control. The
control to output gain varies with operation region (Buck,
Boost, Buck-Boost), but is usually no greater than 15. The
output filter exhibits a double pole response is given by:
fFILTER _ POLE =
fFILTER_POLE =
1
Hz(in Buck mode)
2 • π • L • COUT
Most applications demand an improved transient response
to allow a smaller output filter capacitor. To achieve a higher
bandwidth, Type III compensation is required. Two zeros
are required to compensate for the double-pole response.
1
fPOLE1 ≈
Hz
2 • π •32e3 •R1• CP1
Which is extremely close to DC
VIN
Hz (in Boost mode)
2 • VOUT • π • L •COUT
where L is in Henries and COUT is the output filter capacitor in Farads.
The output filter zero is given by:
fFILTER _ ZERO =
1
2 • π • RESR • COUT
fZERO1 =
1
Hz
2 • π •RZ • CP1
fZERO2 =
1
Hz
2 • π •R1 • CZ 1
fPOLE2 =
1
Hz
2 • π •RZ • CP2
Hz
where RESR is the capacitor equivalent series resistance.
VIN 2
Hz
2 • π •IOUT • L • VOUT
A simple Type I compensation network can be incorporated
to stabilize the loop but at a cost of reduced bandwidth
and slower transient response. To ensure proper phase
margin, the loop requires to be crossed over a decade
before the LC double pole.
–
14
9
CP1
VC
R2
3440 F07
Figure 7. Error Amplifier with Type I Compensation
VOUT
+
ERROR
AMP
–
The unity-gain frequency of the error amplifier with the
Type I compensation is given by:
1
Hz
2 • π • R1• CP1
R1
FB
10
The loop gain is typically rolled off before the RHP zero
frequency.
fUG =
1.22V
ERROR
AMP
A troublesome feature in Boost mode is the right-half
plane zero (RHP), and is given by:
fRHPZ =
VOUT
+
1.22V
R1
CZ1
FB
9
VC
10
CP1
RZ
R2
CP2
3440 F08
Figure 8. Error Amplifier with Type III Compensation
3440fd
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LTC3440
APPLICATIONS INFORMATION
Short-Circuit Improvements
Simple Average Input Current Control
The LTC3440 is current limited to 2.7A peak to protect
the IC from damage. At input voltages above 4.5V a current limit condition may produce undesirable voltages
to the IC due to the series inductance of the package, as
well as the traces and external components. Following
the recommendations for output voltage >4.3V and input
voltage >4.5V will improve this condition. Additional
short-circuit protection can be accomplished with some
external circuitry.
A simple average current limit circuit is shown in
Figure 10. Once the input current of the IC is above approximately 1A, Q1 will start sourcing current into the FB
pin and lower the output voltage to maintain the average
input current. Since the voltage loop is utilized to perform
average current limit, the voltage control loop is maintained and the VC voltage does not slam. The averaging
function of current comes from the fact that voltage loop
compensation is also used with this circuit.
In an overload or short-circuit condition the LTC3440 voltage loop opens and the error amp control voltage on the VC
pin slams to the upper clamp level. This condition forces
boost mode operation in order to attempt to provide more
output voltage and the IC hits a peak switch current limit of
2.7A. When switch current limit is reached switches B and
D turn on for the remainder of the cycle to reverse the volts
• seconds on the inductor. Although this prevents current
run away, this condition produces four switch operation
producing a current foldback characteristic and the average input current drops. The IC is trimmed to guarantee
greater than 1A average input current to meet the maximum
load demand, but in a short-circuit or overload condition
the foldback characteristic will occur producing higher
peak switch currents. To minimize this affect during this
condition the following circuits can be utilized.
VIN
R1
1M
SOFT-START
SO/SS
M2
NMOS
VN2222
C1
4.7nF
M1
NMOS
VN2222
C2
10nF
VOUT
3440 F09
Figure 9. Soft-Start Reset Circuitry for a Sustained Short-Circuit
INPUT_VOLTAGE
V1
Restart Circuit
For a sustained short-circuit the circuit in Figure 9 will force
a soft-start condition. The only design constraint is that
R2/C2 time constant must be longer than the soft-start
components R1/C1 to ensure start-up.
R2
1M
D1
1N4148
C1
10µF
Q1
2N3906
R1
0.5Ω
VIN_PIN
FB_PIN
Figure 10. Simple Input Current Control
Utilizing the Voltage Loop
3440fd
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15
LTC3440
Typical Applications
3-Cell to 3.3V at 600mA Converter
L1
4.7µH
D2
C3
33pF
D1
3
VIN = 2.7V TO 4.5V
7
8
+
3 CELLS
C1 *
10µF
2
1
4
SW1
SW2
LTC3440
6
VIN
VOUT
SHDN/SS
FB
MODE/SYNC
VC
RT
GND
RT f
OSC = 1.5MHz
45.3k
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
R1
340k
9
10
VOUT
3.3V
600mA
R3 15k
C2
22µF
C4 150pF
5
R5
10k
R2
200k
C5 10pF
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
D1, D2: CENTRAL SEMICONDUCTOR CMDSH2-3
L1: SUMIDA CDR43-4R7M
3440 TA03a
3-Cell to 3.3V Efficiency
100
90
EFFICIENCY (%)
80
70
60
50
40
Burst Mode
OPERATION
VIN = 2.7V
VIN = 4.5V
VIN = 3.3V
30
20
10
fOSC = 1.5MHz
0
0.1
10
100
1
OUTPUT CURRENT (mA)
1000
3440 TA03b
16
3440fd
For more information www.linear.com/LTC3440
LTC3440
TYPICAL APPLICATIONS
3-Cell to 5V Boost Converter with Output Disconnect
L1
10µH
3-Cell to 5V Boost Efficiency
D1**
4
SW1
SW2
LTC3440
6
7
VIN
VOUT
3
R4 1M
+
C1
10µF
SD
2
C3 *
0.1µF
1
SHDN/SS
FB
MODE/SYNC
VC
RT
C2**
22µF
15k
10
5
C4
1.5nF
RT
= 1MHz
f
60.4k OSC
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
** LOCATE COMPONENTS AS
CLOSE TO IC AS POSSIBLE
80
R1
619k
9
GND
R2
200k
VIN = 4.5V
Burst Mode
OPERATION
VIN = 3.6V
70
VIN = 2.7V
60
50
40
30
20
10
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
D1: ON SEMICONDUCTOR MBRM120T3
L1: SUMIDA CDRH4D28-100
fOSC = 1MHz
0
1
0.1
10
100
OUTPUT CURRENT (mA)
3440 TA06a
1000
3440 TA06b
Low Profile (