LTC3533
2A Wide Input Voltage
Synchronous Buck-Boost
DC/DC Converter
Description
Features
Regulated Output with Input Voltages Above,
Below or Equal to the Output
n 1.8V to 5.5V (Input) and 5.25V (Output)
Voltage Range
n 0.8A Continuous Output Current: V > 1.8V
IN
n 2A Continuous Output Current: V > 3V
IN
n Single Inductor
n Synchronous Rectification: Up to 96% Efficiency
n Programmable Burst Mode® Operation: I = 40µA
Q
n Output Disconnect in Shutdown
n Programmable Frequency from 300kHz to 2MHz
n 1.6V to ensure the error amp is not clamped
from soft-start. An RC from the shutdown command signal
to this pin will provide a soft-start function by limiting the
rise time of VC
FB (Pin 13): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 1.8V to
5.25V. The feedback reference voltage is typically 1.22V.
VOUT = 1.22 •
R1+ R2
R2
VC (Pin 14): Error Amp Output. An R-C network is connected from this pin to FB for loop compensation. Refer
to “Closing the Feedback Loop” section for component
selection guidelines. During Burst Mode operation, VC is
internally connected to a hold circuit.
Exposed Pad (Pin 15): IC Substrate Ground. This pin must
be soldered to the PCB ground to provide both electrical
contact and a good thermal contact to the PCB.
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LTC3533
Block Diagram
SW2
SW1
VOUT
SW D
SW B
GATE
DRIVERS
AND
ANTI-CROSS
CONDUCTION
–0.5A
SW C
–
SW A
ISENSE
AMP
+
VIN
1.8V TO 5.5V
REVERSE
CURRENT
LIMIT
R1
+
+
SUPPLY
CURRENT
LIMIT
+
+
ERROR
AMP
–
–
–
4.5A
UVLO
+
RT
VC
+
R2
OSC
SLEEP
BURST MODE
OPERATION
CONTROL
BURST
0 = BURST MODE
1 = FIXED FREQUENCY
CLAMP
FB
–
–
1.6V
RT
PWM
LOGIC
AND
OUTPUT
PHASING
PWM
COMPARATORS
1.22V
RUN
GND
RUN/SS
RSS
VIN
CSS
3533 BD
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7
LTC3533
operation
The LTC3533 provides high efficiency, low noise power
for a wide variety of handheld electronic devices. The LTC
proprietary topology allows input voltages above, below
or equal to the output voltage by properly phasing the
output switches. The error amplifier output voltage on VC
determines the output duty cycle of the switches. Since
VC is a filtered signal, it provides rejection of frequencies
well below the switching frequency. The low RDS(ON), low
gate charge synchronous switches provide high frequency
pulse width modulation control at high efficiency. High
efficiency is achieved at light loads when Burst Mode
operation is entered and the LTC3533’s quiescent current
drops to a low 40µA.
LOW NOISE FIXED FREQUENCY OPERATION
Oscillator
The first circuit is a current limit amplifier, sourcing current into FB to drop the output voltage, should the peak
input current exceed 4.5A typical. This method provides a
closed loop means of clamping the input current. During
conditions where VOUT is near ground, such as during a
short circuit or startup, this threshold is cut to 750mA,
providing a fold-back feature. For this current limit feature
to be most effective, the Thevenin resistance from FB to
ground should be greater than 100k.
Should the peak input current exceed 7A typical, the second
circuit, a high speed peak current limit comparator, shuts
off PMOS switch A. The delay to output of this comparator
is typically 50ns.
Reverse Current Limit
f(kHz) = 33,170/RT(k)
During fixed frequency operation, the LTC3533 operates in
forced continuous conduction mode. The reverse current
limit comparator monitors the inductor current from the
output through switch D. Should this negative inductor
current exceed 500mA typical, the LTC3533 shuts off
switch D.
Error Amplifier
Four-Switch Control
The error amplifier is a voltage mode amplifier. The loop
compensation components are configured around the
amplifier (from FB to VC) to obtain stability of the converter.
For improved bandwidth, an additional RC feed-forward
network can be placed across the upper feedback divider
resistor. The voltage on the RUN/SS pin clamps the error
amplifier output, VC, to provide a soft-start function.
Figure 1 shows a simplified diagram of how the four internal switches are connected to the inductor, VIN, VOUT
and GND.Figure 2 shows the regions of operation for the
LTC3533 as a function of the control voltage, VC.
The frequency of operation is programmed by an external
resistor from RT to ground, according to the following
equation:
Supply Current Limits
There are two different supply current limit circuits in the
LTC3533, working consecutively, each having internally
fixed thresholds which vary inversely with VIN.
8
Dependent on VC’s magnitude, the LTC3533 will operate
in either buck, buck/boost or boost mode. The four
power switches are properly phased so the transfer
between operating modes is continuous, smooth and
transparent to the user. When VIN approaches VOUT the
buck/boost region is entered, where the conduction time
of the four switch region is typically 150ns. Referring
to Figures 1 and 2, the various regions of operation will
now be described.
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LTC3533
Operation
PVIN
PVOUT
11
9
PMOS A
SW1
where D4SW = duty cycle % of the four switch range.
D4SW = (150ns • f) • 100 %
PMOS D
L1
SW2
3
7
NMOS B
NMOS C
Figure 1. Simplified Diagram of Output Switches
V4 (≈1.5V)
A ON, B OFF
BOOST REGION
PWM CD SWITCHES
DMIN
BOOST
DMAX
BUCK
V3 (≈1.15V)
FOUR SWITCH PWM
Beyond this point the “four switch,” or buck/boost region
is reached.
Buck/Boost or Four Switch (VIN ~ VOUT)
3533 F01
85%
DMAX
BOOST
where f = operating frequency, Hz.
BUCK/BOOST REGION
V2 (≈1V)
D ON, C OFF
PWM AB SWITCHES BUCK REGION
When the control voltage, VC, is above voltage V2, switch
pair AD remain on for duty cycle DMAX_BUCK, and switch
pair AC begins to phase in. As switch pair AC phases in,
switch pair BD phases out accordingly. When VC reaches
the edge of the buck/boost range, at voltage V3, the AC
switch pair completely phase out the BD pair, and the boost
phase begins at duty cycle D4SW. The input voltage, VIN,
where the four switch region begins is given by:
VIN = VOUT(1 – D) = VOUT(1 – 150ns • f) V
The point at which the four switch region ends is given by:
V1 (≈0.7V)
0%
DUTY
CYCLE
3533 F02
CONTROL
VOLTAGE, VC
Figure 2. Switch Control vs Control Voltage, VC
VIN =
VOUT
V
1− (150ns • f)
where f = operating frequency, Hz.
Boost Region (VIN < VOUT)
Buck Region (VIN > VOUT)
Switch D is always on and switch C is always off during
this mode. When the control voltage, VC, is above voltage
V1, switch A begins to switch. During the off time of switch
A, synchronous switch B turns on for the remainder of
the period. Switches A and B will alternate similar to a
typical synchronous buck regulator. As the control voltage
increases, the duty cycle of switch A increases until the
maximum duty cycle of the converter in buck mode reaches
DMAX_BUCK, given by:
Switch A is always on and switch B is always off during
this mode. When the control voltage, VC, is above voltage
V3, switch pair CD will alternately switch to provide a
boosted output voltage. This operation is typical to a
synchronous boost regulator. The maximum duty cycle
of the converter is limited to 90% typical and is reached
when VC is above V4.
DMAX_BUCK = 100 – D4SW %
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9
LTC3533
Operation
BURST MODE OPERATION
Programmable Automatic Burst Mode Operation
Burst Mode operation reduces the LTC3533’s quiescent
current consumption at light loads and improves overall
conversion efficiency, increasing battery life. During Burst
Mode operation the LTC3533 delivers energy to the output until it is regulated and then goes into a sleep mode
where the outputs are off and the quiescent current drops
to 40µA. In this mode the output ripple has a variable
frequency component that depends upon load current,
and will typically be about 2% peak-to-peak. Burst Mode
operation ripple can be reduced slightly by using more
output capacitance. Another method of reducing Burst
Mode operation ripple is to place a small feed-forward
capacitor across the upper resistor in the VOUT feedback
divider network (as in Type III compensation).
Burst Mode operation can be automatic or digitally controlled with a single pin. In automatic mode, the LTC3533
enters Burst Mode operation at the programmed threshold
and returns to fixed frequency operation when the load
demand increases. The load current at which the mode
transition occurs is programmed using a single external
resistor from BURST to ground, according to the following
equations:
During the period where the device is delivering energy
to the output, the peak switch current will rise to 900mA
typical and the inductor current will terminate at zero
current for each cycle. In this mode, the typical maximum
average output currents are given by:
Where RBURST is in kΩ and IBURST is the load transition
current in Amps. Do not use values of RBURST greater
than 250kΩ.
IMAX(BURST)BUCK ≈ 450mA; VOUT < VIN
Enter Burst Mode Operation: I BURST =
The efficiency below 1mA becomes dominated primarily
by the quiescent current. The Burst Mode operation efficiency is given by:
Efficiency ≅
η •ILOAD
40µA +ILOAD
where h is typically 90% during Burst Mode operation
10
RBURST
19
RBURST
For automatic operation a filter capacitor must also be
connected from BURST to ground. The equation for the
minimum capacitor value is:
IMAX(BURST)BOOST ≈ 450mA • (VIN/VOUT); VOUT > VIN
IMAX(BURST)BUCK-BOOST ≈ 700mA; VOUT ≈ VIN, since the input
and output are connected together for most of the cycle.
Exit Burst Mode Operation: I BURST =
17
CBURST(MIN) ≥
COUT • VOUT
60,000
where CBURST(MIN) and COUT are in µF.
In the event that a load transient causes FB to drop by
more than 4% from the regulation value while in Burst
Mode operation, the LTC3533 will immediately switch
to fixed frequency mode and an internal pull-up will be
momentarily applied to BURST, rapidly charging CBURST.
This prevents the IC from immediately re-entering Burst
mode operation once the output achieves regulation.
3533fc
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LTC3533
Operation
Manual Burst Mode Operation
For manual control of Burst Mode operation, the RC
network connected to BURST can be eliminated. To force
fixed frequency mode, BURST should be connected to
VIN. To force Burst Mode operation, BURST should be
grounded. When commanding Burst Mode operation
manually, the circuit connected to BURST should be able
to sink up to 2mA.
For optimum transient response with large dynamic loads,
the operating mode should be controlled digitally by the
host. By commanding fixed frequency operation prior to a
sudden increase in load, output voltage droop can be minimized. Note that if the load current applied during forced
Burst Mode operation (BURST pin is grounded) exceeds
the current that can be supplied, the output voltage will
start to droop and the LTC3533 will automatically come out
of Burst Mode operation and enter fixed frequency mode,
raising VOUT. Once regulation is achieved, the LTC3533
will then enter Burst Mode operation once again (since the
user is still commanding this by grounding BURST), and
the cycle will repeat, resulting in about 4% output ripple.
incorporates an active clamp circuit that holds the voltage
on VC at an optimal voltage during Burst Mode operation.
This minimizes any output transient when returning to
fixed frequency mode operation. For optimum transient
response, Type 3 compensation is also recommended
to broad band the control loop and roll off past the two
pole response of the output LC filter. (See Closing the
Feedback Loop).
Soft-Start
The soft-start function is combined with shutdown. When
the RUN/SS pin is brought above 1V typical, the LTC3533
is enabled but the error amplifier duty cycle is clamped
from VC. A detailed diagram of this function is shown in
Figure 3. The components RSS and CSS provide a slow
ramping voltage on RUN/SS to provide a soft-start function.
To ensure that VC is not being clamped, RUN/SS must be
raised above 1.6V.
VIN
RUN/SS
VC
Burst Mode Operation to Fixed Frequency Transient
Response
In Burst Mode operation, the compensation network is
not used and VC is disconnected from the error amplifier.
During long periods of Burst Mode operation, leakage
currents in the external components or on the PC board
could cause the compensation capacitor to charge (or
discharge), which could result in a large output transient
when returning to fixed frequency mode of operation, even
at the same load current. To prevent this, the LTC3533
3533 F03
Figure 3.
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11
LTC3533
Applications Information
COMPONENT SELECTION
where f = switching frequency, Hz
∆IL = maximum allowable inductor ripple current
1
RT
VC
14
VIN(MIN) = minimum input voltage
2
BURST
FB
13
VIN(MAX) = maximum input voltage
3
SGND
RUN/SS
12
4
SW1
PVIN
11
5
PGND
VIN
10
6
PGND
PVOUT
9
7
SW2
VOUT
8
GND
VOUT = output voltage
VIN
VOUT
MULTIPLE VIAS
3533 F04
Figure 4. Recommended Component Placement. Traces Carrying
High Current Should be Short and Wide. Trace Area at FB and VC
Pins are Kept Low. Lead Length to Battery Should be Kept Short.
PVOUT and PVIN Ceramic Capacitors Close to the IC Pins.
Inductor Selection
The high frequency operation of the LTC3533 allows the
use of small surface mount inductors. The inductor ripple
current is typically set to 20% to 40% of the maximum
inductor current. For a given ripple the inductance terms
are given as follows:
LBOOST >
LBUCK >
VIN(MIN) • (VOUT − VIN(MIN) )
f • ΔIL • VOUT
VOUT • (VIN(MAX) − VOUT )
f • ΔIL • VIN(MAX)
H
For high efficiency, choose a ferrite inductor with a high
frequency core material to reduce core losses. The inductor should have low ESR (equivalent series resistance) to
reduce the I2R losses, and must be able to handle the peak
inductor current without saturating. Molded chokes or chip
inductors usually do not have enough core to support the
peak inductor currents in the 4A to 6A region. To minimize
radiated noise, use a shielded inductor. See Table 1 for a
suggested list of inductor suppliers.
Output Capacitor Selection
The bulk value of the output filter capacitor is set to reduce
the ripple due to charge into the capacitor each cycle. The
steady state ripple due to charge is given by:
%Ripple _Boost =
%Ripple _Buck =
IOUT(MAX) • (VOUT − VIN(MIN) ) • 100
COUT • VOUT 2 • f
(VIN(MAX) − VOUT ) • 100
8L COUT • VIN(MAX) • f 2
%
%
where COUT = output filter capacitor
IOUT(MAX) = maximum output load current
H
The output capacitance is usually many times larger than
the minimum value in order to handle the transient response
Table 1. Inductor Vendor Information
SUPPLIER
PHONE
FAX
WEB SITE
Coilcraft
(847) 639-6400
(847) 639-1469
www.coilcraft.com
CoEv Magnetics
(800) 227-7040
(650) 361-2508
www.circuitprotection.com/magnetics.asp
Murata
(814) 237-1431
(800) 831-9172
(814) 238-0409
www.murata.com
Sumida
USA: (847) 956-0666
Japan: 81(3) 3607-5111
USA: (847) 956-0702
Japan: 81(3) 3607-5144
www.sumida.com
TDK
(847) 803-6100
(847) 803-6296
www.component.tdk.com
TOKO
(847) 297-0070
(847) 699-7864
www.tokoam.com
12
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LTC3533
Applications Information
requirements of the converter. As a rule of thumb, the ratio
of the operating frequency to the unity-gain bandwidth of
the converter is the amount the output capacitance will
have to increase from the above calculations in order to
maintain the desired transient response.
to provide the conduction path to the output. Note that
Burst Mode operation is inhibited at output voltages below
1V typical.
The other component of ripple is due to the ESR (equivalent series resistance) of the output capacitor. Low ESR
capacitors should be used to minimize output voltage
ripple. For surface mount applications, Taiyo Yuden or TDK
ceramic capacitors, AVX TPS series tantalum capacitors
or Sanyo POSCAP are recommended. See Table 2 for
contact information.
A Schottky diode from SW2 to VOUT is required for output
voltages over 4.3V. The diode must be located as close to
the pins as possible in order to reduce the peak voltage
on SW2 due to parasitic lead and trace inductances.
Output Voltage > 4.3V
Input Voltage > 4.5V
Since PVIN is the supply voltage for the IC it is recommended to place at least a 4.7µF, low ESR ceramic bypass
capacitor close to PVIN and GND. It is also important to
minimize any stray resistance from the converter to the
battery or other power source.
For applications with input voltages above 4.5V which
could exhibit an overload or short-circuit condition, a
2W/1nF series snubber is required between SW1 and
GND. A Schottky diode from SW1 to PVIN should also be
added as close to the pins as possible. For the higher input
voltages, VIN bypassing becomes more critical. Therefore,
a ceramic bypass capacitor as close to the PVIN and GND
pins as possible is also required.
Optional Schottky Diodes
Operating Frequency Selection
Schottky diodes across the synchronous switches B and
D are not required, but do provide a lower drop during the
break-before-make time (typically 15ns), thus improving
efficiency. Use a surface mount Schottky diode such as an
MBRM120T3 or equivalent. Do not use ordinary rectifier
diodes since their slow recovery times will compromise
efficiency.
Higher operating frequencies allow the use of a smaller
inductor and smaller input and output filter capacitors,
thus reducing board area and component height. However, higher operating frequencies also increase the IC’s
total quiescent current due to the gate charge of the four
switches, as given by:
Output Voltage < 1.8V
Boost: IQ = [800e – 12 • (VIN + VOUT) • f ] mA
The LTC3533 can operate as a buck converter with output
voltages as low as 400mV. The part is specified at 1.8V
minimum to allow operation without the requirement of a
Schottky diode; Since synchronous switch D is powered
from PVOUT, and the RDS(ON) will increase at low output
voltages, a Schottky diode is required from SW2 to VOUT
Buck/Boost: IQ = [(1400e – 12 • VIN + 400e – 12 •
VOUT) • f ] mA
Input Capacitor Selection
Buck: IQ = (600e – 12 • VIN • f ) mA
where f = switching frequency in Hz. Therefore frequency
selection is a compromise between the optimal efficiency
and the smallest solution size.
Table 2. Capacitor Vendor Information
SUPPLIER
PHONE
FAX
WEB SITE
AVX
(803) 448-9411
(803) 448-1943
www.avxcorp.com
Sanyo
(619) 661-6322
(619) 661-1055
www.sanyovideo.com
Taiyo Yuden
(408) 573-4150
(408) 573-4159
www.t-yuden.com
TDK
(847) 803-6100
(847) 803-6296
www.component.tdk.com
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13
LTC3533
Applications Information
Closing the Feedback Loop
The LTC3533 incorporates voltage mode PWM control. The
control to output gain varies with operation region (buck,
boost, buck/boost), but is usually no greater than 15. The
output filter exhibits a double pole response, as given by:
f FILTER _POLE =
1
Hz
2 • π • L • COUT
(in buckm ode)
f FILTER _POLE =
VIN
Hz
2 • VOUT • π • L • COUT
(in boostm ode)
where L is in Henries and COUT is in Farads.
The output filter zero is given by:
f FILTER _ ZERO =
1
2 • π • RESR • COUT
Hz
A troublesome feature in boost mode is the right-half plane
zero (RHP), given by:
f UG =
1
Hz
2 • π • R1• CP1
Most applications demand an improved transient response
to allow a smaller output filter capacitor. To achieve a higher
bandwidth, Type III compensation is required, providing
two zeros to compensate for the double-pole response of
the output filter. Referring to Figure 6, the location of the
poles and zeros are given by:
1
f POLE1 =
where RESR is the equivalent series resistance of the
output capacitor.
f RHPZ =
to stabilize the loop, but at a cost of reduced bandwidth
and slower transient response. To ensure proper phase
margin using Type I compensation, the loop must be
crossed over a decade before the LC double pole. Referring
to Figure 5, the unity-gain frequency of the error amplifier
with the Type I compensation is given by:
VIN2
Hz
2 • π •IOUT • L • VOUT
The loop gain is typically rolled off before the RHP zero
frequency.
Hz
2 • π • 10e3 • R1• CP1
(which is a very low frequency)
1
Hz
f ZERO1 =
2 • π • R Z • CP1
1
Hz
f ZERO2 =
2 • π • R1• CZ1
1
Hz
f POLE2 =
2
•
π
•
R
•
C
Z
P2
where resistance is in Ohms and capacitance is in Farads.
A simple Type I compensation network can be incorporated
+
ERROR
AMP
–
VOUT
1.22V
+
ERROR
AMP
–
R1
FB
11
1.22V
CP1
CP1
RZ
R2
CP2
3533 F06
3533 F05
Figure 5. Error Amplifier with Type I Compensation
CZ1
12
11
R2
R1
FB
VC
12
VC
14
VOUT
Figure 6. Error Amplifier with Type III Compensation
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LTC3533
Typical Applications
High Efficiency, High Current LED Driver
3.3μH
11
VIN
3V TO 4.2V
10
OFF ON
12
4
7
SW1
SW2
PVIN
PVOUT
VIN
VOUT
ILED = 1A
8
4.7μF
LTC3533
RUN/SS
9
FB
13
1nF
1
10μF
RT
VC
BURST
44.2k
SGND PGND
3
5
6
14
2
100k
95.3k
100k
47pF
301k
3533 TA02
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15
LTC3533
Package Description
Please refer to http://www.linear.com/product/LTC3533#packaging for the most recent package drawings.
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
0.70 ±0.05
3.30 ±0.05
3.60 ±0.05
2.20 ±0.05
1.70 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
R = 0.05
TYP
3.00 ±0.10
(2 SIDES)
R = 0.115
TYP
8
0.40 ±0.10
14
3.30 ±0.10
1.70 ±0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.75 ±0.05
(DE14) DFN 0806 REV B
7
1
0.25 ±0.05
0.50 BSC
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
16
3533fc
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LTC3533
Revision History
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
B
01/16
Corrected part number in Order Information
2
Modified Burst Mode Operation
10
Moved application circuit to back page
18
Corrected part number in Order Information
2
C
08/16
PAGE NUMBER
3533fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection
its circuits
as described
herein will not infringe on existing patent rights.
Forofmore
information
www.linear.com/LTC3533
17
LTC3533
Typical Application
1MHz Li-Ion to 3.6V at 2A, Pulsed, with Manual Mode Control
6.8μH
11
VIN
3V TO 4.2V
10
12
OFF ON
1
10μF
4
7
SW1
SW2
PVIN
PVOUT
VIN
VOUT
LTC3533
RUN/SS
FB
RT
VC
BURST
64.9k
SGND PGND
3
5
9
8
388k
220pF
13
14
2.2k
VOUT
3.6V AT 2A
15k
470pF
200μF
2
FIXED
BURST
FREQUENCY
6
200k
3533 TA03
Related Parts
PART NUMBER
DESCRIPTION
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LTC3442/LTC3443
LTC3444
1.2A (IOUT), Synchronous Buck-Boost DC/DC Converters,
LTC3442 (1MHz), LTC3443 (600kHz)
500mA (IOUT), Synchronous Buck-Boost DC/DC Converter
LTC3530
600mA (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter
LTC3532
500mA (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter
LTC3536
1A (IOUT) Low Noise Buck-Boost DC/DC Converter
VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.5V, IQ = 300µA,
ISD < 1µA, 20-Pin TSSOP Package, 4mm × 5mm DFN
VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.25V, IQ = 35µA,
ISD < 4mA, 12-Pin MSOP Package, 3mm × 3mm DFN
VIN: 0.5V to 5V, VOUT(MAX) = 6V, IQ = 38mA,
ISD < 1µA, MS Package
VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA,
ISD ≤ 1µA, MS Package
VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA,
ISD ≤ 1µA, TSSOP16E Package
VIN: 0.5V to 4.5V, VOUT(MAX) = 5.25V, IQ = 12µA,
ISD < 1µA, QFN Package
VIN: 2.5V to 5.5V, VOUT(MAX): 2.5V to 5.5V, IQ = 25µA,
ISD < 1µA, MS, DFN Package
VIN: 2.5V to 5.5V, VOUT(MAX): 2.4V to 5.5V, IQ = 25µA,
ISD < 1µA, DFN Package
VIN: 2.4V to 5.5V, VOUT(MAX): 2.4V to 5.25V, IQ = 28µA,
ISD < 1µA, DFN Package
VIN: 2.7V to 5.5V, VOUT = 0.5V to 5V, DFN Package,
Internal Compensation
VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.25V, IQ = 40µA,
ISD < 1µA, 10-Pin MSOP Package, 3mm × 3mm DFN
VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.5V, IQ = 35µA,
ISD < 1µA, 10-Pin MSOP Package, 3mm × 3mm DFN
VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.5V, IQ = 32µA,
ISD < 1µA, 12-Pin MSOP Package, 3mm × 3mm DFN
Thin SOT is a trademark of Linear Technology Corporation.
18 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC3533
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC3533
3533fc
LT 0816 REV C • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2007
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