LTC3612
3A, 4MHz Monolithic
Synchronous Step-Down
DC/DC Converter
Description
Features
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3A Output Current
2.25V to 5.5V Input Voltage Range
Low Output Ripple Burst Mode® Operation: IQ = 70µA
±1% Output Voltage Accuracy
Output Voltage Down to 0.6V
High Efficiency: Up to 95%
Low Dropout Operation: 100% Duty Cycle
Shutdown Current: ≤1µA
Adjustable Switching Frequency: Up to 4MHz
Optional Active Voltage Positioning (AVP) with
Internal Compensation
Selectable Pulse-Skipping/Forced Continuous/
Burst Mode Operation with Adjustable Burst Clamp
Programmable Soft-Start
Inputs for Start-Up Tracking or External Reference
DDR Memory Mode, IOUT = ±1.5A
Available in Thermally Enhanced 20-Pin
(3mm × 4mm) QFN and TSSOP Packages
Applications
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The LTC®3612 is a low quiescent current monolithic synchronous buck regulator using a current mode, constant
frequency architecture. The no-load DC supply current
in sleep mode is only 70µA while maintaining the output
voltage (Burst Mode operation) at no load, dropping to
zero current in shutdown. The 2.25V to 5.5V input supply
voltage range makes the LTC3612 ideally suited for single
Li-Ion as well as fixed low voltage input applications. 100%
duty cycle capability provides low dropout operation,
extending the operating time in battery-powered systems.
The operating frequency is externally programmable up to
4MHz, allowing the use of small surface mount inductors.
For switching noise-sensitive applications, the LTC3612
can be synchronized to an external clock at up to 4MHz.
Forced continuous mode operation in the LTC3612 reduces
noise and RF interference. Adjustable compensation allows
the transient response to be optimized over a wide range
of loads and output capacitors.
The internal synchronous switch increases efficiency and
eliminates the need for an external catch diode, saving
external components and board space. The LTC3612 is
offered in a leadless 20-pin 3mm × 4mm QFN or a thermally
enhanced 20-pin TSSOP package.
Point-of-Load Supplies
Distributed Power Supplies
Portable Computer Systems
DDR Memory Termination
Handheld Devices
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 6580258, 5481178, 5994885, 6304066, 6498466,
6611131.
Typical Application
Efficiency and Power Loss vs Load Current
100
VIN
2.5V TO 5.5V
10
90
210k
47µF
665k
VOUT
2.5V
3A
EFFICIENCY (%)
560nH
80
1
70
60
0.1
50
40
0.01
30
20
3612 TA01a
VIN = 5V
VIN = 3.3V
VIN = 2.8V
10
0
1
100
1000
10
OUTPUT CURRENT (mA)
POWER LOSS (W)
SVIN
PVIN
RUN
PVIN_DRV
DDR
TRACK/SS
RT/SYNC
LTC3612
SW
PGOOD
SGND
ITH
PGND
MODE
VFB
22µF
×2
0.001
10000
3612 TA01b
3612fc
For more information www.linear.com/LTC3612
1
LTC3612
Absolute Maximum Ratings (Note 1)
PVIN, SVIN, PVIN_DRV Voltages...................... –0.3V to 6V
SW Voltage...................................–0.3V to (PVIN + 0.3V)
ITH, RT/SYNC Voltages................ –0.3V to (SVIN + 0.3V)
DDR, TRACK/SS Voltages............ –0.3V to (SVIN + 0.3V)
MODE, RUN, VFB Voltages........... –0.3V to (SVIN + 0.3V)
PGOOD Voltage............................................. –0.3V to 6V
Operating Junction Temperature Range
(Notes 2, 11)........................................... –55°C to 150°C
Storage Temperature............................... –65°C to 150°C
Reflow Peak Body Temperature (QFN)................... 260°C
Lead Temperature (Soldering, 10 sec)
TSSOP............................................................... 300°C
Pin Configuration
TOP VIEW
20 19 18 17
16 PGOOD
DDR 1
15 RUN
RT/SYNC 2
SGND 3
13 PVIN_DRV
SW 6
11 SW
NC
9 10
PVIN
8
PVIN
12 SW
NC
SW 5
7
1
20 PVIN_DRV
RUN
2
19 SW
PGOOD
3
18 NC
MODE
4
17 SW
VFB
5
ITH
6
TRACK/SS
7
14 SW
DDR
8
13 NC
RT/SYNC
9
12 SW
SGND 10
11 NC
14 SVIN
21
NC 4
SVIN
MODE
VFB
ITH
TRACK/SS
TOP VIEW
21
16 PVIN
15 PVIN
FE PACKAGE
20-LEAD PLASTIC TSSOP
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3612EUDC#PBF
LTC3612EUDC#TRPBF
LDQT
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 125°C
LTC3612IUDC#PBF
LTC3612IUDC#TRPBF
LDQT
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 125°C
LTC3612HUDC#PBF
LTC3612HUDC#TRPBF
LDQT
20-Lead (3mm × 4mm) Plastic QFN
–40°C to 150°C
LTC3612MPUDC#PBF
LTC3612MPUDC#TRPBF
LDQT
20-Lead (3mm × 4mm) Plastic QFN
–55°C to 150°C
LTC3612EFE#PBF
LTC3612EFE#TRPBF
LTC3612FE
20-Lead Plastic TSSOP
–40°C to 125°C
LTC3612IFE#PBF
LTC3612IFE#TRPBF
LTC3612FE
20-Lead Plastic TSSOP
–40°C to 125°C
LTC3612HFE#PBF
LTC3612HFE#TRPBF
LTC3612FE
20-Lead Plastic TSSOP
–40°C to 150°C
LTC3612MPFE#PBF
LTC3612MPFE#TRPBF
LTC3612FE
20-Lead Plastic TSSOP
–55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
3612fc
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LTC3612
Electrical
Characteristics l denotes the specifications which apply over the specified operating
The
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 3.3V, RT/SYNC = SVIN, unless otherwise specified.
SYMBOL
PARAMETER
VIN
Operating Voltage Range
VUVLO
Undervoltage Lockout Threshold
VFB
Feedback Voltage Internal Reference
CONDITIONS
MIN
l
2.25
SVIN Ramping Down
SVIN Ramping Up
l
l
1.7
(Notes 3, 4) VTRACK/SS = SVIN, VDDR = 0V
0°C < TJ < 85°C
–40°C < TJ < 125°C
–55°C < TJ < 150°C
l
l
Feedback Voltage External Reference (Notes 3, 4) VTRACK/SS = 0.3V, VDDR = SVIN
(Note 7)
(Notes 3, 4) VTRACK/SS = 0.5V, VDDR = SVIN
0.594
0.591
0.589
TYP
0.6
MAX
UNITS
5.5
V
2.25
V
V
0.606
0.609
0.611
V
V
V
0.289
0.3
0.311
V
0.489
0.5
0.511
V
IFB
Feedback Input Current
VFB = 0.6V
l
±30
nA
∆VLINEREG
Line Regulation
SVIN = PVIN = 2.25V to 5.5V
(Notes 3, 4) TRACK/SS = SVIN
l
0.2
%/V
∆VLOADREG
Load Regulation
ITH from 0.5V to 0.9V (Notes 3, 4)
VITH = SVIN (Note 5)
0.25
2.6
%
%
IS
Active Mode
VFB = 0.5V, VMODE = SVIN (Note 6)
1100
Sleep Mode
VFB = 0.7V, VMODE = 0V, ITH = SVIN
(Note 5)
70
100
VFB = 0.7V, VMODE = 0V (Note 4)
120
160
µA
Shutdown
SVIN = PVIN = 5.5V, VRUN = 0V
0.1
1
µA
mΩ
RDS(ON)
µA
µA
Top Switch On-Resistance
PVIN = 3.3V (Note 10)
70
Bottom Switch On-Resistance
PVIN = 3.3V (Note 10)
45
Top Switch Current Limit
Sourcing (Note 8), VFB = 0.5V
Duty Cycle 1ms
RUN STATE
REDUCED
SWITCHING
FREQUENCY
DOWN
TRACKING
STATE
RUN STATE
3612 F07
UP
TRACKING
STATE
Figure 7. DDR Pin Not Tied to SVIN
0.45V
VFB PIN 0.3V
VOLTAGE 0V
EXTERNAL
VOLTAGE
REFERENCE 0.45V
0.45V
TRACK/SS 0.3V
PIN VOLTAGE 0.2V
0V
RUN PIN
VOLTAGE
SVIN PIN
VOLTAGE
VIN
0V
VIN
0V
TIME
SHUTDOWN SOFT-START
STATE
STATE
tSS > 1ms
RUN STATE
REDUCED
SWITCHING
FREQUENCY
DOWN
TRACKING
STATE
RUN STATE
3612 F08
UP
TRACKING
STATE
Figure 8. DDR Pin Tied to SVIN. Example DDR Application
22
3612fc
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LTC3612
Applications Information
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics curves. To obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3612 does not dissipate much
heat due to its high efficiency.
However, in applications where the LTC3612 is running at
high ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 160°C,
both power switches will be turned off and the SW node
will become high impedance.
To prevent the LTC3612 from exceeding the maximum
junction temperature, some thermal analysis is required.
The temperature rise is given by:
TRISE = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature. The junction temperature, TJ,
is given by:
TJ = TA + TRISE
Therefore, the junction temperature of the regulator operating at 70°C ambient temperature is approximately:
TJ = 0.675W • 43°C/W + 70°C = 99°C
We can safely assume that the actual junction temperature
will not exceed the absolute maximum junction temperature of 125°C.
Note that for very low input voltage, the junction temperature will be higher due to increased switch resistance,
RDS(ON). It is not recommended to use full load current
for high ambient temperature and low input voltage.
To maximize the thermal performance of the LTC3612 the
Exposed Pad should be soldered to a ground plane. See
the PCB Layout Board Checklist.
Design Example
As a design example, consider using the LTC3612 in an
application with the following specifications:
VIN = 2.25V to 5.5V, VOUT = 1.8V, IOUT(MAX) = 3A, IOUT(MIN)
= 100mA, f = 2.6MHz.
Efficiency is important at both high and low load current,
so Burst Mode operation will be utilized.
First, calculate the timing resistor:
PD = (IOUT)2 • RDS(ON) = 675mW
3.82 •1011Hz
Ω – 16kΩ = 130kΩ
2.6MHz
Next, calculate the inductor value for about 30% ripple
current at maximum VIN:
where TA is the ambient temperature.
As an example, consider the case when the LTC3612 is in
dropout at an input voltage of 3.3V with a load current of
3A at an ambient temperature of 70°C. From the Typical
Performance Characteristics graph of Switch Resistance,
the RDS(ON) resistance of the P‑channel switch is 0.075Ω.
Therefore, power dissipated by the part is:
RT =
1.8V 1.8V
L=
• 1–
= 0.466µH
2.6MHz •1A 5.5V
Using a standard value of 0.47µH inductor results in a
maximum ripple current of:
1.8V
1.8V
∆IL =
• 1–
= 0.99A
2.6MHz• 0.47µH 5.5V
For the QFN package, the θJA is 43°C/W.
3612fc
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23
LTC3612
Applications Information
COUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, a
68µF (or 47µF plus 22µF) ceramic capacitor is used with
a X5R or X7R dielectric.
CIN should be sized for a maximum current rating of:
IRMS = 3A •
1.8V 3.6V
•
– 1 = 1.5ARMS
3.6V 1.8V
Decoupling the PVIN with two 22µF capacitors, is adequate
for most applications.
If we set R2 = 196k, the value of R1 can now be determined
by solving the following equation.
1.8V
R1 = 196k •
−1
0.6V
Finally, define the soft start-up time choosing the proper
value for the capacitor and the resistor connected to TRACK/
SS. If we set minimum tSS = 5ms and a resistor of 2M,
the following equation can be solved with the maximum
SVIN = 5.5V :
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3612:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3612.
2. Connect the (+) terminal of the input capacitor(s), CIN,
as close as possible to the PVIN pin, and the (–) terminal
as close as possible to the exposed pad, PGND. This
capacitor provides the AC current into the internal power
MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
A value of 392k will be selected for R1.
CSS =
PC Board Layout Checklist
5ms
= 21.6nF
5.5V
2M •In
5.5V – 0.6V
4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of
power components. Connect the copper areas to PGND
(exposed pad) for best performance.
5. Connect the VFB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
and SGND.
The standard value of 22nF guarantees the minimum softstart up time of 5ms.
Figure 1 shows the schematic for this design example.
24
3612fc
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LTC3612
Typical Applications
General Purpose Buck Regulator Using Ceramic Capacitors, 2.25MHz
VIN
2.25V TO 5.5V
C2
22µF
C1
22µF
RF
24Ω
CF
1µF
RSS
4.7M
CSS
10nF
RC
43k
CC
220pF
PGOOD
CC1
10pF
R5A
1M
R4
100k
PVIN
SVIN
RUN
PVIN_DRV
DDR
TRACK/SS
RT/SYNC
LTC3612
SW
PGOOD
SGND
ITH
PGND
MODE
VFB
R2
196k
R5B
1M
L1: VISHAY IHLP-2020BZ 0.47µH
Efficiency vs Output Current
L1
470nH
CO1
47µF
VOUT
1.8V
CO2 3A
22µF
R1
392k
C3
22pF
3612 TA02a
Load Step Response in Forced Continuous Mode
100
90
VOUT
100mV/DIV
EFFICIENCY (%)
80
70
60
50
IOUT
1A/DIV
40
30
VIN = 2.5V
VIN = 3.3V
VIN = 4V
VIN = 5.5V
20
10
0
1
10
100
1000
OUTPUT CURRENT (mA)
10000
VIN = 3.3V
20µs/DIV
VOUT = 1.8V
IOUT = 100mA TO 3A
VMODE = 1.5V
3612 TA02c
3612 TA02b
3612fc
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25
LTC3612
Typical Applications
Master and Slave for Coincident Tracking Outputs Using a 1MHz External Clock
VIN
2.25V TO 5.5V
C2
22µF
C1
22µF
4.7M
10nF
1MHz
CLOCK
RC1
15k
PGOOD
CC1
470pF
CC2
10pF
RF1
24Ω
CF1
1µF
R5
100k
4.7M
PVIN
SVIN
RUN
PVIN_DRV
DDR
TRACK/SS
RT/SYNC
LTC3612
SW
PGOOD
SGND
ITH
PGND
MODE
VFB
R2
357k
4.7M
C5
22µF
C6
22µF
CHANNEL 1
MASTER
CO11
47µF
R1
715k
CO12
22µF
VOUT1
1.8V
3A
R3
464k
C3
22pF
R4
464k
RF2
24Ω
CF2
1µF
RC2
15k
CC3
470pF
L1
1µH
PGOOD
CC4
10pF
R7
100k
PVIN
SVIN
RUN
PVIN_DRV
DDR
TRACK/SS
RT/SYNC
LTC3612
SW
PGOOD
SGND
ITH
PGND
MODE
VFB
R6
301k
L2
1µH
CHANNEL 2
SLAVE
CO21
47µF
VOUT2
1.2V
3A
CO22
22µF
R5
301k
C7
22pF
3612 TA03a
Coincident Start-Up
Coincident Tracking Up/Down
VOUT1
VOUT1
VOUT2
500mV/DIV
500mV/DIV
2ms/DIV
26
3612 TA03b
VOUT2
200ms/DIV
3612 TA03c
3612fc
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LTC3612
Package Description
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
1.50 REF
2.65 ± 0.05
1.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ± 0.05
4.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ± 0.10
0.75 ± 0.05
1.50 REF
19
R = 0.05 TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
20
0.40 ± 0.10
1
PIN 1
TOP MARK
(NOTE 6)
4.00 ± 0.10
2
2.65 ± 0.10
2.50 REF
1.65 ± 0.10
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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27
LTC3612
Package Description
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation CB
DETAIL A
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
0.60
(.024)
REF
0.28
(.011)
REF
20 1918 17 16 15 14 13 12 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
DETAIL A
6.40
2.74 (.252)
(.108) BSC
SEE NOTE 4
0.45 ±0.05
DETAIL A IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
28
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP REV K 0913
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3612fc
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LTC3612
Revision History
REV
DATE
DESCRIPTION
A
08/10
Updated Temperature Range in Order Information
B
12/13
PAGE NUMBER
Edited Electrical Characteristics table and updated Note 2
3, 4
Updated text in graphs G19, G31
7, 9
Updated Pin 16/Pin 3 and Pin 21/Pin 21 text
10
Updated Functional Block Diagram
11
Updated Burst Mode Operation—External Clamp section
13
Updated Internal and External Compensation section
18
Updated Soft-Start section
19
Updated Timing Resistor equation in Design Example section
23
Updated TA02a and TA02c in Typical Applications
25
Updated Related Parts
30
Add H and MP grades and applicable temperature range refs
Revised Typical Performance Characteristics graphs
Revised inductor and input capacitor sections
C
11/14
2
Changed Minimum Spec for Top Switch Current Limit (Duty Cycle = 100%)
throughout
7-9
15-16
3
3612fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
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29
LTC3612
Typical Application
DDR Termination with Ratiometric Tracking of VDD, 1MHz
VIN
3.3V
C1
22µF
VDD
1.8V
C2
22µF
R6
562k
R3
100k
R7
187k
R8
365k
PGOOD
PVIN
PVIN_DRV
DDR
L1
1µH
LTC3612
PGOOD
RC
6k
R4
1M
SVIN
RUN
TRACK/SS
RT/SYNC
CC
2.2nF
R5
1M
CC1
10pF
SW
C4
100µF
SGND
PGND
ITH
MODE
R1
200k
VFB
C3
22pF
R2
200k
L1: COILCRAFT DO3316T
C5
47µF
VTT
0.9V
±1.5A
3612 TA04a
Ratiometric Start-Up
VDD
VTT
500mV/DIV
500µs/DIV
3612 TA04b
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC3614
5.5V, 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC
Converter with Tracking and DDR
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA,
ISD < 1µA, 3mm × 5mm QFN-24 Package
LTC3616
5.5V, 6A (IOUT), 4MHz, Synchronous Step-Down DC/DC
Converter with Tracking and DDR
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA,
ISD < 1µA, 3mm × 5mm QFN-24 Package
LTC3601
15V, 1.5A (IOUT), Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 300µA,
ISD < 1µA, MSOP-16E and 3mm × 3mm QFN-16 Packages
LTC3603
15V, 2.5A, Synchronous Step-Down DC/DC Converter
92% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA,
4mm × 4mm QFN-16 Package
LTC3605
15V, 5A (IOUT), Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 4V to 15V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD < 15µA,
4mm × 4mm QFN-24 Package
LTC3412A
5.5V, 3A (IOUT), 4MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA,
ISD < 1µA, TSSOP-16E and 4mm × 4mm QFN-16 Packages
LTC3413
5.5V, 3A (IOUT Sink/Source), 2MHz, Monolithic Synchronous
Regulator for DDR/QDR Memory Termination
90% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = VREF /2, IQ = 280µA,
ISD < 1µA, TSSOP-16E Package
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3612fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC3612
(408) 432-1900 ● FAX: (408) 434-0507
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www.linear.com/LTC3612
LT 1114 REV C • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2009
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