LTC3616
6A, 4MHz Monolithic
Synchronous Step-Down
DC/DC Converter
Description
Features
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6A Output Current
2.25V to 5.5V Input Voltage Range
Low Output Ripple Burst Mode® Operation: IQ = 75µA
±1% Output Voltage Accuracy
Output Voltage Down to 0.6V
High Efficiency: Up to 95%
Low Dropout Operation: 100% Duty Cycle
Programmable Slew Rate on SW Node Reduces
Noise and EMI
Adjustable Switching Frequency: Up to 4MHz
Optional Active Voltage Positioning (AVP) with
Internal Compensation
Selectable Pulse-Skipping/Forced Continuous/Burst
Mode Operation with Adjustable Burst Clamp
Programmable Soft-Start
Inputs for Start-Up Tracking or External Reference
DDR Memory Mode, IOUT = ±3A
Available in a 24-Pin 3mm × 5mm QFN
Thermally Enhanced Package
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The operating frequency is externally programmable up to
4MHz, allowing the use of small surface mount inductors.
For switching noise-sensitive applications, the LTC3616
can be synchronized to an external clock at up to 4MHz.
Forced continuous mode operation in the LTC3616 reduces
noise and RF interference. Adjustable compensation allows
the transient response to be optimized over a wide range
of loads and output capacitors.
The internal synchronous switch increases efficiency and
eliminates the need for an external catch diode, saving
external components and board space. The LTC3616
is offered in a leadless 24-pin 3mm × 5mm thermally
enhanced QFN package.
Applications
n
The LTC®3616 is a low quiescent current monolithic synchronous buck regulator using a current mode, constant
frequency architecture. The no-load DC supply current
in sleep mode is only 70µA while maintaining the output
voltage (Burst Mode operation) at no load, dropping to
zero current in shutdown. The 2.25V to 5.5V input supply
voltage range makes the LTC3616 ideally suited for single
Li-Ion as well as fixed low voltage input applications. 100%
duty cycle capability provides low dropout operation,
extending the operating time in battery-powered systems.
Point-of-Load Supplies
Distributed Power Supplies
Portable Computer Systems
DDR Memory Termination
Handheld Devices
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6580258, 5481178, 5994885, 6304066, 6498466, 6611131.
Typical Application
Efficiency and Power Loss
vs Load Current
100
SVIN
PVIN
210k
80
220nH
665k
VOUT
2.5V
47µF 6A
×2
3616 TA01a
1
70
60
0.1
50
40
0.01
30
20
10
0
VOUT = 2.5V
1
VIN = 2.8V
VIN = 3.3V
VIN = 5V
10
100
1000
OUTPUT CURRENT (mA)
0
10000
3616 TA01b
For more information www.linear.com/LTC3616
POWER LOSS (W)
SRLIM/DDR
RUN
TRACK/SS
RT/SYNC
LTC3616
SW
PGOOD
SGND
ITH
PGND
MODE
VFB
90
22µF
×4
EFFICIENCY (%)
VIN
2.7V TO 5.5V
3616fc
1
LTC3616
VFB
MODE
ITH
TOP VIEW
24 23 22 21
SRLIM/DDR 1
20 PGOOD
RT/SYNC 2
19 RUN
SGND 3
18 SVIN
PVIN 4
17 PVIN
25
SW 5
16 SW
SW 6
15 SW
SW 7
14 SW
SW 8
13 SW
10 11 12
NC
NC
9
PVIN
PVIN, SVIN Voltages...................................... –0.3V to 6V
SW Voltage.................................. –0.3V to (PVIN + 0.3V)
ITH, RT/SYNC Voltages................ –0.3V to (SVIN + 0.3V)
SRLIM, TRACK/SS Voltages........ –0.3V to (SVIN + 0.3V)
MODE, RUN, VFB Voltages........... –0.3V to (SVIN + 0.3V)
PGOOD Voltage............................................. –0.3V to 6V
Operating Junction Temperature Range
(Notes 2, 11)........................................... –55°C to 150°C
Storage Temperature.............................. –65°C to 150°C
Reflow Peak Body Temperature (QFN)................... 260°C
Pin Configuration
PVIN
(Note 1)
TRACK/SS
Absolute Maximum Ratings
UDD PACKAGE
24-LEAD (3mm × 5mm) PLASTIC QFN
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3616EUDD#PBF
LTC3616EUDD#TRPBF
LDYG
24-Lead (3mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3616IUDD#PBF
LTC3616IUDD#TRPBF
LDYG
24-Lead (3mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3616HUDD#PBF
LTC3616HUDD#TRPBF
LDYG
24-Lead (3mm × 5mm) Plastic QFN
–40°C to 150°C
LTC3616MPUDD#PBF
LTC3616MPUDD#TRPBF
LDYG
24-Lead (3mm × 5mm) Plastic QFN
–55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
3616fc
For more information www.linear.com/LTC3616
LTC3616
Electrical
Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 3.3V, RT/SYNC = SVIN unless otherwise specified.
SYMBOL
PARAMETER
VIN
Operating Voltage Range
VUVLO
Undervoltage Lockout Threshold
VFB
Feedback Voltage Internal Reference
CONDITIONS
MIN
l
2.25
SVIN Ramping Down
SVIN Ramping Up
l
l
1.7
(Note 3) VTRACK = SVIN, VDDR = 0V
0°C < TJ < 85°C
–40°C < TJ < 125°C
–55°C < TJ < 150°C
l
l
TYP
MAX
UNITS
5.5
V
2.25
V
V
0.594
0.591
0.589
0.6
0.606
0.609
0.609
V
V
V
0.275
0.300
0.325
V
0.475
0.500
Feedback Voltage External Reference
(Note 7)
(Note 3) VTRACK = 0.3V, VDDR = SVIN
0.525
V
IFB
Feedback Input Current
VFB = 0.6V
l
±30
nA
∆VLINEREG
Line Regulation
SVIN = PVIN = 2.25V to 5.5V
(Notes 3, 4) TRACK/SS = SVIN
–40°C < TJ < 125°C
–55°C < TJ < 150°C
l
l
0.2
0.3
%/V
%/V
0.25
2.6
%
%
(Note 3) VTRACK = 0.5V, VDDR = SVIN
∆VLOADREG
Load Regulation
ITH from 0.5V to 0.9V (Notes 3, 4)
VITH = SVIN (Note 5)
IS
Active Mode
VFB = 0.5V, VMODE = SVIN (Note 6)
1100
Sleep Mode
VFB = 0.7V, VMODE = 0V, ITH = SVIN
(Note 5)
75
100
VFB = 0.7V, VMODE = 0V (Note 4)
130
175
µA
Shutdown
SVIN = PVIN = 5.5V, VRUN = 0V
0.1
1
µA
Top Switch On-Resistance
PVIN = 3.3V (Note 10)
35
mΩ
Bottom Switch On-Resistance
PVIN = 3.3V (Note 10)
25
Top Switch Current Limit
Sourcing (Note 8), VFB = 0.5V
Duty Cycle 1ms
RUN STATE
REDUCED
SWITCHING
FREQUENCY
DOWN
TRACKING
STATE
RUN STATE
3616 F08
UP
TRACKING
STATE
Figure 8. DDR Pin Not Tied to SVIN
0.45V
VFB PIN 0.3V
VOLTAGE 0V
EXTERNAL
VOLTAGE
REFERENCE 0.45V
0.45V
TRACK/SS 0.3V
PIN VOLTAGE 0.2V
0V
RUN PIN
VOLTAGE
SVIN PIN
VOLTAGE
VIN
0V
VIN
0V
TIME
SHUTDOWN SOFT-START
STATE
STATE
tSS > 1ms
RUN STATE
REDUCED
SWITCHING
FREQUENCY
DOWN
TRACKING
STATE
RUN STATE
3616 F09
UP
TRACKING
STATE
Figure 9. DDR Pin Tied to SVIN. Example DDR Application
For more information www.linear.com/LTC3616
3616fc
21
LTC3616
Applications Information
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: VIN quiescent current and I2R losses. The VIN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I2R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The VIN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current
out of VIN due to gate charge, and it is typically larger
than the DC bias current. Both the DC bias and gate
charge losses are proportional to VIN; thus, their effects
will be more pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW , and external inductor, RL. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics curves. To obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3616 does not dissipate
much heat due to its high efficiency.
22
However, in applications where the LTC3616 is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the part.
If the junction temperature reaches approximately 170°C,
both power switches will be turned off and the SW node
will become high impedance.
To prevent the LTC3616 from exceeding the maximum
junction temperature, some thermal analysis is required.
The temperature rise is given by:
TRISE = (PD)(θJA)
where PD is the power dissipated by the regulator and
θJA is the thermal resistance from the junction of the die
to the ambient temperature. The junction temperature,
TJ, is given by:
TJ = TA + TRISE
where TA is the ambient temperature.
As an example, consider the case when the LTC3616 is in
dropout at an input voltage of 3.3V with a load current of
6A at an ambient temperature of 70°C. From the Typical
Performance Characteristics graph of Switch Resistance,
the RDS(ON) resistance of the P‑channel switch is 0.035Ω.
Therefore, power dissipated by the part is:
PD = (IOUT)2 • RDS(ON) = 1.26W
For the QFN package, the θJA is 38°C/W.
Therefore, the junction temperature of the regulator operating at 70°C ambient temperature is approximately:
TJ = 1.26W • 38°C/W + 70°C = 118°C
We can safely assume that the actual junction temperature
will not exceed the absolute maximum junction temperature of 125°C.
Note that for very low input voltage, the junction temperature will be higher due to increased switch resistance,
RDS(ON). It is not recommended to use full load current
for high ambient temperature and low input voltage.
To maximize the thermal performance of the LTC3616 the
exposed pad should be soldered to a ground plane. See
the PCB Layout Board Checklist.
3616fc
For more information www.linear.com/LTC3616
LTC3616
Applications Information
Design Example
As a design example, consider using the LTC3616 in an
application with the following specifications:
VIN = 2.25V to 5.5V, VOUT = 1.8V, IOUT(MAX) = 6A, IOUT(MIN)
= 200mA, f = 2.6MHz.
Efficiency is important at both high and low load current,
so Burst Mode operation will be utilized.
First, calculate the timing resistor:
Finally, define the soft start-up time choosing the proper
value for the capacitor and the resistor connected to
TRACK/SS. If we set minimum tSS = 5ms and a resistor
of 2MΩ, the following equation can be solved with the
maximum SVIN = 5.5V :
CSS =
5ms
= 21.6nF
⎛ 5.5V
⎞
2MΩ •In ⎜
⎟
⎝ 5.5V – 0.6V ⎠
The standard value of 22nF guarantees the minimum softstart up time of 5ms.
3.8211Hz
RT =
k – 16k = 130kΩ
2.6MHz
Figure 1 shows the schematic for this design example.
Next, calculate the inductor value for about 30% ripple
current at maximum VIN:
⎛
⎞ ⎛ 1.8V ⎞
1.8V
L =⎜
⎟ • ⎜1–
⎟ = 0.233µH
⎝ 2.6MHz • 2A ⎠ ⎝ 5.5V ⎠
Using a standard value of 0.22µH inductor results in a
maximum ripple current of:
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3616:
⎛
⎞ ⎛ 1.8V ⎞
1.8V
∆IL = ⎜
⎟ = 2.12A
⎟ • ⎜1–
⎝
⎠
2.6MHz
•
0.22µH
5.5V
⎝
⎠
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3616.
COUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design,
a 150µF (or 47µF plus 100µF) ceramic capacitor is used
with a X5R or X7R dielectric.
2. Connect the (+) terminal of the input capacitor(s), CIN,
as close as possible to the PVIN pin, and the (–) terminal
as close as possible to the exposed pad, PGND. This
capacitor provides the AC current into the internal power
MOSFETs.
Assuming worst-case conditions of VIN = 2VOUT, CIN should
be selected for a maximum current rating of:
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
IRMS = 6A •
1.8V ⎛ 3.6V ⎞
• ⎜
– 1⎟ = 3ARMS
3.6V ⎝ 1.8V ⎠
Decoupling PVIN with four 22µF capacitors is adequate
for most applications.
If we set R2 = 196k, the value of R1 can now be determined
by solving the following equation.
4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of
power components. Connect the copper areas to PGND
(exposed pad) for best performance.
5. Connect the VFB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
and SGND.
⎛ 1.8V ⎞
R1 = 196k • ⎜
− 1⎟
⎝ 0.6V ⎠
A value of 392k will be selected for R1.
3616fc
For more information www.linear.com/LTC3616
23
LTC3616
Typical Applications
General Purpose Buck Regulator Using Ceramic Capacitors, 2.25MHz
VIN
2.25V TO 5.5V
22µF
×4
RF
24Ω
CF
1µF
RSS
4.7M
CSS
10nF
RC
15k
CC
470pF
PGOOD
CC1
10pF
R5A
1M
R4
100k
PVIN
SVIN
RUN
TRACK/SS SRLIM/DDR
RT/SYNC
LTC3616
SW
PGOOD
SGND
ITH
PGND
MODE
VFB
R2
196k
R5B
1M
L1
0.22µH
CO1
47µF
CO2
100µF
VOUT
1.8V
6A
R1
392k
C3
22pF
3616 TA02a
L1: VISHAY IHLP-2525CZ-01 220nH
Efficiency vs Output Current
100
Load Step Forced Continuous Mode
VOUT = 1.8V, VIN = 3.3V
90
EFFICIENCY (%)
80
VOUT
200mV/DIV
70
60
50
40
IOUT
5A/DIV
30
VIN = 2.5V
VIN = 3.3V
VIN = 4V
VIN = 5.5V
20
10
0
1
10
100
1000
OUTPUT CURRENT (mA)
10000
50µs/DIV
VIN = 3.3V
VOUT = 1.8V
IOUT = 100mA TO 3A
VMODE = 1.5V
3616 TA02c
3616 TA02b
24
3616fc
For more information www.linear.com/LTC3616
LTC3616
Typical Applications
Master and Slave for Coincident Tracking Outputs Using a 1MHz External Clock
VIN
2.25V TO 5.5V
22µF
×4
4.7M
10nF
1MHz
CLOCK
RC1
15k
CC1
470pF
PGOOD
CC2
10pF
RF1
24Ω
CF1
1µF
R5
100k
4.7M
PVIN
SVIN
RUN
TRACK/SS SRLIM/DDR
RT/SYNC
LTC3616
SW
PGOOD
SGND
ITH
PGND
MODE
VFB
R2
357k
4.7M
L1
0.47µH
CHANNEL 1
MASTER
CO11
47µF
R1
715k
CO12
100µF
VOUT1
1.8V
6A
R3
464k
C3
22pF
R4
464k
RF2
24Ω
22µF
×4
CF2
1µF
RC2
15k
CC3
470pF
PGOOD
CC4
10pF
R7
100k
PVIN
SVIN
RUN
TRACK/SS SRLIM/DDR
RT/SYNC
LTC3616
SW
PGOOD
SGND
ITH
PGND
MODE
VFB
L1, L2: VISHAY IHLP-2525CZ-01 470nH
R6
301k
L2
0.47µH
CHANNEL 2
SLAVE
CO21
47µF
CO22
100µF
VOUT2
1.2V
6A
R5
301k
C7
22pF
3616 TA03a
Coincident Start-Up
Coincident Tracking Up/Down
VOUT1
VOUT1
VOUT2
500mV/DIV
500mV/DIV
2ms/DIV
3616 TA03b
VOUT2
200ms/DIV
3616 TA03c
3616fc
For more information www.linear.com/LTC3616
25
LTC3616
UDD Package
24-Lead Plastic QFN (3mm × 5mm)
Package Description (Reference LTC DWG # 05-08-1833 Rev Ø)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UDD Package
24-Lead Plastic QFN (3mm × 5mm)
(Reference LTC DWG # 05-08-1833)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
3.65 ± 0.05
1.50 REF
1.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ± 0.10
0.75 ± 0.05
1.50 REF
23
R = 0.05 TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
24
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
5.00 ± 0.10
1
2
3.65 ± 0.10
3.50 REF
1.65 ± 0.10
(UDD24) QFN 0808 REV Ø
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
26
3616fc
For more information www.linear.com/LTC3616
LTC3616
Revision History
REV
DATE
DESCRIPTION
A
4/11
Added VRUN specification in the Electrical Characteristics section.
PAGE NUMBER
B
11/13
Add H and MP grades and applicable temperature range references.
Modified Note 2.
C
4/14
4
Throughout
4
Modified Typical Performance Characteristics graphs.
7, 8
Modified Inductor Core Selection section.
15
Modified Input Capacitor Selection section.
15
Modified the top switch current limit specification.
3
3616fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC3616
27
LTC3616
Typical Application
DDR Termination With Ratiometric Tracking of VDD, 1MHz
VIN
3.3V
VDD
1.8V
VDD
C1
22µF
×4
R6
562k
R7
187k
Ratiometric Start-Up
R3
100k
R8
365k
PGOOD
R5
1M
PVIN
L1
0.33µH
LTC3616
CC
2.2nF
CC1
10pF
ITH
MODE
L1: COILCRAFT DO3316T
VTT
500mV/DIV
SRLIM/DDR
PGOOD
RC
6k
R4
1M
SVIN
RUN
TRACK/SS
RT/SYNC
SW
C4
100µF
SGND
PGND
VTT
0.9V
C5 ±3A
47µF
500µs/DIV
3616 TA04b
R1
200k
VFB
R2
200k
C3
22pF
3616 TA04a
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC3418
5.5V, 8A (IOUT), 4MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN(MIN) = 2.25V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.8V,
IQ = 380µA, ISD
