LTC3770
Fast No RSENSETM Step-Down
Synchronous Controller with
Margining, Tracking and PLL
DESCRIPTION
FEATURES
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Wide VIN Range: 4V to 32V
±0.67% 0.6V Reference Voltage
Output Voltage Tracking Capability
Programmable Margining
Sense Resistor Optional
True Current Mode Control
2% to 90% Duty Cycle at 200kHz
tON(MIN) ≤ 100ns
Phase-Locked Loop Frequency Synchronization
Powerful Dual N-Channel MOSFET Driver
Adjustable Cycle-by-Cycle Current Limit
Adjustable Switching Frequency
Programmable Soft-Start
Current Foldback Protection (Disabled at Start-Up)
Output Overvoltage Protection
Micropower Shutdown: IQ < 30μA
Power Good Output Voltage Monitor
Tracks the Reference Input Pin
Available in (5mm × 5mm) QFN and 28-Lead
SSOP Packages
n
The LTC3770 uses a constant on-time, valley current
mode control architecture to deliver very low duty factors
without requiring a sense resistor. The operating frequency
is selected by an external resistor and is compensated for
variations in input supply voltage. An internal phase-locked
loop allows the IC to be synchronized to an external
clock.
Fault protection is provided by an overvoltage comparator
and input undervoltage lockout. The regulator current
limit is user programmable. A wide supply range allows
voltages as high as 32V to be stepped down to as low as
a 0.6V output. Power supply sequencing is accomplished
using an external soft-start timing capacitor.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
RSENSE is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5481178, 5487554, 6580258, 6304066, 6476589,
6774611.
APPLICATIONS
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The LTC®3770 is a synchronous step-down switching
regulator controller with output voltage up/down tracking
capability and voltage margining. Its advanced functions
and high accuracy reference are ideal for powering
high performance server, ASIC and computer memory
systems.
Distributed Power Systems
Server Power Supply
TYPICAL APPLICATION
High Efficiency Step-Down Converter
ION
VIN
10k
Si4884
TG
SW
TRACK/SS
BOOST
I
1.8μH
0.22μF
+
TH
1000pF
10k
VOUT
LTC3770
SGND
RUN
VON
INTVCC
DRVCC
BG
VRNG
SENSE+
VREFOUT
10k
82k
CMDSH-3
Si4874
95.3k
SENSE
PGND
MPGM
VFB
90
EFFICIENCY
85
1
80
75
70
POWER LOSS
0.1
65
55
50
0.01
–
VREFIN
10
VIN = 5V
95 VOUT = 2.5V
60
B340A
4.7μF
VIN
10μF 5V TO 28V
35V
x3
VOUT
2.5V
10A
180μF
4V
x2
POWER LOSS (W)
PLLFLTR
PLLIN
0.1μF
100
68k
EFFICIENCY (%)
0.01μF
PGOOD
MARGIN
Efficiency and Power Loss vs Load Current
30.1k
0.1
1
LOAD CURRENT (A)
0.01
10
3770 TA01b
3770 TA01
3770fc
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LTC3770
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage (VIN , VINSNS) ............ 32V to –0.3V
Boosted Topside Driver Supply Voltage
BOOST ................................................... 38V to –0.3V
SENSE+, SW Voltage ..................................... 32V to –5V
DRVCC , (BOOST – SW) Voltages .................. 7V to –0.3V
VON , VRNG , PGOOD Voltages .....INTVCC + 0.3V to –0.3V
PLLFLTR, ITH , VFB , VREFIN Voltages .......... 2.7V to –0.3V
TRACK/SS, FCB, Z0, Z1, Z2, RUN, PLLIN, MARGIN0,
MARGIN1 Voltages ....................INTVCC + 0.3V to –0.3V
INTVCC , ZVIN Voltages.................................. 7V to –0.3V
TG, BG, INTVCC Peak Currents ....................................4A
TG, BG, INTVCC RMS Currents ...............................50mA
Operating Ambient Temperature
Range (Note 4).........................................–40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range...................–65°C to 125°C
QFN Reflow Peak Body Temperature ..................... 245°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
PIN CONFIGURATION
TOP VIEW
SW
BOOST
FCB
RUN
28 FCB
VON
1
PGOOD
TOP VIEW
RUN
27 Z0
3
26 BOOST
VRNG
4
25 TG
VRNG 1
24 SENSE+
VFB
5
24 SW
VFB 2
23 SENSE–
ITH
6
23 PGND
ITH 3
22 PGND
TRACK/SS 14
18 Z2
VREFIN 8
17 Z1
19 Z1
18 ZVIN
9 10 11 12 13 14 15 16
17 VIN
16 PLLIN
15 PLLFLTR
ZVIN
MPGM 13
19 INTVCC
ION 7
VINSNS
VREFOUT 12
20 Z2
VIN
VREFIN 11
20 DRVCC
MARGIN0 6
PLLIN
ION 10
21 INTVCC
21 BG
33
MARGIN1 5
PLLFLTR
9
22 BG
TRACK/SS
MARGIN0
8
SGND 4
MPGM
MARGIN1
7
32 31 30 29 28 27 26 25
VREFOUT
SGND
TG
2
Z0
VON
PGOOD
UH PACKAGE
32-LEAD (5mm s 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD IS SGND (PIN 33)
MUST BE SOLDERED TO THE PCB
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3770EG#PBF
LTC3770EG#TRPBF
LTC3770EG
28-Lead Plastic SSOP
–40°C to 85°C
LTC3770EUH#PBF
LTC3770EUH#TRPBF
3770
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3770fc
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LTC3770
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1300
30
2200
50
μA
μA
0.6
0.6
0.604
0.606
V
V
Main Control Loop
IQ
Input DC Supply Current
Normal Operation
Shutdown Supply Current
VFB
Feedback Voltage Accuracy (Note 3)
VREFIN = VREFOUT; ITH = 1.2V (0°C to 85°C)
VREFIN = VREFOUT; ITH = 1.2V
l
0.596
0.594
VFB(LINEREG)
Feedback Voltage Line Regulation
VIN = 4V to 30V, ITH = 1.2V (Note 3)
0.002
VFB(LOADREG)
Feedback Voltage Load Regulation
ITH = 0.5V to 1.9V (Note 3)
–0.05
–0.3
%
VRUN
Run Pin On Threshold
VRUN Rising
1
1.5
1.9
V
VSS/TRACK = 0V
ISS/TRACK
Soft-Start Charging Current
IFB
Feedback Pin Input Current
–1.1
–1.4
–1.7
μA
–100
–20
100
nA
l
1
1.3
1.6
mS
l
0.57
0.6
0.63
V
–1
–2
μA
250
115
290
150
ns
ns
gm(EA)
Error Amplifier Transconductance
VFCB
Forced Continuous Threshold
IFCB
Forced Continuous Pin Current
VFCB = 0V
tON
On-Time
ION = –60μA, VON = 1.5V
ION = –60μA, VON = 0V
tON(MIN)
Minimum On-Time
ION = –180μA, VON = 0V
50
100
ns
tOFF(MIN)
Minimum Off-Time
Tested with a Square Wave (Note 5)
250
400
ns
VSENSE(MAX)
Maximum Current Sense Threshold
VSENSE– – VSENSE+
VRNG = 1V, VFB = VREFIN – 30mV
VRNG = 0V, VFB = VREFIN – 30mV
VRNG = INTVCC, VFB = VREFIN – 30mV
133
67
268
153
84
308
mV
mV
mV
VSENSE(MIN)
Minimum Current Sense Threshold
VSENSE– – VSENSE+
VRNG = 1V, VFB = VREFIN + 30mV
VRNG = 0V, VFB = VREFIN + 30mV
VRNG = INTVCC, VFB = VREFIN + 30mV
ΔVFB(OV)
Output Overvoltage Fault Threshold Offset
VIN(UVLO+)
VIN(UVLO–)
Undervoltage Lockout
VIN Falling
Undervoltage Lockout
VIN Rising
VMGN(TH)
MARGIN0, MARGIN1 Input Thresholds
VMPGM
MPGM Pin Voltage
TG RUP
TG Driver Pull-Up On Resistance
TG RDOWN
TG Driver Pull-Down On Resistance
BG RUP
BG Driver Pull-Up On Resistance
BG RDOWN
BG Driver Pull-Down On Resistance
TG tr
TG tf
ITH = 1.2V (Note 3)
%/V
210
90
l
l
l
113
50
228
–60
–30
–120
7
mV
mV
mV
10
13
l
3.2
3.9
V
l
3.3
4
V
1.4
V
1.18
TG High
%
V
1.9
2.5
Ω
TG Low
1.2
2.5
Ω
BG High
1.9
3
Ω
BG Low
0.7
1.5
Ω
TG Rise Time
CLOAD = 3300pF
20
ns
TG Fall Time
CLOAD = 3300pF
20
ns
BG tr
BG Rise Time
CLOAD = 3300pF
20
ns
BG tf
BG Fall Time
CLOAD = 3300pF
20
ns
3770fc
3
LTC3770
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4.7
5
5.3
V
–0.1
±2
%
Internal VCC Regulator
l
VINTVCC
Internal VCC Voltage
6V < VIN < 30V
ΔVLDO(LOADREG)
Internal VCC Load Regulation
ICC = 0mA to 20mA
Phased-Locked Loop
RPLLIN
PLLIN Input Resistance
IPLLFLTR
Phase Detector Output Current
Sink Capability
Source Capability
50
kΩ
fPLLIN < f0
fPLLIN > f0
–15
15
μA
μA
ΔVFBH
PGOOD Upper Threshold
VFB Rising
7
10
13
%
ΔVFBL
PGOOD Lower Threshold
VFB Falling
–7
–10
–13
%
ΔVFB(HYS)
PGOOD Hysteresis
VFB Returning
1.5
3
%
VPGL
PGOOD Low Voltage
IPGOOD = 5mA
0.15
0.4
V
PGOOD Output
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD as follows:
LTC3770EG: TJ = TA + (PD • 130°C/W)
LTC3770EUH: TJ = TA + (PD • 34°C/W)
Note 3: The 3770 is tested in a feedback loop that adjusts VFB to
achieve a specified error amplifier output voltage (ITH). For these tests,
VREFOUT = VREFIN .
Note 4: The LTC3770E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: The minimum off-time condition is specified for large peak-to-peak
inductor ripple current (see Minimum Off-Time Considerations in
the Applications Information section).
TYPICAL PERFORMANCE CHARACTERISTICS
Current Sense Threshold
vs ITH Voltage
VRNG =
200
2V
On-Time vs VON Voltage
VVON = 0V
1V
0
ON-TIME (ns)
1000
0.7V
0.5V
100
100
IION = 60μA
800
600
400
–100
–200
1200
1000
1.4V
ON-TIME (ns)
CURRENT SENSE THRESHOLD (mV)
300
On-Time vs ION Current
10000
200
10
0
0.5
1.0
1.5
2.0
ITH VOLTAGE (V)
2.5
3.0
3770 G01
0
1
10
ION CURRENT (μA)
100
3770 G02
0
1
2
3
VON VOLTAGE (V)
4
5
3770 G03
3770fc
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LTC3770
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense
Threshold vs VRNG Voltage
IION = 30μA
VVON = 0V
250
ON-TIME (ns)
200
150
100
50
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
Maximum Current Sense
Threshold vs Temperature
300
MAXIMUM CURRENT SENSE THRESHOLD (mV)
300
MAXIMUM CURRENT SENSE THRESHOLD (mV)
On-Time vs Temperature
250
200
150
100
50
0
0.5
0.75
1.0
1.25
1.5
VRNG VOLTAGE (V)
1.75
3770 G04
2.0
100
1.5
1.0
20
15
25
10
INPUT VOLTAGE (V)
30
35
–0.50
–0.75
–1.00
–1.25
50
3770 G10
5
20
15
25
10
INPUT VOLTAGE (V)
–1.50
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
30
35
3770 G09
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
FCB PIN CURRENT (μA)
$INTVCC (%)
0
Undervoltage Lockout Threshold
vs Temperature
–0.25
10
30
40
20
INTVCC LOAD CURRENT (mA)
20
0
5
0
–0.3
125
100
30
3770 G08
0
–0.2
50
25
0
75
TEMPERATURE (°C)
40
FCB Pin Current vs Temperature
–0.1
–25
10
0
125
INTVCC Load Regulation
0
100
–50
50
3770 G07
–0.4
110
Shutdown Current vs Input Voltage
0
50
25
0
75
TEMPERATURE (°C)
120
60
0.5
0.8
–25
130
3770 G06
SHUTDOWN CURRENT (μA)
1.4
0.6
–50
140
Input Current vs Input Voltage
2.5
INPUT CURRENT (mA)
gm (mS)
Error Amplifier gm vs Temperature
1.0
VRNG = 1V
3770 G05
1.6
1.2
2.0
150
125
3770 G11
4.0
3.5
3.0
2.5
2.0
–50
–25
75
0
25
50
TEMPERATURE (C)
100
125
3770 G12
3770fc
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LTC3770
TYPICAL PERFORMANCE CHARACTERISTICS
Track Up
Track Down
FIGURE 12 CIRCUIT
Transient Response
FIGURE 12 CIRCUIT
TRACK/SS
TRACK/SS
TRACK/SS
AND VFB
500mV/DIV
VFB
TRACK/SS
AND VFB
500mV/DIV
FIGURE 12 CIRCUIT
VOUT
VOUT
100mV/DIV
VFB
VOUT
VOUT
2V/DIV
IL
5A/DIV
STEP
0A TO 10A
VOUT
2V/DIV
3770 G13
250ms/DIV
Efficiency vs Load Current
100
3770 G14
250ms/DIV
ITH Voltage vs Load Current
2.5
FIGURE 12 CIRCUIT
Frequency vs Input Voltage
480
FIGURE 12 CIRCUIT
95
460
DISCONTINUOUS
MODE
2.0
80
CONTINUOUS
MODE
75
70
1.5
CONTINUOUS
MODE
1.0
65
60
0.5
0
1
0.1
LOAD CURRENT (A)
10
2
0
4
6
8
LOAD CURRENT (A)
10
3770 G16
380
IOUT = 0A
360
12
320 FCB = 0V
FIGURE 12 CIRCUIT
300
5
10
15
0
20
INPUT VOLTAGE (V)
25
30
3770 G18
Frequency vs Load Current
500
FCB = 5V
FIGURE 12 CIRCUIT
FIGURE 12 CIRCUIT
450
95
400
90
FREQUENCY (kHz)
EFFICIENCY (%)
400
3770 G17
Efficiency vs Input Voltage
100
420
340
DISCONTINUOUS
MODE
55
50
0.01
IOUT = 10A
440
FREQUENCY (kHz)
85
ITH VOLTAGE (V)
EFFICIENCY (%)
90
3770 G15
20μs/DIV
ILOAD = 10A
85
ILOAD = 1A
80
350
CONTINUOUS
MODE
300
250
200
DISCONTINUOUS
MODE
150
100
75
50
70
0
0
5
20
10
15
INPUT VOLTAGE (V)
25
30
3770 G19
0
2
4
6
8
LOAD CURRENT (A)
10
12
3770 G20
3770fc
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LTC3770
TYPICAL PERFORMANCE CHARACTERISTICS
Ion Current vs VIN
140
VRNG = 1V
140
100
80
60
40
100
80
60
40
20
20
0
RON = 82k
120
120
ION CURRENT (μA)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
Current Limit Foldback
160
0
0
0.1
0.2
0.3
VFB (V)
0.4
0.5
0.6
3770 G21
PIN FUNCTIONS
0
5
20
15
25
10
INPUT VOLTAGE (V)
30
35
3770 G22
(UH Package/G Package)
VRNG (Pin 1/Pin 4): Sense Voltage Range Input. The
voltage at this pin is ten times the nominal sense voltage
at maximum output current and can be set from 0.5V to
2V by a resistive divider from INTVCC . The nominal sense
voltage defaults to 50mV when this pin is tied to ground,
200mV when tied to INTVCC . Do not set this voltage
between 0.5V to ground or 2V to INTVCC .
VFB (Pin 2/Pin 5): Error Amplifier Feedback Input. This pin
connects the error amplifier input to an external resistive
divider from VOUT.
ITH (Pin 3/Pin 6): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V with 0.75V corresponding to zero
sense voltage (zero current).
SGND (Pin 4/Pin 7): Signal Ground. All small-signal
components and compensation components should
connect to this ground, which in turn connects to PGND
at one point.
MARGIN1 (Pin 5/Pin 8): The MSB Logic Input for the
Margining Function. Together with the MARGIN0 pin
determines whether the IC is in margin high, margin low,
or no margin state. This pin has a 50k internal pull-down
resistor.
MARGIN0 (Pin 6/Pin 9): The LSB Logic Input for the
Margining Function. Together with the MARGIN1 pin
determines whether the IC is in margin high, margin low,
or no margin state. This pin has a 50k internal pull-down
resistor.
ION (Pin 7/Pin 10): On-Time Current Input. Tie a resistor
from this pin to ground to set the one-shot timer current
and thereby set the switching frequency.
VREFIN (Pin 8/Pin 11): Error Amplifier Reference Input.
The voltage at this pin must be greater than 0.5V and
less than 1V.
VREFOUT (Pin 9/Pin 12): Buffered Internal 0.6V Reference
Output. The maximum current sinking limit is 50μA at
this pin. Do not put a filter capacitor larger than 100pF
on this pin.
MPGM (Pin 10/Pin 13): Programmable Margining Input.
A resistor from this pin to ground sets the margining
current. This current, together with the resistor between
the VREFOUT and VREFIN pins, determines the margining
voltage offset.
TRACK/SS (Pin 11/Pin 14): Output Voltage Tracking and
Soft-Start Input. When the IC is configured to be the
master of two outputs, a capacitor to ground at this pin
3770fc
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LTC3770
PIN FUNCTIONS
(UH Package/G Package)
sets the ramp rate for the output voltage. When the IC is
configured to be the slave of two outputs, the VFB voltage
of the master IC is reproduced by a resistor divider and
applied to this pin. An internal 1.4μA soft-start current is
charging this pin during the soft-start phase.
PLLFLTR (Pin 12/Pin 15): The Phase-Locked Loop’s
Lowpass Filter is Tied to This Pin. The voltage at this pin
defaults to 1.18V when the IC is not synchronized with
an external clock at the PLLIN pin.
PLLIN (Pin 13/Pin 16): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with a 50k resistor.
VIN (Pin 14/Pin 17): Main Input Supply. Decouple this pin
to PGND with a capacitor (0.1μF to 1μF).
VINSNS (Pin 15) UH Package: VIN Voltage Sense Input.
Normally this pin is tied to VIN . However, in certain
applications when the IC is powered from a separate
supply, VINSNS is tied to the upper MOSFET supply to
sense the VIN voltage. The pin is co-bonded with VIN in
the SSOP package.
ZVIN (Pin 16/Pin 18): Post-Package Zener-Trim Voltage
Input. Under normal conditions this pin should always be
connected to INTVCC .
Z1 (Pin 17/Pin 19): Post-Package Zener-Trim Control.
This pin is a multifunctional pin used in production for
post-package trimming and tracking. Ground this pin under
normal soft-start operation. Connecting this pin to INTVCC
will turn off the soft-start current during tracking.
Z2 (Pin 18/Pin 20): Post-Package Zener-Trim Control.
This pin is used in production for Post-Package trimming.
Ground this pin or tie to INTVCC under normal operation.
INTVCC (Pin 19/Pin 21): Internal 5V Regulator Output. The
control circuits are powered from this voltage. Decouple this
pin to PGND with a minimum of 4.7μF low ESR tantalum
or ceramic capacitor.
DRVCC (Pin 20) UH Package Gate: Driver Voltage Input.
Must be connected to INTVCC externally. Do not exceed
7V at this pin. This pin is co-bonded to INTVCC internally
in the SSOP package.
BG (Pin 21/Pin 22): Bottom Gate Driver Output. This pin
drives the gate of the bottom N-channel MOSFET between
ground and INTVCC .
PGND (Pin 22/Pin 23): Power Ground. Connect this pin
closely to the source of the bottom N-channel MOSFET,
the (–) terminal of CVCC and the (–) terminal of CIN .
SENSE– (Pin 23) UH Package: Current Sense Comparator
Input. The (–) input to the current comparator is used
to accurately Kelvin sense the bottom side of the sense
resistor or MOSFET. This pin is co-bonded with PGND
internally in the SSOP package.
SENSE+ (Pin 24) UH Package: Current Sense Comparator
Input. The (+) input to the current comparator is normally
connected to the SW node unless using a sense resistor.
This pin is co-bonded with SW internally in the SSOP
package.
SW (Pin 25/Pin 24): Switch Node. The (–) terminal of the
boot-strap capacitor CB connects here. This pin swings
from a diode voltage drop below ground up to VIN.
TG (Pin 26/Pin 25): Top Gate Drive Output. This pin drives
the top N-channel MOSFET with a voltage swing equal to
INTVCC , superimposed on the switch node voltage SW.
BOOST (Pin 27/Pin 26): Boosted Floating Driver Supply.
The (+) terminal of the boot-strap capacitor CB connects
here. This pin swings from a diode voltage drop below
INTVCC up to VIN + INTVCC.
Z0 (Pin 28/Pin 27): Dead Time Control Input. Applying a
DC voltage will vary the dead time between TG-Low and
BG-High transition. Do not force a voltage higher than
5V on this pin.
FCB (Pin 29/Pin 28): Forced Continuous Input. Connect
this pin to SGND to forced continuous synchronization
operation at low load, to INTVCC to enable discontinuous
mode operation at low load or to a resistive divider from
a secondary output when using a secondary winding.
RUN (Pin 30/Pin 1): Run Control Input. A voltage above
1.5V turns on the IC. Forcing this pin below 1.5V shuts
down the device.
3770fc
8
LTC3770
PIN FUNCTIONS
(UH Package/G Package)
VON (Pin 31/Pin 2): On-Time Voltage Input. Connecting this
pin to the output voltage makes the on-time proportional
to VOUT. The comparator input defaults to 0.6V when the
pin is grounded and defaults to 4.8V when the pin is tied
to INTVCC.
PGOOD (Pin 32/Pin 3): Power Good Output. Open drain
FUNCTIONAL DIAGRAM
(UH Package)
VIN
31 VON
4.8V
0.6V
12
Exposed Pad (Pin 33) UH Package: Signal Ground. Must
be soldered to the PCB ground for electrical contact and
optimum thermal performance.
RON
VOUT
PLLFLTR
logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point, after the
internal 25μs power bad mask timer expires.
INTVCC
29 FCB
7 ION
14 VIN
1μA
+
CIN
5V
REG
R
15
ZVIN
VINSNS
R
PLL-SYNC
0.6V
+
–
R
F
PLLIN 13
tON
MPGM 10
17
Z2
18
19
BOOST
Q
TG
26
FCNT
SWITCH
LOGIC
AND
ANTISHOOT
THROUGH
+
–
(0.5~2)
+
FOLDBACK
0.5V
MARGIN1
5
COUT
M2
CVCC
RSENSE
(OPTIONAL)*
PGND
22
0.25V
32
PGOOD
–
3.3μA
+
20
BG
21
FOLDBACK
DISABLED
AT START-UP*
6
VOUT
23
DRVCC
OV
MARGIN0
L1
DB
SENSE–
2.0V
1
M1
25
SENSE+
24
RUN
VRNG
CB
SW
ON
IREV
–
+
–
S
ICMP
1.18V
Z1
INTVCC
R
20k
+
28
27
VVON
= (10pF)
IION
R4
16
Z0
+
VIN
1
240k
0.6V
REF
ITHB
OV
Q6
R2
–
–
Q2 Q4
VFB
10K
+
2
–
SGND
4
R1
Q1
10K
UV
SW
+
–
+
–
SS
RUN
+
–
SENSE+
INTVCC
90K
+
1.4μA
EA
BG
M2
SENSE–
PGND
80% • VREFIN
1.5V
*CONNECTION W/O
SENSE RESISTOR
– + +
12K
9
VREFIN
VREFOUT
R3
8
3 ITH
RC
CC1
RUN 30
11 TRACK/SS
CSS
3770fc
9
LTC3770
OPERATION
Main Control Loop
The LTC3770 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off, the
bottom MOSFET is turned on until the current comparator
ICMP trips, restarting the one-shot timer and initiating the
next cycle. Inductor current is determined by sensing the
voltage between the SENSE– (PGND on G package) and
SENSE+ (SW on G package) pins using a sense resistor
or the bottom MOSFET on-resistance . The voltage on
the ITH pin sets the comparator threshold corresponding
to inductor valley current. The error amplifier EA adjusts
this voltage by comparing the feedback signal VFB from a
reference voltage set by the VREFIN pin. If the load current
increases, it causes a drop in the feedback voltage relative
to the reference. The ITH voltage then rises until the average
inductor current again matches the load current.
At low load currents, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator IREV which then shuts off M2, resulting in
discontinuous operation. Both switches will remain off
with the output capacitor supplying the load current until
the ITH voltage rises above the zero current level (0.75V)
to initiate another cycle. Discontinuous mode operation
is disabled by comparator F when the FCB pin is brought
below 0.6V, forcing continuous synchronous operation.
The operating frequency is determined implicitly by the top
MOSFET on-time and the duty cycle required to maintain
regulation. The one-shot timer generates an on-time that is
proportional to the ideal duty cycle, thus holding frequency
approximately constant with changes in VIN. The nominal
frequency can be adjusted with an external resistor RON.
For applications with stringent constant frequency requirements, the LTC3770 can be synchronized with an
external clock. By programming the nominal frequency
of the LTC3770 the same as the external clock frequency,
the LTC3770 behaves as a constant frequency part against
the load and supply variations.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point after the
internal 25μs power bad mask timer expires. Furthermore,
in an overvoltage condition, M1 is turned off and M2 is
turned on immediately and held on until the overvoltage
condition clears.
Foldback current limiting is provided if the output is shorted
to ground. As VFB drops, the buffered current threshold
voltage ITHB is pulled down and clamped to 0.9V. This
reduces the inductor valley current level to one tenth of its
maximum value as VFB approaches 0V. Foldback current
limiting is disabled at start-up.
Pulling the RUN pin low forces the controller into its
shutdown state, turning off both M1 and M2. Forcing a
voltage above 1.5V will turn on the device.
INTVCC Power
Power for the top and bottom MOSFET drivers and most of
the internal controller circuitry is derived from the INTVCC
pin. The top MOSFET driver is powered from a floating
bootstrap capacitor, CB . This capacitor is recharged from
INTVCC through an external Schottky diode DB when the
top MOSFET is turned off. If the input voltage is low and
INTVCC drops below 3.2V, undervoltage lockout circuitry
prevents the power switches from turning on.
3770fc
10
LTC3770
APPLICATIONS INFORMATION
Maximum Sense Voltage and VRNG Pin
Inductor current is determined by measuring the voltage
across a sense resistance that appears between the SENSE–
(PGND on G package) and SENSE+ (SW on G package)
pins. The maximum sense voltage is set by the voltage
applied to the VRNG pin and is equal to approximately
(0.133)VRNG. The current mode control loop will not allow
the inductor current valleys to exceed (0.133)VRNG /RSENSE .
In practice, one should allow some margin for variations
in the LTC3770 and external component values and a good
guide for selecting the sense resistance is:
RSENSE =
VRNG
10 • IOUT(MAX)
An external resistive divider from INTVCC can be used
to set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 50mV
or 200mV, respectively. The maximum allowed sense voltage is about 1.33 times this nominal value. However tying
the VRNG pin to ground is not recommended because the
current comparator offset is now a bigger proportion of
the total sense voltage.
Connecting the SENSE+ and SENSE– Pins
The LTC3770 comes in UH and G packages. The UH package
IC can be used with or without a sense resistor. When
using a sense resistor, place it between the source of the
bottom MOSFET, M2, and PGND. Connect the SENSE+ and
SENSE– pins to the top and bottom of the sense resistor.
Using a sense resistor provides a well defined current
limit, but adds cost and reduces efficiency. Alternatively,
one can eliminate the sense resistor and use the bottom
MOSFET as the current sense element by simply connecting
the SENSE+ pin to the SW pin and SENSE– pin to PGND.
This improves efficiency, but one must carefully choose
the MOSFET on-resistance as discussed below.
Power MOSFET Selection
The LTC3770 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V(BR)DSS,
threshold voltage V(GS)TH , on-resistance RDS(ON) , reverse
transfer capacitance CRSS and maximum current IDS(MAX).
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be used
in LTC3770 applications. If the input voltage is expected
to drop below 5V, then sub-logic level threshold MOSFETs
should be considered.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-resistance. MOSFET on-resistance is typically specified with
a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
RDS(ON)(MAX) =
RSENSE
ρT
2.0
RT NORMALIZED ON-RESISTANCE
The basic LTC3770 application circuit is shown in Figure 12.
External component selection is primarily determined by
the maximum load current and begins with the selection
of the sense resistance and power MOSFET switches. The
LTC3770 uses either a sense resistor or the on-resistance
of the synchronous power MOSFET for determining the
inductor current. The desired amount of ripple current
and operating frequency largely determines the inductor
value. Finally, CIN is selected for its ability to handle the
large RMS current into the converter and COUT is chosen
with low enough ESR to meet the output voltage ripple
and transient specification.
1.5
1.0
0.5
0
–50
50
100
0
JUNCTION TEMPERATURE (°C)
150
3770 F01
Figure 1. RDS(ON) vs Temperature
3770fc
11
LTC3770
APPLICATIONS INFORMATION
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and the
load current. When the LTC3770 is operating in continuous
mode, the duty cycles for the MOSFETs are:
VOUT
VIN
V –V
DBOT = IN OUT
VIN
DTOP =
The resulting power dissipation in the MOSFETs at
maximum output current are:
PTOP = DTOP IOUT(MAX)2 ρT(TOP) RDS(ON)(MAX)
+ k VIN2 IOUT(MAX) CRSS f
PBOT = DBOT IOUT(MAX)2 ρT(BOT) RDS(ON)(MAX)
Both MOSFETs have I2R losses and the top MOSFET includes
an additional term for transition losses, which are largest at
high input voltages. The constant k = 1.7A–1 can be used to
estimate the amount of transition loss. The bottom MOSFET
losses are greatest when the bottom duty cycle is near 100%,
during a short-circuit or at high input voltage.
Tying a resistor RON to SGND from the ION pin yields an
on-time inversely proportional to 1/3 VIN . The current out
of the ION pin is:
IION =
VIN
3 RON
For a step-down converter, this results in approximately
constant frequency operation as the input supply varies:
f=
VOUT
[H ]
VVON • 3 RON(10pF) Z
To hold frequency constant during output voltage changes,
tie the VON pin to VOUT. The VON pin has internal clamps
that limit its input to the one-shot timer. If the pin is tied
below 0.6V, the input to the one-shot is clamped at 0.6V.
Similarly, if the pin is tied above 4.8V, the input is clamped
at 4.8V. In high VOUT applications, tie VON to INTVCC . Figures
2a and 2b show how RON relates to switching frequency
for several common output voltages.
1000
VOUT = 3.3V
SWITCHING FREQUENCY (kHz)
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 1. For a maximum junction temperature of 100°C,
using a value ρT = 1.3 is reasonable.
VOUT = 2.5V
VOUT = 1.5V
100
100
Operating Frequency
The operating frequency of LTC3770 applications is
determined implicitly by the one-shot timer that controls
the on-time t ON of the top MOSFET switch. The on-time
is set by the current out of the ION pin and the voltage at
the VON pin according to:
V
tON = VON (10pF)
IION
3770 F02a
Figure 2a. Switching Frequency vs RON (VON = 0V)
1000
VOUT = 12V
SWITCHING FREQUENCY (kHz)
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
1000
RON (kΩ)
VOUT = 5V
VOUT = 3.3V
100
10
100
RON (kΩ)
1000
3770 F02b
Figure 2b. Switching Frequency vs RON (VON = INTVCC)
3770fc
12
LTC3770
APPLICATIONS INFORMATION
Changes in the load current magnitude will cause frequency
shift. Parasitic resistance in the MOSFET switches and
inductor reduce the effective voltage across the inductance,
resulting in increased duty cycle as the load current
increases. By lengthening the on-time slightly as current
increases, constant frequency operation can be maintained.
This is accomplished with a resistive divider from the ITH pin
to the VON pin and VOUT. The values required will depend
on the parasitic resistances in the specific application. A
good starting point is to feed about 25% of the voltage
change at the ITH pin to the VON pin as shown in Figure
3a. Place capacitance on the VON pin to filter out the ITH
variations at the switching frequency. The resistor load on
ITH reduces the DC gain of the error amp and degrades
load regulation, which can be avoided by using the PNP
emitter follower of Figure 3b.
Minimum Off-Time and Dropout Operation
The minimum off-time tOFF(MIN) is the smallest amount of
time that the LTC3770 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
VIN(MIN) = VOUT
tON + tOFF(MIN)
tON
A plot of Maximum Duty Cycle vs Frequency is shown in
Figure 4.
2.0
1.5
DROPOUT
REGION
1.0
0.5
0
0
0.25
0.50
0.75
DUTY CYCLE (VOUT/VIN)
1.0
3770 F04
Figure 4. Maximum Switching Frequency vs Duty Cycle
RVON1
30k
VON
VOUT
RVON2
100k
CVON
0.01μF
LTC3770
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
ITH
(3a)
⎛ V ⎞⎛ V ⎞
ΔIL = ⎜ OUT ⎟ ⎜1− OUT ⎟
⎜ f L ⎟⎝
VIN ⎠
⎝
⎠
RVON1
3k
VOUT
10k
Inductor Selection
RC
CC
INTVCC
MOSFET back off. This time is generally about 250ns for
large peak-to-peak inductor ripple current. In applications
where the peak-to-peak inductor ripple current is small,
the minimum off-time can approach 400ns. The minimum
off-time limit imposes a maximum duty cycle of tON/(tON
+ tOFF(MIN)). If the maximum duty cycle is reached, due
to a dropping input voltage for example, then the output
will drop out of regulation. The minimum input voltage
to avoid dropout is:
SWITCHING FREQUENCY (MHz)
When there is no RON resistor connected to the ION pin,
the on-time tON is theoretically infinite, which in turn could
damage the converter. To prevent this, the LTC3770 will
detect this fault condition and provide a minimum ION
current of 5μA to 10μA.
CVON
0.01μF
RVON2
10k
VON
LTC3770
RC
Q1
2N5087
ITH
CC
3770 F03
(3b)
Figure 3. Correcting Frequency Shift with Load Current Changes
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
3770fc
13
LTC3770
APPLICATIONS INFORMATION
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN . To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
⎛ V
⎞⎛
⎞
OUT ⎟ ⎜1− VOUT ⎟
L = ⎜⎜
⎟⎜
⎟
⎝ f ΔIL(MAX ) ⎠ ⎝ VIN(MAX ) ⎠
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mμ® cores. A variety of inductors designed for
high current, low voltage applications are available from
manufacturers such as Sumida, Panasonic, Coiltronics,
Coilcraft and Toko.
Schottky Diode D1 Selection
The Schottky diode D1 shown in Figure 12 conducts during the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
of the bottom MOSFET from turning on and storing charge
during the dead time, which can cause a modest (about
1%) efficiency loss. The diode can be rated for about one
half to one fifth of the full load current since it is on for
only a fraction of the duty cycle. In order for the diode
to be effective, the inductance between it and the bottom
MOSFET must be as small as possible, mandating that
these components be placed adjacently. The diode can
be omitted if the efficiency loss is tolerable.
CIN and COUT Selection
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low ESR
capacitor sized to handle the maximum RMS current.
IRMS ≅ IOUT(MAX )
VOUT
VIN
VIN
–1
VOUT
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX)/2. This simple worst-case condition
is commonly used for design because even significant
deviations do not offer much relief. Note that ripple current
ratings from capacitor manufacturers are often based on
only 2000 hours of life which makes it advisable to derate
the capacitor.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step transients.
The output ripple ΔVOUT is approximately bounded by:
⎛
1 ⎞
ΔVOUT ≤ ΔIL ⎜ESR +
⎟
8 fCOUT ⎠
⎝
Since ΔIL increases with input voltage, the output ripple
is highest at maximum input voltage. Typically, once the
ESR requirement is satisfied, the capacitance is adequate
for filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to significant
ringing. When used as input capacitors, care must be taken
to ensure that ringing from inrush currents and switching
does not pose an overvoltage hazard to the power switches
and controller. To dampen input voltage transients, add
a small 5μF to 50μF aluminum electrolytic capacitor with
an ESR in the range of 0.5Ω to 2Ω. High performance
through-hole capacitors may also be used, but an additional
ceramic capacitor in parallel is recommended to reduce
the effect of their lead inductance.
3770fc
14
LTC3770
APPLICATIONS INFORMATION
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications 0.1μF to 0.47μF, X5R
or X7R dielectric capacitor is adequate.
Discontinuous Mode Operation and FCB Pin
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.6V threshold enables discontinuous
operation where the bottom MOSFET turns off when
inductor current reverses. The load current at which current
reverses and discontinuous operation begins depends on
the amplitude of the inductor ripple current and will vary
with changes in VIN. Tying the FCB pin below the 0.6V
threshold forces continuous synchronous operation,
allowing current to reverse at light loads and maintaining
high frequency operation. To prevent forcing current back
into the main power supply, potentially boosting the input
supply to a dangerous voltage level, forced continuous
mode of operation is disabled when the TRACK/SS voltage
is 20% below the reference voltage during soft-start or
tracking up. Forced continuous mode of operation is also
disabled when the TRACK/SS voltage is below 0.1V during
tracking down operation. During these two periods, the
PGOOD signal is forced low.
+
VIN
CIN
VIN
1N4148
TG
LTC3770
SW
R4
FCB
R3
•
+
T1
1:N
•
+
VOUT2
COUT2
1μF
VOUT1
COUT
BG
SGND
PGND
Figure 5. Secondary Output Loop
3770 F05
In addition to providing a logic input to forced continuous
operation, the FCB pin provides a mean to maintain a
flyback winding output when the primary is operating
in discontinuous mode. The secondary output VOUT2 is
normally set as shown in Figure 5 by the turns ratio N
of the transformer. However, if the controller goes into
discontinuous mode and halts switching due to a light
primary load current, then VOUT2 will droop. An external
resistor divider from VOUT2 to the FCB pin sets a minimum
voltage VOUT2(MIN) below which continuous operation is
forced until VOUT2 has risen above its minimum.
⎛ R4 ⎞
VOUT 2(MIN) = 0.6 V ⎜ 1+ ⎟
⎝ R3 ⎠
Fault Conditions: Current Limit and Foldback
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3770, the maximum sense voltage is controlled
by the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
ILIMIT =
VSNS(MAX )
RDS(ON)
1
+ ΔIL
ρT 2
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The minimum value of current
limit generally occurs with the largest VIN at the highest
ambient temperature, conditions that cause the largest
power loss in the converter. Note that it is important to
check for self-consistency between the assumed MOSFET
junction temperature and the resulting value of ILIMIT which
heats the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET
on-resistance. Data sheets typically specify nominal
and maximum values for RDS(ON), but not a minimum.
A reasonable assumption is that the minimum RDS(ON)
lies the same percentage below the typical value as the
maximum lies above it. Consult the MOSFET manufacturer
for further guidelines.
3770fc
15
LTC3770
APPLICATIONS INFORMATION
To further limit current in the event of a short circuit to
ground, the LTC3770 includes foldback current limiting.
If the output falls by more than 60%, then the maximum
sense voltage is progressively lowered to about one tenth
of its full value.
INTVCC Regulator
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3770. The INTVCC pin can supply up to 50mA
RMS and must be bypassed to ground with a minimum
of 4.7μF low ESR tantalum capacitor or other low ESR
capacitor. Good bypassing is necessary to supply the high
transient currents required by the MOSFET gate drivers.
Applications using large MOSFETs with a high input voltage
and high frequency of operation may cause the LTC3770
to exceed its maximum junction temperature rating or
RMS current rating. Most of the supply current drives the
MOSFET gates. In continuous mode operation, this current
is IGATECHG = f(Qg(TOP) + Qg(BOT)). The junction temperature
can be estimated from the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3770EG is
limited to less than 14mA from a 30V supply:
TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C
External Gate Drive Buffers
The LTC3770 drivers are adequate for driving up to about
50nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating
at frequencies requiring greater RMS currents will benefit
from using external gate drive buffers such as the LTC1693.
Alternately, the external buffer circuit shown in Figure 6
can be used.
INTVCC
BOOST
10Ω
TG
Q1
FMMT619
GATE
OF M1
Q2
FMMT720
SW
10Ω
BG
Q3
FMMT619
GATE
OF M2
Q4
FMMT720
PGND
Figure 6. Optional External Gate Driver
3770 F06
Soft-Start and Tracking
The LTC3770 has the ability to either soft-start by itself with
a capacitor or track the output of another supply. When
the device is configured to soft-start by itself, a capacitor
should be connected to the TRACK/SS pin. The LTC3770 is
put in a low quiescent current shutdown state (IQ < 30μA)
if the RUN pin voltage is below 1.5V. The TRACK/SS pin is
actively pulled to ground in this shutdown state. Once the
RUN pin voltage is above 1.5V, the LTC3770 is powered
up. A soft-start current of 1.4μA then starts to charge the
soft-start capacitor CSS . Pin Z1 must be grounded for
soft-start operation. Note that soft-start is achieved not
by limiting the maximum output current of the controller
but by controlling the ramp rate of the output voltage.
Current foldback is disabled during this soft-start phase.
During the soft-start phase, the LTC3770 is ramping the
reference voltage until it is 20% below the voltage set by
the VREFIN pin. The forced continuous mode is also disabled
and PGOOD signal is forced low during this phase. The
total soft-start time can be calculated as:
tSOFTSTART = 0.8 • VREFIN • CSS/1.4μA
When the device is configured to track another supply,
the feedback voltage of the other supply is duplicated
by a resistor divider and applied to the TRACK/SS pin.
Pin Z1 should be tied to INTVCC to turn off the soft-start
current in this mode. Therefore, the voltage ramp rate on
this pin is determined by the ramp rate of the other supply
output voltage.
Output Voltage Tracking
The LTC3770 allows the user to program how its output
ramps up and down by means of the TRACK/SS pin.
Through this pin, the output can be set up to either coincidentally or ratiometrically track with another supply’s
output, as shown in Figure 7. In the following discussions,
VOUT1 refers to the master LTC3770’s output and VOUT2
refers to the slave LTC3770’s output.
To implement the coincident tracking in Figure 7a, connect
an additional resistive divider to VOUT1 and connect its
midpoint to the TRACK/SS pin of the slave IC. The ratio
of this divider should be selected the same as that of
the slave IC’s feedback divider shown in Figure 8. In this
3770fc
16
LTC3770
APPLICATIONS INFORMATION
VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT1
VOUT2
VOUT2
3770 F07
TIME
TIME
(7a) Coincident Tracking
(7b) Ratiometric Tracking
Figure 7. Two Different Modes of Output Voltage Tracking
VOUT1
VOUT2
R3
R1
TO
VFB1
PIN
TO
TRACK/SS2
PIN
R4
VOUT1
R3
TO
VFB2
PIN
VOUT2
R1
TO
VFB1
PIN
TO
TRACK/SS2
PIN
R2
R4
R3
R2
TO
VFB2
PIN
R4
3770 F08
(8a) Coincident Tracking Setup
(8b) Ratiometric Tracking Setup
Figure 8. Setup for Coincident and Ratiometric Tracking
I
I
+
D1
D2
EA2
TRACK/SS2
0.6V
VFB2
–
D3
3770 F09
Figure 9. Equivalent Input Circuit of Error Amplifier
tracking mode, VOUT1 must be set higher than VOUT2. To
implement the ratiometric tracking, the ratio of the divider
should be exactly the same as the master IC’s feedback
divider. Note that the pin Z1 of the slave IC should be tied
to INTVCC so that the internal soft-start current is disabled
in both tracking modes or it will introduce a small error
on the tracking voltage depending on the absolute values
of the tracking resistive divider.
By selecting different resistors, the LTC3770 can achieve
different modes of tracking including the two in Figure 7.
So which mode should be programmed? While either
mode in Figure 7 satisfies most practical applications,
there do exist some tradeoffs. The ratiometric mode saves
a pair of resistors, but the coincident mode offers better
output regulation. This can be better understood with the
help of Figure 9. At the input stage of the slave IC’s error
amplifier, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode
is used to match the shifted common mode voltage. The
top two current sources are of the same amplitude. In the
coincident mode, the TRACK/SS voltage is substantially
higher than 0.6V at steady state and effectively turns off
D1. D2 and D3 will therefore conduct the same current
and offer tight matching between VFB2 and the internal
precision 0.6V reference. In the ratiometric mode, however,
TRACK/SS equals 0.6V at steady state. D1 will divert part
of the bias current to make VFB2 slightly lower than 0.6V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
of output voltage deviation. Furthermore, when the master
IC’s output experiences dynamic excursion (under load
transient, for example), the slave IC output will be affected
as well. For better output regulation, use the coincident
tracking mode instead of ratiometric.
3770fc
17
LTC3770
APPLICATIONS INFORMATION
Margining
Margining is a way to program the reference voltage to
the error amplifier to a voltage different from the default
0.6V. Margining is useful for customers who want to
stress their systems by varying supply voltages during
testing. The reference voltage to the error amplifier is set
according to the following equation when the margining
function is enabled:
VREFIN = 0.6V ±(1.18V/R4) • R3
Referring to the functional diagram, 0.6V is the buffered
system reference at the VREFOUT pin. R3 and R4 are resistors
used for programming the amount of margining. VREFIN
should be a voltage between 0.5V and 1V.
There are two logic control pins, MARGIN1 and MARGIN0,
to determine whether the margining function is enabled,
Margin up(+) or Margin down(–). Table 1 summarizes
the configurations:
Table 1. Margining Function
MARGIN1
MARGIN0
MODE
LOW
LOW
No Margining
LOW
HIGH
Margin Up
HIGH
LOW
Margin Down
HIGH
HIGH
No Margining
The buffered reference at VREFOUT has the ability to source
a large amount of current. However, it can only sink a
maximum of 50μA of current. To increase the sinking
capability of this reference, connect a resistor to ground
at this pin. One may also be tempted to connect a large
capacitor to this pin to filter out the noise. However, it is
recommended that no larger than 100pF of capacitance
should be connected to this pin.
clock on the PLLIN pin. In turn, it will turn on the phaselocked loop function. The pulse width of the clock has
to be greater than 400ns and the amplitude of the clock
should be greater than 2V.
During the start-up phase, phase-locked loop function is
disabled. When LTC3770 is not in synchronization mode,
PLLFLTR pin voltage is set to around 1.18V. Frequency
synchronization is accomplished by changing the internal
on-time current according to the voltage on the PLLFLTR
pin.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal pulses. This type of phase detector
will not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, ΔfH ,
is equal to the capture range, ΔfC :
ΔfH = ΔfC = ±0.3 fO
The output of the phase detector is a complementary pair of
current sources charging or discharging the external filter
network on the PLLFLTR pin. A simplified block diagram
is shown in Figure 10.
If the external frequency (fPLLIN) is greater than the oscillator frequency fO, current is sourced continuously, pulling
up the PLLFLTR pin. When the external frequency is less
than fO, current is sunk continuously, pulling down the
PLLFLTR pin. If the external and internal frequencies are
the same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. Thus the voltage on the PLLFLTR pin is adjusted
until the phase and frequency of the external and internal
RLP
2.4V
Phase-Locked Loop and Frequency Synchronization
The LTC3770 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±30% around the
center frequency fO. The center frequency is the operating
frequency discussed in the previous section. The LTC3770
incorporates a pulse detection circuit that will detect a
CLP
PLLFLTR
PLLIN
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
3770 F10
Figure 10. Phase-Locked Loop Block Diagram
3770fc
18
LTC3770
APPLICATIONS INFORMATION
oscillators are identical. At this stable operating point the
phase comparator output is open and the filter capacitor
CLP holds the voltage. The LTC3770 PLLIN pin must be
driven from a low impedance source such as a logic gate
located close to the pin.
The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP =10kΩ and CLP is 0.01μF to
0.1μF.
Dead Time Control
To further optimize the efficiency, the LTC3770 gives users some control over the dead time of the Top gate low
and Bottom gate high transition. By applying a DC voltage
on the Z0 pin, the TG low BG high dead time can be programmed. Because the dead time is a strong function of
the load current and the type of MOSFET used, users need
to be careful to optimize the dead time for their particular
applications. Figure 11 shows the relation between the TG
Low BG High Dead time by varying the Z0 voltages. For
an application using LTC3770 with load current of 5A and
IR7811W MOSFETs, the dead time could be optimized. To
make sure that there is no shoot-through under all conditions, a dead time of 70ns is selected. This corresponds to
a DC voltage about 2.6V on Z0 pin. This voltage can easily
be generated with a resistor divider off INTVCC.
180
140
TDEAD TIME (ns)
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3770 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
resistance of one MOSFET can simply be summed with
the resistances of L and the board traces to obtain the
DC I2R loss. For example, if RDS(ON) = 0.01Ω and RL =
0.005Ω, the loss will range from 15mW to 1.5W as the
output current varies from 1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the
input voltage, load current, driver strength and MOSFET
capacitance, among other factors. The loss is significant
at input voltages above 20V and can be estimated from:
Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f
3. INTVCC current. This is the sum of the MOSFET driver
and control currents.
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
160
120
100
80
60
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
40
20
0 IOUT = 5A
IR7811W FETs
–20
0
1
Efficiency Considerations
2
3
Z0 VOLTAGE (V)
4
5
3770 F11
When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency.
Figure 11. TG Low BG High Dead Time vs Z0 Voltage
3770fc
19
LTC3770
APPLICATIONS INFORMATION
If you make a change and the input current decreases, then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators
take several cycles to respond to a step in load current.
When a load step occurs, VOUT immediately shifts by an
amount equal to ΔILOAD (ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability problem.
The ITH pin external components shown in Figure 12 will
provide adequate compensation for most applications. For
a detailed explanation of switching control loop theory see
Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: VIN = 5V to 28V (15V nominal), VOUT =
2.5V ±5%, IOUT(MAX) = 10A, f = 450kHz. First, calculate
the timing resistor with VON = VOUT:
2.5V
RON =
= 74kΩ
3(2.5V )(450kHz)(10pF )
and choose the inductor for about 40% ripple current at
the maximum VIN :
L=
⎛ 2.5V ⎞
2.5V
⎜1−
⎟ = 1.3μH
(450kHz )(0.4)(10A ) ⎝ 28V ⎠
Selecting a standard value of 1.8μH results in a maximum
ripple current of:
ΔIL =
⎛ 2.5V ⎞
2.5V
⎜1 –
⎟ = 2.8 A
(450kHz )(1.8μH) ⎝ 28V ⎠
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (RDS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
θJA = 40°C/W) yields a nominal sense voltage of:
VSNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV
Tying VRNG to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 146mV. To check if the current limit is acceptable,
assume a junction temperature of about 80°C above a
70°C ambient with ρ150°C = 1.5:
ILIMIT ≥
146mV
1
+ (2.8 A ) = 11A
(1.5)(0.010Ω) 2
and double check the assumed TJ in the MOSFET:
PBOT =
28 V – 2 .5V
2
11A ) (1.5 )(0.010 Ω) = 1.65 W
(
28 V
TJ = 70°C + (1.65W)(40°C/W) = 136°C
Because the top MOSFET is on for such a short time, an
Si4884 RDS(ON)(MAX) = 0.0165Ω, CRSS = 100pF, θJA =
40°C/W will be sufficient. Checking its power dissipation
at current limit with ρ100°C = 1.4:
PTOP =
2.5V
2
11A ) (1.4) ( 0.0165Ω ) +
(
28 V
(1.7)(28V )2 (11A )(100pF )(250kHz )
= 0.25W + 0.37 W = 0.62W
TJ = 70°C + (0.62W)(40°C/W) = 95°C
The junction temperature will be significantly less at
nominal current, but this analysis shows that careful attention to heat sinking on the board will be necessary in
this circuit.
CIN is chosen for an RMS current rating of about 3A at 85°C.
The output capacitors are chosen for a low ESR of 0.013Ω
to minimize output voltage changes due to inductor ripple
current and load steps. The ripple voltage will be only:
ΔVOUT(RIPPLE) =ΔIL(MAX) (ESR)
= (2.8A) (0.013Ω) = 36mV
However, a 0A to 10A load step will cause an output
change of up to:
ΔVOUT(STEP) = ΔILOAD (ESR) = (10A) (0.013Ω) = 130mV
An optional 22μF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 12.
3770fc
20
LTC3770
APPLICATIONS INFORMATION
INTVCC
5V
RPG
100k
R7
47k
VIN
5V TO 28V
RUN
R8
51k
R5
39k
1
2
3
4
5
R6
11k
6
7
8
9
10
11
RC
20k
CC2
100pF
CC1
500pF
R1
30.1k
R3
10k
13
14
RON
75k
R2
95.3k
12
RUN
LTC3770EG
VON
PGOOD
FCB
Z0
BOOST
VRNG
TG
VFB
SW
ITH
PGND
SGND
BG
MARGIN1
INTVCC
MARGIN0
Z1
ION
Z2
VREFIN
VREFOUT
MPGM
TRACK/SS
ZVIN
VIN
PLLIN
PLLFLTR
28
27
CIN
10μF
50V
x3
M1
Si4884
26
25
24
23
+
22
CB
0.22μF
L1
1.8μH
VOUT
2.5V
10A
21
20
DB
CMDSH-3
19
+
D1
B340A
18
17
16
15
CSS
0.1μF
CVIN
0.1μF
+
M2
Si4874
CVCC
4.7μF
L1: SUMIDA CEP125-1R8MC-H
COUT: CORNELL DUBILIER ESRE181E04B
CIN: UNITED CHEMICON THCR60E1H106ZT
R4
82k
COUT1-2
180μF
4V
x2
COUT3
23μF
x5R
x2
3770 F12
Figure 12. Design Example: 2.5V/10A at 450kHz
To set a ±25% margining, select the resistors R3, R4
such that:
VREFIN = 0.6 ± 25% • 0.6
or
1.18 • R3
= 25% • 0.6
R4
R4 ≈ 8R3
Choose R3 to be 10k, R4 to be 82k for this application.
PC Board Layout Checklist
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a
dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place CIN , COUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3770.
Use several bigger vias for power components.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
component. You can connect the copper areas to any
DC net (VIN , VOUT, GND or to any other DC rail in your
system).
3770fc
21
LTC3770
APPLICATIONS INFORMATION
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper operation of the controller.
MOSFETs. This capacitor carries the MOSFET AC
current.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and PGND pins.
• Connect the top driver boost capacitor CB closely to
the BOOST and SW pins.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
• Connect the VIN pin decoupling capacitor CIN closely
to the VIN and PGND pins.
• Connect the input capacitor(s) CIN close to the power
TYPICAL APPLICATIONS
1.8V/5A at 450kHz with Tracking
CIN: TDK C4532X5R1H685M
COUT: PANASONIC EEFUE0G181R
L1: BI TECH 1.8μH HM65-H1R8-TB
M1, M2: PHILIPS PH3230
RPG
100k
PGOOD
RUN
FCB
R7
47k
32
1
2
3
4
CF
220pF
R2
60.4k
RC
10k
R1
30.1k
CC2
100pF
MARGIN1
MARGIN0
5
6
7
CC1
1000pF
30
29
PGOOD VON RUN FCB
R8
51k
RRUN
51k
31
RON
75k
R5
10k
8
VIN
4V TO 28V
28
27
26
Z0 BOOST TG
25
M1
PH3230
SW
VRNG
SENSE+
VFB
SENSE–
PGND
ITH
BG
SGND
LTC3770EUH
MARGIN1
DRVCC
MARGIN0
INTVCC
ION
Z2
VREFIN
Z1
VREFOUT MPGM TRACK/SS PLLFLTR PLLIN VIN VINSNS ZVIN
9
10
11
12
13
14
15
24
23
22
1000pF
CB
0.22μF
R6
200k
VCC
5V
VOUT
1.8V
5A
21
20
19
DB
CMDSH-3
D1
B340A
18
17
M2
PH3230
+
COUT
180μF
4V
x2
INTVCC
16
CVCC
4.7μF
TRACK/SS
L1
1.8μH
COUT3
22μF
X5R
x2
CIN
6.8μF
50V
x3
3770 TA02a
3770fc
22
LTC3770
PACKAGE DESCRIPTION
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1.25 p0.12
7.8 – 8.2
7.40 – 8.20
(.291 – .323)
5.3 – 5.7
0.42 p0.03
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.65 BSC
G28 SSOP 0204
RECOMMENDED SOLDER PAD LAYOUT
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.65
(.0256)
BSC
0.55 – 0.95
(.022 – .037)
0.05
(.002)
MIN
0.22 – 0.38
(.009 – .015)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3. DRAWING NOT TO SCALE
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
BOTTOM VIEW—EXPOSED PAD
5.00 p 0.10
(4 SIDES)
0.70 p0.05
0.75 p 0.05
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 s 45o CHAMFER
31 32
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.50 p0.05
4.10 p0.05
3.45 p 0.05
3.50 REF
(4 SIDES)
3.50 REF
(4-SIDES)
3.45 p 0.05
3.45 p 0.10
3.45 p 0.10
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 p 0.05
0.50 BSC
(UH32) QFN 0406 REV D
3770fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC3770
TYPICAL APPLICATION
Typical Application 2.5V/10A Synchronized at 450kHz
CIN: TDK C4532X5R1H685M
COUT: PANASONIC EEFUE0G181R
L1: BI TECH 1.8μH HM65-H1R8-TB
M1, M2: PHILIPS PH3230
RPG
100k
PGOOD
RUN
FCB
VIN
5V TO 28V
R7
47k
32
R4
39k
RRUN
51k
R8
51k
1
2
R3
11k
3
4
CF
220pF
R2
95.3k
RC
10k
5
MARGIN1
6
MARGIN0
7
CC2
100pF
R1
30.1k
8
RON
75k
CC1
1000pF
31
30
29
PGOOD VON RUN FCB
28
27
26
Z0 BOOST TG
25
M1
PH3230
SW
VRNG
SENSE+
VFB
SENSE–
PGND
ITH
BG
SGND
LTC3770EUH
MARGIN1
DRVCC
MARGIN0
INTVCC
ION
Z2
VREFIN
Z1
24
23
1000pF
R6
82k
CSS
0.1μF
CPL
0.01μF
VOUT
2.5V
10A
21
20
D1
B340A
DB
CMDSH-3
19
18
17
M2
PH3230
+
COUT
180μF
4V
x2
INTVCC
R5 VREFOUT MPGM TRACK/SS PLLFLTR PLLIN VIN VINSNS ZVIN
10k
9
10
11
12
13
14
15
16
COUT3
22μF
X5R
x2
CVCC
4.7μF
PLLIN
RPL
10k
L1
1.8μH
CB
0.22μF
22
CIN
10μF
50V
x3
0.1μF
CP
1000pF
CVIN
0.01μF
RVIN
10Ω
3770 TA02b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Up to 95% Efficiency, 550kHz, 2.65V ≤ VIN ≤ 8.5V,
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LTC1876
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LTC3708
Dual, 2-Phase, No RSENSE Synchronous Step-Down Controller with
Output Tracking
Fast Transient Response Reduces COUT; 4V ≤ VIN ≤ 36V,
0.6V ≤ VOUT ≤ 6V; 2-Phase Operation Reduces CIN
LTC3713
Low VIN High Current Synchronous Step-Down Controller
1.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)VIN , IOUT Up to 20A
LTC3731
3-Phase Synchronous Step-Down Controller
600kHz; Up to 60A Output
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Low VOUT, No RSENSE Synchronous Step-Down Controller
0.6V ≤ VOUT ≤ (0.9)VIN , 4V ≤ VIN ≤ 36V, IOUT Up to 20A
®
Burst Mode is a trademark of Linear Technology Corporation.
3770fc
24 Linear Technology Corporation
LT 0209 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
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